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Jia Liu9f610112012-02-17 08:55:11 +00001//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00007//
Akira Hatanakae2489122011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00009//
Evan Cheng0d639a22011-07-01 21:01:15 +000010// This file implements the Mips specific subclass of TargetSubtargetInfo.
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000011//
Akira Hatanakae2489122011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000013
Reed Kotler1595f362013-04-09 19:46:01 +000014#include "MipsMachineFunction.h"
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000015#include "Mips.h"
Akira Hatanaka047473e2012-03-28 00:24:17 +000016#include "MipsRegisterInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +000017#include "MipsSubtarget.h"
18#include "MipsTargetMachine.h"
Reed Kotler1595f362013-04-09 19:46:01 +000019#include "llvm/IR/Attributes.h"
20#include "llvm/IR/Function.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/Debug.h"
Evan Cheng2bb40352011-08-24 18:08:43 +000023#include "llvm/Support/TargetRegistry.h"
Reed Kotler1595f362013-04-09 19:46:01 +000024#include "llvm/Support/raw_ostream.h"
Evan Cheng54b68e32011-07-01 20:45:01 +000025
Chandler Carruthd174b722014-04-22 02:03:14 +000026using namespace llvm;
27
Chandler Carruth84e68b22014-04-22 02:41:26 +000028#define DEBUG_TYPE "mips-subtarget"
29
Evan Cheng54b68e32011-07-01 20:45:01 +000030#define GET_SUBTARGETINFO_TARGET_DESC
Evan Cheng4d1ca962011-07-08 01:53:10 +000031#define GET_SUBTARGETINFO_CTOR
Evan Chengc9c090d2011-07-01 22:36:09 +000032#include "MipsGenSubtargetInfo.inc"
Evan Cheng54b68e32011-07-01 20:45:01 +000033
Reed Kotler1595f362013-04-09 19:46:01 +000034// FIXME: Maybe this should be on by default when Mips16 is specified
35//
Eric Christopher0218f8c2015-02-20 08:42:34 +000036static cl::opt<bool>
37 Mixed16_32("mips-mixed-16-32", cl::init(false),
38 cl::desc("Allow for a mixture of Mips16 "
39 "and Mips32 code in a single output file"),
40 cl::Hidden);
Reed Kotler1595f362013-04-09 19:46:01 +000041
Eric Christopher0218f8c2015-02-20 08:42:34 +000042static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
43 cl::desc("Compile all functions that don't use "
44 "floating point as Mips 16"),
45 cl::Hidden);
46
47static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
48 cl::desc("Enable mips16 hard float."),
49 cl::init(false));
Reed Kotlerfe94cc32013-04-10 16:58:04 +000050
Reed Kotler783c7942013-05-10 22:25:39 +000051static cl::opt<bool>
Eric Christopher0218f8c2015-02-20 08:42:34 +000052 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
53 cl::desc("Enable mips16 constant islands."),
54 cl::init(true));
Reed Kotler783c7942013-05-10 22:25:39 +000055
Reed Kotler91ae9822013-10-27 21:57:36 +000056static cl::opt<bool>
Eric Christopher0218f8c2015-02-20 08:42:34 +000057 GPOpt("mgpopt", cl::Hidden,
58 cl::desc("Enable gp-relative addressing of mips small data items"));
Sasa Stankovicb38db1e2014-11-06 13:20:12 +000059
David Blaikiea379b1812011-12-20 02:50:00 +000060void MipsSubtarget::anchor() { }
61
Evan Chengfe6e4052011-06-30 01:53:36 +000062MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
Akira Hatanakaad495022012-08-22 03:18:13 +000063 const std::string &FS, bool little,
Eric Christopher90724282015-01-08 18:18:57 +000064 const MipsTargetMachine &TM)
Vasileios Kalintirisb2dd15f2014-11-11 11:43:55 +000065 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
Toma Tabacu506cfd02015-05-07 10:29:52 +000066 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
67 NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
68 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
69 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
70 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
Eric Christopher8985ba92014-12-19 23:46:53 +000071 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
72 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
Eric Christopher8b770652015-01-26 19:03:15 +000073 HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(*TM.getDataLayout()),
74 InstrInfo(
75 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
Eric Christophere54f10e2014-07-18 23:33:47 +000076 FrameLowering(MipsFrameLowering::create(*this)),
Eric Christopher90724282015-01-08 18:18:57 +000077 TLInfo(MipsTargetLowering::create(TM, *this)) {
Simon Atanasyan1093afe22013-11-19 12:20:17 +000078
Reed Kotler1595f362013-04-09 19:46:01 +000079 PreviousInMips16Mode = InMips16Mode;
80
Vasileios Kalintirisb2dd15f2014-11-11 11:43:55 +000081 if (MipsArchVersion == MipsDefault)
82 MipsArchVersion = Mips32;
83
Vasileios Kalintiris8edbcad2014-12-12 15:16:46 +000084 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
85 // been tested and currently exist for the integrated assembler only.
Daniel Sandersd2409532014-05-07 16:25:22 +000086 if (MipsArchVersion == Mips1)
87 report_fatal_error("Code generation for MIPS-I is not implemented", false);
Daniel Sandersd2409532014-05-07 16:25:22 +000088 if (MipsArchVersion == Mips5)
89 report_fatal_error("Code generation for MIPS-V is not implemented", false);
90
Akira Hatanaka6de4d122011-09-21 02:45:29 +000091 // Check if Architecture and ABI are compatible.
Daniel Sanders5e94e682014-03-27 16:42:17 +000092 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
93 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
Akira Hatanaka6de4d122011-09-21 02:45:29 +000094 "Invalid Arch & ABI pair.");
95
Daniel Sanders1b1e25b2013-09-27 10:08:31 +000096 if (hasMSA() && !isFP64bit())
97 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
98 "See -mattr=+fp64.",
99 false);
100
Daniel Sanders7e527422014-07-10 13:38:23 +0000101 if (!isABI_O32() && !useOddSPReg())
Daniel Sanders7ddb0ab2014-07-14 13:08:14 +0000102 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
Daniel Sanders7e527422014-07-10 13:38:23 +0000103
Sasa Stankovicb976fee2014-07-14 09:40:29 +0000104 if (IsFPXX && (isABI_N32() || isABI_N64()))
105 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
106
Daniel Sandersb7f1c6f2014-05-09 09:46:21 +0000107 if (hasMips32r6()) {
108 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
109
110 assert(isFP64bit());
111 assert(isNaN2008());
112 if (hasDSP())
113 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
114 }
115
Eric Christopher90724282015-01-08 18:18:57 +0000116 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
Sasa Stankovicb38db1e2014-11-06 13:20:12 +0000117 report_fatal_error("position-independent code requires '-mabicalls'");
118
Akira Hatanakaad495022012-08-22 03:18:13 +0000119 // Set UseSmallSection.
Sasa Stankovicb38db1e2014-11-06 13:20:12 +0000120 UseSmallSection = GPOpt;
121 if (!NoABICalls && GPOpt) {
122 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
123 << "\n";
124 UseSmallSection = false;
125 }
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000126}
Akira Hatanaka047473e2012-03-28 00:24:17 +0000127
Sanjay Patela2f658d2014-07-15 22:39:58 +0000128/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
129bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
130
131void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
Akira Hatanaka047473e2012-03-28 00:24:17 +0000132 CriticalPathRCs.clear();
Sanjay Patela2f658d2014-07-15 22:39:58 +0000133 CriticalPathRCs.push_back(isGP64bit() ?
134 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
135}
136
137CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
138 return CodeGenOpt::Aggressive;
Akira Hatanaka047473e2012-03-28 00:24:17 +0000139}
Reed Kotler1595f362013-04-09 19:46:01 +0000140
Eric Christopherdaa9dbb2014-07-03 00:10:24 +0000141MipsSubtarget &
142MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
Eric Christopher90724282015-01-08 18:18:57 +0000143 const TargetMachine &TM) {
Eric Christopherbbe6ff52015-02-18 00:55:06 +0000144 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
145
Eric Christopher5b336a22014-07-02 01:14:43 +0000146 // Parse features string.
147 ParseSubtargetFeatures(CPUName, FS);
148 // Initialize scheduling itinerary for the specified CPU.
149 InstrItins = getInstrItineraryForCPU(CPUName);
Eric Christopherdaa9dbb2014-07-03 00:10:24 +0000150
Toma Tabacu506cfd02015-05-07 10:29:52 +0000151 if (InMips16Mode && !IsSoftFloat)
Eric Christopherdaa9dbb2014-07-03 00:10:24 +0000152 InMips16HardFloat = true;
Eric Christopherdaa9dbb2014-07-03 00:10:24 +0000153
Eric Christopher5b336a22014-07-02 01:14:43 +0000154 return *this;
155}
156
Reed Kotler91ae9822013-10-27 21:57:36 +0000157bool MipsSubtarget::useConstantIslands() {
158 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
159 return Mips16ConstantIslands;
160}
Eric Christopherf74faf42014-07-18 22:34:20 +0000161
162Reloc::Model MipsSubtarget::getRelocationModel() const {
Eric Christopher90724282015-01-08 18:18:57 +0000163 return TM.getRelocationModel();
Eric Christopherf74faf42014-07-18 22:34:20 +0000164}
Eric Christophera5762812015-01-26 17:33:46 +0000165
166bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
167bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
168bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
169bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
170const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }