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gerrit-public.fairphone.software / toolchain / llvm-project / f836af869deeef065f0bc0217c9f313c8642c9b4 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: 19783d3f9d3e3713769468b5134827748b3f9b33 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]58static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 unsigned RegNo, uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 unsigned RegNo, uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]88static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
89 uint64_t Address,
90 const void *Decode);
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame^]91static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
92 uint64_t Address,
93 const void *Decode);
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]94static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
95 uint64_t Address,
96 const void *Decode);
Sander de Smalen906a5de2018-01-09 17:01:27 +0000[diff] [blame]97static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
98 uint64_t Address,
99 const void *Decode);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]101static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]102 uint64_t Address,
103 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]104static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 uint64_t Address,
106 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]107static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]108 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]109static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]110 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]111static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]113static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]115static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]116 uint64_t Address,
117 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address,
120 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]121static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]122 uint64_t Address,
123 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
125 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address,
129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]131 uint64_t Address,
132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
134 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]135 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]136static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
137 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]139static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]140 uint64_t Address,
141 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]142static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
143 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]144 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]145static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]147static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]148 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]149static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]150 uint64_t Address,
151 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]152static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]153 uint64_t Address,
154 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]155static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]156 uint64_t Address, const void *Decoder);
157
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]158static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]159 uint64_t Address,
160 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]163static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]164 uint64_t Addr,
165 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]166static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]167 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]168static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169 uint64_t Addr,
170 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]171static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]172 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]173static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 uint64_t Addr,
175 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]176static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]177 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]178static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]180static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]181 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]182static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]183 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]184static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]186static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
187 unsigned RegNo,
188 uint64_t Addr,
189 const void *Decoder);
190static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
191 unsigned RegNo,
192 uint64_t Addr,
193 const void *Decoder);
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]194static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
195 uint32_t insn,
196 uint64_t Address,
197 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]198template<int Bits>
199static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
200 uint64_t Address, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]201
202static bool Check(DecodeStatus &Out, DecodeStatus In) {
203 switch (In) {
204 case MCDisassembler::Success:
205 // Out stays the same.
206 return true;
207 case MCDisassembler::SoftFail:
208 Out = In;
209 return true;
210 case MCDisassembler::Fail:
211 Out = In;
212 return false;
213 }
214 llvm_unreachable("Invalid DecodeStatus!");
215}
216
217#include "AArch64GenDisassemblerTables.inc"
218#include "AArch64GenInstrInfo.inc"
219
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]220#define Success MCDisassembler::Success
221#define Fail MCDisassembler::Fail
222#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]223
224static MCDisassembler *createAArch64Disassembler(const Target &T,
225 const MCSubtargetInfo &STI,
226 MCContext &Ctx) {
227 return new AArch64Disassembler(STI, Ctx);
228}
229
230DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]231 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]232 uint64_t Address,
233 raw_ostream &OS,
234 raw_ostream &CS) const {
235 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]236
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]237 Size = 0;
238 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]239 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]240 return Fail;
241 Size = 4;
242
243 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]244 uint32_t Insn =
245 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246
247 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]248 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249}
250
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]251static MCSymbolizer *
252createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
253 LLVMSymbolLookupCallback SymbolLookUp,
254 void *DisInfo, MCContext *Ctx,
255 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]256 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
257 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]258}
259
260extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]261 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]262 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]263 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]264 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]265 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]266 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]267 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]268 createAArch64ExternalSymbolizer);
269
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]270 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]271 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]272 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]273 createAArch64ExternalSymbolizer);
274}
275
276static const unsigned FPR128DecoderTable[] = {
277 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
278 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
279 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
280 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
281 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
282 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
283 AArch64::Q30, AArch64::Q31
284};
285
286static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
287 uint64_t Addr,
288 const void *Decoder) {
289 if (RegNo > 31)
290 return Fail;
291
292 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]293 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]294 return Success;
295}
296
297static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
298 uint64_t Addr,
299 const void *Decoder) {
300 if (RegNo > 15)
301 return Fail;
302 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
303}
304
305static const unsigned FPR64DecoderTable[] = {
306 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
307 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
308 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
309 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
310 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
311 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
312 AArch64::D30, AArch64::D31
313};
314
315static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
316 uint64_t Addr,
317 const void *Decoder) {
318 if (RegNo > 31)
319 return Fail;
320
321 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]322 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]323 return Success;
324}
325
326static const unsigned FPR32DecoderTable[] = {
327 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
328 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
329 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
330 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
331 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
332 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
333 AArch64::S30, AArch64::S31
334};
335
336static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
337 uint64_t Addr,
338 const void *Decoder) {
339 if (RegNo > 31)
340 return Fail;
341
342 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]343 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]344 return Success;
345}
346
347static const unsigned FPR16DecoderTable[] = {
348 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
349 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
350 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
351 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
352 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
353 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
354 AArch64::H30, AArch64::H31
355};
356
357static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
358 uint64_t Addr,
359 const void *Decoder) {
360 if (RegNo > 31)
361 return Fail;
362
363 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]364 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]365 return Success;
366}
367
368static const unsigned FPR8DecoderTable[] = {
369 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
370 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
371 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
372 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
373 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
374 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
375 AArch64::B30, AArch64::B31
376};
377
378static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
379 uint64_t Addr,
380 const void *Decoder) {
381 if (RegNo > 31)
382 return Fail;
383
384 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]385 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]386 return Success;
387}
388
389static const unsigned GPR64DecoderTable[] = {
390 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
391 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
392 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
393 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
394 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
395 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
396 AArch64::LR, AArch64::XZR
397};
398
399static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
400 uint64_t Addr,
401 const void *Decoder) {
402 if (RegNo > 31)
403 return Fail;
404
405 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]406 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]407 return Success;
408}
409
410static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
411 uint64_t Addr,
412 const void *Decoder) {
413 if (RegNo > 31)
414 return Fail;
415 unsigned Register = GPR64DecoderTable[RegNo];
416 if (Register == AArch64::XZR)
417 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]418 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]419 return Success;
420}
421
422static const unsigned GPR32DecoderTable[] = {
423 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
424 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
425 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
426 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
427 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
428 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
429 AArch64::W30, AArch64::WZR
430};
431
432static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
433 uint64_t Addr,
434 const void *Decoder) {
435 if (RegNo > 31)
436 return Fail;
437
438 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]439 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]440 return Success;
441}
442
443static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
444 uint64_t Addr,
445 const void *Decoder) {
446 if (RegNo > 31)
447 return Fail;
448
449 unsigned Register = GPR32DecoderTable[RegNo];
450 if (Register == AArch64::WZR)
451 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]452 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]453 return Success;
454}
Florian Hahn91f11e52017-11-07 16:45:48 +0000[diff] [blame]455static const unsigned ZPRDecoderTable[] = {
456 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
457 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
458 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
459 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
460 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
461 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
462 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
463 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
464};
465
466static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
467 uint64_t Address,
468 const void* Decoder) {
469 if (RegNo > 31)
470 return Fail;
471
472 unsigned Register = ZPRDecoderTable[RegNo];
473 Inst.addOperand(MCOperand::createReg(Register));
474 return Success;
475}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]476
Sander de Smalenf836af82018-04-16 07:09:29 +0000[diff] [blame^]477static const unsigned ZZDecoderTable[] = {
478 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
479 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
480 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
481 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
482 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
483 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
484 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
485 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
486};
487
488static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
489 uint64_t Address,
490 const void* Decoder) {
491 if (RegNo > 31)
492 return Fail;
493 unsigned Register = ZZDecoderTable[RegNo];
494 Inst.addOperand(MCOperand::createReg(Register));
495 return Success;
496}
497
Sander de Smalencd6be962017-12-20 11:02:42 +0000[diff] [blame]498static const unsigned PPRDecoderTable[] = {
499 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
500 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
501 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
502 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
503};
504
505static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
506 uint64_t Addr, const void *Decoder) {
507 if (RegNo > 15)
508 return Fail;
509
510 unsigned Register = PPRDecoderTable[RegNo];
511 Inst.addOperand(MCOperand::createReg(Register));
512 return Success;
513}
514
Sander de Smalendc5e0812018-01-03 10:15:46 +0000[diff] [blame]515static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
516 uint64_t Addr,
517 const void* Decoder) {
518 if (RegNo > 7)
519 return Fail;
520
521 // Just reuse the PPR decode table
522 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
523}
524
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]525static const unsigned VectorDecoderTable[] = {
526 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
527 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
528 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
529 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
530 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
531 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
532 AArch64::Q30, AArch64::Q31
533};
534
535static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
536 uint64_t Addr,
537 const void *Decoder) {
538 if (RegNo > 31)
539 return Fail;
540
541 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]542 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]543 return Success;
544}
545
546static const unsigned QQDecoderTable[] = {
547 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
548 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
549 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
550 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
551 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
552 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
553 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
554 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
555};
556
557static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
558 uint64_t Addr, const void *Decoder) {
559 if (RegNo > 31)
560 return Fail;
561 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]562 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]563 return Success;
564}
565
566static const unsigned QQQDecoderTable[] = {
567 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
568 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
569 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
570 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
571 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
572 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
573 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
574 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
575 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
576 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
577 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
578};
579
580static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
581 uint64_t Addr, const void *Decoder) {
582 if (RegNo > 31)
583 return Fail;
584 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]585 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]586 return Success;
587}
588
589static const unsigned QQQQDecoderTable[] = {
590 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
591 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
592 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
593 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
594 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
595 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
596 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
597 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
598 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
599 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
600 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
601};
602
603static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
604 uint64_t Addr,
605 const void *Decoder) {
606 if (RegNo > 31)
607 return Fail;
608 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]609 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]610 return Success;
611}
612
613static const unsigned DDDecoderTable[] = {
614 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
615 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
616 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
617 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
618 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
619 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
620 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
621 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
622};
623
624static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
625 uint64_t Addr, const void *Decoder) {
626 if (RegNo > 31)
627 return Fail;
628 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]629 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]630 return Success;
631}
632
633static const unsigned DDDDecoderTable[] = {
634 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
635 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
636 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
637 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
638 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
639 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
640 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
641 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
642 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
643 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
644 AArch64::D30_D31_D0, AArch64::D31_D0_D1
645};
646
647static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
648 uint64_t Addr, const void *Decoder) {
649 if (RegNo > 31)
650 return Fail;
651 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]652 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]653 return Success;
654}
655
656static const unsigned DDDDDecoderTable[] = {
657 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
658 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
659 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
660 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
661 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
662 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
663 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
664 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
665 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
666 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
667 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
668};
669
670static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
671 uint64_t Addr,
672 const void *Decoder) {
673 if (RegNo > 31)
674 return Fail;
675 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]676 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]677 return Success;
678}
679
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]680static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]681 uint64_t Addr,
682 const void *Decoder) {
683 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]684 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]685 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]686 return Success;
687}
688
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]689static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]690 uint64_t Addr,
691 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]692 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]693 return Success;
694}
695
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]696static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]697 uint64_t Addr, const void *Decoder) {
698 int64_t ImmVal = Imm;
699 const AArch64Disassembler *Dis =
700 static_cast<const AArch64Disassembler *>(Decoder);
701
702 // Sign-extend 19-bit immediate.
703 if (ImmVal & (1 << (19 - 1)))
704 ImmVal |= ~((1LL << 19) - 1);
705
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]706 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]707 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]708 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]709 return Success;
710}
711
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]712static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]713 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]714 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
715 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]716 return Success;
717}
718
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]719static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]720 uint64_t Address,
721 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]722 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]723
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]724 // Every system register in the encoding space is valid with the syntax
725 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
726 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]727}
728
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]729static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]730 uint64_t Address,
731 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]732 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]733
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]734 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]735}
736
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]737static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]738 uint64_t Address,
739 const void *Decoder) {
740 // This decoder exists to add the dummy Lane operand to the MCInst, which must
741 // be 1 in assembly but has no other real manifestation.
742 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
743 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
744 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
745
746 if (IsToVec) {
747 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
748 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
749 } else {
750 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
751 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
752 }
753
754 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]755 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]756
757 return Success;
758}
759
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]760static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]761 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]762 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]763 return Success;
764}
765
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]766static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]767 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]768 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]769 return Success;
770}
771
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]772static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]773 uint64_t Addr, const void *Decoder) {
774 return DecodeVecShiftRImm(Inst, Imm, 64);
775}
776
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]777static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]778 uint64_t Addr,
779 const void *Decoder) {
780 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
781}
782
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]783static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]784 uint64_t Addr, const void *Decoder) {
785 return DecodeVecShiftRImm(Inst, Imm, 32);
786}
787
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]788static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]789 uint64_t Addr,
790 const void *Decoder) {
791 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
792}
793
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]794static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]795 uint64_t Addr, const void *Decoder) {
796 return DecodeVecShiftRImm(Inst, Imm, 16);
797}
798
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]799static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]800 uint64_t Addr,
801 const void *Decoder) {
802 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
803}
804
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]805static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]806 uint64_t Addr, const void *Decoder) {
807 return DecodeVecShiftRImm(Inst, Imm, 8);
808}
809
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]810static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]811 uint64_t Addr, const void *Decoder) {
812 return DecodeVecShiftLImm(Inst, Imm, 64);
813}
814
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]815static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]816 uint64_t Addr, const void *Decoder) {
817 return DecodeVecShiftLImm(Inst, Imm, 32);
818}
819
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]820static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]821 uint64_t Addr, const void *Decoder) {
822 return DecodeVecShiftLImm(Inst, Imm, 16);
823}
824
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]825static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]826 uint64_t Addr, const void *Decoder) {
827 return DecodeVecShiftLImm(Inst, Imm, 8);
828}
829
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]830static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
831 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]832 const void *Decoder) {
833 unsigned Rd = fieldFromInstruction(insn, 0, 5);
834 unsigned Rn = fieldFromInstruction(insn, 5, 5);
835 unsigned Rm = fieldFromInstruction(insn, 16, 5);
836 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
837 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
838 unsigned shift = (shiftHi << 6) | shiftLo;
839 switch (Inst.getOpcode()) {
840 default:
841 return Fail;
842 case AArch64::ADDWrs:
843 case AArch64::ADDSWrs:
844 case AArch64::SUBWrs:
845 case AArch64::SUBSWrs:
846 // if shift == '11' then ReservedValue()
847 if (shiftHi == 0x3)
848 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]849 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]850 case AArch64::ANDWrs:
851 case AArch64::ANDSWrs:
852 case AArch64::BICWrs:
853 case AArch64::BICSWrs:
854 case AArch64::ORRWrs:
855 case AArch64::ORNWrs:
856 case AArch64::EORWrs:
857 case AArch64::EONWrs: {
858 // if sf == '0' and imm6<5> == '1' then ReservedValue()
859 if (shiftLo >> 5 == 1)
860 return Fail;
861 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
862 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
863 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
864 break;
865 }
866 case AArch64::ADDXrs:
867 case AArch64::ADDSXrs:
868 case AArch64::SUBXrs:
869 case AArch64::SUBSXrs:
870 // if shift == '11' then ReservedValue()
871 if (shiftHi == 0x3)
872 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]873 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]874 case AArch64::ANDXrs:
875 case AArch64::ANDSXrs:
876 case AArch64::BICXrs:
877 case AArch64::BICSXrs:
878 case AArch64::ORRXrs:
879 case AArch64::ORNXrs:
880 case AArch64::EORXrs:
881 case AArch64::EONXrs:
882 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
883 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
884 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
885 break;
886 }
887
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]888 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]889 return Success;
890}
891
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]892static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]893 uint64_t Addr,
894 const void *Decoder) {
895 unsigned Rd = fieldFromInstruction(insn, 0, 5);
896 unsigned imm = fieldFromInstruction(insn, 5, 16);
897 unsigned shift = fieldFromInstruction(insn, 21, 2);
898 shift <<= 4;
899 switch (Inst.getOpcode()) {
900 default:
901 return Fail;
902 case AArch64::MOVZWi:
903 case AArch64::MOVNWi:
904 case AArch64::MOVKWi:
905 if (shift & (1U << 5))
906 return Fail;
907 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
908 break;
909 case AArch64::MOVZXi:
910 case AArch64::MOVNXi:
911 case AArch64::MOVKXi:
912 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
913 break;
914 }
915
916 if (Inst.getOpcode() == AArch64::MOVKWi ||
917 Inst.getOpcode() == AArch64::MOVKXi)
918 Inst.addOperand(Inst.getOperand(0));
919
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]920 Inst.addOperand(MCOperand::createImm(imm));
921 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]922 return Success;
923}
924
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]925static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
926 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]927 const void *Decoder) {
928 unsigned Rt = fieldFromInstruction(insn, 0, 5);
929 unsigned Rn = fieldFromInstruction(insn, 5, 5);
930 unsigned offset = fieldFromInstruction(insn, 10, 12);
931 const AArch64Disassembler *Dis =
932 static_cast<const AArch64Disassembler *>(Decoder);
933
934 switch (Inst.getOpcode()) {
935 default:
936 return Fail;
937 case AArch64::PRFMui:
938 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]939 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]940 break;
941 case AArch64::STRBBui:
942 case AArch64::LDRBBui:
943 case AArch64::LDRSBWui:
944 case AArch64::STRHHui:
945 case AArch64::LDRHHui:
946 case AArch64::LDRSHWui:
947 case AArch64::STRWui:
948 case AArch64::LDRWui:
949 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
950 break;
951 case AArch64::LDRSBXui:
952 case AArch64::LDRSHXui:
953 case AArch64::LDRSWui:
954 case AArch64::STRXui:
955 case AArch64::LDRXui:
956 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
957 break;
958 case AArch64::LDRQui:
959 case AArch64::STRQui:
960 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
961 break;
962 case AArch64::LDRDui:
963 case AArch64::STRDui:
964 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
965 break;
966 case AArch64::LDRSui:
967 case AArch64::STRSui:
968 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
969 break;
970 case AArch64::LDRHui:
971 case AArch64::STRHui:
972 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
973 break;
974 case AArch64::LDRBui:
975 case AArch64::STRBui:
976 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
977 break;
978 }
979
980 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
981 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]982 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]983 return Success;
984}
985
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]986static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
987 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]988 const void *Decoder) {
989 unsigned Rt = fieldFromInstruction(insn, 0, 5);
990 unsigned Rn = fieldFromInstruction(insn, 5, 5);
991 int64_t offset = fieldFromInstruction(insn, 12, 9);
992
993 // offset is a 9-bit signed immediate, so sign extend it to
994 // fill the unsigned.
995 if (offset & (1 << (9 - 1)))
996 offset |= ~((1LL << 9) - 1);
997
998 // First operand is always the writeback to the address register, if needed.
999 switch (Inst.getOpcode()) {
1000 default:
1001 break;
1002 case AArch64::LDRSBWpre:
1003 case AArch64::LDRSHWpre:
1004 case AArch64::STRBBpre:
1005 case AArch64::LDRBBpre:
1006 case AArch64::STRHHpre:
1007 case AArch64::LDRHHpre:
1008 case AArch64::STRWpre:
1009 case AArch64::LDRWpre:
1010 case AArch64::LDRSBWpost:
1011 case AArch64::LDRSHWpost:
1012 case AArch64::STRBBpost:
1013 case AArch64::LDRBBpost:
1014 case AArch64::STRHHpost:
1015 case AArch64::LDRHHpost:
1016 case AArch64::STRWpost:
1017 case AArch64::LDRWpost:
1018 case AArch64::LDRSBXpre:
1019 case AArch64::LDRSHXpre:
1020 case AArch64::STRXpre:
1021 case AArch64::LDRSWpre:
1022 case AArch64::LDRXpre:
1023 case AArch64::LDRSBXpost:
1024 case AArch64::LDRSHXpost:
1025 case AArch64::STRXpost:
1026 case AArch64::LDRSWpost:
1027 case AArch64::LDRXpost:
1028 case AArch64::LDRQpre:
1029 case AArch64::STRQpre:
1030 case AArch64::LDRQpost:
1031 case AArch64::STRQpost:
1032 case AArch64::LDRDpre:
1033 case AArch64::STRDpre:
1034 case AArch64::LDRDpost:
1035 case AArch64::STRDpost:
1036 case AArch64::LDRSpre:
1037 case AArch64::STRSpre:
1038 case AArch64::LDRSpost:
1039 case AArch64::STRSpost:
1040 case AArch64::LDRHpre:
1041 case AArch64::STRHpre:
1042 case AArch64::LDRHpost:
1043 case AArch64::STRHpost:
1044 case AArch64::LDRBpre:
1045 case AArch64::STRBpre:
1046 case AArch64::LDRBpost:
1047 case AArch64::STRBpost:
1048 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1049 break;
1050 }
1051
1052 switch (Inst.getOpcode()) {
1053 default:
1054 return Fail;
1055 case AArch64::PRFUMi:
1056 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1057 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1058 break;
1059 case AArch64::STURBBi:
1060 case AArch64::LDURBBi:
1061 case AArch64::LDURSBWi:
1062 case AArch64::STURHHi:
1063 case AArch64::LDURHHi:
1064 case AArch64::LDURSHWi:
1065 case AArch64::STURWi:
1066 case AArch64::LDURWi:
1067 case AArch64::LDTRSBWi:
1068 case AArch64::LDTRSHWi:
1069 case AArch64::STTRWi:
1070 case AArch64::LDTRWi:
1071 case AArch64::STTRHi:
1072 case AArch64::LDTRHi:
1073 case AArch64::LDTRBi:
1074 case AArch64::STTRBi:
1075 case AArch64::LDRSBWpre:
1076 case AArch64::LDRSHWpre:
1077 case AArch64::STRBBpre:
1078 case AArch64::LDRBBpre:
1079 case AArch64::STRHHpre:
1080 case AArch64::LDRHHpre:
1081 case AArch64::STRWpre:
1082 case AArch64::LDRWpre:
1083 case AArch64::LDRSBWpost:
1084 case AArch64::LDRSHWpost:
1085 case AArch64::STRBBpost:
1086 case AArch64::LDRBBpost:
1087 case AArch64::STRHHpost:
1088 case AArch64::LDRHHpost:
1089 case AArch64::STRWpost:
1090 case AArch64::LDRWpost:
1091 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1092 break;
1093 case AArch64::LDURSBXi:
1094 case AArch64::LDURSHXi:
1095 case AArch64::LDURSWi:
1096 case AArch64::STURXi:
1097 case AArch64::LDURXi:
1098 case AArch64::LDTRSBXi:
1099 case AArch64::LDTRSHXi:
1100 case AArch64::LDTRSWi:
1101 case AArch64::STTRXi:
1102 case AArch64::LDTRXi:
1103 case AArch64::LDRSBXpre:
1104 case AArch64::LDRSHXpre:
1105 case AArch64::STRXpre:
1106 case AArch64::LDRSWpre:
1107 case AArch64::LDRXpre:
1108 case AArch64::LDRSBXpost:
1109 case AArch64::LDRSHXpost:
1110 case AArch64::STRXpost:
1111 case AArch64::LDRSWpost:
1112 case AArch64::LDRXpost:
1113 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1114 break;
1115 case AArch64::LDURQi:
1116 case AArch64::STURQi:
1117 case AArch64::LDRQpre:
1118 case AArch64::STRQpre:
1119 case AArch64::LDRQpost:
1120 case AArch64::STRQpost:
1121 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1122 break;
1123 case AArch64::LDURDi:
1124 case AArch64::STURDi:
1125 case AArch64::LDRDpre:
1126 case AArch64::STRDpre:
1127 case AArch64::LDRDpost:
1128 case AArch64::STRDpost:
1129 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1130 break;
1131 case AArch64::LDURSi:
1132 case AArch64::STURSi:
1133 case AArch64::LDRSpre:
1134 case AArch64::STRSpre:
1135 case AArch64::LDRSpost:
1136 case AArch64::STRSpost:
1137 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1138 break;
1139 case AArch64::LDURHi:
1140 case AArch64::STURHi:
1141 case AArch64::LDRHpre:
1142 case AArch64::STRHpre:
1143 case AArch64::LDRHpost:
1144 case AArch64::STRHpost:
1145 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1146 break;
1147 case AArch64::LDURBi:
1148 case AArch64::STURBi:
1149 case AArch64::LDRBpre:
1150 case AArch64::STRBpre:
1151 case AArch64::LDRBpost:
1152 case AArch64::STRBpost:
1153 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1154 break;
1155 }
1156
1157 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1158 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1159
1160 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1161 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1162 bool IsFP = fieldFromInstruction(insn, 26, 1);
1163
1164 // Cannot write back to a transfer register (but xzr != sp).
1165 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1166 return SoftFail;
1167
1168 return Success;
1169}
1170
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1171static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1172 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1173 const void *Decoder) {
1174 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1175 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1176 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1177 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1178
1179 unsigned Opcode = Inst.getOpcode();
1180 switch (Opcode) {
1181 default:
1182 return Fail;
1183 case AArch64::STLXRW:
1184 case AArch64::STLXRB:
1185 case AArch64::STLXRH:
1186 case AArch64::STXRW:
1187 case AArch64::STXRB:
1188 case AArch64::STXRH:
1189 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1190 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1191 case AArch64::LDARW:
1192 case AArch64::LDARB:
1193 case AArch64::LDARH:
1194 case AArch64::LDAXRW:
1195 case AArch64::LDAXRB:
1196 case AArch64::LDAXRH:
1197 case AArch64::LDXRW:
1198 case AArch64::LDXRB:
1199 case AArch64::LDXRH:
1200 case AArch64::STLRW:
1201 case AArch64::STLRB:
1202 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1203 case AArch64::STLLRW:
1204 case AArch64::STLLRB:
1205 case AArch64::STLLRH:
1206 case AArch64::LDLARW:
1207 case AArch64::LDLARB:
1208 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1209 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1210 break;
1211 case AArch64::STLXRX:
1212 case AArch64::STXRX:
1213 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1214 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1215 case AArch64::LDARX:
1216 case AArch64::LDAXRX:
1217 case AArch64::LDXRX:
1218 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1219 case AArch64::LDLARX:
1220 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1221 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1222 break;
1223 case AArch64::STLXPW:
1224 case AArch64::STXPW:
1225 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1226 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1227 case AArch64::LDAXPW:
1228 case AArch64::LDXPW:
1229 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1230 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1231 break;
1232 case AArch64::STLXPX:
1233 case AArch64::STXPX:
1234 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1235 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1236 case AArch64::LDAXPX:
1237 case AArch64::LDXPX:
1238 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1239 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1240 break;
1241 }
1242
1243 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1244
1245 // You shouldn't load to the same register twice in an instruction...
1246 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1247 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1248 Rt == Rt2)
1249 return SoftFail;
1250
1251 return Success;
1252}
1253
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1254static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1255 uint64_t Addr,
1256 const void *Decoder) {
1257 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1258 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1259 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1260 int64_t offset = fieldFromInstruction(insn, 15, 7);
1261 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1262
1263 // offset is a 7-bit signed immediate, so sign extend it to
1264 // fill the unsigned.
1265 if (offset & (1 << (7 - 1)))
1266 offset |= ~((1LL << 7) - 1);
1267
1268 unsigned Opcode = Inst.getOpcode();
1269 bool NeedsDisjointWritebackTransfer = false;
1270
1271 // First operand is always writeback of base register.
1272 switch (Opcode) {
1273 default:
1274 break;
1275 case AArch64::LDPXpost:
1276 case AArch64::STPXpost:
1277 case AArch64::LDPSWpost:
1278 case AArch64::LDPXpre:
1279 case AArch64::STPXpre:
1280 case AArch64::LDPSWpre:
1281 case AArch64::LDPWpost:
1282 case AArch64::STPWpost:
1283 case AArch64::LDPWpre:
1284 case AArch64::STPWpre:
1285 case AArch64::LDPQpost:
1286 case AArch64::STPQpost:
1287 case AArch64::LDPQpre:
1288 case AArch64::STPQpre:
1289 case AArch64::LDPDpost:
1290 case AArch64::STPDpost:
1291 case AArch64::LDPDpre:
1292 case AArch64::STPDpre:
1293 case AArch64::LDPSpost:
1294 case AArch64::STPSpost:
1295 case AArch64::LDPSpre:
1296 case AArch64::STPSpre:
1297 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1298 break;
1299 }
1300
1301 switch (Opcode) {
1302 default:
1303 return Fail;
1304 case AArch64::LDPXpost:
1305 case AArch64::STPXpost:
1306 case AArch64::LDPSWpost:
1307 case AArch64::LDPXpre:
1308 case AArch64::STPXpre:
1309 case AArch64::LDPSWpre:
1310 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1311 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1312 case AArch64::LDNPXi:
1313 case AArch64::STNPXi:
1314 case AArch64::LDPXi:
1315 case AArch64::STPXi:
1316 case AArch64::LDPSWi:
1317 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1318 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1319 break;
1320 case AArch64::LDPWpost:
1321 case AArch64::STPWpost:
1322 case AArch64::LDPWpre:
1323 case AArch64::STPWpre:
1324 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1325 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1326 case AArch64::LDNPWi:
1327 case AArch64::STNPWi:
1328 case AArch64::LDPWi:
1329 case AArch64::STPWi:
1330 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1331 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1332 break;
1333 case AArch64::LDNPQi:
1334 case AArch64::STNPQi:
1335 case AArch64::LDPQpost:
1336 case AArch64::STPQpost:
1337 case AArch64::LDPQi:
1338 case AArch64::STPQi:
1339 case AArch64::LDPQpre:
1340 case AArch64::STPQpre:
1341 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1342 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1343 break;
1344 case AArch64::LDNPDi:
1345 case AArch64::STNPDi:
1346 case AArch64::LDPDpost:
1347 case AArch64::STPDpost:
1348 case AArch64::LDPDi:
1349 case AArch64::STPDi:
1350 case AArch64::LDPDpre:
1351 case AArch64::STPDpre:
1352 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1353 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1354 break;
1355 case AArch64::LDNPSi:
1356 case AArch64::STNPSi:
1357 case AArch64::LDPSpost:
1358 case AArch64::STPSpost:
1359 case AArch64::LDPSi:
1360 case AArch64::STPSi:
1361 case AArch64::LDPSpre:
1362 case AArch64::STPSpre:
1363 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1364 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1365 break;
1366 }
1367
1368 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1369 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1370
1371 // You shouldn't load to the same register twice in an instruction...
1372 if (IsLoad && Rt == Rt2)
1373 return SoftFail;
1374
1375 // ... or do any operation that writes-back to a transfer register. But note
1376 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1377 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1378 return SoftFail;
1379
1380 return Success;
1381}
1382
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1383static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1384 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1385 const void *Decoder) {
1386 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1387 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1388 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1389 unsigned extend = fieldFromInstruction(insn, 10, 6);
1390
1391 unsigned shift = extend & 0x7;
1392 if (shift > 4)
1393 return Fail;
1394
1395 switch (Inst.getOpcode()) {
1396 default:
1397 return Fail;
1398 case AArch64::ADDWrx:
1399 case AArch64::SUBWrx:
1400 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1401 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1402 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1403 break;
1404 case AArch64::ADDSWrx:
1405 case AArch64::SUBSWrx:
1406 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1407 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1408 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1409 break;
1410 case AArch64::ADDXrx:
1411 case AArch64::SUBXrx:
1412 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1413 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1414 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1415 break;
1416 case AArch64::ADDSXrx:
1417 case AArch64::SUBSXrx:
1418 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1419 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1420 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1421 break;
1422 case AArch64::ADDXrx64:
1423 case AArch64::SUBXrx64:
1424 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1425 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1426 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1427 break;
1428 case AArch64::SUBSXrx64:
1429 case AArch64::ADDSXrx64:
1430 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1431 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1432 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1433 break;
1434 }
1435
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1436 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1437 return Success;
1438}
1439
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1440static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1441 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1442 const void *Decoder) {
1443 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1444 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1445 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1446 unsigned imm;
1447
1448 if (Datasize) {
1449 if (Inst.getOpcode() == AArch64::ANDSXri)
1450 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1451 else
1452 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1453 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1454 imm = fieldFromInstruction(insn, 10, 13);
1455 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1456 return Fail;
1457 } else {
1458 if (Inst.getOpcode() == AArch64::ANDSWri)
1459 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1460 else
1461 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1462 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1463 imm = fieldFromInstruction(insn, 10, 12);
1464 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1465 return Fail;
1466 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1467 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1468 return Success;
1469}
1470
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1471static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1472 uint64_t Addr,
1473 const void *Decoder) {
1474 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1475 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1476 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1477 imm |= fieldFromInstruction(insn, 5, 5);
1478
1479 if (Inst.getOpcode() == AArch64::MOVID)
1480 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1481 else
1482 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1483
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1484 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1485
1486 switch (Inst.getOpcode()) {
1487 default:
1488 break;
1489 case AArch64::MOVIv4i16:
1490 case AArch64::MOVIv8i16:
1491 case AArch64::MVNIv4i16:
1492 case AArch64::MVNIv8i16:
1493 case AArch64::MOVIv2i32:
1494 case AArch64::MOVIv4i32:
1495 case AArch64::MVNIv2i32:
1496 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1497 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1498 break;
1499 case AArch64::MOVIv2s_msl:
1500 case AArch64::MOVIv4s_msl:
1501 case AArch64::MVNIv2s_msl:
1502 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1503 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1504 break;
1505 }
1506
1507 return Success;
1508}
1509
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1510static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1511 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1512 const void *Decoder) {
1513 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1514 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1515 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1516 imm |= fieldFromInstruction(insn, 5, 5);
1517
1518 // Tied operands added twice.
1519 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1520 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1521
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1522 Inst.addOperand(MCOperand::createImm(imm));
1523 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1524
1525 return Success;
1526}
1527
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1528static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1529 uint64_t Addr, const void *Decoder) {
1530 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1531 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1532 imm |= fieldFromInstruction(insn, 29, 2);
1533 const AArch64Disassembler *Dis =
1534 static_cast<const AArch64Disassembler *>(Decoder);
1535
1536 // Sign-extend the 21-bit immediate.
1537 if (imm & (1 << (21 - 1)))
1538 imm |= ~((1LL << 21) - 1);
1539
1540 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1541 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1542 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1543
1544 return Success;
1545}
1546
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1547static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1548 uint64_t Addr, const void *Decoder) {
1549 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1550 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1551 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1552 unsigned S = fieldFromInstruction(insn, 29, 1);
1553 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1554
1555 unsigned ShifterVal = (Imm >> 12) & 3;
1556 unsigned ImmVal = Imm & 0xFFF;
1557 const AArch64Disassembler *Dis =
1558 static_cast<const AArch64Disassembler *>(Decoder);
1559
1560 if (ShifterVal != 0 && ShifterVal != 1)
1561 return Fail;
1562
1563 if (Datasize) {
1564 if (Rd == 31 && !S)
1565 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1566 else
1567 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1568 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1569 } else {
1570 if (Rd == 31 && !S)
1571 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1572 else
1573 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1574 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1575 }
1576
1577 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1578 Inst.addOperand(MCOperand::createImm(ImmVal));
1579 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1580 return Success;
1581}
1582
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1583static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1584 uint64_t Addr,
1585 const void *Decoder) {
1586 int64_t imm = fieldFromInstruction(insn, 0, 26);
1587 const AArch64Disassembler *Dis =
1588 static_cast<const AArch64Disassembler *>(Decoder);
1589
1590 // Sign-extend the 26-bit immediate.
1591 if (imm & (1 << (26 - 1)))
1592 imm |= ~((1LL << 26) - 1);
1593
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1594 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1595 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1596
1597 return Success;
1598}
1599
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1600static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1601 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1602 const void *Decoder) {
1603 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1604 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1605 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1606
1607 uint64_t pstate_field = (op1 << 3) | op2;
1608
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1609 if ((pstate_field == AArch64PState::PAN ||
1610 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1611 return Fail;
1612
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1613 Inst.addOperand(MCOperand::createImm(pstate_field));
1614 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1615
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1616 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1617 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1618 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1619 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1620 return Success;
1621 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1622}
1623
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1624static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1625 uint64_t Addr, const void *Decoder) {
1626 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1627 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1628 bit |= fieldFromInstruction(insn, 19, 5);
1629 int64_t dst = fieldFromInstruction(insn, 5, 14);
1630 const AArch64Disassembler *Dis =
1631 static_cast<const AArch64Disassembler *>(Decoder);
1632
1633 // Sign-extend 14-bit immediate.
1634 if (dst & (1 << (14 - 1)))
1635 dst |= ~((1LL << 14) - 1);
1636
1637 if (fieldFromInstruction(insn, 31, 1) == 0)
1638 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1639 else
1640 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1641 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1642 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1643 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1644
1645 return Success;
1646}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1647
1648static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1649 unsigned RegClassID,
1650 unsigned RegNo,
1651 uint64_t Addr,
1652 const void *Decoder) {
1653 // Register number must be even (see CASP instruction)
1654 if (RegNo & 0x1)
1655 return Fail;
1656
1657 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1658 Inst.addOperand(MCOperand::createReg(Register));
1659 return Success;
1660}
1661
1662static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1663 unsigned RegNo,
1664 uint64_t Addr,
1665 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1666 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1667 AArch64::WSeqPairsClassRegClassID,
1668 RegNo, Addr, Decoder);
1669}
1670
1671static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1672 unsigned RegNo,
1673 uint64_t Addr,
1674 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1675 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1676 AArch64::XSeqPairsClassRegClassID,
1677 RegNo, Addr, Decoder);
1678}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1679
Sander de Smalen81fcf862018-02-06 13:13:21 +0000[diff] [blame]1680static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1681 uint32_t insn,
1682 uint64_t Addr,
1683 const void *Decoder) {
1684 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1685 unsigned imm = fieldFromInstruction(insn, 5, 13);
1686 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1687 return Fail;
1688
1689 // The same (tied) operand is added twice to the instruction.
1690 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1691 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1692 Inst.addOperand(MCOperand::createImm(imm));
1693 return Success;
1694}
1695
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1696template<int Bits>
1697static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1698 uint64_t Address, const void *Decoder) {
1699 if (Imm & ~((1LL << Bits) - 1))
1700 return Fail;
1701
1702 // Imm is a signed immediate, so sign extend it.
1703 if (Imm & (1 << (Bits - 1)))
1704 Imm |= ~((1LL << Bits) - 1);
1705
1706 Inst.addOperand(MCOperand::createImm(Imm));
1707 return Success;
1708}
1709