Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 1 | //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==// |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | /// \file |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Matt Arsenault | 6b6a2c3 | 2016-03-11 08:00:27 +0000 | [diff] [blame] | 14 | #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H |
| 15 | #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 16 | |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 17 | #include "AMDGPUArgumentUsageInfo.h" |
David Blaikie | 3f833ed | 2017-11-08 01:01:31 +0000 | [diff] [blame] | 18 | #include "AMDGPUMachineFunction.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 19 | #include "SIRegisterInfo.h" |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/ArrayRef.h" |
| 21 | #include "llvm/ADT/DenseMap.h" |
| 22 | #include "llvm/ADT/Optional.h" |
| 23 | #include "llvm/ADT/SmallVector.h" |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/PseudoSourceValue.h" |
David Blaikie | 3f833ed | 2017-11-08 01:01:31 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/TargetInstrInfo.h" |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 26 | #include "llvm/MC/MCRegisterInfo.h" |
| 27 | #include "llvm/Support/ErrorHandling.h" |
NAKAMURA Takumi | 5cbd41e | 2016-06-27 10:26:43 +0000 | [diff] [blame] | 28 | #include <array> |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 29 | #include <cassert> |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 30 | #include <utility> |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 31 | #include <vector> |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 32 | |
| 33 | namespace llvm { |
| 34 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 35 | class MachineFrameInfo; |
| 36 | class MachineFunction; |
Matt Arsenault | 905f351 | 2017-12-29 17:18:14 +0000 | [diff] [blame] | 37 | class SIInstrInfo; |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 38 | class TargetRegisterClass; |
| 39 | |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 40 | class AMDGPUImagePseudoSourceValue : public PseudoSourceValue { |
| 41 | public: |
Matt Arsenault | 905f351 | 2017-12-29 17:18:14 +0000 | [diff] [blame] | 42 | // TODO: Is the img rsrc useful? |
Jan Sjodin | 312ccf7 | 2017-09-14 20:53:51 +0000 | [diff] [blame] | 43 | explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII) : |
Matt Arsenault | 905f351 | 2017-12-29 17:18:14 +0000 | [diff] [blame] | 44 | PseudoSourceValue(PseudoSourceValue::TargetCustom, TII) {} |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 45 | |
| 46 | bool isConstant(const MachineFrameInfo *) const override { |
| 47 | // This should probably be true for most images, but we will start by being |
| 48 | // conservative. |
| 49 | return false; |
| 50 | } |
| 51 | |
| 52 | bool isAliased(const MachineFrameInfo *) const override { |
Tim Renouf | 75ced9d | 2018-01-12 22:57:24 +0000 | [diff] [blame] | 53 | return true; |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 56 | bool mayAlias(const MachineFrameInfo *) const override { |
Tim Renouf | 75ced9d | 2018-01-12 22:57:24 +0000 | [diff] [blame] | 57 | return true; |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 58 | } |
| 59 | }; |
| 60 | |
Tom Stellard | 6f9ef14 | 2016-12-20 17:19:44 +0000 | [diff] [blame] | 61 | class AMDGPUBufferPseudoSourceValue : public PseudoSourceValue { |
| 62 | public: |
Jan Sjodin | 312ccf7 | 2017-09-14 20:53:51 +0000 | [diff] [blame] | 63 | explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII) : |
| 64 | PseudoSourceValue(PseudoSourceValue::TargetCustom, TII) { } |
Tom Stellard | 6f9ef14 | 2016-12-20 17:19:44 +0000 | [diff] [blame] | 65 | |
| 66 | bool isConstant(const MachineFrameInfo *) const override { |
| 67 | // This should probably be true for most images, but we will start by being |
| 68 | // conservative. |
| 69 | return false; |
| 70 | } |
| 71 | |
| 72 | bool isAliased(const MachineFrameInfo *) const override { |
Tim Renouf | 8234b48 | 2018-02-20 10:03:38 +0000 | [diff] [blame] | 73 | return true; |
Tom Stellard | 6f9ef14 | 2016-12-20 17:19:44 +0000 | [diff] [blame] | 74 | } |
| 75 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 76 | bool mayAlias(const MachineFrameInfo *) const override { |
Tim Renouf | 8234b48 | 2018-02-20 10:03:38 +0000 | [diff] [blame] | 77 | return true; |
Tom Stellard | 6f9ef14 | 2016-12-20 17:19:44 +0000 | [diff] [blame] | 78 | } |
| 79 | }; |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 80 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 81 | /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which |
| 82 | /// tells the hardware which interpolation parameters to load. |
Matt Arsenault | 6b6a2c3 | 2016-03-11 08:00:27 +0000 | [diff] [blame] | 83 | class SIMachineFunctionInfo final : public AMDGPUMachineFunction { |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 84 | unsigned TIDReg = AMDGPU::NoRegister; |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 85 | |
| 86 | // Registers that may be reserved for spilling purposes. These may be the same |
| 87 | // as the input registers. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 88 | unsigned ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG; |
| 89 | unsigned ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG; |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 90 | |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 91 | // This is the current function's incremented size from the kernel's scratch |
| 92 | // wave offset register. For an entry function, this is exactly the same as |
| 93 | // the ScratchWaveOffsetReg. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 94 | unsigned FrameOffsetReg = AMDGPU::FP_REG; |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 95 | |
| 96 | // Top of the stack SGPR offset derived from the ScratchWaveOffsetReg. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 97 | unsigned StackPtrOffsetReg = AMDGPU::SP_REG; |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 98 | |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 99 | AMDGPUFunctionArgInfo ArgInfo; |
Matt Arsenault | e15855d | 2017-07-17 22:35:50 +0000 | [diff] [blame] | 100 | |
Marek Olsak | fccabaf | 2016-01-13 11:45:36 +0000 | [diff] [blame] | 101 | // Graphics info. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 102 | unsigned PSInputAddr = 0; |
| 103 | unsigned PSInputEnable = 0; |
Matt Arsenault | e622dc3 | 2017-04-11 22:29:24 +0000 | [diff] [blame] | 104 | |
Matt Arsenault | 71bcbd4 | 2017-08-11 20:42:08 +0000 | [diff] [blame] | 105 | /// Number of bytes of arguments this function has on the stack. If the callee |
| 106 | /// is expected to restore the argument stack this should be a multiple of 16, |
| 107 | /// all usable during a tail call. |
| 108 | /// |
| 109 | /// The alternative would forbid tail call optimisation in some cases: if we |
| 110 | /// want to transfer control from a function with 8-bytes of stack-argument |
| 111 | /// space to a function with 16-bytes then misalignment of this value would |
| 112 | /// make a stack adjustment necessary, which could not be undone by the |
| 113 | /// callee. |
| 114 | unsigned BytesInStackArgArea = 0; |
| 115 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 116 | bool ReturnsVoid = true; |
Marek Olsak | fccabaf | 2016-01-13 11:45:36 +0000 | [diff] [blame] | 117 | |
Konstantin Zhuravlyov | 1d65026 | 2016-09-06 20:22:28 +0000 | [diff] [blame] | 118 | // A pair of default/requested minimum/maximum flat work group sizes. |
| 119 | // Minimum - first, maximum - second. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 120 | std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0}; |
Tom Stellard | 79a1fd7 | 2016-04-14 16:27:07 +0000 | [diff] [blame] | 121 | |
Konstantin Zhuravlyov | 1d65026 | 2016-09-06 20:22:28 +0000 | [diff] [blame] | 122 | // A pair of default/requested minimum/maximum number of waves per execution |
| 123 | // unit. Minimum - first, maximum - second. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 124 | std::pair<unsigned, unsigned> WavesPerEU = {0, 0}; |
Konstantin Zhuravlyov | 1d65026 | 2016-09-06 20:22:28 +0000 | [diff] [blame] | 125 | |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 126 | // Stack object indices for work group IDs. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 127 | std::array<int, 3> DebuggerWorkGroupIDStackObjectIndices = {{0, 0, 0}}; |
| 128 | |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 129 | // Stack object indices for work item IDs. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 130 | std::array<int, 3> DebuggerWorkItemIDStackObjectIndices = {{0, 0, 0}}; |
Konstantin Zhuravlyov | 71515e5 | 2016-04-26 17:24:40 +0000 | [diff] [blame] | 131 | |
Matt Arsenault | e19bc2e | 2017-12-29 17:18:21 +0000 | [diff] [blame] | 132 | DenseMap<const Value *, |
| 133 | std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs; |
Matt Arsenault | 905f351 | 2017-12-29 17:18:14 +0000 | [diff] [blame] | 134 | DenseMap<const Value *, |
| 135 | std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs; |
| 136 | |
Matt Arsenault | 161e2b4 | 2017-04-18 20:59:40 +0000 | [diff] [blame] | 137 | private: |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 138 | unsigned LDSWaveSpillSize = 0; |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 139 | unsigned NumUserSGPRs = 0; |
| 140 | unsigned NumSystemSGPRs = 0; |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 141 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 142 | bool HasSpilledSGPRs = false; |
| 143 | bool HasSpilledVGPRs = false; |
| 144 | bool HasNonSpillStackObjects = false; |
Tom Stellard | 9646890 | 2014-09-24 01:33:17 +0000 | [diff] [blame] | 145 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 146 | unsigned NumSpilledSGPRs = 0; |
| 147 | unsigned NumSpilledVGPRs = 0; |
Marek Olsak | 0532c19 | 2016-07-13 17:35:15 +0000 | [diff] [blame] | 148 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 149 | // Feature bits required for inputs passed in user SGPRs. |
| 150 | bool PrivateSegmentBuffer : 1; |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 151 | bool DispatchPtr : 1; |
| 152 | bool QueuePtr : 1; |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 153 | bool KernargSegmentPtr : 1; |
Matt Arsenault | 8d718dc | 2016-07-22 17:01:30 +0000 | [diff] [blame] | 154 | bool DispatchID : 1; |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 155 | bool FlatScratchInit : 1; |
| 156 | bool GridWorkgroupCountX : 1; |
| 157 | bool GridWorkgroupCountY : 1; |
| 158 | bool GridWorkgroupCountZ : 1; |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 159 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 160 | // Feature bits required for inputs passed in system SGPRs. |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 161 | bool WorkGroupIDX : 1; // Always initialized. |
| 162 | bool WorkGroupIDY : 1; |
| 163 | bool WorkGroupIDZ : 1; |
| 164 | bool WorkGroupInfo : 1; |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 165 | bool PrivateSegmentWaveByteOffset : 1; |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 166 | |
| 167 | bool WorkItemIDX : 1; // Always initialized. |
| 168 | bool WorkItemIDY : 1; |
| 169 | bool WorkItemIDZ : 1; |
| 170 | |
Tom Stellard | 2f3f985 | 2017-01-25 01:25:13 +0000 | [diff] [blame] | 171 | // Private memory buffer |
| 172 | // Compute directly in sgpr[0:1] |
| 173 | // Other shaders indirect 64-bits at sgpr[0:1] |
Matt Arsenault | 10fc062 | 2017-06-26 03:01:31 +0000 | [diff] [blame] | 174 | bool ImplicitBufferPtr : 1; |
Tom Stellard | 2f3f985 | 2017-01-25 01:25:13 +0000 | [diff] [blame] | 175 | |
Matt Arsenault | 9166ce8 | 2017-07-28 15:52:08 +0000 | [diff] [blame] | 176 | // Pointer to where the ABI inserts special kernel arguments separate from the |
| 177 | // user arguments. This is an offset from the KernargSegmentPtr. |
| 178 | bool ImplicitArgPtr : 1; |
| 179 | |
Tim Renouf | 1322915 | 2017-09-29 09:49:35 +0000 | [diff] [blame] | 180 | // The hard-wired high half of the address of the global information table |
| 181 | // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since |
| 182 | // current hardware only allows a 16 bit value. |
| 183 | unsigned GITPtrHigh; |
| 184 | |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 185 | unsigned HighBitsOf32BitAddress; |
| 186 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 187 | MCPhysReg getNextUserSGPR() const { |
| 188 | assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs"); |
| 189 | return AMDGPU::SGPR0 + NumUserSGPRs; |
| 190 | } |
| 191 | |
| 192 | MCPhysReg getNextSystemSGPR() const { |
| 193 | return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; |
| 194 | } |
| 195 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 196 | public: |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 197 | struct SpilledReg { |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 198 | unsigned VGPR = AMDGPU::NoRegister; |
| 199 | int Lane = -1; |
| 200 | |
| 201 | SpilledReg() = default; |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 202 | SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {} |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 203 | |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 204 | bool hasLane() { return Lane != -1;} |
Tom Stellard | 649b5db | 2016-03-04 18:31:18 +0000 | [diff] [blame] | 205 | bool hasReg() { return VGPR != AMDGPU::NoRegister;} |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 206 | }; |
| 207 | |
Matt Arsenault | 8e8f8f4 | 2017-08-02 01:52:45 +0000 | [diff] [blame] | 208 | struct SGPRSpillVGPRCSR { |
| 209 | // VGPR used for SGPR spills |
| 210 | unsigned VGPR; |
| 211 | |
| 212 | // If the VGPR is a CSR, the stack slot used to save/restore it in the |
| 213 | // prolog/epilog. |
| 214 | Optional<int> FI; |
| 215 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 216 | SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {} |
Matt Arsenault | 8e8f8f4 | 2017-08-02 01:52:45 +0000 | [diff] [blame] | 217 | }; |
| 218 | |
Matt Arsenault | e0bf7d0 | 2017-02-21 19:12:08 +0000 | [diff] [blame] | 219 | private: |
| 220 | // SGPR->VGPR spilling support. |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 221 | using SpillRegMask = std::pair<unsigned, unsigned>; |
Matt Arsenault | e0bf7d0 | 2017-02-21 19:12:08 +0000 | [diff] [blame] | 222 | |
| 223 | // Track VGPR + wave index for each subregister of the SGPR spilled to |
| 224 | // frameindex key. |
| 225 | DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills; |
| 226 | unsigned NumVGPRSpillLanes = 0; |
Matt Arsenault | 8e8f8f4 | 2017-08-02 01:52:45 +0000 | [diff] [blame] | 227 | SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs; |
Matt Arsenault | e0bf7d0 | 2017-02-21 19:12:08 +0000 | [diff] [blame] | 228 | |
| 229 | public: |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 230 | SIMachineFunctionInfo(const MachineFunction &MF); |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 231 | |
Matt Arsenault | e0bf7d0 | 2017-02-21 19:12:08 +0000 | [diff] [blame] | 232 | ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const { |
| 233 | auto I = SGPRToVGPRSpills.find(FrameIndex); |
| 234 | return (I == SGPRToVGPRSpills.end()) ? |
| 235 | ArrayRef<SpilledReg>() : makeArrayRef(I->second); |
| 236 | } |
| 237 | |
Matt Arsenault | 8e8f8f4 | 2017-08-02 01:52:45 +0000 | [diff] [blame] | 238 | ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const { |
| 239 | return SpillVGPRs; |
| 240 | } |
| 241 | |
Matt Arsenault | e0bf7d0 | 2017-02-21 19:12:08 +0000 | [diff] [blame] | 242 | bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI); |
| 243 | void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI); |
| 244 | |
Eugene Zelenko | 59e1282 | 2017-08-08 00:47:13 +0000 | [diff] [blame] | 245 | bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; } |
| 246 | unsigned getTIDReg() const { return TIDReg; } |
Tom Stellard | 9646890 | 2014-09-24 01:33:17 +0000 | [diff] [blame] | 247 | void setTIDReg(unsigned Reg) { TIDReg = Reg; } |
Matt Arsenault | 5b22dfa | 2015-11-05 05:27:10 +0000 | [diff] [blame] | 248 | |
Matt Arsenault | 71bcbd4 | 2017-08-11 20:42:08 +0000 | [diff] [blame] | 249 | unsigned getBytesInStackArgArea() const { |
| 250 | return BytesInStackArgArea; |
| 251 | } |
| 252 | |
| 253 | void setBytesInStackArgArea(unsigned Bytes) { |
| 254 | BytesInStackArgArea = Bytes; |
| 255 | } |
| 256 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 257 | // Add user SGPRs. |
| 258 | unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI); |
| 259 | unsigned addDispatchPtr(const SIRegisterInfo &TRI); |
| 260 | unsigned addQueuePtr(const SIRegisterInfo &TRI); |
| 261 | unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI); |
Matt Arsenault | 8d718dc | 2016-07-22 17:01:30 +0000 | [diff] [blame] | 262 | unsigned addDispatchID(const SIRegisterInfo &TRI); |
Matt Arsenault | 296b849 | 2016-02-12 06:31:30 +0000 | [diff] [blame] | 263 | unsigned addFlatScratchInit(const SIRegisterInfo &TRI); |
Matt Arsenault | 10fc062 | 2017-06-26 03:01:31 +0000 | [diff] [blame] | 264 | unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 265 | |
| 266 | // Add system SGPRs. |
| 267 | unsigned addWorkGroupIDX() { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 268 | ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR()); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 269 | NumSystemSGPRs += 1; |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 270 | return ArgInfo.WorkGroupIDX.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | unsigned addWorkGroupIDY() { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 274 | ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR()); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 275 | NumSystemSGPRs += 1; |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 276 | return ArgInfo.WorkGroupIDY.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | unsigned addWorkGroupIDZ() { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 280 | ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR()); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 281 | NumSystemSGPRs += 1; |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 282 | return ArgInfo.WorkGroupIDZ.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | unsigned addWorkGroupInfo() { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 286 | ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR()); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 287 | NumSystemSGPRs += 1; |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 288 | return ArgInfo.WorkGroupInfo.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 289 | } |
| 290 | |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 291 | // Add special VGPR inputs |
| 292 | void setWorkItemIDX(ArgDescriptor Arg) { |
| 293 | ArgInfo.WorkItemIDX = Arg; |
| 294 | } |
| 295 | |
| 296 | void setWorkItemIDY(ArgDescriptor Arg) { |
| 297 | ArgInfo.WorkItemIDY = Arg; |
| 298 | } |
| 299 | |
| 300 | void setWorkItemIDZ(ArgDescriptor Arg) { |
| 301 | ArgInfo.WorkItemIDZ = Arg; |
| 302 | } |
| 303 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 304 | unsigned addPrivateSegmentWaveByteOffset() { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 305 | ArgInfo.PrivateSegmentWaveByteOffset |
| 306 | = ArgDescriptor::createRegister(getNextSystemSGPR()); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 307 | NumSystemSGPRs += 1; |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 308 | return ArgInfo.PrivateSegmentWaveByteOffset.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 309 | } |
| 310 | |
Tom Stellard | f110f8f | 2016-04-14 16:27:03 +0000 | [diff] [blame] | 311 | void setPrivateSegmentWaveByteOffset(unsigned Reg) { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 312 | ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg); |
Tom Stellard | f110f8f | 2016-04-14 16:27:03 +0000 | [diff] [blame] | 313 | } |
| 314 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 315 | bool hasPrivateSegmentBuffer() const { |
| 316 | return PrivateSegmentBuffer; |
| 317 | } |
| 318 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 319 | bool hasDispatchPtr() const { |
| 320 | return DispatchPtr; |
| 321 | } |
| 322 | |
| 323 | bool hasQueuePtr() const { |
| 324 | return QueuePtr; |
| 325 | } |
| 326 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 327 | bool hasKernargSegmentPtr() const { |
| 328 | return KernargSegmentPtr; |
| 329 | } |
| 330 | |
Matt Arsenault | 8d718dc | 2016-07-22 17:01:30 +0000 | [diff] [blame] | 331 | bool hasDispatchID() const { |
| 332 | return DispatchID; |
| 333 | } |
| 334 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 335 | bool hasFlatScratchInit() const { |
| 336 | return FlatScratchInit; |
| 337 | } |
| 338 | |
| 339 | bool hasGridWorkgroupCountX() const { |
| 340 | return GridWorkgroupCountX; |
| 341 | } |
| 342 | |
| 343 | bool hasGridWorkgroupCountY() const { |
| 344 | return GridWorkgroupCountY; |
| 345 | } |
| 346 | |
| 347 | bool hasGridWorkgroupCountZ() const { |
| 348 | return GridWorkgroupCountZ; |
| 349 | } |
| 350 | |
| 351 | bool hasWorkGroupIDX() const { |
| 352 | return WorkGroupIDX; |
| 353 | } |
| 354 | |
| 355 | bool hasWorkGroupIDY() const { |
| 356 | return WorkGroupIDY; |
| 357 | } |
| 358 | |
| 359 | bool hasWorkGroupIDZ() const { |
| 360 | return WorkGroupIDZ; |
| 361 | } |
| 362 | |
| 363 | bool hasWorkGroupInfo() const { |
| 364 | return WorkGroupInfo; |
| 365 | } |
| 366 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 367 | bool hasPrivateSegmentWaveByteOffset() const { |
| 368 | return PrivateSegmentWaveByteOffset; |
| 369 | } |
| 370 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 371 | bool hasWorkItemIDX() const { |
| 372 | return WorkItemIDX; |
| 373 | } |
| 374 | |
| 375 | bool hasWorkItemIDY() const { |
| 376 | return WorkItemIDY; |
| 377 | } |
| 378 | |
| 379 | bool hasWorkItemIDZ() const { |
| 380 | return WorkItemIDZ; |
| 381 | } |
| 382 | |
Matt Arsenault | 9166ce8 | 2017-07-28 15:52:08 +0000 | [diff] [blame] | 383 | bool hasImplicitArgPtr() const { |
| 384 | return ImplicitArgPtr; |
| 385 | } |
| 386 | |
Matt Arsenault | 10fc062 | 2017-06-26 03:01:31 +0000 | [diff] [blame] | 387 | bool hasImplicitBufferPtr() const { |
| 388 | return ImplicitBufferPtr; |
Tom Stellard | 2f3f985 | 2017-01-25 01:25:13 +0000 | [diff] [blame] | 389 | } |
| 390 | |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 391 | AMDGPUFunctionArgInfo &getArgInfo() { |
| 392 | return ArgInfo; |
| 393 | } |
| 394 | |
| 395 | const AMDGPUFunctionArgInfo &getArgInfo() const { |
| 396 | return ArgInfo; |
| 397 | } |
| 398 | |
| 399 | std::pair<const ArgDescriptor *, const TargetRegisterClass *> |
| 400 | getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const { |
| 401 | return ArgInfo.getPreloadedValue(Value); |
| 402 | } |
| 403 | |
| 404 | unsigned getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const { |
| 405 | return ArgInfo.getPreloadedValue(Value).first->getRegister(); |
| 406 | } |
| 407 | |
Tim Renouf | 1322915 | 2017-09-29 09:49:35 +0000 | [diff] [blame] | 408 | unsigned getGITPtrHigh() const { |
| 409 | return GITPtrHigh; |
| 410 | } |
| 411 | |
Matt Arsenault | 923712b | 2018-02-09 16:57:57 +0000 | [diff] [blame] | 412 | unsigned get32BitAddressHighBits() const { |
| 413 | return HighBitsOf32BitAddress; |
| 414 | } |
| 415 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 416 | unsigned getNumUserSGPRs() const { |
| 417 | return NumUserSGPRs; |
| 418 | } |
| 419 | |
| 420 | unsigned getNumPreloadedSGPRs() const { |
| 421 | return NumUserSGPRs + NumSystemSGPRs; |
| 422 | } |
| 423 | |
| 424 | unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 425 | return ArgInfo.PrivateSegmentWaveByteOffset.getRegister(); |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 426 | } |
| 427 | |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 428 | /// \brief Returns the physical register reserved for use as the resource |
| 429 | /// descriptor for scratch accesses. |
| 430 | unsigned getScratchRSrcReg() const { |
| 431 | return ScratchRSrcReg; |
| 432 | } |
| 433 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 434 | void setScratchRSrcReg(unsigned Reg) { |
| 435 | assert(Reg != AMDGPU::NoRegister && "Should never be unset"); |
| 436 | ScratchRSrcReg = Reg; |
| 437 | } |
| 438 | |
| 439 | unsigned getScratchWaveOffsetReg() const { |
| 440 | return ScratchWaveOffsetReg; |
| 441 | } |
| 442 | |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 443 | unsigned getFrameOffsetReg() const { |
| 444 | return FrameOffsetReg; |
| 445 | } |
| 446 | |
| 447 | void setStackPtrOffsetReg(unsigned Reg) { |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 448 | StackPtrOffsetReg = Reg; |
| 449 | } |
| 450 | |
Matt Arsenault | 1cc47f8 | 2017-07-18 16:44:56 +0000 | [diff] [blame] | 451 | // Note the unset value for this is AMDGPU::SP_REG rather than |
| 452 | // NoRegister. This is mostly a workaround for MIR tests where state that |
| 453 | // can't be directly computed from the function is not preserved in serialized |
| 454 | // MIR. |
Matt Arsenault | 1c0ae39 | 2017-04-24 18:05:16 +0000 | [diff] [blame] | 455 | unsigned getStackPtrOffsetReg() const { |
| 456 | return StackPtrOffsetReg; |
| 457 | } |
| 458 | |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 459 | void setScratchWaveOffsetReg(unsigned Reg) { |
| 460 | assert(Reg != AMDGPU::NoRegister && "Should never be unset"); |
| 461 | ScratchWaveOffsetReg = Reg; |
Matt Arsenault | 2b1f9aa | 2017-05-17 21:56:25 +0000 | [diff] [blame] | 462 | if (isEntryFunction()) |
| 463 | FrameOffsetReg = ScratchWaveOffsetReg; |
Matt Arsenault | 26f8f3d | 2015-11-30 21:16:03 +0000 | [diff] [blame] | 464 | } |
Matt Arsenault | 49affb8 | 2015-11-25 20:55:12 +0000 | [diff] [blame] | 465 | |
Matt Arsenault | 99c1452 | 2016-04-25 19:27:24 +0000 | [diff] [blame] | 466 | unsigned getQueuePtrUserSGPR() const { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 467 | return ArgInfo.QueuePtr.getRegister(); |
Matt Arsenault | 99c1452 | 2016-04-25 19:27:24 +0000 | [diff] [blame] | 468 | } |
| 469 | |
Matt Arsenault | 10fc062 | 2017-06-26 03:01:31 +0000 | [diff] [blame] | 470 | unsigned getImplicitBufferPtrUserSGPR() const { |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 471 | return ArgInfo.ImplicitBufferPtr.getRegister(); |
Tom Stellard | 2f3f985 | 2017-01-25 01:25:13 +0000 | [diff] [blame] | 472 | } |
| 473 | |
Matt Arsenault | 5b22dfa | 2015-11-05 05:27:10 +0000 | [diff] [blame] | 474 | bool hasSpilledSGPRs() const { |
| 475 | return HasSpilledSGPRs; |
| 476 | } |
| 477 | |
| 478 | void setHasSpilledSGPRs(bool Spill = true) { |
| 479 | HasSpilledSGPRs = Spill; |
| 480 | } |
| 481 | |
| 482 | bool hasSpilledVGPRs() const { |
| 483 | return HasSpilledVGPRs; |
| 484 | } |
| 485 | |
| 486 | void setHasSpilledVGPRs(bool Spill = true) { |
| 487 | HasSpilledVGPRs = Spill; |
| 488 | } |
Tom Stellard | 9646890 | 2014-09-24 01:33:17 +0000 | [diff] [blame] | 489 | |
Matt Arsenault | 296b849 | 2016-02-12 06:31:30 +0000 | [diff] [blame] | 490 | bool hasNonSpillStackObjects() const { |
| 491 | return HasNonSpillStackObjects; |
| 492 | } |
| 493 | |
| 494 | void setHasNonSpillStackObjects(bool StackObject = true) { |
| 495 | HasNonSpillStackObjects = StackObject; |
| 496 | } |
| 497 | |
Marek Olsak | 0532c19 | 2016-07-13 17:35:15 +0000 | [diff] [blame] | 498 | unsigned getNumSpilledSGPRs() const { |
| 499 | return NumSpilledSGPRs; |
| 500 | } |
| 501 | |
| 502 | unsigned getNumSpilledVGPRs() const { |
| 503 | return NumSpilledVGPRs; |
| 504 | } |
| 505 | |
| 506 | void addToSpilledSGPRs(unsigned num) { |
| 507 | NumSpilledSGPRs += num; |
| 508 | } |
| 509 | |
| 510 | void addToSpilledVGPRs(unsigned num) { |
| 511 | NumSpilledVGPRs += num; |
| 512 | } |
| 513 | |
Marek Olsak | fccabaf | 2016-01-13 11:45:36 +0000 | [diff] [blame] | 514 | unsigned getPSInputAddr() const { |
| 515 | return PSInputAddr; |
| 516 | } |
| 517 | |
Matt Arsenault | e622dc3 | 2017-04-11 22:29:24 +0000 | [diff] [blame] | 518 | unsigned getPSInputEnable() const { |
| 519 | return PSInputEnable; |
| 520 | } |
| 521 | |
Marek Olsak | fccabaf | 2016-01-13 11:45:36 +0000 | [diff] [blame] | 522 | bool isPSInputAllocated(unsigned Index) const { |
| 523 | return PSInputAddr & (1 << Index); |
| 524 | } |
| 525 | |
| 526 | void markPSInputAllocated(unsigned Index) { |
| 527 | PSInputAddr |= 1 << Index; |
| 528 | } |
| 529 | |
Matt Arsenault | e622dc3 | 2017-04-11 22:29:24 +0000 | [diff] [blame] | 530 | void markPSInputEnabled(unsigned Index) { |
| 531 | PSInputEnable |= 1 << Index; |
| 532 | } |
| 533 | |
Marek Olsak | 8e9cc63 | 2016-01-13 17:23:09 +0000 | [diff] [blame] | 534 | bool returnsVoid() const { |
| 535 | return ReturnsVoid; |
| 536 | } |
| 537 | |
| 538 | void setIfReturnsVoid(bool Value) { |
| 539 | ReturnsVoid = Value; |
| 540 | } |
| 541 | |
Konstantin Zhuravlyov | 1d65026 | 2016-09-06 20:22:28 +0000 | [diff] [blame] | 542 | /// \returns A pair of default/requested minimum/maximum flat work group sizes |
| 543 | /// for this function. |
| 544 | std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const { |
| 545 | return FlatWorkGroupSizes; |
| 546 | } |
| 547 | |
| 548 | /// \returns Default/requested minimum flat work group size for this function. |
| 549 | unsigned getMinFlatWorkGroupSize() const { |
| 550 | return FlatWorkGroupSizes.first; |
| 551 | } |
| 552 | |
| 553 | /// \returns Default/requested maximum flat work group size for this function. |
| 554 | unsigned getMaxFlatWorkGroupSize() const { |
| 555 | return FlatWorkGroupSizes.second; |
| 556 | } |
| 557 | |
| 558 | /// \returns A pair of default/requested minimum/maximum number of waves per |
| 559 | /// execution unit. |
| 560 | std::pair<unsigned, unsigned> getWavesPerEU() const { |
| 561 | return WavesPerEU; |
| 562 | } |
| 563 | |
| 564 | /// \returns Default/requested minimum number of waves per execution unit. |
| 565 | unsigned getMinWavesPerEU() const { |
| 566 | return WavesPerEU.first; |
| 567 | } |
| 568 | |
| 569 | /// \returns Default/requested maximum number of waves per execution unit. |
| 570 | unsigned getMaxWavesPerEU() const { |
| 571 | return WavesPerEU.second; |
Konstantin Zhuravlyov | 71515e5 | 2016-04-26 17:24:40 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 574 | /// \returns Stack object index for \p Dim's work group ID. |
| 575 | int getDebuggerWorkGroupIDStackObjectIndex(unsigned Dim) const { |
| 576 | assert(Dim < 3); |
| 577 | return DebuggerWorkGroupIDStackObjectIndices[Dim]; |
| 578 | } |
| 579 | |
| 580 | /// \brief Sets stack object index for \p Dim's work group ID to \p ObjectIdx. |
| 581 | void setDebuggerWorkGroupIDStackObjectIndex(unsigned Dim, int ObjectIdx) { |
| 582 | assert(Dim < 3); |
| 583 | DebuggerWorkGroupIDStackObjectIndices[Dim] = ObjectIdx; |
| 584 | } |
| 585 | |
| 586 | /// \returns Stack object index for \p Dim's work item ID. |
| 587 | int getDebuggerWorkItemIDStackObjectIndex(unsigned Dim) const { |
| 588 | assert(Dim < 3); |
| 589 | return DebuggerWorkItemIDStackObjectIndices[Dim]; |
| 590 | } |
| 591 | |
| 592 | /// \brief Sets stack object index for \p Dim's work item ID to \p ObjectIdx. |
| 593 | void setDebuggerWorkItemIDStackObjectIndex(unsigned Dim, int ObjectIdx) { |
| 594 | assert(Dim < 3); |
| 595 | DebuggerWorkItemIDStackObjectIndices[Dim] = ObjectIdx; |
| 596 | } |
| 597 | |
| 598 | /// \returns SGPR used for \p Dim's work group ID. |
| 599 | unsigned getWorkGroupIDSGPR(unsigned Dim) const { |
| 600 | switch (Dim) { |
| 601 | case 0: |
| 602 | assert(hasWorkGroupIDX()); |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 603 | return ArgInfo.WorkGroupIDX.getRegister(); |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 604 | case 1: |
| 605 | assert(hasWorkGroupIDY()); |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 606 | return ArgInfo.WorkGroupIDY.getRegister(); |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 607 | case 2: |
| 608 | assert(hasWorkGroupIDZ()); |
Matt Arsenault | 8623e8d | 2017-08-03 23:00:29 +0000 | [diff] [blame] | 609 | return ArgInfo.WorkGroupIDZ.getRegister(); |
Konstantin Zhuravlyov | f2f3d14 | 2016-06-25 03:11:28 +0000 | [diff] [blame] | 610 | } |
| 611 | llvm_unreachable("unexpected dimension"); |
| 612 | } |
| 613 | |
| 614 | /// \returns VGPR used for \p Dim' work item ID. |
| 615 | unsigned getWorkItemIDVGPR(unsigned Dim) const { |
| 616 | switch (Dim) { |
| 617 | case 0: |
| 618 | assert(hasWorkItemIDX()); |
| 619 | return AMDGPU::VGPR0; |
| 620 | case 1: |
| 621 | assert(hasWorkItemIDY()); |
| 622 | return AMDGPU::VGPR1; |
| 623 | case 2: |
| 624 | assert(hasWorkItemIDZ()); |
| 625 | return AMDGPU::VGPR2; |
| 626 | } |
| 627 | llvm_unreachable("unexpected dimension"); |
| 628 | } |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 629 | |
Matt Arsenault | 161e2b4 | 2017-04-18 20:59:40 +0000 | [diff] [blame] | 630 | unsigned getLDSWaveSpillSize() const { |
| 631 | return LDSWaveSpillSize; |
| 632 | } |
| 633 | |
Matt Arsenault | e19bc2e | 2017-12-29 17:18:21 +0000 | [diff] [blame] | 634 | const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII, |
| 635 | const Value *BufferRsrc) { |
| 636 | assert(BufferRsrc); |
| 637 | auto PSV = BufferPSVs.try_emplace( |
| 638 | BufferRsrc, |
| 639 | llvm::make_unique<AMDGPUBufferPseudoSourceValue>(TII)); |
| 640 | return PSV.first->second.get(); |
Tom Stellard | 6f9ef14 | 2016-12-20 17:19:44 +0000 | [diff] [blame] | 641 | } |
| 642 | |
Matt Arsenault | 905f351 | 2017-12-29 17:18:14 +0000 | [diff] [blame] | 643 | const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII, |
| 644 | const Value *ImgRsrc) { |
| 645 | assert(ImgRsrc); |
| 646 | auto PSV = ImagePSVs.try_emplace( |
| 647 | ImgRsrc, |
| 648 | llvm::make_unique<AMDGPUImagePseudoSourceValue>(TII)); |
| 649 | return PSV.first->second.get(); |
Tom Stellard | 244891d | 2016-12-20 15:52:17 +0000 | [diff] [blame] | 650 | } |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 651 | }; |
| 652 | |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 653 | } // end namespace llvm |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 654 | |
Eugene Zelenko | 6620376 | 2017-01-21 00:53:49 +0000 | [diff] [blame] | 655 | #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H |