Blame - llvm/lib/Target/X86/X86SchedSkylakeClient.td - toolchain/llvm-project

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//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//

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//

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// The LLVM Compiler Infrastructure

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//

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// This file is distributed under the University of Illinois Open Source

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// License. See LICENSE.TXT for details.

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//

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//===----------------------------------------------------------------------===//

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//

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// This file defines the machine model for Skylake Client to support

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// instruction scheduling and other instruction cost heuristics.

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//

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//===----------------------------------------------------------------------===//

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def SkylakeClientModel : SchedMachineModel {

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// All x86 instructions are modeled as a single micro-op, and SKylake can

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// decode 6 instructions per cycle.

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let IssueWidth = 6;

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let MicroOpBufferSize = 224; // Based on the reorder buffer.

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let LoadLatency = 5;

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let MispredictPenalty = 14;

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// Based on the LSD (loop-stream detector) queue size and benchmarking data.

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let LoopMicroOpBufferSize = 50;

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// This flag is set to allow the scheduler to assign a default model to

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// unrecognized opcodes.

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let CompleteModel = 0;

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}

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let SchedModel = SkylakeClientModel in {

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// Skylake Client can issue micro-ops to 8 different ports in one cycle.

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// Ports 0, 1, 5, and 6 handle all computation.

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// Port 4 gets the data half of stores. Store data can be available later than

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// the store address, but since we don't model the latency of stores, we can

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// ignore that.

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// Ports 2 and 3 are identical. They handle loads and the address half of

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// stores. Port 7 can handle address calculations.

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def SKLPort0 : ProcResource<1>;

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def SKLPort1 : ProcResource<1>;

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def SKLPort2 : ProcResource<1>;

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def SKLPort3 : ProcResource<1>;

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def SKLPort4 : ProcResource<1>;

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def SKLPort5 : ProcResource<1>;

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def SKLPort6 : ProcResource<1>;

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def SKLPort7 : ProcResource<1>;

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// Many micro-ops are capable of issuing on multiple ports.

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def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>;

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def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>;

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def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;

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def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>;

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def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>;

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def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>;

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def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>;

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def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>;

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def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>;

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def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;

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def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;

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def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;

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// 60 Entry Unified Scheduler

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def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,

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SKLPort5, SKLPort6, SKLPort7]> {

let BufferSize=60;

}

// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5

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// cycles after the memory operand.

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def : ReadAdvance<ReadAfterLd, 5>;

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// Many SchedWrites are defined in pairs with and without a folded load.

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// Instructions with folded loads are usually micro-fused, so they only appear

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// as two micro-ops when queued in the reservation station.

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// This multiclass defines the resource usage for variants with and without

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// folded loads.

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multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,

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list<ProcResourceKind> ExePorts,

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int Lat, list<int> Res = [1], int UOps = 1> {

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// Register variant is using a single cycle on ExePort.

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def : WriteRes<SchedRW, ExePorts> {

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let Latency = Lat;

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let ResourceCycles = Res;

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let NumMicroOps = UOps;

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}

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// Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the

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// latency.

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def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {

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let Latency = !add(Lat, 5);

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let ResourceCycles = !listconcat([1], Res);

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let NumMicroOps = UOps;

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}

}

// A folded store needs a cycle on port 4 for the store data, but it does not

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// need an extra port 2/3 cycle to recompute the address.

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def : WriteRes<WriteRMW, [SKLPort4]>;

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// Arithmetic.

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defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.

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defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.

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def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.

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def SKLDivider : ProcResource<1>; // Integer division issued on port 0.

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def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.

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let Latency = 25;

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let ResourceCycles = [1, 10];

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}

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def : WriteRes<WriteIDivLd, [SKLPort23, SKLPort0, SKLDivider]> {

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let Latency = 29;

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let ResourceCycles = [1, 1, 10];

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}

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def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.

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// Integer shifts and rotates.

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defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>;

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// Loads, stores, and moves, not folded with other operations.

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def : WriteRes<WriteLoad, [SKLPort23]> { let Latency = 5; }

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def : WriteRes<WriteStore, [SKLPort237, SKLPort4]>;

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def : WriteRes<WriteMove, [SKLPort0156]>;

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// Idioms that clear a register, like xorps %xmm0, %xmm0.

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// These can often bypass execution ports completely.

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def : WriteRes<WriteZero, []>;

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// Branches don't produce values, so they have no latency, but they still

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// consume resources. Indirect branches can fold loads.

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defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>;

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// Floating point. This covers both scalar and vector operations.

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def : WriteRes<WriteFLoad, [SKLPort23]> { let Latency = 6; }

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def : WriteRes<WriteFStore, [SKLPort237, SKLPort4]>;

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def : WriteRes<WriteFMove, [SKLPort015]>;

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defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub/compare.

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defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.

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defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division.

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defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root.

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defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.

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defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.

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defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.

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defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1>; // Floating point vector shuffles.

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defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1>; // Floating point vector blends.

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defm : SKLWriteResPair<WriteFVarBlend, [SKLPort5], 2, [2]>; // Fp vector variable blends.

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// FMA Scheduling helper class.

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// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }

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// Vector integer operations.

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def : WriteRes<WriteVecLoad, [SKLPort23]> { let Latency = 6; }

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def : WriteRes<WriteVecStore, [SKLPort237, SKLPort4]>;

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def : WriteRes<WriteVecMove, [SKLPort015]>;

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defm : SKLWriteResPair<WriteVecALU, [SKLPort15], 1>; // Vector integer ALU op, no logicals.

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defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1>; // Vector integer shifts.

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defm : SKLWriteResPair<WriteVecIMul, [SKLPort0], 5>; // Vector integer multiply.

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defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1>; // Vector shuffles.

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defm : SKLWriteResPair<WriteBlend, [SKLPort15], 1>; // Vector blends.

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defm : SKLWriteResPair<WriteVarBlend, [SKLPort5], 2, [2]>; // Vector variable blends.

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defm : SKLWriteResPair<WriteMPSAD, [SKLPort0, SKLPort5], 6, [1, 2]>; // Vector MPSAD.

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// Vector bitwise operations.

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// These are often used on both floating point and integer vectors.

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defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1>; // Vector and/or/xor.

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// Conversion between integer and float.

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defm : SKLWriteResPair<WriteCvtF2I, [SKLPort1], 3>; // Float -> Integer.

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defm : SKLWriteResPair<WriteCvtI2F, [SKLPort1], 4>; // Integer -> Float.

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defm : SKLWriteResPair<WriteCvtF2F, [SKLPort1], 3>; // Float -> Float size conversion.

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// Strings instructions.

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// Packed Compare Implicit Length Strings, Return Mask

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// String instructions.

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def : WriteRes<WritePCmpIStrM, [SKLPort0]> {

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let Latency = 10;

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let ResourceCycles = [3];

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}

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def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {

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let Latency = 10;

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let ResourceCycles = [3, 1];

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}

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// Packed Compare Explicit Length Strings, Return Mask

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def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort16, SKLPort5]> {

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let Latency = 10;

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let ResourceCycles = [3, 2, 4];

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}

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def : WriteRes<WritePCmpEStrMLd, [SKLPort05, SKLPort16, SKLPort23]> {

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let Latency = 10;

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let ResourceCycles = [6, 2, 1];

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}

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// Packed Compare Implicit Length Strings, Return Index

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def : WriteRes<WritePCmpIStrI, [SKLPort0]> {

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let Latency = 11;

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let ResourceCycles = [3];

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}

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def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {

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let Latency = 11;

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let ResourceCycles = [3, 1];

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}

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// Packed Compare Explicit Length Strings, Return Index

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def : WriteRes<WritePCmpEStrI, [SKLPort05, SKLPort16]> {

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let Latency = 11;

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let ResourceCycles = [6, 2];

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}

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def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> {

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let Latency = 11;

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let ResourceCycles = [3, 2, 2, 1];

}

// AES instructions.

def : WriteRes<WriteAESDecEnc, [SKLPort5]> { // Decryption, encryption.

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let Latency = 7;

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let ResourceCycles = [1];

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}

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def : WriteRes<WriteAESDecEncLd, [SKLPort5, SKLPort23]> {

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let Latency = 7;

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let ResourceCycles = [1, 1];

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}

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def : WriteRes<WriteAESIMC, [SKLPort5]> { // InvMixColumn.

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let Latency = 14;

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let ResourceCycles = [2];

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}

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def : WriteRes<WriteAESIMCLd, [SKLPort5, SKLPort23]> {

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let Latency = 14;

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let ResourceCycles = [2, 1];

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}

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def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5]> { // Key Generation.

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let Latency = 10;

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let ResourceCycles = [2, 8];

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}

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def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23]> {

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let Latency = 10;

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let ResourceCycles = [2, 7, 1];

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}

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// Carry-less multiplication instructions.

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def : WriteRes<WriteCLMul, [SKLPort0, SKLPort5]> {

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let Latency = 7;

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let ResourceCycles = [2, 1];

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}

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def : WriteRes<WriteCLMulLd, [SKLPort0, SKLPort5, SKLPort23]> {

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let Latency = 7;

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let ResourceCycles = [2, 1, 1];

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}

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// Catch-all for expensive system instructions.

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def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;

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// AVX2.

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defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3>; // Fp 256-bit width vector shuffles.

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defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3>; // 256-bit width vector shuffles.

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defm : SKLWriteResPair<WriteVarVecShift, [SKLPort0, SKLPort5], 2, [2, 1]>; // Variable vector shifts.

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// Old microcoded instructions that nobody use.

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def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;

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// Fence instructions.

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def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;

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// Nop, not very useful expect it provides a model for nops!

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def : WriteRes<WriteNop, []>;

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////////////////////////////////////////////////////////////////////////////////

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// Horizontal add/sub instructions.

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////////////////////////////////////////////////////////////////////////////////

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defm : SKLWriteResPair<WriteFHAdd, [SKLPort1], 3>;

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defm : SKLWriteResPair<WritePHAdd, [SKLPort15], 1>;

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// Remaining instrs.

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def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {

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let Latency = 1;

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let NumMicroOps = 1;

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let ResourceCycles = [1];

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}

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def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDSBirr",

"MMX_PADDSWirr",

"MMX_PADDUSBirr",

"MMX_PADDUSWirr",

"MMX_PAVGBirr",

"MMX_PAVGWirr",

"MMX_PCMPEQBirr",

"MMX_PCMPEQDirr",

"MMX_PCMPEQWirr",

"MMX_PCMPGTBirr",

"MMX_PCMPGTDirr",

"MMX_PCMPGTWirr",

"MMX_PMAXSWirr",

"MMX_PMAXUBirr",

"MMX_PMINSWirr",

"MMX_PMINUBirr",

"MMX_PSLLDri",

"MMX_PSLLDrr",

"MMX_PSLLQri",

"MMX_PSLLQrr",

"MMX_PSLLWri",

"MMX_PSLLWrr",

"MMX_PSRADri",

"MMX_PSRADrr",

"MMX_PSRAWri",

"MMX_PSRAWrr",

"MMX_PSRLDri",

"MMX_PSRLDrr",

"MMX_PSRLQri",

"MMX_PSRLQrr",

"MMX_PSRLWri",

"MMX_PSRLWrr",

"MMX_PSUBSBirr",

"MMX_PSUBSWirr",

"MMX_PSUBUSBirr",

"MMX_PSUBUSWirr")>;

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def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {

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let Latency = 1;

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let NumMicroOps = 1;

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let ResourceCycles = [1];

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}

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def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",

"COM_FST0r",

"INSERTPSrr",

"MMX_MOVD64rr",

"MMX_MOVD64to64rr",

"MMX_PALIGNRrri",

"MMX_PSHUFBrr",

"MMX_PSHUFWri",

"MMX_PUNPCKHBWirr",

"MMX_PUNPCKHDQirr",

"MMX_PUNPCKHWDirr",

"MMX_PUNPCKLBWirr",

"MMX_PUNPCKLDQirr",

"MMX_PUNPCKLWDirr",

"MOV64toPQIrr",

"MOVDDUPrr",

"MOVDI2PDIrr",

"MOVHLPSrr",

"MOVLHPSrr",

"MOVSDrr",

"MOVSHDUPrr",

"MOVSLDUPrr",

"MOVUPDrr",

"MOVUPSrr",

"PACKSSDWrr",

"PACKSSWBrr",

"PACKUSDWrr",

"PACKUSWBrr",

"PALIGNRrri",

"PBLENDWrri",

"PMOVSXBDrr",

"PMOVSXBQrr",

"PMOVSXBWrr",

"PMOVSXDQrr",

"PMOVSXWDrr",

"PMOVSXWQrr",

"PMOVZXBDrr",

"PMOVZXBQrr",

"PMOVZXBWrr",

"PMOVZXDQrr",

"PMOVZXWDrr",

"PMOVZXWQrr",

"PSHUFBrr",

"PSHUFDri",

"PSHUFHWri",

"PSHUFLWri",

"PSLLDQri",

"PSRLDQri",

"PUNPCKHBWrr",

"PUNPCKHDQrr",

"PUNPCKHQDQrr",

"PUNPCKHWDrr",

"PUNPCKLBWrr",

"PUNPCKLDQrr",

"PUNPCKLQDQrr",

"PUNPCKLWDrr",

"SHUFPDrri",

"SHUFPSrri",

"UCOM_FPr",

"UCOM_Fr",

"UNPCKHPDrr",

"UNPCKHPSrr",

"UNPCKLPDrr",

"UNPCKLPSrr",

"VBROADCASTSSrr",

"VINSERTPSrr",

"VMOV64toPQIrr",

"VMOVDDUPYrr",

"VMOVDDUPrr",

"VMOVDI2PDIrr",

"VMOVHLPSrr",

"VMOVLHPSrr",

"VMOVSDrr",

"VMOVSHDUPYrr",

"VMOVSHDUPrr",

"VMOVSLDUPYrr",

"VMOVSLDUPrr",

"VMOVUPDYrr",

"VMOVUPDrr",

"VMOVUPSYrr",

"VMOVUPSrr",

"VPACKSSDWYrr",

"VPACKSSDWrr",

"VPACKSSWBYrr",

"VPACKSSWBrr",

"VPACKUSDWYrr",

"VPACKUSDWrr",

"VPACKUSWBYrr",

"VPACKUSWBrr",

"VPALIGNRYrri",

"VPALIGNRrri",

"VPBLENDWYrri",

"VPBLENDWrri",

"VPBROADCASTDrr",

"VPBROADCASTQrr",

"VPERMILPDYri",

"VPERMILPDYrr",

"VPERMILPDri",

"VPERMILPDrr",

"VPERMILPSYri",

"VPERMILPSYrr",

"VPERMILPSri",

"VPERMILPSrr",

"VPMOVSXBDrr",

"VPMOVSXBQrr",

"VPMOVSXBWrr",

"VPMOVSXDQrr",

"VPMOVSXWDrr",

"VPMOVSXWQrr",

"VPMOVZXBDrr",

"VPMOVZXBQrr",

"VPMOVZXBWrr",

"VPMOVZXDQrr",

"VPMOVZXWDrr",

"VPMOVZXWQrr",

"VPSHUFBYrr",

"VPSHUFBrr",

"VPSHUFDYri",

"VPSHUFDri",

"VPSHUFHWYri",

"VPSHUFHWri",

"VPSHUFLWYri",

"VPSHUFLWri",

"VPSLLDQYri",

"VPSLLDQri",

"VPSRLDQYri",

"VPSRLDQri",

"VPUNPCKHBWYrr",

"VPUNPCKHBWrr",

"VPUNPCKHDQYrr",

"VPUNPCKHDQrr",

"VPUNPCKHQDQYrr",

"VPUNPCKHQDQrr",

"VPUNPCKHWDYrr",

"VPUNPCKHWDrr",

"VPUNPCKLBWYrr",

"VPUNPCKLBWrr",

"VPUNPCKLDQYrr",

"VPUNPCKLDQrr",

"VPUNPCKLQDQYrr",

"VPUNPCKLQDQrr",

"VPUNPCKLWDYrr",

"VPUNPCKLWDrr",

"VSHUFPDYrri",

"VSHUFPDrri",

"VSHUFPSYrri",

"VSHUFPSrri",

"VUNPCKHPDYrr",

"VUNPCKHPDrr",

"VUNPCKHPSYrr",

"VUNPCKHPSrr",

"VUNPCKLPDYrr",

"VUNPCKLPDrr",

"VUNPCKLPSYrr",

"VUNPCKLPSrr")>;

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def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {

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let Latency = 1;

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let NumMicroOps = 1;

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let ResourceCycles = [1];

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}

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def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;

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486

def SKLWriteResGroup5 : SchedWriteRes<[SKLPort01]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

487

let Latency = 1;

488

let NumMicroOps = 1;

489

let ResourceCycles = [1];

490

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

491

def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr",

"PABSDrr",

"PABSWrr",

"PADDSBrr",

"PADDSWrr",

"PADDUSBrr",

"PADDUSWrr",

"PAVGBrr",

"PAVGWrr",

"PCMPEQBrr",

"PCMPEQDrr",

"PCMPEQQrr",

"PCMPEQWrr",

"PCMPGTBrr",

"PCMPGTDrr",

"PCMPGTWrr",

"PMAXSBrr",

"PMAXSDrr",

"PMAXSWrr",

"PMAXUBrr",

"PMAXUDrr",

"PMAXUWrr",

"PMINSBrr",

"PMINSDrr",

"PMINSWrr",

"PMINUBrr",

"PMINUDrr",

"PMINUWrr",

"PSIGNBrr",

"PSIGNDrr",

"PSIGNWrr",

"PSLLDri",

"PSLLQri",

"PSLLWri",

"PSRADri",

"PSRAWri",

"PSRLDri",

"PSRLQri",

"PSRLWri",

"PSUBSBrr",

"PSUBSWrr",

"PSUBUSBrr",

"PSUBUSWrr",

"VPABSBYrr",

"VPABSBrr",

"VPABSDYrr",

"VPABSDrr",

"VPABSWYrr",

"VPABSWrr",

"VPADDSBYrr",

"VPADDSBrr",

"VPADDSWYrr",

"VPADDSWrr",

"VPADDUSBYrr",

"VPADDUSBrr",

"VPADDUSWYrr",

"VPADDUSWrr",

"VPAVGBYrr",

"VPAVGBrr",

"VPAVGWYrr",

"VPAVGWrr",

"VPCMPEQBYrr",

"VPCMPEQBrr",

"VPCMPEQDYrr",

"VPCMPEQDrr",

"VPCMPEQQYrr",

"VPCMPEQQrr",

"VPCMPEQWYrr",

"VPCMPEQWrr",

"VPCMPGTBYrr",

"VPCMPGTBrr",

"VPCMPGTDYrr",

"VPCMPGTDrr",

"VPCMPGTWYrr",

"VPCMPGTWrr",

"VPMAXSBYrr",

"VPMAXSBrr",

"VPMAXSDYrr",

"VPMAXSDrr",

"VPMAXSWYrr",

"VPMAXSWrr",

"VPMAXUBYrr",

"VPMAXUBrr",

"VPMAXUDYrr",

"VPMAXUDrr",

"VPMAXUWYrr",

"VPMAXUWrr",

"VPMINSBYrr",

"VPMINSBrr",

"VPMINSDYrr",

"VPMINSDrr",

"VPMINSWYrr",

"VPMINSWrr",

"VPMINUBYrr",

"VPMINUBrr",

"VPMINUDYrr",

"VPMINUDrr",

"VPMINUWYrr",

"VPMINUWrr",

"VPSIGNBYrr",

"VPSIGNBrr",

"VPSIGNDYrr",

"VPSIGNDrr",

"VPSIGNWYrr",

"VPSIGNWrr",

"VPSLLDYri",

"VPSLLDri",

"VPSLLQYri",

"VPSLLQri",

"VPSLLVDYrr",

"VPSLLVDrr",

"VPSLLVQYrr",

"VPSLLVQrr",

"VPSLLWYri",

"VPSLLWri",

"VPSRADYri",

"VPSRADri",

"VPSRAVDYrr",

"VPSRAVDrr",

"VPSRAWYri",

"VPSRAWri",

"VPSRLDYri",

"VPSRLDri",

"VPSRLQYri",

"VPSRLQri",

"VPSRLVDYrr",

"VPSRLVDrr",

"VPSRLVQYrr",

"VPSRLVQrr",

"VPSRLWYri",

"VPSRLWri",

"VPSUBSBYrr",

"VPSUBSBrr",

"VPSUBSWYrr",

"VPSUBSWrr",

"VPSUBUSBYrr",

"VPSUBUSBrr",

"VPSUBUSWYrr",

"VPSUBUSWrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

630

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

631

def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

632

let Latency = 1;

633

let NumMicroOps = 1;

634

let ResourceCycles = [1];

635

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

636

def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP",

"FNOP",

"MMX_MOVQ64rr",

"MMX_PABSBrr",

"MMX_PABSDrr",

"MMX_PABSWrr",

"MMX_PADDBirr",

"MMX_PADDDirr",

"MMX_PADDQirr",

"MMX_PADDWirr",

"MMX_PANDNirr",

"MMX_PANDirr",

"MMX_PORirr",

"MMX_PSIGNBrr",

"MMX_PSIGNDrr",

"MMX_PSIGNWrr",

"MMX_PSUBBirr",

"MMX_PSUBDirr",

"MMX_PSUBQirr",

"MMX_PSUBWirr",

"MMX_PXORirr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

657

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

658

def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

659

let Latency = 1;

660

let NumMicroOps = 1;

661

let ResourceCycles = [1];

662

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

663

def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",

"ADC(16|32|64)i",

"ADC(8|16|32|64)rr",

"ADCX(32|64)rr",

"ADOX(32|64)rr",

"BT(16|32|64)ri8",

"BT(16|32|64)rr",

"BTC(16|32|64)ri8",

"BTC(16|32|64)rr",

"BTR(16|32|64)ri8",

"BTR(16|32|64)rr",

"BTS(16|32|64)ri8",

"BTS(16|32|64)rr",

"CDQ",

"CLAC",

"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",

679

"CQO",

680

"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",

681

"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",

"JMP_1",

"JMP_4",

"RORX(32|64)ri",

"SAR(8|16|32|64)r1",

"SAR(8|16|32|64)ri",

"SARX(32|64)rr",

"SBB(16|32|64)ri",

"SBB(16|32|64)i",

"SBB(8|16|32|64)rr",

"SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",

"SHL(8|16|32|64)r1",

"SHL(8|16|32|64)ri",

"SHLX(32|64)rr",

"SHR(8|16|32|64)r1",

"SHR(8|16|32|64)ri",

"SHRX(32|64)rr",

"STAC")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

699

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

700

def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {

701

let Latency = 1;

702

let NumMicroOps = 1;

703

let ResourceCycles = [1];

704

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

705

def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",

"BLSI(32|64)rr",

"BLSMSK(32|64)rr",

"BLSR(32|64)rr",

"BZHI(32|64)rr",

"LEA(16|32|64)(_32)?r")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

711

712

def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {

713

let Latency = 1;

714

let NumMicroOps = 1;

715

let ResourceCycles = [1];

716

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

717

def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr",

"ANDNPSrr",

"ANDPDrr",

"ANDPSrr",

"BLENDPDrri",

"BLENDPSrri",

"MOVAPDrr",

"MOVAPSrr",

"MOVDQArr",

"MOVDQUrr",

"MOVPQI2QIrr",

"MOVSSrr",

"ORPDrr",

"ORPSrr",

"PADDBrr",

"PADDDrr",

"PADDQrr",

"PADDWrr",

"PANDNrr",

"PANDrr",

"PORrr",

"PSUBBrr",

"PSUBDrr",

"PSUBQrr",

"PSUBWrr",

"PXORrr",

"VANDNPDYrr",

"VANDNPDrr",

"VANDNPSYrr",

"VANDNPSrr",

"VANDPDYrr",

"VANDPDrr",

"VANDPSYrr",

"VANDPSrr",

"VBLENDPDYrri",

"VBLENDPDrri",

"VBLENDPSYrri",

"VBLENDPSrri",

"VMOVAPDYrr",

"VMOVAPDrr",

"VMOVAPSYrr",

"VMOVAPSrr",

"VMOVDQAYrr",

"VMOVDQArr",

"VMOVDQUYrr",

"VMOVDQUrr",

"VMOVPQI2QIrr",

"VMOVSSrr",

"VMOVZPQILo2PQIrr",

"VORPDYrr",

"VORPDrr",

"VORPSYrr",

"VORPSrr",

"VPADDBYrr",

"VPADDBrr",

"VPADDDYrr",

"VPADDDrr",

"VPADDQYrr",

"VPADDQrr",

"VPADDWYrr",

"VPADDWrr",

"VPANDNYrr",

"VPANDNrr",

"VPANDYrr",

"VPANDrr",

"VPBLENDDYrri",

"VPBLENDDrri",

"VPORYrr",

"VPORrr",

"VPSUBBYrr",

"VPSUBBrr",

"VPSUBDYrr",

"VPSUBDrr",

"VPSUBQYrr",

"VPSUBQrr",

"VPSUBWYrr",

"VPSUBWrr",

"VPXORYrr",

"VPXORrr",

"VXORPDYrr",

"VXORPDrr",

"VXORPSYrr",

"VXORPSrr",

"XORPDrr",

"XORPSrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

802

803

def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {

804

let Latency = 1;

805

let NumMicroOps = 1;

806

let ResourceCycles = [1];

807

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

808

def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

809

def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",

"ADD(8|16|32|64)rr",

"ADD(8|16|32|64)i",

"AND(8|16|32|64)ri",

"AND(8|16|32|64)rr",

"AND(8|16|32|64)i",

"CBW",

"CLC",

"CMC",

"CMP(8|16|32|64)ri",

"CMP(8|16|32|64)rr",

"CMP(8|16|32|64)i",

"DEC(8|16|32|64)r",

"INC(8|16|32|64)r",

"LAHF",

"MOV(8|16|32|64)rr",

"MOV(8|16|32|64)ri",

"MOVSX(16|32|64)rr16",

827

"MOVSX(16|32|64)rr32",

828

"MOVSX(16|32|64)rr8",

829

"MOVZX(16|32|64)rr16",

830

"MOVZX(16|32|64)rr8",

"NEG(8|16|32|64)r",

"NOOP",

"NOT(8|16|32|64)r",

"OR(8|16|32|64)ri",

"OR(8|16|32|64)rr",

"OR(8|16|32|64)i",

"SAHF",

"SGDT64m",

"SIDT64m",

"SLDT64m",

"SMSW16m",

"STC",

"STRm",

"SUB(8|16|32|64)ri",

"SUB(8|16|32|64)rr",

"SUB(8|16|32|64)i",

"SYSCALL",

"TEST(8|16|32|64)rr",

849

"TEST(8|16|32|64)i",

850

"TEST(8|16|32|64)ri",

"XCHG(16|32|64)rr",

"XOR(8|16|32|64)ri",

"XOR(8|16|32|64)rr",

"XOR(8|16|32|64)i")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

855

856

def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

857

let Latency = 1;

858

let NumMicroOps = 2;

859

let ResourceCycles = [1,1];

860

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

861

def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",

862

"MMX_MOVD64from64rm",

"MMX_MOVD64mr",

"MMX_MOVNTQmr",

"MMX_MOVQ64mr",

"MOV(8|16|32|64)mr",

"MOV8mi",

"MOVAPDmr",

"MOVAPSmr",

"MOVDQAmr",

"MOVDQUmr",

"MOVHPDmr",

"MOVHPSmr",

"MOVLPDmr",

"MOVLPSmr",

"MOVNTDQmr",

"MOVNTI_64mr",

"MOVNTImr",

"MOVNTPDmr",

"MOVNTPSmr",

"MOVPDI2DImr",

"MOVPQI2QImr",

"MOVPQIto64mr",

"MOVSDmr",

"MOVSSmr",

"MOVUPDmr",

"MOVUPSmr",

"ST_FP32m",

"ST_FP64m",

"ST_FP80m",

"VEXTRACTF128mr",

"VEXTRACTI128mr",

"VMOVAPDYmr",

"VMOVAPDmr",

"VMOVAPSYmr",

"VMOVAPSmr",

"VMOVDQAYmr",

"VMOVDQAmr",

"VMOVDQUYmr",

"VMOVDQUmr",

"VMOVHPDmr",

"VMOVHPSmr",

"VMOVLPDmr",

"VMOVLPSmr",

"VMOVNTDQYmr",

"VMOVNTDQmr",

"VMOVNTPDYmr",

"VMOVNTPDmr",

"VMOVNTPSYmr",

"VMOVNTPSmr",

"VMOVPDI2DImr",

"VMOVPQI2QImr",

"VMOVPQIto64mr",

"VMOVSDmr",

"VMOVSSmr",

"VMOVUPDYmr",

"VMOVUPDmr",

"VMOVUPSYmr",

"VMOVUPSmr",

"VMPTRSTm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

921

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

922

def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

923

let Latency = 2;

924

let NumMicroOps = 1;

925

let ResourceCycles = [1];

926

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

927

def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr",

928

"COMISSrr",

929

"MMX_MOVD64from64rr",

"MMX_MOVD64grr",

"MMX_PMOVMSKBrr",

"MOVMSKPDrr",

"MOVMSKPSrr",

"MOVPDI2DIrr",

"MOVPQIto64rr",

"PMOVMSKBrr",

"UCOMISDrr",

"UCOMISSrr",

"VCOMISDrr",

"VCOMISSrr",

"VMOVMSKPDYrr",

"VMOVMSKPDrr",

"VMOVMSKPSYrr",

"VMOVMSKPSrr",

"VMOVPDI2DIrr",

"VMOVPQIto64rr",

"VPMOVMSKBYrr",

"VPMOVMSKBrr",

"VTESTPDYrr",

"VTESTPDrr",

"VTESTPSYrr",

"VTESTPSrr",

"VUCOMISDrr",

"VUCOMISSrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

955

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

956

def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

957

let Latency = 2;

958

let NumMicroOps = 2;

959

let ResourceCycles = [2];

960

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

961

def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr",

"MMX_PINSRWrr",

"PINSRBrr",

"PINSRDrr",

"PINSRQrr",

"PINSRWrr",

"VPINSRBrr",

"VPINSRDrr",

"VPINSRQrr",

"VPINSRWrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

971

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

972

def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

973

let Latency = 2;

974

let NumMicroOps = 2;

975

let ResourceCycles = [2];

976

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

977

def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP",

978

"MMX_MOVDQ2Qrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

979

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

980

def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

981

let Latency = 2;

982

let NumMicroOps = 2;

983

let ResourceCycles = [2];

984

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

985

def: InstRW<[SKLWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr",

"ROL(8|16|32|64)r1",

"ROL(8|16|32|64)ri",

"ROR(8|16|32|64)r1",

"ROR(8|16|32|64)ri",

"SET(A|BE)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

991

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

992

def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

993

let Latency = 2;

994

let NumMicroOps = 2;

995

let ResourceCycles = [2];

996

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

997

def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0",

"BLENDVPSrr0",

"PBLENDVBrr0",

"VBLENDVPDYrr",

"VBLENDVPDrr",

"VBLENDVPSYrr",

"VBLENDVPSrr",

"VPBLENDVBYrr",

"VPBLENDVBrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1006

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1007

def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1008

let Latency = 2;

1009

let NumMicroOps = 2;

1010

let ResourceCycles = [2];

1011

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1012

def: InstRW<[SKLWriteResGroup17], (instregex "LFENCE",

1013

"WAIT",

1014

"XGETBV")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1015

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1016

def SKLWriteResGroup18 : SchedWriteRes<[SKLPort0,SKLPort237]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1017

let Latency = 2;

1018

let NumMicroOps = 2;

1019

let ResourceCycles = [1,1];

1020

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1021

def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr",

"VMASKMOVPDmr",

"VMASKMOVPSYmr",

"VMASKMOVPSmr",

"VPMASKMOVDYmr",

"VPMASKMOVDmr",

"VPMASKMOVQYmr",

"VPMASKMOVQmr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1029

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1030

def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,SKLPort01]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1031

let Latency = 2;

1032

let NumMicroOps = 2;

1033

let ResourceCycles = [1,1];

1034

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1035

def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr",

"PSLLQrr",

"PSLLWrr",

"PSRADrr",

"PSRAWrr",

"PSRLDrr",

"PSRLQrr",

"PSRLWrr",

"VPSLLDrr",

"VPSLLQrr",

"VPSLLWrr",

"VPSRADrr",

"VPSRAWrr",

"VPSRLDrr",

"VPSRLQrr",

"VPSRLWrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1051

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1052

def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1053

let Latency = 2;

1054

let NumMicroOps = 2;

1055

let ResourceCycles = [1,1];

1056

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1057

def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1058

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1059

def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1060

let Latency = 2;

1061

let NumMicroOps = 2;

1062

let ResourceCycles = [1,1];

1063

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1064

def: InstRW<[SKLWriteResGroup21], (instregex "SFENCE")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1065

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1066

def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1067

let Latency = 2;

1068

let NumMicroOps = 2;

1069

let ResourceCycles = [1,1];

1070

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1071

def: InstRW<[SKLWriteResGroup22], (instregex "BEXTR(32|64)rr",

1072

"BSWAP(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1073

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1074

def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1075

let Latency = 2;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1076

let NumMicroOps = 2;

1077

let ResourceCycles = [1,1];

1078

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

1079

def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;

Craig Topper

b4c7873

2018-03-19 19:00:32 +0000

[diff] [blame]

1080

def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1081

def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",

1082

"ADC8ri",

1083

"SBB8i8",

1084

"SBB8ri")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1085

1086

def SKLWriteResGroup24 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {

1087

let Latency = 2;

1088

let NumMicroOps = 3;

1089

let ResourceCycles = [1,1,1];

1090

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1091

def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr",

"PEXTRBmr",

"PEXTRDmr",

"PEXTRQmr",

"PEXTRWmr",

"STMXCSR",

"VEXTRACTPSmr",

"VPEXTRBmr",

"VPEXTRDmr",

"VPEXTRQmr",

"VPEXTRWmr",

"VSTMXCSR")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1103

1104

def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {

1105

let Latency = 2;

1106

let NumMicroOps = 3;

1107

let ResourceCycles = [1,1,1];

1108

}

1109

def: InstRW<[SKLWriteResGroup25], (instregex "FNSTCW16m")>;

1110

1111

def SKLWriteResGroup26 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {

1112

let Latency = 2;

1113

let NumMicroOps = 3;

1114

let ResourceCycles = [1,1,1];

1115

}

Craig Topper

f4cd908

2018-01-19 05:47:32 +0000

[diff] [blame]

1116

def: InstRW<[SKLWriteResGroup26], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1117

1118

def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {

1119

let Latency = 2;

1120

let NumMicroOps = 3;

1121

let ResourceCycles = [1,1,1];

1122

}

1123

def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;

1124

1125

def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {

1126

let Latency = 2;

1127

let NumMicroOps = 3;

1128

let ResourceCycles = [1,1,1];

1129

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

1130

def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1131

def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",

"PUSH64i8",

"STOSB",

"STOSL",

"STOSQ",

"STOSW")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1137

1138

def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {

1139

let Latency = 3;

1140

let NumMicroOps = 1;

1141

let ResourceCycles = [1];

1142

}

Clement Courbet

327fac4

2018-03-07 08:14:02 +0000

[diff] [blame]

1143

def: InstRW<[SKLWriteResGroup29], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1144

def: InstRW<[SKLWriteResGroup29], (instrs IMUL8r, MUL8r)>;

1145

def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr",

"BSR(16|32|64)rr",

"LZCNT(16|32|64)rr",

"PDEP(32|64)rr",

"PEXT(32|64)rr",

"POPCNT(16|32|64)rr",

1151

"SHLD(16|32|64)rri8",

1152

"SHRD(16|32|64)rri8",

1153

"TZCNT(16|32|64)rr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1154

Clement Courbet

327fac4

2018-03-07 08:14:02 +0000

[diff] [blame]

1155

def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1156

let Latency = 3;

1157

let NumMicroOps = 2;

1158

let ResourceCycles = [1,1];

1159

}

Clement Courbet

327fac4

2018-03-07 08:14:02 +0000

[diff] [blame]

1160

def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1161

1162

def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {

1163

let Latency = 3;

1164

let NumMicroOps = 1;

1165

let ResourceCycles = [1];

1166

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1167

def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",

"ADD_FST0r",

"ADD_FrST0",

"MMX_PSADBWirr",

"PCMPGTQrr",

"PSADBWrr",

"SUBR_FPrST0",

"SUBR_FST0r",

"SUBR_FrST0",

"SUB_FPrST0",

"SUB_FST0r",

"SUB_FrST0",

"VBROADCASTSDYrr",

"VBROADCASTSSYrr",

"VEXTRACTF128rr",

"VEXTRACTI128rr",

"VINSERTF128rr",

"VINSERTI128rr",

"VPBROADCASTBYrr",

"VPBROADCASTBrr",

"VPBROADCASTDYrr",

"VPBROADCASTQYrr",

"VPBROADCASTWYrr",

"VPBROADCASTWrr",

"VPCMPGTQYrr",

"VPCMPGTQrr",

"VPERM2F128rr",

"VPERM2I128rr",

"VPERMDYrr",

"VPERMPDYri",

"VPERMPSYrr",

"VPERMQYri",

"VPMOVSXBDYrr",

"VPMOVSXBQYrr",

"VPMOVSXBWYrr",

"VPMOVSXDQYrr",

"VPMOVSXWDYrr",

"VPMOVSXWQYrr",

"VPMOVZXBDYrr",

"VPMOVZXBQYrr",

"VPMOVZXBWYrr",

"VPMOVZXDQYrr",

"VPMOVZXWDYrr",

"VPMOVZXWQYrr",

"VPSADBWYrr",

"VPSADBWrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1213

1214

def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {

1215

let Latency = 3;

1216

let NumMicroOps = 2;

1217

let ResourceCycles = [1,1];

1218

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1219

def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr",

"MMX_PEXTRWrr",

"PEXTRBrr",

"PEXTRDrr",

"PEXTRQrr",

"PEXTRWrr",

"PTESTrr",

"VEXTRACTPSrr",

"VPEXTRBrr",

"VPEXTRDrr",

"VPEXTRQrr",

"VPEXTRWrr",

"VPTESTYrr",

"VPTESTrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1233

1234

def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {

1235

let Latency = 3;

1236

let NumMicroOps = 2;

1237

let ResourceCycles = [1,1];

1238

}

1239

def: InstRW<[SKLWriteResGroup32], (instregex "FNSTSW16r")>;

1240

1241

def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {

1242

let Latency = 3;

1243

let NumMicroOps = 3;

1244

let ResourceCycles = [3];

1245

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1246

def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",

1247

"ROR(8|16|32|64)rCL",

1248

"SAR(8|16|32|64)rCL",

1249

"SHL(8|16|32|64)rCL",

1250

"SHR(8|16|32|64)rCL")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1251

1252

def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {

1253

let Latency = 3;

1254

let NumMicroOps = 3;

1255

let ResourceCycles = [3];

1256

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1257

def: InstRW<[SKLWriteResGroup34], (instregex "XADD(8|16|32|64)rr",

1258

"XCHG8rr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1259

1260

def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {

1261

let Latency = 3;

1262

let NumMicroOps = 3;

1263

let ResourceCycles = [1,2];

1264

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1265

def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr",

1266

"MMX_PHSUBSWrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1267

1268

def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {

1269

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1270

let NumMicroOps = 3;

1271

let ResourceCycles = [2,1];

1272

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1273

def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr",

"PHSUBSWrr",

"VPHADDSWrr",

"VPHADDSWYrr",

"VPHSUBSWrr",

"VPHSUBSWYrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1279

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1280

def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {

1281

let Latency = 3;

1282

let NumMicroOps = 3;

1283

let ResourceCycles = [2,1];

1284

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1285

def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr",

1286

"MMX_PHADDWrr",

1287

"MMX_PHSUBDrr",

1288

"MMX_PHSUBWrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1289

1290

def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {

1291

let Latency = 3;

1292

let NumMicroOps = 3;

1293

let ResourceCycles = [2,1];

1294

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1295

def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr",

"PHADDWrr",

"PHSUBDrr",

"PHSUBWrr",

"VPHADDDYrr",

"VPHADDDrr",

"VPHADDWYrr",

"VPHADDWrr",

"VPHSUBDYrr",

"VPHSUBDrr",

"VPHSUBWYrr",

"VPHSUBWrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1307

1308

def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {

1309

let Latency = 3;

1310

let NumMicroOps = 3;

1311

let ResourceCycles = [2,1];

1312

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1313

def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",

1314

"MMX_PACKSSWBirr",

1315

"MMX_PACKUSWBirr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1316

1317

def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {

1318

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1319

let NumMicroOps = 3;

1320

let ResourceCycles = [1,2];

1321

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1322

def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1323

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1324

def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {

1325

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1326

let NumMicroOps = 3;

1327

let ResourceCycles = [1,2];

1328

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1329

def: InstRW<[SKLWriteResGroup41], (instregex "MFENCE")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1330

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1331

def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {

1332

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1333

let NumMicroOps = 3;

1334

let ResourceCycles = [1,2];

1335

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1336

def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",

1337

"RCL(8|16|32|64)ri",

1338

"RCR(8|16|32|64)r1",

1339

"RCR(8|16|32|64)ri")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1340

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1341

def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {

1342

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1343

let NumMicroOps = 3;

1344

let ResourceCycles = [1,1,1];

1345

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1346

def: InstRW<[SKLWriteResGroup43], (instregex "FNSTSWm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1347

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1348

def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {

1349

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1350

let NumMicroOps = 4;

1351

let ResourceCycles = [1,1,2];

1352

}

Craig Topper

f4cd908

2018-01-19 05:47:32 +0000

[diff] [blame]

1353

def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1354

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1355

def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {

1356

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1357

let NumMicroOps = 4;

1358

let ResourceCycles = [1,1,1,1];

1359

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1360

def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1361

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1362

def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {

1363

let Latency = 3;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1364

let NumMicroOps = 4;

1365

let ResourceCycles = [1,1,1,1];

1366

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1367

def: InstRW<[SKLWriteResGroup46], (instregex "CALL64pcrel32")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1368

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1369

def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1370

let Latency = 4;

1371

let NumMicroOps = 1;

1372

let ResourceCycles = [1];

1373

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1374

def: InstRW<[SKLWriteResGroup47], (instregex "AESDECLASTrr",

"AESDECrr",

"AESENCLASTrr",

"AESENCrr",

"MMX_PMADDUBSWrr",

"MMX_PMADDWDirr",

"MMX_PMULHRSWrr",

"MMX_PMULHUWirr",

"MMX_PMULHWirr",

"MMX_PMULLWirr",

"MMX_PMULUDQirr",

"MUL_FPrST0",

"MUL_FST0r",

"MUL_FrST0",

"RCPPSr",

"RCPSSr",

"RSQRTPSr",

"RSQRTSSr",

"VAESDECLASTrr",

"VAESDECrr",

"VAESENCLASTrr",

"VAESENCrr",

"VRCPPSYr",

"VRCPPSr",

"VRCPSSr",

"VRSQRTPSYr",

"VRSQRTPSr",

"VRSQRTSSr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1402

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1403

def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1404

let Latency = 4;

1405

let NumMicroOps = 1;

1406

let ResourceCycles = [1];

1407

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1408

def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr",

"ADDPSrr",

"ADDSDrr",

"ADDSSrr",

"ADDSUBPDrr",

"ADDSUBPSrr",

"MULPDrr",

"MULPSrr",

"MULSDrr",

"MULSSrr",

"SUBPDrr",

"SUBPSrr",

"SUBSDrr",

"SUBSSrr",

"VADDPDYrr",

"VADDPDrr",

"VADDPSYrr",

"VADDPSrr",

"VADDSDrr",

"VADDSSrr",

"VADDSUBPDYrr",

"VADDSUBPDrr",

"VADDSUBPSYrr",

"VADDSUBPSrr",

"VMULPDYrr",

"VMULPDrr",

"VMULPSYrr",

"VMULPSrr",

"VMULSDrr",

"VMULSSrr",

"VSUBPDYrr",

"VSUBPDrr",

"VSUBPSYrr",

"VSUBPSrr",

"VSUBSDrr",

"VSUBSSrr")>;

Craig Topper

2017-12-13 23:11:30 +0000

[diff] [blame]

1444

def: InstRW<[SKLWriteResGroup48],

1445

(instregex

1446

"VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",

1447

"VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1448

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1449

def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1450

let Latency = 4;

1451

let NumMicroOps = 1;

1452

let ResourceCycles = [1];

1453

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1454

def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",

"CMPPSrri",

"CMPSDrr",

"CMPSSrr",

"CVTDQ2PSrr",

"CVTPS2DQrr",

"CVTTPS2DQrr",

"MAX(C?)PDrr",

"MAX(C?)PSrr",

"MAX(C?)SDrr",

"MAX(C?)SSrr",

"MIN(C?)PDrr",

"MIN(C?)PSrr",

"MIN(C?)SDrr",

"MIN(C?)SSrr",

"PHMINPOSUWrr",

"PMADDUBSWrr",

"PMADDWDrr",

"PMULDQrr",

"PMULHRSWrr",

"PMULHUWrr",

"PMULHWrr",

"PMULLWrr",

"PMULUDQrr",

"VCMPPDYrri",

"VCMPPDrri",

"VCMPPSYrri",

"VCMPPSrri",

"VCMPSDrr",

"VCMPSSrr",

"VCVTDQ2PSYrr",

"VCVTDQ2PSrr",

"VCVTPS2DQYrr",

"VCVTPS2DQrr",

"VCVTTPS2DQYrr",

"VCVTTPS2DQrr",

"VMAX(C?)PDYrr",

"VMAX(C?)PDrr",

"VMAX(C?)PSYrr",

"VMAX(C?)PSrr",

"VMAX(C?)SDrr",

"VMAX(C?)SSrr",

"VMIN(C?)PDYrr",

"VMIN(C?)PDrr",

"VMIN(C?)PSYrr",

"VMIN(C?)PSrr",

"VMIN(C?)SDrr",

"VMIN(C?)SSrr",

"VPHMINPOSUWrr",

"VPMADDUBSWYrr",

"VPMADDUBSWrr",

"VPMADDWDYrr",

"VPMADDWDrr",

"VPMULDQYrr",

"VPMULDQrr",

"VPMULHRSWYrr",

"VPMULHRSWrr",

"VPMULHUWYrr",

"VPMULHUWrr",

"VPMULHWYrr",

"VPMULHWrr",

"VPMULLWYrr",

"VPMULLWrr",

"VPMULUDQYrr",

"VPMULUDQrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1519

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1520

def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1521

let Latency = 4;

1522

let NumMicroOps = 2;

1523

let ResourceCycles = [2];

1524

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1525

def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri",

1526

"VMPSADBWYrri",

1527

"VMPSADBWrri")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1528

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1529

def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1530

let Latency = 4;

1531

let NumMicroOps = 2;

1532

let ResourceCycles = [1,1];

1533

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1534

def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r,

1535

MULX64rr)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1536

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1537

def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {

1538

let Latency = 4;

1539

let NumMicroOps = 4;

1540

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1541

def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1542

1543

def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,SKLPort01]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1544

let Latency = 4;

1545

let NumMicroOps = 2;

1546

let ResourceCycles = [1,1];

1547

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1548

def: InstRW<[SKLWriteResGroup52], (instregex "VPSLLDYrr",

"VPSLLQYrr",

"VPSLLWYrr",

"VPSRADYrr",

"VPSRAWYrr",

"VPSRLDYrr",

"VPSRLQYrr",

"VPSRLWYrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1556

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1557

def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1558

let Latency = 4;

1559

let NumMicroOps = 3;

1560

let ResourceCycles = [1,1,1];

1561

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1562

def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m",

"ISTT_FP32m",

"ISTT_FP64m",

"IST_F16m",

"IST_F32m",

"IST_FP16m",

"IST_FP32m",

"IST_FP64m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1570

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1571

def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1572

let Latency = 4;

1573

let NumMicroOps = 4;

1574

let ResourceCycles = [4];

1575

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1576

def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1577

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1578

def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1579

let Latency = 4;

1580

let NumMicroOps = 4;

1581

let ResourceCycles = [1,3];

1582

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1583

def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1584

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1585

def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1586

let Latency = 4;

1587

let NumMicroOps = 4;

1588

let ResourceCycles = [1,3];

1589

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1590

def: InstRW<[SKLWriteResGroup56], (instregex "VZEROUPPER")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1591

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1592

def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1593

let Latency = 4;

1594

let NumMicroOps = 4;

1595

let ResourceCycles = [1,1,2];

1596

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1597

def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1598

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1599

def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {

1600

let Latency = 5;

1601

let NumMicroOps = 1;

1602

let ResourceCycles = [1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1603

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1604

def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm",

"MMX_MOVD64to64rm",

"MMX_MOVQ64rm",

"MOV(8|16|32|64)rm",

"MOV64toPQIrm",

"MOVDDUPrm",

"MOVDI2PDIrm",

"MOVQI2PQIrm",

"MOVSDrm",

"MOVSSrm",

"MOVSX(16|32|64)rm16",

1615

"MOVSX(16|32|64)rm32",

1616

"MOVSX(16|32|64)rm8",

1617

"MOVZX(16|32|64)rm16",

1618

"MOVZX(16|32|64)rm8",

"PREFETCHNTA",

"PREFETCHT0",

"PREFETCHT1",

"PREFETCHT2",

"VMOV64toPQIrm",

"VMOVDDUPrm",

"VMOVDI2PDIrm",

"VMOVQI2PQIrm",

"VMOVSDrm",

"VMOVSSrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1629

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1630

def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1631

let Latency = 5;

1632

let NumMicroOps = 2;

1633

let ResourceCycles = [1,1];

1634

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1635

def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr",

1636

"MMX_CVTPI2PDirr",

1637

"VCVTDQ2PDrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1638

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1639

def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1640

let Latency = 5;

1641

let NumMicroOps = 2;

1642

let ResourceCycles = [1,1];

1643

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1644

def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr",

"CVTPD2PSrr",

"CVTPS2PDrr",

"CVTSD2SSrr",

"CVTSI642SDrr",

"CVTSI2SDrr",

"CVTSI2SSrr",

"CVTSS2SDrr",

"CVTTPD2DQrr",

"MMX_CVTPD2PIirr",

"MMX_CVTPS2PIirr",

"MMX_CVTTPD2PIirr",

"MMX_CVTTPS2PIirr",

"VCVTPD2DQrr",

"VCVTPD2PSrr",

"VCVTPH2PSrr",

"VCVTPS2PDrr",

"VCVTPS2PHrr",

"VCVTSD2SSrr",

"VCVTSI642SDrr",

"VCVTSI2SDrr",

"VCVTSI2SSrr",

"VCVTSS2SDrr",

"VCVTTPD2DQrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1668

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1669

def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1670

let Latency = 5;

1671

let NumMicroOps = 3;

1672

let ResourceCycles = [1,1,1];

1673

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1674

def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1675

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1676

def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1677

let Latency = 5;

1678

let NumMicroOps = 3;

1679

let ResourceCycles = [1,1,1];

1680

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1681

def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r)>;

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

1682

def: InstRW<[SKLWriteResGroup62], (instrs MULX32rr)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1683

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1684

def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1685

let Latency = 5;

1686

let NumMicroOps = 5;

1687

let ResourceCycles = [1,4];

1688

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1689

def: InstRW<[SKLWriteResGroup63], (instregex "XSETBV")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1690

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1691

def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1692

let Latency = 5;

1693

let NumMicroOps = 5;

1694

let ResourceCycles = [2,3];

1695

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

1696

def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1697

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1698

def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1699

let Latency = 5;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1700

let NumMicroOps = 6;

1701

let ResourceCycles = [1,1,4];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1702

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1703

def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF16",

1704

"PUSHF64")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1705

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1706

def SKLWriteResGroup66 : SchedWriteRes<[SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1707

let Latency = 6;

1708

let NumMicroOps = 1;

1709

let ResourceCycles = [1];

1710

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1711

def: InstRW<[SKLWriteResGroup66], (instregex "(V?)PCLMULQDQrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1712

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1713

def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {

1714

let Latency = 6;

1715

let NumMicroOps = 1;

1716

let ResourceCycles = [1];

1717

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1718

def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm",

"MOVAPDrm",

"MOVAPSrm",

"MOVDQArm",

"MOVDQUrm",

"MOVNTDQArm",

"MOVSHDUPrm",

"MOVSLDUPrm",

"MOVUPDrm",

"MOVUPSrm",

"VBROADCASTSSrm",

"VLDDQUrm",

"VMOVAPDrm",

"VMOVAPSrm",

"VMOVDQArm",

"VMOVDQUrm",

"VMOVNTDQArm",

"VMOVSHDUPrm",

"VMOVSLDUPrm",

"VMOVUPDrm",

"VMOVUPSrm",

"VPBROADCASTDrm",

"VPBROADCASTQrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1741

1742

def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1743

let Latency = 6;

1744

let NumMicroOps = 2;

1745

let ResourceCycles = [2];

1746

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1747

def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1748

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1749

def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1750

let Latency = 6;

1751

let NumMicroOps = 2;

1752

let ResourceCycles = [1,1];

1753

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1754

def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",

"MMX_PADDSWirm",

"MMX_PADDUSBirm",

"MMX_PADDUSWirm",

"MMX_PAVGBirm",

"MMX_PAVGWirm",

"MMX_PCMPEQBirm",

"MMX_PCMPEQDirm",

"MMX_PCMPEQWirm",

"MMX_PCMPGTBirm",

"MMX_PCMPGTDirm",

"MMX_PCMPGTWirm",

"MMX_PMAXSWirm",

"MMX_PMAXUBirm",

"MMX_PMINSWirm",

"MMX_PMINUBirm",

"MMX_PSLLDrm",

"MMX_PSLLQrm",

"MMX_PSLLWrm",

"MMX_PSRADrm",

"MMX_PSRAWrm",

"MMX_PSRLDrm",

"MMX_PSRLQrm",

"MMX_PSRLWrm",

"MMX_PSUBSBirm",

"MMX_PSUBSWirm",

"MMX_PSUBUSBirm",

"MMX_PSUBUSWirm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1782

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1783

def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1784

let Latency = 6;

1785

let NumMicroOps = 2;

1786

let ResourceCycles = [1,1];

1787

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1788

def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr",

"CVTSD2SIrr",

"CVTSS2SI64rr",

"CVTSS2SIrr",

"CVTTSD2SI64rr",

"CVTTSD2SIrr",

"VCVTSD2SI64rr",

"VCVTSD2SIrr",

"VCVTSS2SI64rr",

"VCVTSS2SIrr",

"VCVTTSD2SI64rr",

"VCVTTSD2SIrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1800

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1801

def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {

1802

let Latency = 6;

1803

let NumMicroOps = 2;

1804

let ResourceCycles = [1,1];

1805

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1806

def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",

"MMX_PINSRWrm",

"MMX_PSHUFBrm",

"MMX_PSHUFWmi",

"MMX_PUNPCKHBWirm",

"MMX_PUNPCKHDQirm",

"MMX_PUNPCKHWDirm",

"MMX_PUNPCKLBWirm",

"MMX_PUNPCKLDQirm",

"MMX_PUNPCKLWDirm",

"MOVHPDrm",

"MOVHPSrm",

"MOVLPDrm",

"MOVLPSrm",

"PINSRBrm",

"PINSRDrm",

"PINSRQrm",

"PINSRWrm",

"PMOVSXBDrm",

"PMOVSXBQrm",

"PMOVSXBWrm",

"PMOVSXDQrm",

"PMOVSXWDrm",

"PMOVSXWQrm",

"PMOVZXBDrm",

"PMOVZXBQrm",

"PMOVZXBWrm",

"PMOVZXDQrm",

"PMOVZXWDrm",

"PMOVZXWQrm",

"VMOVHPDrm",

"VMOVHPSrm",

"VMOVLPDrm",

"VMOVLPSrm",

"VPINSRBrm",

"VPINSRDrm",

"VPINSRQrm",

"VPINSRWrm",

"VPMOVSXBDrm",

"VPMOVSXBQrm",

"VPMOVSXBWrm",

"VPMOVSXDQrm",

"VPMOVSXWDrm",

"VPMOVSXWQrm",

"VPMOVZXBDrm",

"VPMOVZXBQrm",

"VPMOVZXBWrm",

"VPMOVZXDQrm",

"VPMOVZXWDrm",

"VPMOVZXWQrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1856

1857

def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {

1858

let Latency = 6;

1859

let NumMicroOps = 2;

1860

let ResourceCycles = [1,1];

1861

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1862

def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",

1863

"JMP(16|32|64)m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1864

1865

def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,SKLPort05]> {

1866

let Latency = 6;

1867

let NumMicroOps = 2;

1868

let ResourceCycles = [1,1];

1869

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1870

def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm",

"MMX_PABSDrm",

"MMX_PABSWrm",

"MMX_PADDBirm",

"MMX_PADDDirm",

"MMX_PADDQirm",

"MMX_PADDWirm",

"MMX_PANDNirm",

"MMX_PANDirm",

"MMX_PORirm",

"MMX_PSIGNBrm",

"MMX_PSIGNDrm",

"MMX_PSIGNWrm",

"MMX_PSUBBirm",

"MMX_PSUBDirm",

"MMX_PSUBQirm",

"MMX_PSUBWirm",

"MMX_PXORirm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1888

1889

def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {

1890

let Latency = 6;

1891

let NumMicroOps = 2;

1892

let ResourceCycles = [1,1];

1893

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1894

def: InstRW<[SKLWriteResGroup74], (instregex "ADC(8|16|32|64)rm",

"ADCX(32|64)rm",

"ADOX(32|64)rm",

"BT(16|32|64)mi8",

"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",

"RORX(32|64)mi",

"SARX(32|64)rm",

"SBB(8|16|32|64)rm",

"SHLX(32|64)rm",

"SHRX(32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1904

1905

def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {

1906

let Latency = 6;

1907

let NumMicroOps = 2;

1908

let ResourceCycles = [1,1];

1909

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1910

def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",

"BLSI(32|64)rm",

"BLSMSK(32|64)rm",

"BLSR(32|64)rm",

"BZHI(32|64)rm",

"MOVBE(16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1916

1917

def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {

1918

let Latency = 6;

1919

let NumMicroOps = 2;

1920

let ResourceCycles = [1,1];

1921

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

1922

def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1923

def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm",

"AND(8|16|32|64)rm",

"CMP(8|16|32|64)mi",

"CMP(8|16|32|64)mr",

"CMP(8|16|32|64)rm",

"OR(8|16|32|64)rm",

"POP(16|32|64)rmr",

"SUB(8|16|32|64)rm",

"TEST(8|16|32|64)mr",

1932

"TEST(8|16|32|64)mi",

1933

"XOR(8|16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1934

1935

def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1936

let Latency = 6;

1937

let NumMicroOps = 3;

1938

let ResourceCycles = [2,1];

1939

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1940

def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr",

"HADDPSrr",

"HSUBPDrr",

"HSUBPSrr",

"VHADDPDYrr",

"VHADDPDrr",

"VHADDPSYrr",

"VHADDPSrr",

"VHSUBPDYrr",

"VHSUBPDrr",

"VHSUBPSYrr",

"VHSUBPSrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1952

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1953

def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1954

let Latency = 6;

1955

let NumMicroOps = 3;

1956

let ResourceCycles = [2,1];

1957

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1958

def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1959

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1960

def SKLWriteResGroup79 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1961

let Latency = 6;

1962

let NumMicroOps = 4;

1963

let ResourceCycles = [1,2,1];

1964

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1965

def: InstRW<[SKLWriteResGroup79], (instregex "SHLD(16|32|64)rrCL",

1966

"SHRD(16|32|64)rrCL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1967

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1968

def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1969

let Latency = 6;

1970

let NumMicroOps = 4;

1971

let ResourceCycles = [1,1,1,1];

1972

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1973

def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

1974

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1975

def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {

1976

let Latency = 6;

1977

let NumMicroOps = 4;

1978

let ResourceCycles = [1,1,1,1];

1979

}

1980

def: InstRW<[SKLWriteResGroup81], (instregex "VCVTPS2PHmr")>;

1981

1982

def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {

1983

let Latency = 6;

1984

let NumMicroOps = 4;

1985

let ResourceCycles = [1,1,1,1];

1986

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

1987

def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",

"BTR(16|32|64)mi8",

"BTS(16|32|64)mi8",

"SAR(8|16|32|64)m1",

"SAR(8|16|32|64)mi",

"SHL(8|16|32|64)m1",

"SHL(8|16|32|64)mi",

"SHR(8|16|32|64)m1",

"SHR(8|16|32|64)mi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

1996

1997

def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {

1998

let Latency = 6;

1999

let NumMicroOps = 4;

2000

let ResourceCycles = [1,1,1,1];

2001

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2002

def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi",

"ADD(8|16|32|64)mr",

"AND(8|16|32|64)mi",

"AND(8|16|32|64)mr",

"DEC(8|16|32|64)m",

"INC(8|16|32|64)m",

"NEG(8|16|32|64)m",

"NOT(8|16|32|64)m",

"OR(8|16|32|64)mi",

"OR(8|16|32|64)mr",

"POP(16|32|64)rmm",

"PUSH(16|32|64)rmm",

"SUB(8|16|32|64)mi",

"SUB(8|16|32|64)mr",

"XOR(8|16|32|64)mi",

"XOR(8|16|32|64)mr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2018

2019

def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2020

let Latency = 6;

2021

let NumMicroOps = 6;

2022

let ResourceCycles = [1,5];

2023

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2024

def: InstRW<[SKLWriteResGroup84], (instregex "STD")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2025

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2026

def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {

2027

let Latency = 7;

2028

let NumMicroOps = 1;

2029

let ResourceCycles = [1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2030

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2031

def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m",

"LD_F64m",

"LD_F80m",

"VBROADCASTF128",

"VBROADCASTI128",

"VBROADCASTSDYrm",

"VBROADCASTSSYrm",

"VLDDQUYrm",

"VMOVAPDYrm",

"VMOVAPSYrm",

"VMOVDDUPYrm",

"VMOVDQAYrm",

"VMOVDQUYrm",

"VMOVNTDQAYrm",

"VMOVSHDUPYrm",

"VMOVSLDUPYrm",

"VMOVUPDYrm",

"VMOVUPSYrm",

"VPBROADCASTDYrm",

"VPBROADCASTQYrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2051

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2052

def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2053

let Latency = 7;

2054

let NumMicroOps = 2;

2055

let ResourceCycles = [1,1];

2056

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2057

def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2058

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2059

def SKLWriteResGroup87 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2060

let Latency = 7;

2061

let NumMicroOps = 2;

2062

let ResourceCycles = [1,1];

2063

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2064

def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm",

"COMISSrm",

"UCOMISDrm",

"UCOMISSrm",

"VCOMISDrm",

"VCOMISSrm",

"VUCOMISDrm",

"VUCOMISSrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2072

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2073

def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2074

let Latency = 7;

2075

let NumMicroOps = 2;

2076

let ResourceCycles = [1,1];

2077

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2078

def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm",

"PACKSSDWrm",

"PACKSSWBrm",

"PACKUSDWrm",

"PACKUSWBrm",

"PALIGNRrmi",

"PBLENDWrmi",

"PSHUFBrm",

"PSHUFDmi",

"PSHUFHWmi",

"PSHUFLWmi",

"PUNPCKHBWrm",

"PUNPCKHDQrm",

"PUNPCKHQDQrm",

"PUNPCKHWDrm",

"PUNPCKLBWrm",

"PUNPCKLDQrm",

"PUNPCKLQDQrm",

"PUNPCKLWDrm",

"SHUFPDrmi",

"SHUFPSrmi",

"UNPCKHPDrm",

"UNPCKHPSrm",

"UNPCKLPDrm",

"UNPCKLPSrm",

"VINSERTPSrm",

"VPACKSSDWrm",

"VPACKSSWBrm",

"VPACKUSDWrm",

"VPACKUSWBrm",

"VPALIGNRrmi",

"VPBLENDWrmi",

"VPBROADCASTBrm",

"VPBROADCASTWrm",

"VPERMILPDmi",

"VPERMILPDrm",

"VPERMILPSmi",

"VPERMILPSrm",

"VPSHUFBrm",

"VPSHUFDmi",

"VPSHUFHWmi",

"VPSHUFLWmi",

"VPUNPCKHBWrm",

"VPUNPCKHDQrm",

"VPUNPCKHQDQrm",

"VPUNPCKHWDrm",

"VPUNPCKLBWrm",

"VPUNPCKLDQrm",

"VPUNPCKLQDQrm",

"VPUNPCKLWDrm",

"VSHUFPDrmi",

"VSHUFPSrmi",

"VUNPCKHPDrm",

"VUNPCKHPSrm",

"VUNPCKLPDrm",

"VUNPCKLPSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2134

2135

def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort015]> {

2136

let Latency = 7;

2137

let NumMicroOps = 2;

2138

let ResourceCycles = [1,1];

2139

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2140

def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2DQYrr",

"VCVTPD2PSYrr",

"VCVTPH2PSYrr",

"VCVTPS2PDYrr",

"VCVTPS2PHYrr",

"VCVTTPD2DQYrr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2146

2147

def SKLWriteResGroup90 : SchedWriteRes<[SKLPort01,SKLPort23]> {

2148

let Latency = 7;

2149

let NumMicroOps = 2;

2150

let ResourceCycles = [1,1];

2151

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2152

def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm",

"PABSDrm",

"PABSWrm",

"PADDSBrm",

"PADDSWrm",

"PADDUSBrm",

"PADDUSWrm",

"PAVGBrm",

"PAVGWrm",

"PCMPEQBrm",

"PCMPEQDrm",

"PCMPEQQrm",

"PCMPEQWrm",

"PCMPGTBrm",

"PCMPGTDrm",

"PCMPGTWrm",

"PMAXSBrm",

"PMAXSDrm",

"PMAXSWrm",

"PMAXUBrm",

"PMAXUDrm",

"PMAXUWrm",

"PMINSBrm",

"PMINSDrm",

"PMINSWrm",

"PMINUBrm",

"PMINUDrm",

"PMINUWrm",

"PSIGNBrm",

"PSIGNDrm",

"PSIGNWrm",

"PSLLDrm",

"PSLLQrm",

"PSLLWrm",

"PSRADrm",

"PSRAWrm",

"PSRLDrm",

"PSRLQrm",

"PSRLWrm",

"PSUBSBrm",

"PSUBSWrm",

"PSUBUSBrm",

"PSUBUSWrm",

"VPABSBrm",

"VPABSDrm",

"VPABSWrm",

"VPADDSBrm",

"VPADDSWrm",

"VPADDUSBrm",

"VPADDUSWrm",

"VPAVGBrm",

"VPAVGWrm",

"VPCMPEQBrm",

"VPCMPEQDrm",

"VPCMPEQQrm",

"VPCMPEQWrm",

"VPCMPGTBrm",

"VPCMPGTDrm",

"VPCMPGTWrm",

"VPMAXSBrm",

"VPMAXSDrm",

"VPMAXSWrm",

"VPMAXUBrm",

"VPMAXUDrm",

"VPMAXUWrm",

"VPMINSBrm",

"VPMINSDrm",

"VPMINSWrm",

"VPMINUBrm",

"VPMINUDrm",

"VPMINUWrm",

"VPSIGNBrm",

"VPSIGNDrm",

"VPSIGNWrm",

"VPSLLDrm",

"VPSLLQrm",

"VPSLLVDrm",

"VPSLLVQrm",

"VPSLLWrm",

"VPSRADrm",

"VPSRAVDrm",

"VPSRAWrm",

"VPSRLDrm",

"VPSRLQrm",

"VPSRLVDrm",

"VPSRLVQrm",

"VPSRLWrm",

"VPSUBSBrm",

"VPSUBSWrm",

"VPSUBUSBrm",

"VPSUBUSWrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2243

2244

def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {

2245

let Latency = 7;

2246

let NumMicroOps = 2;

2247

let ResourceCycles = [1,1];

2248

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2249

def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm",

"ANDNPSrm",

"ANDPDrm",

"ANDPSrm",

"BLENDPDrmi",

"BLENDPSrmi",

"ORPDrm",

"ORPSrm",

"PADDBrm",

"PADDDrm",

"PADDQrm",

"PADDWrm",

"PANDNrm",

"PANDrm",

"PORrm",

"PSUBBrm",

"PSUBDrm",

"PSUBQrm",

"PSUBWrm",

"PXORrm",

"VANDNPDrm",

"VANDNPSrm",

"VANDPDrm",

"VANDPSrm",

"VBLENDPDrmi",

"VBLENDPSrmi",

"VINSERTF128rm",

"VINSERTI128rm",

"VMASKMOVPDrm",

"VMASKMOVPSrm",

"VORPDrm",

"VORPSrm",

"VPADDBrm",

"VPADDDrm",

"VPADDQrm",

"VPADDWrm",

"VPANDNrm",

"VPANDrm",

"VPBLENDDrmi",

"VPMASKMOVDrm",

"VPMASKMOVQrm",

"VPORrm",

"VPSUBBrm",

"VPSUBDrm",

"VPSUBQrm",

"VPSUBWrm",

"VPXORrm",

"VXORPDrm",

"VXORPSrm",

"XORPDrm",

"XORPSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2300

2301

def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2302

let Latency = 7;

2303

let NumMicroOps = 3;

2304

let ResourceCycles = [2,1];

2305

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2306

def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",

2307

"MMX_PACKSSWBirm",

2308

"MMX_PACKUSWBirm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2309

2310

def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,SKLPort06]> {

2311

let Latency = 7;

2312

let NumMicroOps = 3;

2313

let ResourceCycles = [1,2];

2314

}

Craig Topper

f4cd908

2018-01-19 05:47:32 +0000

[diff] [blame]

2315

def: InstRW<[SKLWriteResGroup93], (instregex "CMOV(A|BE)(16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2316

2317

def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {

2318

let Latency = 7;

2319

let NumMicroOps = 3;

2320

let ResourceCycles = [1,2];

2321

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2322

def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64",

"SCASB",

"SCASL",

"SCASQ",

"SCASW")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2327

2328

def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2329

let Latency = 7;

2330

let NumMicroOps = 3;

2331

let ResourceCycles = [1,1,1];

2332

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2333

def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI64rr",

2334

"(V?)CVTTSS2SIrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2335

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2336

def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2337

let Latency = 7;

2338

let NumMicroOps = 3;

2339

let ResourceCycles = [1,1,1];

2340

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2341

def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2342

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2343

def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2344

let Latency = 7;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2345

let NumMicroOps = 3;

2346

let ResourceCycles = [1,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2347

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2348

def: InstRW<[SKLWriteResGroup97], (instregex "(V?)LDMXCSR")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2349

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2350

def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2351

let Latency = 7;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2352

let NumMicroOps = 3;

2353

let ResourceCycles = [1,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2354

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2355

def: InstRW<[SKLWriteResGroup98], (instregex "LRETQ",

2356

"RETQ")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2357

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2358

def SKLWriteResGroup99 : SchedWriteRes<[SKLPort23,SKLPort06,SKLPort15]> {

2359

let Latency = 7;

2360

let NumMicroOps = 3;

2361

let ResourceCycles = [1,1,1];

2362

}

Craig Topper

a42a2ba

2017-12-16 18:35:31 +0000

[diff] [blame]

2363

def: InstRW<[SKLWriteResGroup99], (instregex "BEXTR(32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2364

2365

def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {

2366

let Latency = 7;

2367

let NumMicroOps = 5;

2368

let ResourceCycles = [1,1,1,2];

2369

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2370

def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",

2371

"ROL(8|16|32|64)mi",

2372

"ROR(8|16|32|64)m1",

2373

"ROR(8|16|32|64)mi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2374

2375

def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {

2376

let Latency = 7;

2377

let NumMicroOps = 5;

2378

let ResourceCycles = [1,1,1,2];

2379

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

2380

def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2381

2382

def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {

2383

let Latency = 7;

2384

let NumMicroOps = 5;

2385

let ResourceCycles = [1,1,1,1,1];

2386

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2387

def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",

2388

"FARCALL64")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2389

2390

def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2391

let Latency = 7;

2392

let NumMicroOps = 7;

2393

let ResourceCycles = [1,3,1,2];

2394

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

2395

def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2396

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2397

def SKLWriteResGroup104 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2398

let Latency = 8;

2399

let NumMicroOps = 2;

2400

let ResourceCycles = [2];

2401

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2402

def: InstRW<[SKLWriteResGroup104], (instregex "(V?)AESIMCrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2403

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2404

def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2405

let Latency = 8;

2406

let NumMicroOps = 2;

2407

let ResourceCycles = [2];

2408

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2409

def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr",

"ROUNDPSr",

"ROUNDSDr",

"ROUNDSSr",

"VROUNDPDr",

"VROUNDPSr",

"VROUNDSDr",

"VROUNDSSr",

"VROUNDYPDr",

"VROUNDYPSr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2419

Craig Topper

2018-03-20 23:39:48 +0000

[diff] [blame]

2420

def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> {

2421

let Latency = 10;

2422

let NumMicroOps = 2;

2423

let ResourceCycles = [2];

2424

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2425

def: InstRW<[SKLWriteResGroup105_2], (instregex "PMULLDrr",

2426

"VPMULLDYrr",

2427

"VPMULLDrr")>;

Craig Topper

2018-03-20 23:39:48 +0000

[diff] [blame]

2428

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2429

def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2430

let Latency = 8;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2431

let NumMicroOps = 2;

2432

let ResourceCycles = [1,1];

2433

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2434

def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm",

2435

"VTESTPSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2436

2437

def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {

2438

let Latency = 8;

2439

let NumMicroOps = 2;

2440

let ResourceCycles = [1,1];

2441

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2442

def: InstRW<[SKLWriteResGroup107], (instrs IMUL64m, MUL64m)>;

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2443

def: InstRW<[SKLWriteResGroup107], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>;

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2444

def: InstRW<[SKLWriteResGroup107], (instrs IMUL8m, MUL8m)>;

2445

def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm",

"BSR(16|32|64)rm",

"LZCNT(16|32|64)rm",

"PDEP(32|64)rm",

"PEXT(32|64)rm",

"POPCNT(16|32|64)rm",

2451

"TZCNT(16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2452

2453

def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2454

let Latency = 8;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2455

let NumMicroOps = 3;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2456

let ResourceCycles = [1,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2457

}

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2458

def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2459

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2460

def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2461

let Latency = 8;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2462

let NumMicroOps = 5;

2463

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2464

def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2465

2466

def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2467

let Latency = 8;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2468

let NumMicroOps = 3;

2469

let ResourceCycles = [1,1,1];

2470

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2471

def: InstRW<[SKLWriteResGroup107_32], (instrs IMUL32m, MUL32m)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2472

2473

def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2474

let Latency = 8;

2475

let NumMicroOps = 2;

2476

let ResourceCycles = [1,1];

2477

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2478

def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m",

"FCOM64m",

"FCOMP32m",

"FCOMP64m",

"MMX_PSADBWirm",

"VPACKSSDWYrm",

"VPACKSSWBYrm",

"VPACKUSDWYrm",

"VPACKUSWBYrm",

"VPALIGNRYrmi",

"VPBLENDWYrmi",

"VPBROADCASTBYrm",

"VPBROADCASTWYrm",

"VPERMILPDYmi",

"VPERMILPDYrm",

"VPERMILPSYmi",

"VPERMILPSYrm",

"VPMOVSXBDYrm",

"VPMOVSXBQYrm",

"VPMOVSXWQYrm",

"VPSHUFBYrm",

"VPSHUFDYmi",

"VPSHUFHWYmi",

"VPSHUFLWYmi",

"VPUNPCKHBWYrm",

"VPUNPCKHDQYrm",

"VPUNPCKHQDQYrm",

"VPUNPCKHWDYrm",

"VPUNPCKLBWYrm",

"VPUNPCKLDQYrm",

"VPUNPCKLQDQYrm",

"VPUNPCKLWDYrm",

"VSHUFPDYrmi",

"VSHUFPSYrmi",

"VUNPCKHPDYrm",

"VUNPCKHPSYrm",

"VUNPCKLPDYrm",

"VUNPCKLPSYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2516

2517

def SKLWriteResGroup109 : SchedWriteRes<[SKLPort01,SKLPort23]> {

2518

let Latency = 8;

2519

let NumMicroOps = 2;

2520

let ResourceCycles = [1,1];

2521

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2522

def: InstRW<[SKLWriteResGroup109], (instregex "VPABSBYrm",

"VPABSDYrm",

"VPABSWYrm",

"VPADDSBYrm",

"VPADDSWYrm",

"VPADDUSBYrm",

"VPADDUSWYrm",

"VPAVGBYrm",

"VPAVGWYrm",

"VPCMPEQBYrm",

"VPCMPEQDYrm",

"VPCMPEQQYrm",

"VPCMPEQWYrm",

"VPCMPGTBYrm",

"VPCMPGTDYrm",

"VPCMPGTWYrm",

"VPMAXSBYrm",

"VPMAXSDYrm",

"VPMAXSWYrm",

"VPMAXUBYrm",

"VPMAXUDYrm",

"VPMAXUWYrm",

"VPMINSBYrm",

"VPMINSDYrm",

"VPMINSWYrm",

"VPMINUBYrm",

"VPMINUDYrm",

"VPMINUWYrm",

"VPSIGNBYrm",

"VPSIGNDYrm",

"VPSIGNWYrm",

"VPSLLDYrm",

"VPSLLQYrm",

"VPSLLVDYrm",

"VPSLLVQYrm",

"VPSLLWYrm",

"VPSRADYrm",

"VPSRAVDYrm",

"VPSRAWYrm",

"VPSRLDYrm",

"VPSRLQYrm",

"VPSRLVDYrm",

"VPSRLVQYrm",

"VPSRLWYrm",

"VPSUBSBYrm",

"VPSUBSWYrm",

"VPSUBUSBYrm",

"VPSUBUSWYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2570

2571

def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {

2572

let Latency = 8;

2573

let NumMicroOps = 2;

2574

let ResourceCycles = [1,1];

2575

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2576

def: InstRW<[SKLWriteResGroup110], (instregex "VANDNPDYrm",

"VANDNPSYrm",

"VANDPDYrm",

"VANDPSYrm",

"VBLENDPDYrmi",

"VBLENDPSYrmi",

"VMASKMOVPDYrm",

"VMASKMOVPSYrm",

"VORPDYrm",

"VORPSYrm",

"VPADDBYrm",

"VPADDDYrm",

"VPADDQYrm",

"VPADDWYrm",

"VPANDNYrm",

"VPANDYrm",

"VPBLENDDYrmi",

"VPMASKMOVDYrm",

"VPMASKMOVQYrm",

"VPORYrm",

"VPSUBBYrm",

"VPSUBDYrm",

"VPSUBQYrm",

"VPSUBWYrm",

"VPXORYrm",

"VXORPDYrm",

"VXORPSYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2603

2604

def SKLWriteResGroup111 : SchedWriteRes<[SKLPort23,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2605

let Latency = 8;

2606

let NumMicroOps = 3;

2607

let ResourceCycles = [1,2];

2608

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2609

def: InstRW<[SKLWriteResGroup111], (instregex "BLENDVPDrm0",

"BLENDVPSrm0",

"PBLENDVBrm0",

"VBLENDVPDrm",

"VBLENDVPSrm",

"VPBLENDVBYrm",

"VPBLENDVBrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2616

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2617

def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

2618

let Latency = 8;

2619

let NumMicroOps = 4;

2620

let ResourceCycles = [1,2,1];

2621

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2622

def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm",

2623

"MMX_PHSUBSWrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2624

2625

def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {

2626

let Latency = 8;

2627

let NumMicroOps = 4;

2628

let ResourceCycles = [2,1,1];

2629

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2630

def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm",

2631

"MMX_PHADDWrm",

2632

"MMX_PHSUBDrm",

2633

"MMX_PHSUBWrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2634

2635

def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {

2636

let Latency = 8;

2637

let NumMicroOps = 4;

2638

let ResourceCycles = [1,1,1,1];

2639

}

2640

def: InstRW<[SKLWriteResGroup114], (instregex "VCVTPS2PHYmr")>;

2641

2642

def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {

2643

let Latency = 8;

2644

let NumMicroOps = 5;

2645

let ResourceCycles = [1,1,3];

2646

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

2647

def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2648

2649

def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

2650

let Latency = 8;

2651

let NumMicroOps = 5;

2652

let ResourceCycles = [1,1,1,2];

2653

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2654

def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",

2655

"RCL(8|16|32|64)mi",

2656

"RCR(8|16|32|64)m1",

2657

"RCR(8|16|32|64)mi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2658

2659

def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {

2660

let Latency = 8;

2661

let NumMicroOps = 6;

2662

let ResourceCycles = [1,1,1,3];

2663

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2664

def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",

2665

"SAR(8|16|32|64)mCL",

2666

"SHL(8|16|32|64)mCL",

2667

"SHR(8|16|32|64)mCL")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2668

2669

def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {

2670

let Latency = 8;

2671

let NumMicroOps = 6;

2672

let ResourceCycles = [1,1,1,3];

2673

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

2674

def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2675

2676

def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

2677

let Latency = 8;

2678

let NumMicroOps = 6;

2679

let ResourceCycles = [1,1,1,2,1];

2680

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2681

def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",

2682

"CMPXCHG(8|16|32|64)rm",

2683

"SBB(8|16|32|64)mi",

2684

"SBB(8|16|32|64)mr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2685

2686

def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {

2687

let Latency = 9;

2688

let NumMicroOps = 2;

2689

let ResourceCycles = [1,1];

2690

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2691

def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm",

"MMX_PMADDUBSWrm",

"MMX_PMADDWDirm",

"MMX_PMULHRSWrm",

"MMX_PMULHUWirm",

"MMX_PMULHWirm",

"MMX_PMULLWirm",

"MMX_PMULUDQirm",

"RCPSSm",

"RSQRTSSm",

"VRCPSSm",

"VRSQRTSSm",

"VTESTPDYrm",

"VTESTPSYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2705

2706

def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2707

let Latency = 9;

2708

let NumMicroOps = 2;

2709

let ResourceCycles = [1,1];

2710

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2711

def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm",

"PSADBWrm",

"VPCMPGTQrm",

"VPMOVSXBWYrm",

"VPMOVSXDQYrm",

"VPMOVSXWDYrm",

"VPMOVZXWDYrm",

"VPSADBWrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2719

2720

def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {

2721

let Latency = 9;

2722

let NumMicroOps = 2;

2723

let ResourceCycles = [1,1];

2724

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2725

def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",

"ADDSSrm",

"MULSDrm",

"MULSSrm",

"SUBSDrm",

"SUBSSrm",

"VADDSDrm",

"VADDSSrm",

"VMULSDrm",

"VMULSSrm",

"VSUBSDrm",

"VSUBSSrm")>;

Craig Topper

2017-12-13 23:11:30 +0000

[diff] [blame]

2737

def: InstRW<[SKLWriteResGroup122],

2738

(instregex "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2739

2740

def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {

2741

let Latency = 9;

2742

let NumMicroOps = 2;

2743

let ResourceCycles = [1,1];

2744

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2745

def: InstRW<[SKLWriteResGroup123], (instregex "CMPSDrm",

"CMPSSrm",

"CVTPS2PDrm",

"MAX(C?)SDrm",

"MAX(C?)SSrm",

"MIN(C?)SDrm",

"MIN(C?)SSrm",

"MMX_CVTPS2PIirm",

"MMX_CVTTPS2PIirm",

"VCMPSDrm",

"VCMPSSrm",

"VCVTPH2PSrm",

"VCVTPS2PDrm",

"VMAX(C?)SDrm",

"VMAX(C?)SSrm",

"VMIN(C?)SDrm",

"VMIN(C?)SSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2762

2763

def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2764

let Latency = 9;

2765

let NumMicroOps = 3;

2766

let ResourceCycles = [1,2];

2767

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2768

def: InstRW<[SKLWriteResGroup124], (instregex "(V?)DPPDrri")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2769

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2770

def SKLWriteResGroup125 : SchedWriteRes<[SKLPort23,SKLPort015]> {

2771

let Latency = 9;

2772

let NumMicroOps = 3;

2773

let ResourceCycles = [1,2];

2774

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2775

def: InstRW<[SKLWriteResGroup125], (instregex "VBLENDVPDYrm",

2776

"VBLENDVPSYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2777

2778

def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

2779

let Latency = 9;

2780

let NumMicroOps = 3;

2781

let ResourceCycles = [1,1,1];

2782

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2783

def: InstRW<[SKLWriteResGroup126], (instregex "(V?)PTESTrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2784

2785

def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {

2786

let Latency = 9;

2787

let NumMicroOps = 3;

2788

let ResourceCycles = [1,1,1];

2789

}

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2790

def: InstRW<[SKLWriteResGroup127], (instrs MULX64rm)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2791

2792

def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2793

let Latency = 9;

2794

let NumMicroOps = 4;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2795

let ResourceCycles = [2,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2796

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2797

def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",

2798

"(V?)PHSUBSWrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2799

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2800

def SKLWriteResGroup129 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

2801

let Latency = 9;

2802

let NumMicroOps = 4;

2803

let ResourceCycles = [2,1,1];

2804

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2805

def: InstRW<[SKLWriteResGroup129], (instregex "(V?)PHADDDrm",

2806

"(V?)PHADDWrm",

2807

"(V?)PHSUBDrm",

2808

"(V?)PHSUBWrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2809

2810

def SKLWriteResGroup130 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort0156]> {

2811

let Latency = 9;

2812

let NumMicroOps = 4;

2813

let ResourceCycles = [1,1,1,1];

2814

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2815

def: InstRW<[SKLWriteResGroup130], (instregex "SHLD(16|32|64)mri8",

2816

"SHRD(16|32|64)mri8")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2817

2818

def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {

2819

let Latency = 9;

2820

let NumMicroOps = 5;

2821

let ResourceCycles = [1,2,1,1];

2822

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2823

def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",

2824

"LSL(16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2825

2826

def SKLWriteResGroup132 : SchedWriteRes<[SKLPort0,SKLPort23]> {

2827

let Latency = 10;

2828

let NumMicroOps = 2;

2829

let ResourceCycles = [1,1];

2830

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2831

def: InstRW<[SKLWriteResGroup132], (instregex "(V?)AESDECLASTrm",

"(V?)AESDECrm",

"(V?)AESENCLASTrm",

"(V?)AESENCrm",

"(V?)RCPPSm",

"(V?)RSQRTPSm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2837

2838

def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2839

let Latency = 10;

2840

let NumMicroOps = 2;

2841

let ResourceCycles = [1,1];

2842

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2843

def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m",

"ADD_F64m",

"ILD_F16m",

"ILD_F32m",

"ILD_F64m",

"SUBR_F32m",

"SUBR_F64m",

"SUB_F32m",

"SUB_F64m",

"VPCMPGTQYrm",

"VPERM2F128rm",

"VPERM2I128rm",

"VPERMDYrm",

"VPERMPDYmi",

"VPERMPSYrm",

"VPERMQYmi",

"VPMOVZXBDYrm",

"VPMOVZXBQYrm",

"VPMOVZXBWYrm",

"VPMOVZXDQYrm",

"VPMOVZXWQYrm",

"VPSADBWYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2865

2866

def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {

2867

let Latency = 10;

2868

let NumMicroOps = 2;

2869

let ResourceCycles = [1,1];

2870

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2871

def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm",

"ADDPSrm",

"ADDSUBPDrm",

"ADDSUBPSrm",

"MULPDrm",

"MULPSrm",

"SUBPDrm",

"SUBPSrm",

"VADDPDrm",

"VADDPSrm",

"VADDSUBPDrm",

"VADDSUBPSrm",

"VMULPDrm",

"VMULPSrm",

"VSUBPDrm",

"VSUBPSrm")>;

Craig Topper

2017-12-13 23:11:30 +0000

[diff] [blame]

2887

def: InstRW<[SKLWriteResGroup134],

2888

(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2889

2890

def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,SKLPort015]> {

2891

let Latency = 10;

2892

let NumMicroOps = 2;

2893

let ResourceCycles = [1,1];

2894

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2895

def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",

"CMPPSrmi",

"CVTDQ2PSrm",

"CVTPS2DQrm",

"CVTSS2SDrm",

"CVTTPS2DQrm",

"MAX(C?)PDrm",

"MAX(C?)PSrm",

"MIN(C?)PDrm",

"MIN(C?)PSrm",

"PHMINPOSUWrm",

"PMADDUBSWrm",

"PMADDWDrm",

"PMULDQrm",

"PMULHRSWrm",

"PMULHUWrm",

"PMULHWrm",

"PMULLWrm",

"PMULUDQrm",

"VCMPPDrmi",

"VCMPPSrmi",

"VCVTDQ2PSrm",

"VCVTPH2PSYrm",

"VCVTPS2DQrm",

"VCVTSS2SDrm",

"VCVTTPS2DQrm",

"VMAX(C?)PDrm",

"VMAX(C?)PSrm",

"VMIN(C?)PDrm",

"VMIN(C?)PSrm",

"VPHMINPOSUWrm",

"VPMADDUBSWrm",

"VPMADDWDrm",

"VPMULDQrm",

"VPMULHRSWrm",

"VPMULHUWrm",

"VPMULHWrm",

"VPMULLWrm",

"VPMULUDQrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2934

2935

def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2936

let Latency = 10;

2937

let NumMicroOps = 3;

2938

let ResourceCycles = [3];

2939

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2940

def: InstRW<[SKLWriteResGroup136], (instregex "(V?)PCMPISTRIrr",

2941

"(V?)PCMPISTRM128rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2942

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2943

def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {

2944

let Latency = 10;

2945

let NumMicroOps = 3;

2946

let ResourceCycles = [2,1];

2947

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2948

def: InstRW<[SKLWriteResGroup137], (instregex "(V?)MPSADBWrmi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2949

2950

def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

2951

let Latency = 10;

2952

let NumMicroOps = 3;

2953

let ResourceCycles = [1,1,1];

2954

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2955

def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm",

2956

"VPTESTYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2957

2958

def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

2959

let Latency = 10;

2960

let NumMicroOps = 3;

2961

let ResourceCycles = [1,1,1];

2962

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2963

def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2964

2965

def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2966

let Latency = 10;

2967

let NumMicroOps = 4;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2968

let ResourceCycles = [2,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2969

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2970

def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",

2971

"VPHSUBSWYrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2972

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2973

def SKLWriteResGroup141 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

2974

let Latency = 10;

2975

let NumMicroOps = 4;

2976

let ResourceCycles = [2,1,1];

2977

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

2978

def: InstRW<[SKLWriteResGroup141], (instregex "VPHADDDYrm",

2979

"VPHADDWYrm",

2980

"VPHSUBDYrm",

2981

"VPHSUBWYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2982

2983

def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {

2984

let Latency = 10;

2985

let NumMicroOps = 4;

2986

let ResourceCycles = [1,1,1,1];

2987

}

Craig Topper

2018-01-25 06:57:42 +0000

[diff] [blame]

2988

def: InstRW<[SKLWriteResGroup142], (instrs MULX32rm)>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2989

2990

def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

2991

let Latency = 10;

2992

let NumMicroOps = 8;

2993

let ResourceCycles = [1,1,1,1,1,3];

2994

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

2995

def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

2996

2997

def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

2998

let Latency = 10;

2999

let NumMicroOps = 10;

3000

let ResourceCycles = [9,1];

3001

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3002

def: InstRW<[SKLWriteResGroup144], (instregex "MMX_EMMS")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3003

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3004

def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3005

let Latency = 11;

3006

let NumMicroOps = 1;

3007

let ResourceCycles = [1];

3008

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3009

def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr",

"DIVSSrr",

"VDIVPSYrr",

"VDIVPSrr",

"VDIVSSrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3014

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3015

def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3016

let Latency = 11;

3017

let NumMicroOps = 2;

3018

let ResourceCycles = [1,1];

3019

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3020

def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m",

3021

"MUL_F64m",

3022

"VRCPPSYm",

3023

"VRSQRTPSYm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3024

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3025

def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {

3026

let Latency = 11;

3027

let NumMicroOps = 2;

3028

let ResourceCycles = [1,1];

3029

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3030

def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm",

"VADDPSYrm",

"VADDSUBPDYrm",

"VADDSUBPSYrm",

"VMULPDYrm",

"VMULPSYrm",

"VSUBPDYrm",

"VSUBPSYrm")>;

Craig Topper

2017-12-13 23:11:30 +0000

[diff] [blame]

3038

def: InstRW<[SKLWriteResGroup147],

3039

(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3040

3041

def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,SKLPort015]> {

3042

let Latency = 11;

3043

let NumMicroOps = 2;

3044

let ResourceCycles = [1,1];

3045

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3046

def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",

"VCMPPSYrmi",

"VCVTDQ2PSYrm",

"VCVTPS2DQYrm",

"VCVTPS2PDYrm",

"VCVTTPS2DQYrm",

"VMAX(C?)PDYrm",

"VMAX(C?)PSYrm",

"VMIN(C?)PDYrm",

"VMIN(C?)PSYrm",

"VPMADDUBSWYrm",

"VPMADDWDYrm",

"VPMULDQYrm",

"VPMULHRSWYrm",

"VPMULHUWYrm",

"VPMULHWYrm",

"VPMULLWYrm",

"VPMULUDQYrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3064

3065

def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {

3066

let Latency = 11;

3067

let NumMicroOps = 3;

3068

let ResourceCycles = [2,1];

3069

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3070

def: InstRW<[SKLWriteResGroup149], (instregex "FICOM16m",

"FICOM32m",

"FICOMP16m",

"FICOMP32m",

"VMPSADBWYrmi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3075

3076

def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

3077

let Latency = 11;

3078

let NumMicroOps = 3;

3079

let ResourceCycles = [1,1,1];

3080

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3081

def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3082

3083

def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {

3084

let Latency = 11;

3085

let NumMicroOps = 3;

3086

let ResourceCycles = [1,1,1];

3087

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3088

def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm",

"CVTSD2SIrm",

"CVTSS2SI64rm",

"CVTSS2SIrm",

"CVTTSD2SI64rm",

"CVTTSD2SIrm",

"CVTTSS2SIrm",

"VCVTSD2SI64rm",

"VCVTSD2SIrm",

"VCVTSS2SI64rm",

"VCVTSS2SIrm",

"VCVTTSD2SI64rm",

"VCVTTSD2SIrm",

"VCVTTSS2SI64rm",

"VCVTTSS2SIrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3103

3104

def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

3105

let Latency = 11;

3106

let NumMicroOps = 3;

3107

let ResourceCycles = [1,1,1];

3108

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3109

def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2DQrm",

"CVTPD2PSrm",

"CVTTPD2DQrm",

"MMX_CVTPD2PIirm",

"MMX_CVTTPD2PIirm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3114

3115

def SKLWriteResGroup153 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

3116

let Latency = 11;

3117

let NumMicroOps = 6;

3118

let ResourceCycles = [1,1,1,2,1];

3119

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3120

def: InstRW<[SKLWriteResGroup153], (instregex "SHLD(16|32|64)mrCL",

3121

"SHRD(16|32|64)mrCL")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3122

3123

def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3124

let Latency = 11;

3125

let NumMicroOps = 7;

3126

let ResourceCycles = [2,3,2];

3127

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3128

def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",

3129

"RCR(16|32|64)rCL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3130

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3131

def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3132

let Latency = 11;

3133

let NumMicroOps = 9;

3134

let ResourceCycles = [1,5,1,2];

3135

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3136

def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3137

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3138

def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3139

let Latency = 11;

3140

let NumMicroOps = 11;

3141

let ResourceCycles = [2,9];

3142

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3143

def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3144

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3145

def SKLWriteResGroup157 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3146

let Latency = 12;

3147

let NumMicroOps = 1;

3148

let ResourceCycles = [1];

3149

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3150

def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr",

3151

"VSQRTPSr",

3152

"VSQRTSSr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3153

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3154

def SKLWriteResGroup158 : SchedWriteRes<[SKLPort5,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3155

let Latency = 12;

3156

let NumMicroOps = 2;

3157

let ResourceCycles = [1,1];

3158

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3159

def: InstRW<[SKLWriteResGroup158], (instregex "(V?)PCLMULQDQrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3160

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3161

def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {

3162

let Latency = 12;

3163

let NumMicroOps = 4;

3164

let ResourceCycles = [2,1,1];

3165

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3166

def: InstRW<[SKLWriteResGroup159], (instregex "(V?)HADDPDrm",

3167

"(V?)HADDPSrm",

3168

"(V?)HSUBPDrm",

3169

"(V?)HSUBPSrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3170

3171

def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {

3172

let Latency = 12;

3173

let NumMicroOps = 4;

3174

let ResourceCycles = [1,1,1,1];

3175

}

3176

def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;

3177

3178

def SKLWriteResGroup161 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3179

let Latency = 13;

3180

let NumMicroOps = 1;

3181

let ResourceCycles = [1];

3182

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3183

def: InstRW<[SKLWriteResGroup161], (instregex "SQRTPSr",

3184

"SQRTSSr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3185

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3186

def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3187

let Latency = 13;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3188

let NumMicroOps = 3;

3189

let ResourceCycles = [2,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3190

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3191

def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m",

"ADD_FI32m",

"SUBR_FI16m",

"SUBR_FI32m",

"SUB_FI16m",

"SUB_FI32m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3197

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3198

def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

3199

let Latency = 13;

3200

let NumMicroOps = 3;

3201

let ResourceCycles = [1,1,1];

3202

}

3203

def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;

3204

3205

def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3206

let Latency = 13;

3207

let NumMicroOps = 4;

3208

let ResourceCycles = [1,3];

3209

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3210

def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri",

3211

"VDPPSYrri",

3212

"VDPPSrri")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3213

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3214

def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3215

let Latency = 13;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3216

let NumMicroOps = 4;

3217

let ResourceCycles = [2,1,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3218

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3219

def: InstRW<[SKLWriteResGroup165], (instregex "VHADDPDYrm",

3220

"VHADDPSYrm",

3221

"VHSUBPDYrm",

3222

"VHSUBPSYrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3223

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3224

def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3225

let Latency = 14;

3226

let NumMicroOps = 1;

3227

let ResourceCycles = [1];

3228

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3229

def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr",

"DIVSDrr",

"VDIVPDYrr",

"VDIVPDrr",

"VDIVSDrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3234

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3235

def SKLWriteResGroup167 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3236

let Latency = 14;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3237

let NumMicroOps = 3;

3238

let ResourceCycles = [2,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3239

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3240

def: InstRW<[SKLWriteResGroup167], (instregex "(V?)AESIMCrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3241

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3242

def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {

3243

let Latency = 14;

3244

let NumMicroOps = 3;

3245

let ResourceCycles = [1,2];

3246

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3247

def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPDm")>;

3248

def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDPSm")>;

3249

def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSDm")>;

3250

def: InstRW<[SKLWriteResGroup168], (instregex "(V?)ROUNDSSm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3251

Craig Topper

2018-03-20 23:39:48 +0000

[diff] [blame]

3252

def SKLWriteResGroup168_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {

3253

let Latency = 16;

3254

let NumMicroOps = 3;

3255

let ResourceCycles = [1,2];

3256

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3257

def: InstRW<[SKLWriteResGroup168_2], (instregex "(V?)PMULLDrm")>;

Craig Topper

2018-03-20 23:39:48 +0000

[diff] [blame]

3258

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3259

def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

3260

let Latency = 14;

3261

let NumMicroOps = 3;

3262

let ResourceCycles = [1,1,1];

3263

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3264

def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m",

3265

"MUL_FI32m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3266

3267

def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3268

let Latency = 14;

3269

let NumMicroOps = 10;

3270

let ResourceCycles = [2,4,1,3];

3271

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3272

def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3273

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3274

def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3275

let Latency = 15;

3276

let NumMicroOps = 1;

3277

let ResourceCycles = [1];

3278

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3279

def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0",

3280

"DIVR_FST0r",

3281

"DIVR_FrST0")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3282

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3283

def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3284

let Latency = 15;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3285

let NumMicroOps = 3;

3286

let ResourceCycles = [1,2];

3287

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3288

def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm",

3289

"VROUNDYPSm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3290

Craig Topper

2018-03-20 23:39:48 +0000

[diff] [blame]

3291

def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {

3292

let Latency = 17;

3293

let NumMicroOps = 3;

3294

let ResourceCycles = [1,2];

3295

}

3296

def: InstRW<[SKLWriteResGroup172_2], (instregex "VPMULLDYrm")>;

3297

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3298

def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

3299

let Latency = 15;

3300

let NumMicroOps = 4;

3301

let ResourceCycles = [1,1,2];

3302

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3303

def: InstRW<[SKLWriteResGroup173], (instregex "(V?)DPPDrmi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3304

3305

def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {

3306

let Latency = 15;

3307

let NumMicroOps = 10;

3308

let ResourceCycles = [1,1,1,5,1,1];

3309

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

3310

def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3311

3312

def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3313

let Latency = 16;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3314

let NumMicroOps = 2;

3315

let ResourceCycles = [1,1];

3316

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3317

def: InstRW<[SKLWriteResGroup175], (instregex "(V?)DIVSSrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3318

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3319

def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3320

let Latency = 16;

3321

let NumMicroOps = 4;

3322

let ResourceCycles = [3,1];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3323

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3324

def: InstRW<[SKLWriteResGroup176], (instregex "(V?)PCMPISTRIrm",

3325

"(V?)PCMPISTRM128rm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3326

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3327

def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {

3328

let Latency = 16;

3329

let NumMicroOps = 14;

3330

let ResourceCycles = [1,1,1,4,2,5];

3331

}

3332

def: InstRW<[SKLWriteResGroup177], (instregex "CMPXCHG8B")>;

3333

3334

def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3335

let Latency = 16;

3336

let NumMicroOps = 16;

3337

let ResourceCycles = [16];

3338

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3339

def: InstRW<[SKLWriteResGroup178], (instregex "VZEROALL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3340

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3341

def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3342

let Latency = 17;

3343

let NumMicroOps = 2;

3344

let ResourceCycles = [1,1];

3345

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3346

def: InstRW<[SKLWriteResGroup179], (instregex "(V?)DIVPSrm",

3347

"VSQRTSSm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3348

3349

def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3350

let Latency = 17;

3351

let NumMicroOps = 15;

3352

let ResourceCycles = [2,1,2,4,2,4];

3353

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3354

def: InstRW<[SKLWriteResGroup180], (instregex "XCH_F")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3355

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3356

def SKLWriteResGroup181 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3357

let Latency = 18;

3358

let NumMicroOps = 1;

3359

let ResourceCycles = [1];

3360

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3361

def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr",

3362

"VSQRTPDr",

3363

"VSQRTSDr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3364

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3365

def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3366

let Latency = 18;

3367

let NumMicroOps = 2;

3368

let ResourceCycles = [1,1];

3369

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3370

def: InstRW<[SKLWriteResGroup182], (instregex "SQRTSSm",

3371

"VDIVPSYrm",

3372

"VSQRTPSm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3373

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3374

def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3375

let Latency = 18;

3376

let NumMicroOps = 8;

3377

let ResourceCycles = [4,3,1];

3378

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3379

def: InstRW<[SKLWriteResGroup183], (instregex "(V?)PCMPESTRIrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3380

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3381

def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3382

let Latency = 18;

3383

let NumMicroOps = 8;

3384

let ResourceCycles = [1,1,1,5];

3385

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3386

def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3387

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3388

def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3389

let Latency = 18;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3390

let NumMicroOps = 11;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3391

let ResourceCycles = [2,1,1,4,1,2];

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3392

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

3393

def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3394

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3395

def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3396

let Latency = 19;

3397

let NumMicroOps = 2;

3398

let ResourceCycles = [1,1];

3399

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3400

def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm",

3401

"SQRTPSm",

3402

"VDIVSDrm",

3403

"VSQRTPSYm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3404

3405

def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

3406

let Latency = 19;

3407

let NumMicroOps = 5;

3408

let ResourceCycles = [1,1,3];

3409

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3410

def: InstRW<[SKLWriteResGroup187], (instregex "(V?)DPPSrmi")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3411

3412

def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {

3413

let Latency = 19;

3414

let NumMicroOps = 9;

3415

let ResourceCycles = [4,3,1,1];

3416

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3417

def: InstRW<[SKLWriteResGroup188], (instregex "(V?)PCMPESTRM128rr")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3418

3419

def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3420

let Latency = 20;

3421

let NumMicroOps = 1;

3422

let ResourceCycles = [1];

3423

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3424

def: InstRW<[SKLWriteResGroup189], (instregex "DIV_FPrST0",

"DIV_FST0r",

"DIV_FrST0",

"SQRTPDr",

"SQRTSDr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3429

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3430

def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3431

let Latency = 20;

3432

let NumMicroOps = 2;

3433

let ResourceCycles = [1,1];

3434

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3435

def: InstRW<[SKLWriteResGroup190], (instregex "(V?)DIVPDrm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3436

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3437

def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {

3438

let Latency = 20;

3439

let NumMicroOps = 5;

3440

let ResourceCycles = [1,1,3];

3441

}

3442

def: InstRW<[SKLWriteResGroup191], (instregex "VDPPSYrmi")>;

3443

3444

def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

3445

let Latency = 20;

3446

let NumMicroOps = 8;

3447

let ResourceCycles = [1,1,1,1,1,1,2];

3448

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3449

def: InstRW<[SKLWriteResGroup192], (instregex "INSB",

3450

"INSL",

3451

"INSW")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3452

3453

def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3454

let Latency = 20;

3455

let NumMicroOps = 10;

3456

let ResourceCycles = [1,2,7];

3457

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3458

def: InstRW<[SKLWriteResGroup193], (instregex "MWAITrr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3459

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3460

def SKLWriteResGroup194 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3461

let Latency = 20;

3462

let NumMicroOps = 11;

3463

let ResourceCycles = [3,6,2];

3464

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3465

def: InstRW<[SKLWriteResGroup194], (instregex "(V?)AESKEYGENASSIST128rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3466

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3467

def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3468

let Latency = 21;

3469

let NumMicroOps = 2;

3470

let ResourceCycles = [1,1];

3471

}

3472

def: InstRW<[SKLWriteResGroup195], (instregex "VDIVPDYrm")>;

3473

3474

def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3475

let Latency = 22;

3476

let NumMicroOps = 2;

3477

let ResourceCycles = [1,1];

3478

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3479

def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m",

3480

"DIV_F64m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3481

3482

def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {

3483

let Latency = 22;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3484

let NumMicroOps = 5;

3485

let ResourceCycles = [1,2,1,1];

3486

}

Craig Topper

17a3118

2017-12-16 18:35:29 +0000

[diff] [blame]

3487

def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,

VGATHERDPDrm,

VGATHERQPDrm,

VGATHERQPSrm,

VPGATHERDDrm,

VPGATHERDQrm,

VPGATHERQDrm,

VPGATHERQQrm)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3495

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3496

def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {

3497

let Latency = 25;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3498

let NumMicroOps = 5;

3499

let ResourceCycles = [1,2,1,1];

3500

}

Craig Topper

17a3118

2017-12-16 18:35:29 +0000

[diff] [blame]

3501

def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,

VGATHERQPDYrm,

VGATHERQPSYrm,

VPGATHERDDYrm,

VPGATHERDQYrm,

VPGATHERQDYrm,

VPGATHERQQYrm,

VGATHERDPDYrm)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3509

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3510

def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3511

let Latency = 23;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3512

let NumMicroOps = 2;

3513

let ResourceCycles = [1,1];

3514

}

3515

def: InstRW<[SKLWriteResGroup197], (instregex "VSQRTSDm")>;

3516

3517

def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

3518

let Latency = 23;

3519

let NumMicroOps = 19;

3520

let ResourceCycles = [2,1,4,1,1,4,6];

3521

}

3522

def: InstRW<[SKLWriteResGroup198], (instregex "CMPXCHG16B")>;

3523

3524

def SKLWriteResGroup199 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3525

let Latency = 24;

3526

let NumMicroOps = 2;

3527

let ResourceCycles = [1,1];

3528

}

3529

def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;

3530

3531

def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {

3532

let Latency = 24;

3533

let NumMicroOps = 9;

3534

let ResourceCycles = [4,3,1,1];

3535

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3536

def: InstRW<[SKLWriteResGroup200], (instregex "(V?)PCMPESTRIrm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3537

3538

def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3539

let Latency = 25;

3540

let NumMicroOps = 2;

3541

let ResourceCycles = [1,1];

3542

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3543

def: InstRW<[SKLWriteResGroup201], (instregex "SQRTSDm",

3544

"VSQRTPDYm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3545

3546

def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

3547

let Latency = 25;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3548

let NumMicroOps = 3;

3549

let ResourceCycles = [1,1,1];

3550

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3551

def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m",

3552

"DIV_FI32m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3553

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3554

def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {

3555

let Latency = 25;

3556

let NumMicroOps = 10;

3557

let ResourceCycles = [4,3,1,1,1];

3558

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3559

def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3560

3561

def SKLWriteResGroup204 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {

3562

let Latency = 25;

3563

let NumMicroOps = 11;

3564

let ResourceCycles = [3,6,1,1];

3565

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3566

def: InstRW<[SKLWriteResGroup204], (instregex "(V?)AESKEYGENASSIST128rm")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3567

3568

def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3569

let Latency = 26;

3570

let NumMicroOps = 2;

3571

let ResourceCycles = [1,1];

3572

}

3573

def: InstRW<[SKLWriteResGroup205], (instregex "SQRTPDm")>;

3574

3575

def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {

3576

let Latency = 27;

3577

let NumMicroOps = 2;

3578

let ResourceCycles = [1,1];

3579

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3580

def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m",

3581

"DIVR_F64m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3582

3583

def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {

3584

let Latency = 28;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3585

let NumMicroOps = 8;

3586

let ResourceCycles = [2,4,1,1];

3587

}

Craig Topper

2018-03-19 00:56:09 +0000

[diff] [blame]

3588

def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3589

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3590

def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3591

let Latency = 30;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3592

let NumMicroOps = 3;

3593

let ResourceCycles = [1,1,1];

3594

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3595

def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m",

3596

"DIVR_FI32m")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3597

3598

def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {

3599

let Latency = 35;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3600

let NumMicroOps = 23;

3601

let ResourceCycles = [1,5,3,4,10];

3602

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3603

def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",

3604

"IN(8|16|32)rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3605

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3606

def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {

3607

let Latency = 35;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3608

let NumMicroOps = 23;

3609

let ResourceCycles = [1,5,2,1,4,10];

3610

}

Craig Topper

2018-03-22 04:23:41 +0000

[diff] [blame^]

3611

def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",

3612

"OUT(8|16|32)rr")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3613

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3614

def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {

3615

let Latency = 37;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3616

let NumMicroOps = 31;

3617

let ResourceCycles = [1,8,1,21];

3618

}

Craig Topper

391c6f9

2017-12-10 01:24:08 +0000

[diff] [blame]

3619

def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3620

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3621

def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {

3622

let Latency = 40;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3623

let NumMicroOps = 18;

3624

let ResourceCycles = [1,1,2,3,1,1,1,8];

3625

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3626

def: InstRW<[SKLWriteResGroup212], (instregex "VMCLEARm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3627

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3628

def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {

3629

let Latency = 41;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3630

let NumMicroOps = 39;

3631

let ResourceCycles = [1,10,1,1,26];

3632

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3633

def: InstRW<[SKLWriteResGroup213], (instregex "XSAVE64")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3634

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3635

def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3636

let Latency = 42;

3637

let NumMicroOps = 22;

3638

let ResourceCycles = [2,20];

3639

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

3640

def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3641

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3642

def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {

3643

let Latency = 42;

3644

let NumMicroOps = 40;

3645

let ResourceCycles = [1,11,1,1,26];

3646

}

Craig Topper

391c6f9

2017-12-10 01:24:08 +0000

[diff] [blame]

3647

def: InstRW<[SKLWriteResGroup215], (instregex "^XSAVE$", "XSAVEC", "XSAVES")>;

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3648

3649

def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {

3650

let Latency = 46;

3651

let NumMicroOps = 44;

3652

let ResourceCycles = [1,11,1,1,30];

3653

}

3654

def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;

3655

3656

def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {

3657

let Latency = 62;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3658

let NumMicroOps = 64;

3659

let ResourceCycles = [2,8,5,10,39];

3660

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3661

def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3662

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3663

def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {

3664

let Latency = 63;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3665

let NumMicroOps = 88;

3666

let ResourceCycles = [4,4,31,1,2,1,45];

3667

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

3668

def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3669

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3670

def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {

3671

let Latency = 63;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3672

let NumMicroOps = 90;

3673

let ResourceCycles = [4,2,33,1,2,1,47];

3674

}

Craig Topper

2018-03-18 08:38:06 +0000

[diff] [blame]

3675

def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3676

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3677

def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3678

let Latency = 75;

3679

let NumMicroOps = 15;

3680

let ResourceCycles = [6,3,6];

3681

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3682

def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3683

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3684

def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3685

let Latency = 76;

3686

let NumMicroOps = 32;

3687

let ResourceCycles = [7,2,8,3,1,11];

3688

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3689

def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3690

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3691

def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3692

let Latency = 102;

3693

let NumMicroOps = 66;

3694

let ResourceCycles = [4,2,4,8,14,34];

3695

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3696

def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3697

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3698

def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {

3699

let Latency = 106;

Gadi Haber

2017-09-19 06:19:27 +0000

[diff] [blame]

3700

let NumMicroOps = 100;

3701

let ResourceCycles = [9,1,11,16,1,11,21,30];

3702

}

Gadi Haber

2017-10-17 06:47:04 +0000

[diff] [blame]

3703

def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;

Gadi Haber