blob: 129ac36ddc58437730eb540d63acd72a84a5e4c7 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Eric Anholt673a3942008-07-30 12:06:12 -070034#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include <linux/pci.h>
Eric Anholt673a3942008-07-30 12:06:12 -070036
Eric Anholt28dfe522008-11-13 15:00:55 -080037#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
Eric Anholte47c68e2008-11-14 13:35:19 -080039static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080042static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070048static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -080049static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
Jesse Barnesde151cf2008-11-12 10:03:55 -080051static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
Chris Wilson07f73f62009-09-14 16:50:30 +010052static int i915_gem_evict_something(struct drm_device *dev, int min_size);
Chris Wilsonab5ee572009-09-20 19:25:47 +010053static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
Dave Airlie71acb5e2008-12-30 20:31:46 +100054static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -070057
Chris Wilson31169712009-09-14 16:50:28 +010058static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
Jesse Barnes79e53942008-11-07 14:24:08 -080061int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
65
66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
69 return -EINVAL;
70 }
71
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
74
75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
Keith Packard6dbe2772008-10-14 21:41:13 -070079
Eric Anholt673a3942008-07-30 12:06:12 -070080int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
Eric Anholt673a3942008-07-30 12:06:12 -070084 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080085 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070086
87 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080088 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -070089 mutex_unlock(&dev->struct_mutex);
90
Jesse Barnes79e53942008-11-07 14:24:08 -080091 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -070092}
93
Eric Anholt5a125c32008-10-22 21:40:13 -070094int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
Eric Anholt5a125c32008-10-22 21:40:13 -070098 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -070099
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700106
107 return 0;
108}
109
Eric Anholt673a3942008-07-30 12:06:12 -0700110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300120 int ret;
121 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
Eric Anholt40123c12009-03-09 13:42:30 -0700143static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200150 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700156 kunmap_atomic(vaddr, KM_USER0);
157
Florian Mickler2bc43b52009-04-06 22:55:41 +0200158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700162}
163
Eric Anholt280b7132009-03-12 16:56:27 -0700164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
Eric Anholteb014592009-03-10 11:44:52 -0700173static inline int
Eric Anholt40123c12009-03-09 13:42:30 -0700174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
Eric Anholt280b7132009-03-12 16:56:27 -0700200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
Eric Anholt673a3942008-07-30 12:06:12 -0700258/**
Eric Anholteb014592009-03-10 11:44:52 -0700259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
Chris Wilson4bdadb92010-01-27 13:36:32 +0000280 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholteb014592009-03-10 11:44:52 -0700281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
Chris Wilson07f73f62009-09-14 16:50:30 +0100324static int
325i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326{
327 int ret;
328
Chris Wilson4bdadb92010-01-27 13:36:32 +0000329 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
Chris Wilson07f73f62009-09-14 16:50:30 +0100330
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
333 */
334 if (ret == -ENOMEM) {
335 struct drm_device *dev = obj->dev;
Chris Wilson07f73f62009-09-14 16:50:30 +0100336
337 ret = i915_gem_evict_something(dev, obj->size);
338 if (ret)
339 return ret;
340
Chris Wilson4bdadb92010-01-27 13:36:32 +0000341 ret = i915_gem_object_get_pages(obj, 0);
Chris Wilson07f73f62009-09-14 16:50:30 +0100342 }
343
344 return ret;
345}
346
Eric Anholteb014592009-03-10 11:44:52 -0700347/**
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
352 */
353static int
354i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
355 struct drm_i915_gem_pread *args,
356 struct drm_file *file_priv)
357{
358 struct drm_i915_gem_object *obj_priv = obj->driver_private;
359 struct mm_struct *mm = current->mm;
360 struct page **user_pages;
361 ssize_t remain;
362 loff_t offset, pinned_pages, i;
363 loff_t first_data_page, last_data_page, num_pages;
364 int shmem_page_index, shmem_page_offset;
365 int data_page_index, data_page_offset;
366 int page_length;
367 int ret;
368 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700369 int do_bit17_swizzling;
Eric Anholteb014592009-03-10 11:44:52 -0700370
371 remain = args->size;
372
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
376 */
377 first_data_page = data_ptr / PAGE_SIZE;
378 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
379 num_pages = last_data_page - first_data_page + 1;
380
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700381 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholteb014592009-03-10 11:44:52 -0700382 if (user_pages == NULL)
383 return -ENOMEM;
384
385 down_read(&mm->mmap_sem);
386 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700387 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700388 up_read(&mm->mmap_sem);
389 if (pinned_pages < num_pages) {
390 ret = -EFAULT;
391 goto fail_put_user_pages;
392 }
393
Eric Anholt280b7132009-03-12 16:56:27 -0700394 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
395
Eric Anholteb014592009-03-10 11:44:52 -0700396 mutex_lock(&dev->struct_mutex);
397
Chris Wilson07f73f62009-09-14 16:50:30 +0100398 ret = i915_gem_object_get_pages_or_evict(obj);
399 if (ret)
Eric Anholteb014592009-03-10 11:44:52 -0700400 goto fail_unlock;
401
402 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
403 args->size);
404 if (ret != 0)
405 goto fail_put_pages;
406
407 obj_priv = obj->driver_private;
408 offset = args->offset;
409
410 while (remain > 0) {
411 /* Operation in this page
412 *
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
418 */
419 shmem_page_index = offset / PAGE_SIZE;
420 shmem_page_offset = offset & ~PAGE_MASK;
421 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
422 data_page_offset = data_ptr & ~PAGE_MASK;
423
424 page_length = remain;
425 if ((shmem_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - shmem_page_offset;
427 if ((data_page_offset + page_length) > PAGE_SIZE)
428 page_length = PAGE_SIZE - data_page_offset;
429
Eric Anholt280b7132009-03-12 16:56:27 -0700430 if (do_bit17_swizzling) {
431 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432 shmem_page_offset,
433 user_pages[data_page_index],
434 data_page_offset,
435 page_length,
436 1);
437 } else {
438 ret = slow_shmem_copy(user_pages[data_page_index],
439 data_page_offset,
440 obj_priv->pages[shmem_page_index],
441 shmem_page_offset,
442 page_length);
443 }
Eric Anholteb014592009-03-10 11:44:52 -0700444 if (ret)
445 goto fail_put_pages;
446
447 remain -= page_length;
448 data_ptr += page_length;
449 offset += page_length;
450 }
451
452fail_put_pages:
453 i915_gem_object_put_pages(obj);
454fail_unlock:
455 mutex_unlock(&dev->struct_mutex);
456fail_put_user_pages:
457 for (i = 0; i < pinned_pages; i++) {
458 SetPageDirty(user_pages[i]);
459 page_cache_release(user_pages[i]);
460 }
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700461 drm_free_large(user_pages);
Eric Anholteb014592009-03-10 11:44:52 -0700462
463 return ret;
464}
465
Eric Anholt673a3942008-07-30 12:06:12 -0700466/**
467 * Reads data from the object referenced by handle.
468 *
469 * On error, the contents of *data are undefined.
470 */
471int
472i915_gem_pread_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file_priv)
474{
475 struct drm_i915_gem_pread *args = data;
476 struct drm_gem_object *obj;
477 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700478 int ret;
479
480 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 if (obj == NULL)
482 return -EBADF;
483 obj_priv = obj->driver_private;
484
485 /* Bounds check source.
486 *
487 * XXX: This could use review for overflow issues...
488 */
489 if (args->offset > obj->size || args->size > obj->size ||
490 args->offset + args->size > obj->size) {
491 drm_gem_object_unreference(obj);
492 return -EINVAL;
493 }
494
Eric Anholt280b7132009-03-12 16:56:27 -0700495 if (i915_gem_object_needs_bit17_swizzle(obj)) {
Eric Anholteb014592009-03-10 11:44:52 -0700496 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt280b7132009-03-12 16:56:27 -0700497 } else {
498 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499 if (ret != 0)
500 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 file_priv);
502 }
Eric Anholt673a3942008-07-30 12:06:12 -0700503
504 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700505
Eric Anholteb014592009-03-10 11:44:52 -0700506 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700507}
508
Keith Packard0839ccb2008-10-30 19:38:48 -0700509/* This is the fast write path which cannot handle
510 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700511 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700512
Keith Packard0839ccb2008-10-30 19:38:48 -0700513static inline int
514fast_user_write(struct io_mapping *mapping,
515 loff_t page_base, int page_offset,
516 char __user *user_data,
517 int length)
518{
519 char *vaddr_atomic;
520 unsigned long unwritten;
521
522 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
523 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524 user_data, length);
525 io_mapping_unmap_atomic(vaddr_atomic);
526 if (unwritten)
527 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700528 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700529}
530
531/* Here's the write path which can sleep for
532 * page faults
533 */
534
535static inline int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700536slow_kernel_write(struct io_mapping *mapping,
537 loff_t gtt_base, int gtt_offset,
538 struct page *user_page, int user_offset,
539 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700540{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700541 char *src_vaddr, *dst_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700542 unsigned long unwritten;
543
Eric Anholt3de09aa2009-03-09 09:42:23 -0700544 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
545 src_vaddr = kmap_atomic(user_page, KM_USER1);
546 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
547 src_vaddr + user_offset,
548 length);
549 kunmap_atomic(src_vaddr, KM_USER1);
550 io_mapping_unmap_atomic(dst_vaddr);
Keith Packard0839ccb2008-10-30 19:38:48 -0700551 if (unwritten)
552 return -EFAULT;
553 return 0;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700554}
555
Eric Anholt40123c12009-03-09 13:42:30 -0700556static inline int
557fast_shmem_write(struct page **pages,
558 loff_t page_base, int page_offset,
559 char __user *data,
560 int length)
561{
562 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400563 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700564
565 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566 if (vaddr == NULL)
567 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400568 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700569 kunmap_atomic(vaddr, KM_USER0);
570
Dave Airlied0088772009-03-28 20:29:48 -0400571 if (unwritten)
572 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700573 return 0;
574}
575
Eric Anholt3de09aa2009-03-09 09:42:23 -0700576/**
577 * This is the fast pwrite path, where we copy the data directly from the
578 * user into the GTT, uncached.
579 */
Eric Anholt673a3942008-07-30 12:06:12 -0700580static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700581i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
582 struct drm_i915_gem_pwrite *args,
583 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700584{
585 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Keith Packard0839ccb2008-10-30 19:38:48 -0700586 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700587 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700588 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700589 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700590 int page_offset, page_length;
591 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700592
593 user_data = (char __user *) (uintptr_t) args->data_ptr;
594 remain = args->size;
595 if (!access_ok(VERIFY_READ, user_data, remain))
596 return -EFAULT;
597
598
599 mutex_lock(&dev->struct_mutex);
600 ret = i915_gem_object_pin(obj, 0);
601 if (ret) {
602 mutex_unlock(&dev->struct_mutex);
603 return ret;
604 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800605 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700606 if (ret)
607 goto fail;
608
609 obj_priv = obj->driver_private;
610 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700611
612 while (remain > 0) {
613 /* Operation in this page
614 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700618 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700619 page_base = (offset & ~(PAGE_SIZE-1));
620 page_offset = offset & (PAGE_SIZE-1);
621 page_length = remain;
622 if ((page_offset + remain) > PAGE_SIZE)
623 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700624
Keith Packard0839ccb2008-10-30 19:38:48 -0700625 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
626 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700627
Keith Packard0839ccb2008-10-30 19:38:48 -0700628 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700631 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700632 if (ret)
633 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700634
Keith Packard0839ccb2008-10-30 19:38:48 -0700635 remain -= page_length;
636 user_data += page_length;
637 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700638 }
Eric Anholt673a3942008-07-30 12:06:12 -0700639
640fail:
641 i915_gem_object_unpin(obj);
642 mutex_unlock(&dev->struct_mutex);
643
644 return ret;
645}
646
Eric Anholt3de09aa2009-03-09 09:42:23 -0700647/**
648 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649 * the memory and maps it using kmap_atomic for copying.
650 *
651 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 */
Eric Anholt3043c602008-10-02 12:24:47 -0700654static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700655i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700658{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700659 struct drm_i915_gem_object *obj_priv = obj->driver_private;
660 drm_i915_private_t *dev_priv = dev->dev_private;
661 ssize_t remain;
662 loff_t gtt_page_base, offset;
663 loff_t first_data_page, last_data_page, num_pages;
664 loff_t pinned_pages, i;
665 struct page **user_pages;
666 struct mm_struct *mm = current->mm;
667 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700668 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700669 uint64_t data_ptr = args->data_ptr;
670
671 remain = args->size;
672
673 /* Pin the user pages containing the data. We can't fault while
674 * holding the struct mutex, and all of the pwrite implementations
675 * want to hold it while dereferencing the user data.
676 */
677 first_data_page = data_ptr / PAGE_SIZE;
678 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
679 num_pages = last_data_page - first_data_page + 1;
680
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700681 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt3de09aa2009-03-09 09:42:23 -0700682 if (user_pages == NULL)
683 return -ENOMEM;
684
685 down_read(&mm->mmap_sem);
686 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
687 num_pages, 0, 0, user_pages, NULL);
688 up_read(&mm->mmap_sem);
689 if (pinned_pages < num_pages) {
690 ret = -EFAULT;
691 goto out_unpin_pages;
692 }
693
694 mutex_lock(&dev->struct_mutex);
695 ret = i915_gem_object_pin(obj, 0);
696 if (ret)
697 goto out_unlock;
698
699 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700 if (ret)
701 goto out_unpin_object;
702
703 obj_priv = obj->driver_private;
704 offset = obj_priv->gtt_offset + args->offset;
705
706 while (remain > 0) {
707 /* Operation in this page
708 *
709 * gtt_page_base = page offset within aperture
710 * gtt_page_offset = offset within page in aperture
711 * data_page_index = page number in get_user_pages return
712 * data_page_offset = offset with data_page_index page.
713 * page_length = bytes to copy for this page
714 */
715 gtt_page_base = offset & PAGE_MASK;
716 gtt_page_offset = offset & ~PAGE_MASK;
717 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
718 data_page_offset = data_ptr & ~PAGE_MASK;
719
720 page_length = remain;
721 if ((gtt_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - gtt_page_offset;
723 if ((data_page_offset + page_length) > PAGE_SIZE)
724 page_length = PAGE_SIZE - data_page_offset;
725
726 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
727 gtt_page_base, gtt_page_offset,
728 user_pages[data_page_index],
729 data_page_offset,
730 page_length);
731
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
735 */
736 if (ret)
737 goto out_unpin_object;
738
739 remain -= page_length;
740 offset += page_length;
741 data_ptr += page_length;
742 }
743
744out_unpin_object:
745 i915_gem_object_unpin(obj);
746out_unlock:
747 mutex_unlock(&dev->struct_mutex);
748out_unpin_pages:
749 for (i = 0; i < pinned_pages; i++)
750 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700751 drm_free_large(user_pages);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700752
753 return ret;
754}
755
Eric Anholt40123c12009-03-09 13:42:30 -0700756/**
757 * This is the fast shmem pwrite path, which attempts to directly
758 * copy_from_user into the kmapped pages backing the object.
759 */
Eric Anholt673a3942008-07-30 12:06:12 -0700760static int
Eric Anholt40123c12009-03-09 13:42:30 -0700761i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700764{
Eric Anholt40123c12009-03-09 13:42:30 -0700765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
766 ssize_t remain;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700770 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700771
772 user_data = (char __user *) (uintptr_t) args->data_ptr;
773 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700774
775 mutex_lock(&dev->struct_mutex);
776
Chris Wilson4bdadb92010-01-27 13:36:32 +0000777 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholt40123c12009-03-09 13:42:30 -0700778 if (ret != 0)
779 goto fail_unlock;
780
Eric Anholte47c68e2008-11-14 13:35:19 -0800781 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700782 if (ret != 0)
783 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700784
Eric Anholt40123c12009-03-09 13:42:30 -0700785 obj_priv = obj->driver_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700786 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700787 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700788
Eric Anholt40123c12009-03-09 13:42:30 -0700789 while (remain > 0) {
790 /* Operation in this page
791 *
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
795 */
796 page_base = (offset & ~(PAGE_SIZE-1));
797 page_offset = offset & (PAGE_SIZE-1);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
801
802 ret = fast_shmem_write(obj_priv->pages,
803 page_base, page_offset,
804 user_data, page_length);
805 if (ret)
806 goto fail_put_pages;
807
808 remain -= page_length;
809 user_data += page_length;
810 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700811 }
812
Eric Anholt40123c12009-03-09 13:42:30 -0700813fail_put_pages:
814 i915_gem_object_put_pages(obj);
815fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700816 mutex_unlock(&dev->struct_mutex);
817
Eric Anholt40123c12009-03-09 13:42:30 -0700818 return ret;
819}
820
821/**
822 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823 * the memory and maps it using kmap_atomic for copying.
824 *
825 * This avoids taking mmap_sem for faulting on the user's address while the
826 * struct_mutex is held.
827 */
828static int
829i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
830 struct drm_i915_gem_pwrite *args,
831 struct drm_file *file_priv)
832{
833 struct drm_i915_gem_object *obj_priv = obj->driver_private;
834 struct mm_struct *mm = current->mm;
835 struct page **user_pages;
836 ssize_t remain;
837 loff_t offset, pinned_pages, i;
838 loff_t first_data_page, last_data_page, num_pages;
839 int shmem_page_index, shmem_page_offset;
840 int data_page_index, data_page_offset;
841 int page_length;
842 int ret;
843 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700844 int do_bit17_swizzling;
Eric Anholt40123c12009-03-09 13:42:30 -0700845
846 remain = args->size;
847
848 /* Pin the user pages containing the data. We can't fault while
849 * holding the struct mutex, and all of the pwrite implementations
850 * want to hold it while dereferencing the user data.
851 */
852 first_data_page = data_ptr / PAGE_SIZE;
853 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
854 num_pages = last_data_page - first_data_page + 1;
855
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700856 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt40123c12009-03-09 13:42:30 -0700857 if (user_pages == NULL)
858 return -ENOMEM;
859
860 down_read(&mm->mmap_sem);
861 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
862 num_pages, 0, 0, user_pages, NULL);
863 up_read(&mm->mmap_sem);
864 if (pinned_pages < num_pages) {
865 ret = -EFAULT;
866 goto fail_put_user_pages;
867 }
868
Eric Anholt280b7132009-03-12 16:56:27 -0700869 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
870
Eric Anholt40123c12009-03-09 13:42:30 -0700871 mutex_lock(&dev->struct_mutex);
872
Chris Wilson07f73f62009-09-14 16:50:30 +0100873 ret = i915_gem_object_get_pages_or_evict(obj);
874 if (ret)
Eric Anholt40123c12009-03-09 13:42:30 -0700875 goto fail_unlock;
876
877 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 if (ret != 0)
879 goto fail_put_pages;
880
881 obj_priv = obj->driver_private;
882 offset = args->offset;
883 obj_priv->dirty = 1;
884
885 while (remain > 0) {
886 /* Operation in this page
887 *
888 * shmem_page_index = page number within shmem file
889 * shmem_page_offset = offset within page in shmem file
890 * data_page_index = page number in get_user_pages return
891 * data_page_offset = offset with data_page_index page.
892 * page_length = bytes to copy for this page
893 */
894 shmem_page_index = offset / PAGE_SIZE;
895 shmem_page_offset = offset & ~PAGE_MASK;
896 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
897 data_page_offset = data_ptr & ~PAGE_MASK;
898
899 page_length = remain;
900 if ((shmem_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - shmem_page_offset;
902 if ((data_page_offset + page_length) > PAGE_SIZE)
903 page_length = PAGE_SIZE - data_page_offset;
904
Eric Anholt280b7132009-03-12 16:56:27 -0700905 if (do_bit17_swizzling) {
906 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907 shmem_page_offset,
908 user_pages[data_page_index],
909 data_page_offset,
910 page_length,
911 0);
912 } else {
913 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914 shmem_page_offset,
915 user_pages[data_page_index],
916 data_page_offset,
917 page_length);
918 }
Eric Anholt40123c12009-03-09 13:42:30 -0700919 if (ret)
920 goto fail_put_pages;
921
922 remain -= page_length;
923 data_ptr += page_length;
924 offset += page_length;
925 }
926
927fail_put_pages:
928 i915_gem_object_put_pages(obj);
929fail_unlock:
930 mutex_unlock(&dev->struct_mutex);
931fail_put_user_pages:
932 for (i = 0; i < pinned_pages; i++)
933 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700934 drm_free_large(user_pages);
Eric Anholt40123c12009-03-09 13:42:30 -0700935
936 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700937}
938
939/**
940 * Writes data to the object referenced by handle.
941 *
942 * On error, the contents of the buffer that were to be modified are undefined.
943 */
944int
945i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv)
947{
948 struct drm_i915_gem_pwrite *args = data;
949 struct drm_gem_object *obj;
950 struct drm_i915_gem_object *obj_priv;
951 int ret = 0;
952
953 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954 if (obj == NULL)
955 return -EBADF;
956 obj_priv = obj->driver_private;
957
958 /* Bounds check destination.
959 *
960 * XXX: This could use review for overflow issues...
961 */
962 if (args->offset > obj->size || args->size > obj->size ||
963 args->offset + args->size > obj->size) {
964 drm_gem_object_unreference(obj);
965 return -EINVAL;
966 }
967
968 /* We can only do the GTT pwrite on untiled buffers, as otherwise
969 * it would end up going through the fenced access, and we'll get
970 * different detiling behavior between reading and writing.
971 * pread/pwrite currently are reading and writing from the CPU
972 * perspective, requiring manual detiling by the client.
973 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000974 if (obj_priv->phys_obj)
975 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
976 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Eric Anholt3de09aa2009-03-09 09:42:23 -0700977 dev->gtt_total != 0) {
978 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
979 if (ret == -EFAULT) {
980 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 file_priv);
982 }
Eric Anholt280b7132009-03-12 16:56:27 -0700983 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
984 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
Eric Anholt40123c12009-03-09 13:42:30 -0700985 } else {
986 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
987 if (ret == -EFAULT) {
988 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
989 file_priv);
990 }
991 }
Eric Anholt673a3942008-07-30 12:06:12 -0700992
993#if WATCH_PWRITE
994 if (ret)
995 DRM_INFO("pwrite failed %d\n", ret);
996#endif
997
998 drm_gem_object_unreference(obj);
999
1000 return ret;
1001}
1002
1003/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001004 * Called when user space prepares to use an object with the CPU, either
1005 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -07001006 */
1007int
1008i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv)
1010{
Eric Anholta09ba7f2009-08-29 12:49:51 -07001011 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07001012 struct drm_i915_gem_set_domain *args = data;
1013 struct drm_gem_object *obj;
Jesse Barnes652c3932009-08-17 13:31:43 -07001014 struct drm_i915_gem_object *obj_priv;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001015 uint32_t read_domains = args->read_domains;
1016 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07001017 int ret;
1018
1019 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 return -ENODEV;
1021
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001022 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +01001023 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001024 return -EINVAL;
1025
Chris Wilson21d509e2009-06-06 09:46:02 +01001026 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001027 return -EINVAL;
1028
1029 /* Having something in the write domain implies it's in the read
1030 * domain, and only that read domain. Enforce that in the request.
1031 */
1032 if (write_domain != 0 && read_domains != write_domain)
1033 return -EINVAL;
1034
Eric Anholt673a3942008-07-30 12:06:12 -07001035 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 if (obj == NULL)
1037 return -EBADF;
Jesse Barnes652c3932009-08-17 13:31:43 -07001038 obj_priv = obj->driver_private;
Eric Anholt673a3942008-07-30 12:06:12 -07001039
1040 mutex_lock(&dev->struct_mutex);
Jesse Barnes652c3932009-08-17 13:31:43 -07001041
1042 intel_mark_busy(dev, obj);
1043
Eric Anholt673a3942008-07-30 12:06:12 -07001044#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001045 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001046 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07001047#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001048 if (read_domains & I915_GEM_DOMAIN_GTT) {
1049 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001050
Eric Anholta09ba7f2009-08-29 12:49:51 -07001051 /* Update the LRU on the fence for the CPU access that's
1052 * about to occur.
1053 */
1054 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055 list_move_tail(&obj_priv->fence_list,
1056 &dev_priv->mm.fence_list);
1057 }
1058
Eric Anholt02354392008-11-26 13:58:13 -08001059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1062 */
1063 if (ret == -EINVAL)
1064 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001065 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001066 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001067 }
1068
Eric Anholt673a3942008-07-30 12:06:12 -07001069 drm_gem_object_unreference(obj);
1070 mutex_unlock(&dev->struct_mutex);
1071 return ret;
1072}
1073
1074/**
1075 * Called when user space has done writes to this buffer
1076 */
1077int
1078i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1080{
1081 struct drm_i915_gem_sw_finish *args = data;
1082 struct drm_gem_object *obj;
1083 struct drm_i915_gem_object *obj_priv;
1084 int ret = 0;
1085
1086 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 return -ENODEV;
1088
1089 mutex_lock(&dev->struct_mutex);
1090 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 if (obj == NULL) {
1092 mutex_unlock(&dev->struct_mutex);
1093 return -EBADF;
1094 }
1095
1096#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
Eric Anholt673a3942008-07-30 12:06:12 -07001098 __func__, args->handle, obj, obj->size);
1099#endif
1100 obj_priv = obj->driver_private;
1101
1102 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -08001103 if (obj_priv->pin_count)
1104 i915_gem_object_flush_cpu_write_domain(obj);
1105
Eric Anholt673a3942008-07-30 12:06:12 -07001106 drm_gem_object_unreference(obj);
1107 mutex_unlock(&dev->struct_mutex);
1108 return ret;
1109}
1110
1111/**
1112 * Maps the contents of an object, returning the address it is mapped
1113 * into.
1114 *
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1117 */
1118int
1119i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv)
1121{
1122 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj;
1124 loff_t offset;
1125 unsigned long addr;
1126
1127 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 return -ENODEV;
1129
1130 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131 if (obj == NULL)
1132 return -EBADF;
1133
1134 offset = args->offset;
1135
1136 down_write(&current->mm->mmap_sem);
1137 addr = do_mmap(obj->filp, 0, args->size,
1138 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 args->offset);
1140 up_write(&current->mm->mmap_sem);
1141 mutex_lock(&dev->struct_mutex);
1142 drm_gem_object_unreference(obj);
1143 mutex_unlock(&dev->struct_mutex);
1144 if (IS_ERR((void *)addr))
1145 return addr;
1146
1147 args->addr_ptr = (uint64_t) addr;
1148
1149 return 0;
1150}
1151
Jesse Barnesde151cf2008-11-12 10:03:55 -08001152/**
1153 * i915_gem_fault - fault a page into the GTT
1154 * vma: VMA in question
1155 * vmf: fault info
1156 *
1157 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158 * from userspace. The fault handler takes care of binding the object to
1159 * the GTT (if needed), allocating and programming a fence register (again,
1160 * only if needed based on whether the old reg is still valid or the object
1161 * is tiled) and inserting a new PTE into the faulting process.
1162 *
1163 * Note that the faulting process may involve evicting existing objects
1164 * from the GTT and/or fence registers to make room. So performance may
1165 * suffer if the GTT working set is large or there are few fence registers
1166 * left.
1167 */
1168int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169{
1170 struct drm_gem_object *obj = vma->vm_private_data;
1171 struct drm_device *dev = obj->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174 pgoff_t page_offset;
1175 unsigned long pfn;
1176 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001177 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001178
1179 /* We don't use vmf->pgoff since that has the fake offset */
1180 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181 PAGE_SHIFT;
1182
1183 /* Now bind it into the GTT if needed */
1184 mutex_lock(&dev->struct_mutex);
1185 if (!obj_priv->gtt_space) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001186 ret = i915_gem_object_bind_to_gtt(obj, 0);
Chris Wilsonc7150892009-09-23 00:43:56 +01001187 if (ret)
1188 goto unlock;
Kristian Høgsberg07f4f3e2009-05-27 14:37:28 -04001189
Jesse Barnes14b60392009-05-20 16:47:08 -04001190 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001191
1192 ret = i915_gem_object_set_to_gtt_domain(obj, write);
Chris Wilsonc7150892009-09-23 00:43:56 +01001193 if (ret)
1194 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001195 }
1196
1197 /* Need a new fence register? */
Eric Anholta09ba7f2009-08-29 12:49:51 -07001198 if (obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001199 ret = i915_gem_object_get_fence_reg(obj);
Chris Wilsonc7150892009-09-23 00:43:56 +01001200 if (ret)
1201 goto unlock;
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001202 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001203
1204 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205 page_offset;
1206
1207 /* Finally, remap it using the new GTT offset */
1208 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
Chris Wilsonc7150892009-09-23 00:43:56 +01001209unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001210 mutex_unlock(&dev->struct_mutex);
1211
1212 switch (ret) {
Chris Wilsonc7150892009-09-23 00:43:56 +01001213 case 0:
1214 case -ERESTARTSYS:
1215 return VM_FAULT_NOPAGE;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001216 case -ENOMEM:
1217 case -EAGAIN:
1218 return VM_FAULT_OOM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001219 default:
Chris Wilsonc7150892009-09-23 00:43:56 +01001220 return VM_FAULT_SIGBUS;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001221 }
1222}
1223
1224/**
1225 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226 * @obj: obj in question
1227 *
1228 * GEM memory mapping works by handing back to userspace a fake mmap offset
1229 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1230 * up the object based on the offset and sets up the various memory mapping
1231 * structures.
1232 *
1233 * This routine allocates and attaches a fake offset for @obj.
1234 */
1235static int
1236i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1237{
1238 struct drm_device *dev = obj->dev;
1239 struct drm_gem_mm *mm = dev->mm_private;
1240 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001242 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001243 int ret = 0;
1244
1245 /* Set the object up for mmap'ing */
1246 list = &obj->map_list;
Eric Anholt9a298b22009-03-24 12:23:04 -07001247 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001248 if (!list->map)
1249 return -ENOMEM;
1250
1251 map = list->map;
1252 map->type = _DRM_GEM;
1253 map->size = obj->size;
1254 map->handle = obj;
1255
1256 /* Get a DRM GEM mmap offset allocated... */
1257 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258 obj->size / PAGE_SIZE, 0, 0);
1259 if (!list->file_offset_node) {
1260 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261 ret = -ENOMEM;
1262 goto out_free_list;
1263 }
1264
1265 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266 obj->size / PAGE_SIZE, 0);
1267 if (!list->file_offset_node) {
1268 ret = -ENOMEM;
1269 goto out_free_list;
1270 }
1271
1272 list->hash.key = list->file_offset_node->start;
1273 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274 DRM_ERROR("failed to add to map hash\n");
Chris Wilson5618ca62009-12-02 15:15:30 +00001275 ret = -ENOMEM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001276 goto out_free_mm;
1277 }
1278
1279 /* By now we should be all set, any drm_mmap request on the offset
1280 * below will get to our mmap & fault handler */
1281 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282
1283 return 0;
1284
1285out_free_mm:
1286 drm_mm_put_block(list->file_offset_node);
1287out_free_list:
Eric Anholt9a298b22009-03-24 12:23:04 -07001288 kfree(list->map);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001289
1290 return ret;
1291}
1292
Chris Wilson901782b2009-07-10 08:18:50 +01001293/**
1294 * i915_gem_release_mmap - remove physical page mappings
1295 * @obj: obj in question
1296 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001297 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001298 * relinquish ownership of the pages back to the system.
1299 *
1300 * It is vital that we remove the page mapping if we have mapped a tiled
1301 * object through the GTT and then lose the fence register due to
1302 * resource pressure. Similarly if the object has been moved out of the
1303 * aperture, than pages mapped into userspace must be revoked. Removing the
1304 * mapping will then trigger a page fault on the next user access, allowing
1305 * fixup by i915_gem_fault().
1306 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001307void
Chris Wilson901782b2009-07-10 08:18:50 +01001308i915_gem_release_mmap(struct drm_gem_object *obj)
1309{
1310 struct drm_device *dev = obj->dev;
1311 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1312
1313 if (dev->dev_mapping)
1314 unmap_mapping_range(dev->dev_mapping,
1315 obj_priv->mmap_offset, obj->size, 1);
1316}
1317
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001318static void
1319i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1320{
1321 struct drm_device *dev = obj->dev;
1322 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323 struct drm_gem_mm *mm = dev->mm_private;
1324 struct drm_map_list *list;
1325
1326 list = &obj->map_list;
1327 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1328
1329 if (list->file_offset_node) {
1330 drm_mm_put_block(list->file_offset_node);
1331 list->file_offset_node = NULL;
1332 }
1333
1334 if (list->map) {
Eric Anholt9a298b22009-03-24 12:23:04 -07001335 kfree(list->map);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001336 list->map = NULL;
1337 }
1338
1339 obj_priv->mmap_offset = 0;
1340}
1341
Jesse Barnesde151cf2008-11-12 10:03:55 -08001342/**
1343 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344 * @obj: object to check
1345 *
1346 * Return the required GTT alignment for an object, taking into account
1347 * potential fence register mapping if needed.
1348 */
1349static uint32_t
1350i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1351{
1352 struct drm_device *dev = obj->dev;
1353 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354 int start, i;
1355
1356 /*
1357 * Minimum alignment is 4k (GTT page size), but might be greater
1358 * if a fence register is needed for the object.
1359 */
1360 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 return 4096;
1362
1363 /*
1364 * Previous chips need to be aligned to the size of the smallest
1365 * fence register that can contain the object.
1366 */
1367 if (IS_I9XX(dev))
1368 start = 1024*1024;
1369 else
1370 start = 512*1024;
1371
1372 for (i = start; i < obj->size; i <<= 1)
1373 ;
1374
1375 return i;
1376}
1377
1378/**
1379 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380 * @dev: DRM device
1381 * @data: GTT mapping ioctl data
1382 * @file_priv: GEM object info
1383 *
1384 * Simply returns the fake offset to userspace so it can mmap it.
1385 * The mmap call will end up in drm_gem_mmap(), which will set things
1386 * up so we can get faults in the handler above.
1387 *
1388 * The fault handler will take care of binding the object into the GTT
1389 * (since it may have been evicted to make room for something), allocating
1390 * a fence register, and mapping the appropriate aperture address into
1391 * userspace.
1392 */
1393int
1394i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv)
1396{
1397 struct drm_i915_gem_mmap_gtt *args = data;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct drm_gem_object *obj;
1400 struct drm_i915_gem_object *obj_priv;
1401 int ret;
1402
1403 if (!(dev->driver->driver_features & DRIVER_GEM))
1404 return -ENODEV;
1405
1406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 if (obj == NULL)
1408 return -EBADF;
1409
1410 mutex_lock(&dev->struct_mutex);
1411
1412 obj_priv = obj->driver_private;
1413
Chris Wilsonab182822009-09-22 18:46:17 +01001414 if (obj_priv->madv != I915_MADV_WILLNEED) {
1415 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1418 return -EINVAL;
1419 }
1420
1421
Jesse Barnesde151cf2008-11-12 10:03:55 -08001422 if (!obj_priv->mmap_offset) {
1423 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001424 if (ret) {
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001427 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001428 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001429 }
1430
1431 args->offset = obj_priv->mmap_offset;
1432
Jesse Barnesde151cf2008-11-12 10:03:55 -08001433 /*
1434 * Pull it into the GTT so that we have a page list (makes the
1435 * initial fault faster and any subsequent flushing possible).
1436 */
1437 if (!obj_priv->agp_mem) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001438 ret = i915_gem_object_bind_to_gtt(obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001439 if (ret) {
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
1442 return ret;
1443 }
Jesse Barnes14b60392009-05-20 16:47:08 -04001444 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001445 }
1446
1447 drm_gem_object_unreference(obj);
1448 mutex_unlock(&dev->struct_mutex);
1449
1450 return 0;
1451}
1452
Ben Gamari6911a9b2009-04-02 11:24:54 -07001453void
Eric Anholt856fa192009-03-19 14:10:50 -07001454i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001455{
1456 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457 int page_count = obj->size / PAGE_SIZE;
1458 int i;
1459
Eric Anholt856fa192009-03-19 14:10:50 -07001460 BUG_ON(obj_priv->pages_refcount == 0);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001461 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001462
1463 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001464 return;
1465
Eric Anholt280b7132009-03-12 16:56:27 -07001466 if (obj_priv->tiling_mode != I915_TILING_NONE)
1467 i915_gem_object_save_bit_17_swizzle(obj);
1468
Chris Wilson3ef94da2009-09-14 16:50:29 +01001469 if (obj_priv->madv == I915_MADV_DONTNEED)
Chris Wilson13a05fd2009-09-20 23:03:19 +01001470 obj_priv->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001471
1472 for (i = 0; i < page_count; i++) {
1473 if (obj_priv->pages[i] == NULL)
1474 break;
1475
1476 if (obj_priv->dirty)
1477 set_page_dirty(obj_priv->pages[i]);
1478
1479 if (obj_priv->madv == I915_MADV_WILLNEED)
Eric Anholt856fa192009-03-19 14:10:50 -07001480 mark_page_accessed(obj_priv->pages[i]);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001481
1482 page_cache_release(obj_priv->pages[i]);
1483 }
Eric Anholt673a3942008-07-30 12:06:12 -07001484 obj_priv->dirty = 0;
1485
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07001486 drm_free_large(obj_priv->pages);
Eric Anholt856fa192009-03-19 14:10:50 -07001487 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001488}
1489
1490static void
Eric Anholtce44b0e2008-11-06 16:00:31 -08001491i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
Eric Anholt673a3942008-07-30 12:06:12 -07001492{
1493 struct drm_device *dev = obj->dev;
1494 drm_i915_private_t *dev_priv = dev->dev_private;
1495 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1496
1497 /* Add a reference if we're newly entering the active list. */
1498 if (!obj_priv->active) {
1499 drm_gem_object_reference(obj);
1500 obj_priv->active = 1;
1501 }
1502 /* Move from whatever list we were on to the tail of execution. */
Carl Worth5e118f42009-03-20 11:54:25 -07001503 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001504 list_move_tail(&obj_priv->list,
1505 &dev_priv->mm.active_list);
Carl Worth5e118f42009-03-20 11:54:25 -07001506 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001507 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001508}
1509
Eric Anholtce44b0e2008-11-06 16:00:31 -08001510static void
1511i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1512{
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1516
1517 BUG_ON(!obj_priv->active);
1518 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519 obj_priv->last_rendering_seqno = 0;
1520}
Eric Anholt673a3942008-07-30 12:06:12 -07001521
Chris Wilson963b4832009-09-20 23:03:54 +01001522/* Immediately discard the backing storage */
1523static void
1524i915_gem_object_truncate(struct drm_gem_object *obj)
1525{
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527 struct inode *inode;
Chris Wilson963b4832009-09-20 23:03:54 +01001528
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001529 inode = obj->filp->f_path.dentry->d_inode;
1530 if (inode->i_op->truncate)
1531 inode->i_op->truncate (inode);
1532
1533 obj_priv->madv = __I915_MADV_PURGED;
Chris Wilson963b4832009-09-20 23:03:54 +01001534}
1535
1536static inline int
1537i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1538{
1539 return obj_priv->madv == I915_MADV_DONTNEED;
1540}
1541
Eric Anholt673a3942008-07-30 12:06:12 -07001542static void
1543i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1544{
1545 struct drm_device *dev = obj->dev;
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1548
1549 i915_verify_inactive(dev, __FILE__, __LINE__);
1550 if (obj_priv->pin_count != 0)
1551 list_del_init(&obj_priv->list);
1552 else
1553 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1554
Daniel Vetter99fcb762010-02-07 16:20:18 +01001555 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1556
Eric Anholtce44b0e2008-11-06 16:00:31 -08001557 obj_priv->last_rendering_seqno = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001558 if (obj_priv->active) {
1559 obj_priv->active = 0;
1560 drm_gem_object_unreference(obj);
1561 }
1562 i915_verify_inactive(dev, __FILE__, __LINE__);
1563}
1564
1565/**
1566 * Creates a new sequence number, emitting a write of it to the status page
1567 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1568 *
1569 * Must be called with struct_lock held.
1570 *
1571 * Returned sequence numbers are nonzero on success.
1572 */
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001573uint32_t
Eric Anholtb9624422009-06-03 07:27:35 +00001574i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1575 uint32_t flush_domains)
Eric Anholt673a3942008-07-30 12:06:12 -07001576{
1577 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00001578 struct drm_i915_file_private *i915_file_priv = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001579 struct drm_i915_gem_request *request;
1580 uint32_t seqno;
1581 int was_empty;
1582 RING_LOCALS;
1583
Eric Anholtb9624422009-06-03 07:27:35 +00001584 if (file_priv != NULL)
1585 i915_file_priv = file_priv->driver_priv;
1586
Eric Anholt9a298b22009-03-24 12:23:04 -07001587 request = kzalloc(sizeof(*request), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07001588 if (request == NULL)
1589 return 0;
1590
1591 /* Grab the seqno we're going to make this request be, and bump the
1592 * next (skipping 0 so it can be the reserved no-seqno value).
1593 */
1594 seqno = dev_priv->mm.next_gem_seqno;
1595 dev_priv->mm.next_gem_seqno++;
1596 if (dev_priv->mm.next_gem_seqno == 0)
1597 dev_priv->mm.next_gem_seqno++;
1598
1599 BEGIN_LP_RING(4);
1600 OUT_RING(MI_STORE_DWORD_INDEX);
1601 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1602 OUT_RING(seqno);
1603
1604 OUT_RING(MI_USER_INTERRUPT);
1605 ADVANCE_LP_RING();
1606
Zhao Yakui44d98a62009-10-09 11:39:40 +08001607 DRM_DEBUG_DRIVER("%d\n", seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001608
1609 request->seqno = seqno;
1610 request->emitted_jiffies = jiffies;
Eric Anholt673a3942008-07-30 12:06:12 -07001611 was_empty = list_empty(&dev_priv->mm.request_list);
1612 list_add_tail(&request->list, &dev_priv->mm.request_list);
Eric Anholtb9624422009-06-03 07:27:35 +00001613 if (i915_file_priv) {
1614 list_add_tail(&request->client_list,
1615 &i915_file_priv->mm.request_list);
1616 } else {
1617 INIT_LIST_HEAD(&request->client_list);
1618 }
Eric Anholt673a3942008-07-30 12:06:12 -07001619
Eric Anholtce44b0e2008-11-06 16:00:31 -08001620 /* Associate any objects on the flushing list matching the write
1621 * domain we're flushing with our flush.
1622 */
1623 if (flush_domains != 0) {
1624 struct drm_i915_gem_object *obj_priv, *next;
1625
1626 list_for_each_entry_safe(obj_priv, next,
Daniel Vetter99fcb762010-02-07 16:20:18 +01001627 &dev_priv->mm.gpu_write_list,
1628 gpu_write_list) {
Eric Anholtce44b0e2008-11-06 16:00:31 -08001629 struct drm_gem_object *obj = obj_priv->obj;
1630
1631 if ((obj->write_domain & flush_domains) ==
1632 obj->write_domain) {
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001633 uint32_t old_write_domain = obj->write_domain;
1634
Eric Anholtce44b0e2008-11-06 16:00:31 -08001635 obj->write_domain = 0;
Daniel Vetter99fcb762010-02-07 16:20:18 +01001636 list_del_init(&obj_priv->gpu_write_list);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001637 i915_gem_object_move_to_active(obj, seqno);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001638
1639 trace_i915_gem_object_change_domain(obj,
1640 obj->read_domains,
1641 old_write_domain);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001642 }
1643 }
1644
1645 }
1646
Ben Gamarif65d9422009-09-14 17:48:44 -04001647 if (!dev_priv->mm.suspended) {
1648 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1649 if (was_empty)
1650 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1651 }
Eric Anholt673a3942008-07-30 12:06:12 -07001652 return seqno;
1653}
1654
1655/**
1656 * Command execution barrier
1657 *
1658 * Ensures that all commands in the ring are finished
1659 * before signalling the CPU
1660 */
Eric Anholt3043c602008-10-02 12:24:47 -07001661static uint32_t
Eric Anholt673a3942008-07-30 12:06:12 -07001662i915_retire_commands(struct drm_device *dev)
1663{
1664 drm_i915_private_t *dev_priv = dev->dev_private;
1665 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1666 uint32_t flush_domains = 0;
1667 RING_LOCALS;
1668
1669 /* The sampler always gets flushed on i965 (sigh) */
1670 if (IS_I965G(dev))
1671 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1672 BEGIN_LP_RING(2);
1673 OUT_RING(cmd);
1674 OUT_RING(0); /* noop */
1675 ADVANCE_LP_RING();
1676 return flush_domains;
1677}
1678
1679/**
1680 * Moves buffers associated only with the given active seqno from the active
1681 * to inactive list, potentially freeing them.
1682 */
1683static void
1684i915_gem_retire_request(struct drm_device *dev,
1685 struct drm_i915_gem_request *request)
1686{
1687 drm_i915_private_t *dev_priv = dev->dev_private;
1688
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001689 trace_i915_gem_request_retire(dev, request->seqno);
1690
Eric Anholt673a3942008-07-30 12:06:12 -07001691 /* Move any buffers on the active list that are no longer referenced
1692 * by the ringbuffer to the flushing/inactive lists as appropriate.
1693 */
Carl Worth5e118f42009-03-20 11:54:25 -07001694 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001695 while (!list_empty(&dev_priv->mm.active_list)) {
1696 struct drm_gem_object *obj;
1697 struct drm_i915_gem_object *obj_priv;
1698
1699 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1700 struct drm_i915_gem_object,
1701 list);
1702 obj = obj_priv->obj;
1703
1704 /* If the seqno being retired doesn't match the oldest in the
1705 * list, then the oldest in the list must still be newer than
1706 * this seqno.
1707 */
1708 if (obj_priv->last_rendering_seqno != request->seqno)
Carl Worth5e118f42009-03-20 11:54:25 -07001709 goto out;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001710
Eric Anholt673a3942008-07-30 12:06:12 -07001711#if WATCH_LRU
1712 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1713 __func__, request->seqno, obj);
1714#endif
1715
Eric Anholtce44b0e2008-11-06 16:00:31 -08001716 if (obj->write_domain != 0)
1717 i915_gem_object_move_to_flushing(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001718 else {
1719 /* Take a reference on the object so it won't be
1720 * freed while the spinlock is held. The list
1721 * protection for this spinlock is safe when breaking
1722 * the lock like this since the next thing we do
1723 * is just get the head of the list again.
1724 */
1725 drm_gem_object_reference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001726 i915_gem_object_move_to_inactive(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001727 spin_unlock(&dev_priv->mm.active_list_lock);
1728 drm_gem_object_unreference(obj);
1729 spin_lock(&dev_priv->mm.active_list_lock);
1730 }
Eric Anholt673a3942008-07-30 12:06:12 -07001731 }
Carl Worth5e118f42009-03-20 11:54:25 -07001732out:
1733 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001734}
1735
1736/**
1737 * Returns true if seq1 is later than seq2.
1738 */
Ben Gamari22be1722009-09-14 17:48:43 -04001739bool
Eric Anholt673a3942008-07-30 12:06:12 -07001740i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1741{
1742 return (int32_t)(seq1 - seq2) >= 0;
1743}
1744
1745uint32_t
1746i915_get_gem_seqno(struct drm_device *dev)
1747{
1748 drm_i915_private_t *dev_priv = dev->dev_private;
1749
1750 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1751}
1752
1753/**
1754 * This function clears the request list as sequence numbers are passed.
1755 */
1756void
1757i915_gem_retire_requests(struct drm_device *dev)
1758{
1759 drm_i915_private_t *dev_priv = dev->dev_private;
1760 uint32_t seqno;
1761
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001762 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001763 return;
1764
Eric Anholt673a3942008-07-30 12:06:12 -07001765 seqno = i915_get_gem_seqno(dev);
1766
1767 while (!list_empty(&dev_priv->mm.request_list)) {
1768 struct drm_i915_gem_request *request;
1769 uint32_t retiring_seqno;
1770
1771 request = list_first_entry(&dev_priv->mm.request_list,
1772 struct drm_i915_gem_request,
1773 list);
1774 retiring_seqno = request->seqno;
1775
1776 if (i915_seqno_passed(seqno, retiring_seqno) ||
Ben Gamariba1234d2009-09-14 17:48:47 -04001777 atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001778 i915_gem_retire_request(dev, request);
1779
1780 list_del(&request->list);
Eric Anholtb9624422009-06-03 07:27:35 +00001781 list_del(&request->client_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07001782 kfree(request);
Eric Anholt673a3942008-07-30 12:06:12 -07001783 } else
1784 break;
1785 }
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001786
1787 if (unlikely (dev_priv->trace_irq_seqno &&
1788 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1789 i915_user_irq_put(dev);
1790 dev_priv->trace_irq_seqno = 0;
1791 }
Eric Anholt673a3942008-07-30 12:06:12 -07001792}
1793
1794void
1795i915_gem_retire_work_handler(struct work_struct *work)
1796{
1797 drm_i915_private_t *dev_priv;
1798 struct drm_device *dev;
1799
1800 dev_priv = container_of(work, drm_i915_private_t,
1801 mm.retire_work.work);
1802 dev = dev_priv->dev;
1803
1804 mutex_lock(&dev->struct_mutex);
1805 i915_gem_retire_requests(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07001806 if (!dev_priv->mm.suspended &&
1807 !list_empty(&dev_priv->mm.request_list))
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07001808 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
Eric Anholt673a3942008-07-30 12:06:12 -07001809 mutex_unlock(&dev->struct_mutex);
1810}
1811
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001812int
Daniel Vetter48764bf2009-09-15 22:57:32 +02001813i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
Eric Anholt673a3942008-07-30 12:06:12 -07001814{
1815 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001816 u32 ier;
Eric Anholt673a3942008-07-30 12:06:12 -07001817 int ret = 0;
1818
1819 BUG_ON(seqno == 0);
1820
Ben Gamariba1234d2009-09-14 17:48:47 -04001821 if (atomic_read(&dev_priv->mm.wedged))
Ben Gamariffed1d02009-09-14 17:48:41 -04001822 return -EIO;
1823
Eric Anholt673a3942008-07-30 12:06:12 -07001824 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001825 if (IS_IRONLAKE(dev))
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001826 ier = I915_READ(DEIER) | I915_READ(GTIER);
1827 else
1828 ier = I915_READ(IER);
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001829 if (!ier) {
1830 DRM_ERROR("something (likely vbetool) disabled "
1831 "interrupts, re-enabling\n");
1832 i915_driver_irq_preinstall(dev);
1833 i915_driver_irq_postinstall(dev);
1834 }
1835
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001836 trace_i915_gem_request_wait_begin(dev, seqno);
1837
Eric Anholt673a3942008-07-30 12:06:12 -07001838 dev_priv->mm.waiting_gem_seqno = seqno;
1839 i915_user_irq_get(dev);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001840 if (interruptible)
1841 ret = wait_event_interruptible(dev_priv->irq_queue,
1842 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1843 atomic_read(&dev_priv->mm.wedged));
1844 else
1845 wait_event(dev_priv->irq_queue,
1846 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1847 atomic_read(&dev_priv->mm.wedged));
1848
Eric Anholt673a3942008-07-30 12:06:12 -07001849 i915_user_irq_put(dev);
1850 dev_priv->mm.waiting_gem_seqno = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001851
1852 trace_i915_gem_request_wait_end(dev, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001853 }
Ben Gamariba1234d2009-09-14 17:48:47 -04001854 if (atomic_read(&dev_priv->mm.wedged))
Eric Anholt673a3942008-07-30 12:06:12 -07001855 ret = -EIO;
1856
1857 if (ret && ret != -ERESTARTSYS)
1858 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1859 __func__, ret, seqno, i915_get_gem_seqno(dev));
1860
1861 /* Directly dispatch request retiring. While we have the work queue
1862 * to handle this, the waiter on a request often wants an associated
1863 * buffer to have made it to the inactive list, and we would need
1864 * a separate wait queue to handle that.
1865 */
1866 if (ret == 0)
1867 i915_gem_retire_requests(dev);
1868
1869 return ret;
1870}
1871
Daniel Vetter48764bf2009-09-15 22:57:32 +02001872/**
1873 * Waits for a sequence number to be signaled, and cleans up the
1874 * request and object lists appropriately for that event.
1875 */
1876static int
1877i915_wait_request(struct drm_device *dev, uint32_t seqno)
1878{
1879 return i915_do_wait_request(dev, seqno, 1);
1880}
1881
Eric Anholt673a3942008-07-30 12:06:12 -07001882static void
1883i915_gem_flush(struct drm_device *dev,
1884 uint32_t invalidate_domains,
1885 uint32_t flush_domains)
1886{
1887 drm_i915_private_t *dev_priv = dev->dev_private;
1888 uint32_t cmd;
1889 RING_LOCALS;
1890
1891#if WATCH_EXEC
1892 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1893 invalidate_domains, flush_domains);
1894#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001895 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1896 invalidate_domains, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001897
1898 if (flush_domains & I915_GEM_DOMAIN_CPU)
1899 drm_agp_chipset_flush(dev);
1900
Chris Wilson21d509e2009-06-06 09:46:02 +01001901 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
Eric Anholt673a3942008-07-30 12:06:12 -07001902 /*
1903 * read/write caches:
1904 *
1905 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1907 * also flushed at 2d versus 3d pipeline switches.
1908 *
1909 * read-only caches:
1910 *
1911 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912 * MI_READ_FLUSH is set, and is always flushed on 965.
1913 *
1914 * I915_GEM_DOMAIN_COMMAND may not exist?
1915 *
1916 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917 * invalidated when MI_EXE_FLUSH is set.
1918 *
1919 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920 * invalidated with every MI_FLUSH.
1921 *
1922 * TLBs:
1923 *
1924 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927 * are flushed at any MI_FLUSH.
1928 */
1929
1930 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1931 if ((invalidate_domains|flush_domains) &
1932 I915_GEM_DOMAIN_RENDER)
1933 cmd &= ~MI_NO_WRITE_FLUSH;
1934 if (!IS_I965G(dev)) {
1935 /*
1936 * On the 965, the sampler cache always gets flushed
1937 * and this bit is reserved.
1938 */
1939 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1940 cmd |= MI_READ_FLUSH;
1941 }
1942 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1943 cmd |= MI_EXE_FLUSH;
1944
1945#if WATCH_EXEC
1946 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1947#endif
1948 BEGIN_LP_RING(2);
1949 OUT_RING(cmd);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001950 OUT_RING(MI_NOOP);
Eric Anholt673a3942008-07-30 12:06:12 -07001951 ADVANCE_LP_RING();
1952 }
1953}
1954
1955/**
1956 * Ensures that all rendering to the object has completed and the object is
1957 * safe to unbind from the GTT or access from the CPU.
1958 */
1959static int
1960i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961{
1962 struct drm_device *dev = obj->dev;
1963 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1964 int ret;
1965
Eric Anholte47c68e2008-11-14 13:35:19 -08001966 /* This function only exists to support waiting for existing rendering,
1967 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001968 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001969 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001970
1971 /* If there is rendering queued on the buffer being evicted, wait for
1972 * it.
1973 */
1974 if (obj_priv->active) {
1975#if WATCH_BUF
1976 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977 __func__, obj, obj_priv->last_rendering_seqno);
1978#endif
1979 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1980 if (ret != 0)
1981 return ret;
1982 }
1983
1984 return 0;
1985}
1986
1987/**
1988 * Unbinds an object from the GTT aperture.
1989 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001990int
Eric Anholt673a3942008-07-30 12:06:12 -07001991i915_gem_object_unbind(struct drm_gem_object *obj)
1992{
1993 struct drm_device *dev = obj->dev;
1994 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1995 int ret = 0;
1996
1997#if WATCH_BUF
1998 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1999 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000#endif
2001 if (obj_priv->gtt_space == NULL)
2002 return 0;
2003
2004 if (obj_priv->pin_count != 0) {
2005 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006 return -EINVAL;
2007 }
2008
Eric Anholt5323fd02009-09-09 11:50:45 -07002009 /* blow away mappings if mapped through GTT */
2010 i915_gem_release_mmap(obj);
2011
Eric Anholt673a3942008-07-30 12:06:12 -07002012 /* Move the object to the CPU domain to ensure that
2013 * any possible CPU writes while it's not in the GTT
2014 * are flushed when we go to remap it. This will
2015 * also ensure that all pending GPU writes are finished
2016 * before we unbind.
2017 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002018 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07002019 if (ret) {
Eric Anholte47c68e2008-11-14 13:35:19 -08002020 if (ret != -ERESTARTSYS)
2021 DRM_ERROR("set_domain failed: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07002022 return ret;
2023 }
2024
Eric Anholt5323fd02009-09-09 11:50:45 -07002025 BUG_ON(obj_priv->active);
2026
Daniel Vetter96b47b62009-12-15 17:50:00 +01002027 /* release the fence reg _after_ flushing */
2028 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2029 i915_gem_clear_fence_reg(obj);
2030
Eric Anholt673a3942008-07-30 12:06:12 -07002031 if (obj_priv->agp_mem != NULL) {
2032 drm_unbind_agp(obj_priv->agp_mem);
2033 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2034 obj_priv->agp_mem = NULL;
2035 }
2036
Eric Anholt856fa192009-03-19 14:10:50 -07002037 i915_gem_object_put_pages(obj);
Chris Wilsona32808c2009-09-20 21:29:47 +01002038 BUG_ON(obj_priv->pages_refcount);
Eric Anholt673a3942008-07-30 12:06:12 -07002039
2040 if (obj_priv->gtt_space) {
2041 atomic_dec(&dev->gtt_count);
2042 atomic_sub(obj->size, &dev->gtt_memory);
2043
2044 drm_mm_put_block(obj_priv->gtt_space);
2045 obj_priv->gtt_space = NULL;
2046 }
2047
2048 /* Remove ourselves from the LRU list if present. */
2049 if (!list_empty(&obj_priv->list))
2050 list_del_init(&obj_priv->list);
2051
Chris Wilson963b4832009-09-20 23:03:54 +01002052 if (i915_gem_object_is_purgeable(obj_priv))
2053 i915_gem_object_truncate(obj);
2054
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002055 trace_i915_gem_object_unbind(obj);
2056
Eric Anholt673a3942008-07-30 12:06:12 -07002057 return 0;
2058}
2059
Chris Wilson07f73f62009-09-14 16:50:30 +01002060static struct drm_gem_object *
2061i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2062{
2063 drm_i915_private_t *dev_priv = dev->dev_private;
2064 struct drm_i915_gem_object *obj_priv;
2065 struct drm_gem_object *best = NULL;
2066 struct drm_gem_object *first = NULL;
2067
2068 /* Try to find the smallest clean object */
2069 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2070 struct drm_gem_object *obj = obj_priv->obj;
2071 if (obj->size >= min_size) {
Chris Wilson963b4832009-09-20 23:03:54 +01002072 if ((!obj_priv->dirty ||
2073 i915_gem_object_is_purgeable(obj_priv)) &&
Chris Wilson07f73f62009-09-14 16:50:30 +01002074 (!best || obj->size < best->size)) {
2075 best = obj;
2076 if (best->size == min_size)
2077 return best;
2078 }
2079 if (!first)
2080 first = obj;
2081 }
2082 }
2083
2084 return best ? best : first;
2085}
2086
Eric Anholt673a3942008-07-30 12:06:12 -07002087static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002088i915_gem_evict_everything(struct drm_device *dev)
2089{
2090 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson07f73f62009-09-14 16:50:30 +01002091 int ret;
Daniel Vetter99fcb762010-02-07 16:20:18 +01002092 uint32_t seqno;
Chris Wilson07f73f62009-09-14 16:50:30 +01002093 bool lists_empty;
2094
Chris Wilson07f73f62009-09-14 16:50:30 +01002095 spin_lock(&dev_priv->mm.active_list_lock);
2096 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097 list_empty(&dev_priv->mm.flushing_list) &&
2098 list_empty(&dev_priv->mm.active_list));
2099 spin_unlock(&dev_priv->mm.active_list_lock);
2100
Chris Wilson97311292009-09-21 00:22:34 +01002101 if (lists_empty)
Chris Wilson07f73f62009-09-14 16:50:30 +01002102 return -ENOSPC;
Chris Wilson07f73f62009-09-14 16:50:30 +01002103
2104 /* Flush everything (on to the inactive lists) and evict */
2105 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2106 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2107 if (seqno == 0)
2108 return -ENOMEM;
2109
2110 ret = i915_wait_request(dev, seqno);
2111 if (ret)
2112 return ret;
2113
Daniel Vetter99fcb762010-02-07 16:20:18 +01002114 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2115
Chris Wilsonab5ee572009-09-20 19:25:47 +01002116 ret = i915_gem_evict_from_inactive_list(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01002117 if (ret)
2118 return ret;
2119
2120 spin_lock(&dev_priv->mm.active_list_lock);
2121 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2122 list_empty(&dev_priv->mm.flushing_list) &&
2123 list_empty(&dev_priv->mm.active_list));
2124 spin_unlock(&dev_priv->mm.active_list_lock);
2125 BUG_ON(!lists_empty);
2126
Eric Anholt673a3942008-07-30 12:06:12 -07002127 return 0;
2128}
2129
2130static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002131i915_gem_evict_something(struct drm_device *dev, int min_size)
Eric Anholt673a3942008-07-30 12:06:12 -07002132{
2133 drm_i915_private_t *dev_priv = dev->dev_private;
2134 struct drm_gem_object *obj;
Chris Wilson07f73f62009-09-14 16:50:30 +01002135 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002136
2137 for (;;) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002138 i915_gem_retire_requests(dev);
2139
Eric Anholt673a3942008-07-30 12:06:12 -07002140 /* If there's an inactive buffer available now, grab it
2141 * and be done.
2142 */
Chris Wilson07f73f62009-09-14 16:50:30 +01002143 obj = i915_gem_find_inactive_object(dev, min_size);
2144 if (obj) {
2145 struct drm_i915_gem_object *obj_priv;
2146
Eric Anholt673a3942008-07-30 12:06:12 -07002147#if WATCH_LRU
2148 DRM_INFO("%s: evicting %p\n", __func__, obj);
2149#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002150 obj_priv = obj->driver_private;
2151 BUG_ON(obj_priv->pin_count != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07002152 BUG_ON(obj_priv->active);
2153
2154 /* Wait on the rendering and unbind the buffer. */
Chris Wilson07f73f62009-09-14 16:50:30 +01002155 return i915_gem_object_unbind(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002156 }
2157
2158 /* If we didn't get anything, but the ring is still processing
Chris Wilson07f73f62009-09-14 16:50:30 +01002159 * things, wait for the next to finish and hopefully leave us
2160 * a buffer to evict.
Eric Anholt673a3942008-07-30 12:06:12 -07002161 */
2162 if (!list_empty(&dev_priv->mm.request_list)) {
2163 struct drm_i915_gem_request *request;
2164
2165 request = list_first_entry(&dev_priv->mm.request_list,
2166 struct drm_i915_gem_request,
2167 list);
2168
2169 ret = i915_wait_request(dev, request->seqno);
2170 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002171 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002172
Chris Wilson07f73f62009-09-14 16:50:30 +01002173 continue;
Eric Anholt673a3942008-07-30 12:06:12 -07002174 }
2175
2176 /* If we didn't have anything on the request list but there
2177 * are buffers awaiting a flush, emit one and try again.
2178 * When we wait on it, those buffers waiting for that flush
2179 * will get moved to inactive.
2180 */
2181 if (!list_empty(&dev_priv->mm.flushing_list)) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002182 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002183
Chris Wilson9a1e2582009-09-20 20:16:50 +01002184 /* Find an object that we can immediately reuse */
2185 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2186 obj = obj_priv->obj;
2187 if (obj->size >= min_size)
2188 break;
Eric Anholt673a3942008-07-30 12:06:12 -07002189
Chris Wilson9a1e2582009-09-20 20:16:50 +01002190 obj = NULL;
2191 }
Eric Anholt673a3942008-07-30 12:06:12 -07002192
Chris Wilson9a1e2582009-09-20 20:16:50 +01002193 if (obj != NULL) {
2194 uint32_t seqno;
Chris Wilson07f73f62009-09-14 16:50:30 +01002195
Chris Wilson9a1e2582009-09-20 20:16:50 +01002196 i915_gem_flush(dev,
2197 obj->write_domain,
2198 obj->write_domain);
2199 seqno = i915_add_request(dev, NULL, obj->write_domain);
2200 if (seqno == 0)
2201 return -ENOMEM;
2202
2203 ret = i915_wait_request(dev, seqno);
2204 if (ret)
2205 return ret;
2206
2207 continue;
2208 }
Eric Anholt673a3942008-07-30 12:06:12 -07002209 }
2210
Chris Wilson07f73f62009-09-14 16:50:30 +01002211 /* If we didn't do any of the above, there's no single buffer
2212 * large enough to swap out for the new one, so just evict
2213 * everything and start again. (This should be rare.)
Eric Anholt673a3942008-07-30 12:06:12 -07002214 */
Chris Wilson97311292009-09-21 00:22:34 +01002215 if (!list_empty (&dev_priv->mm.inactive_list))
Chris Wilsonab5ee572009-09-20 19:25:47 +01002216 return i915_gem_evict_from_inactive_list(dev);
Chris Wilson97311292009-09-21 00:22:34 +01002217 else
Chris Wilson07f73f62009-09-14 16:50:30 +01002218 return i915_gem_evict_everything(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002219 }
Keith Packardac94a962008-11-20 23:30:27 -08002220}
2221
Ben Gamari6911a9b2009-04-02 11:24:54 -07002222int
Chris Wilson4bdadb92010-01-27 13:36:32 +00002223i915_gem_object_get_pages(struct drm_gem_object *obj,
2224 gfp_t gfpmask)
Eric Anholt673a3942008-07-30 12:06:12 -07002225{
2226 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2227 int page_count, i;
2228 struct address_space *mapping;
2229 struct inode *inode;
2230 struct page *page;
2231 int ret;
2232
Eric Anholt856fa192009-03-19 14:10:50 -07002233 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002234 return 0;
2235
2236 /* Get the list of pages out of our struct file. They'll be pinned
2237 * at this point until we release them.
2238 */
2239 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07002240 BUG_ON(obj_priv->pages != NULL);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07002241 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
Eric Anholt856fa192009-03-19 14:10:50 -07002242 if (obj_priv->pages == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002243 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07002244 return -ENOMEM;
2245 }
2246
2247 inode = obj->filp->f_path.dentry->d_inode;
2248 mapping = inode->i_mapping;
2249 for (i = 0; i < page_count; i++) {
Chris Wilson4bdadb92010-01-27 13:36:32 +00002250 page = read_cache_page_gfp(mapping, i,
2251 mapping_gfp_mask (mapping) |
2252 __GFP_COLD |
2253 gfpmask);
Eric Anholt673a3942008-07-30 12:06:12 -07002254 if (IS_ERR(page)) {
2255 ret = PTR_ERR(page);
Eric Anholt856fa192009-03-19 14:10:50 -07002256 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002257 return ret;
2258 }
Eric Anholt856fa192009-03-19 14:10:50 -07002259 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07002260 }
Eric Anholt280b7132009-03-12 16:56:27 -07002261
2262 if (obj_priv->tiling_mode != I915_TILING_NONE)
2263 i915_gem_object_do_bit_17_swizzle(obj);
2264
Eric Anholt673a3942008-07-30 12:06:12 -07002265 return 0;
2266}
2267
Jesse Barnesde151cf2008-11-12 10:03:55 -08002268static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2269{
2270 struct drm_gem_object *obj = reg->obj;
2271 struct drm_device *dev = obj->dev;
2272 drm_i915_private_t *dev_priv = dev->dev_private;
2273 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274 int regnum = obj_priv->fence_reg;
2275 uint64_t val;
2276
2277 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2278 0xfffff000) << 32;
2279 val |= obj_priv->gtt_offset & 0xfffff000;
2280 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2281 if (obj_priv->tiling_mode == I915_TILING_Y)
2282 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2283 val |= I965_FENCE_REG_VALID;
2284
2285 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2286}
2287
2288static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2289{
2290 struct drm_gem_object *obj = reg->obj;
2291 struct drm_device *dev = obj->dev;
2292 drm_i915_private_t *dev_priv = dev->dev_private;
2293 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2294 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08002295 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07002296 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002297 uint32_t pitch_val;
2298
2299 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2300 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08002301 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002302 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002303 return;
2304 }
2305
Jesse Barnes0f973f22009-01-26 17:10:45 -08002306 if (obj_priv->tiling_mode == I915_TILING_Y &&
2307 HAS_128_BYTE_Y_TILING(dev))
2308 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002309 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08002310 tile_width = 512;
2311
2312 /* Note: pitch better be a power of two tile widths */
2313 pitch_val = obj_priv->stride / tile_width;
2314 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002315
2316 val = obj_priv->gtt_offset;
2317 if (obj_priv->tiling_mode == I915_TILING_Y)
2318 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2319 val |= I915_FENCE_SIZE_BITS(obj->size);
2320 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2321 val |= I830_FENCE_REG_VALID;
2322
Eric Anholtdc529a42009-03-10 22:34:49 -07002323 if (regnum < 8)
2324 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2325 else
2326 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2327 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002328}
2329
2330static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2331{
2332 struct drm_gem_object *obj = reg->obj;
2333 struct drm_device *dev = obj->dev;
2334 drm_i915_private_t *dev_priv = dev->dev_private;
2335 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2336 int regnum = obj_priv->fence_reg;
2337 uint32_t val;
2338 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002339 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002340
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002341 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002342 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002343 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002344 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002345 return;
2346 }
2347
Eric Anholte76a16d2009-05-26 17:44:56 -07002348 pitch_val = obj_priv->stride / 128;
2349 pitch_val = ffs(pitch_val) - 1;
2350 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2351
Jesse Barnesde151cf2008-11-12 10:03:55 -08002352 val = obj_priv->gtt_offset;
2353 if (obj_priv->tiling_mode == I915_TILING_Y)
2354 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002355 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2356 WARN_ON(fence_size_bits & ~0x00000f00);
2357 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002358 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2359 val |= I830_FENCE_REG_VALID;
2360
2361 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002362}
2363
2364/**
2365 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2366 * @obj: object to map through a fence reg
2367 *
2368 * When mapping objects through the GTT, userspace wants to be able to write
2369 * to them without having to worry about swizzling if the object is tiled.
2370 *
2371 * This function walks the fence regs looking for a free one for @obj,
2372 * stealing one if it can't find any.
2373 *
2374 * It then sets up the reg based on the object's properties: address, pitch
2375 * and tiling format.
2376 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01002377int
2378i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002379{
2380 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002381 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002382 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2383 struct drm_i915_fence_reg *reg = NULL;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002384 struct drm_i915_gem_object *old_obj_priv = NULL;
2385 int i, ret, avail;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002386
Eric Anholta09ba7f2009-08-29 12:49:51 -07002387 /* Just update our place in the LRU if our fence is getting used. */
2388 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2389 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2390 return 0;
2391 }
2392
Jesse Barnesde151cf2008-11-12 10:03:55 -08002393 switch (obj_priv->tiling_mode) {
2394 case I915_TILING_NONE:
2395 WARN(1, "allocating a fence for non-tiled object?\n");
2396 break;
2397 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002398 if (!obj_priv->stride)
2399 return -EINVAL;
2400 WARN((obj_priv->stride & (512 - 1)),
2401 "object 0x%08x is X tiled but has non-512B pitch\n",
2402 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002403 break;
2404 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002405 if (!obj_priv->stride)
2406 return -EINVAL;
2407 WARN((obj_priv->stride & (128 - 1)),
2408 "object 0x%08x is Y tiled but has non-128B pitch\n",
2409 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002410 break;
2411 }
2412
2413 /* First try to find a free reg */
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002414 avail = 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002415 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416 reg = &dev_priv->fence_regs[i];
2417 if (!reg->obj)
2418 break;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002419
2420 old_obj_priv = reg->obj->driver_private;
2421 if (!old_obj_priv->pin_count)
2422 avail++;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002423 }
2424
2425 /* None available, try to steal one or wait for a user to finish */
2426 if (i == dev_priv->num_fence_regs) {
Eric Anholta09ba7f2009-08-29 12:49:51 -07002427 struct drm_gem_object *old_obj = NULL;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002428
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002429 if (avail == 0)
Chris Wilson2939e1f2009-06-06 09:46:03 +01002430 return -ENOSPC;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002431
Eric Anholta09ba7f2009-08-29 12:49:51 -07002432 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2433 fence_list) {
2434 old_obj = old_obj_priv->obj;
Chris Wilsond7619c42009-02-11 14:26:47 +00002435
Chris Wilsond7619c42009-02-11 14:26:47 +00002436 if (old_obj_priv->pin_count)
2437 continue;
2438
Eric Anholta09ba7f2009-08-29 12:49:51 -07002439 /* Take a reference, as otherwise the wait_rendering
2440 * below may cause the object to get freed out from
2441 * under us.
2442 */
2443 drm_gem_object_reference(old_obj);
2444
Chris Wilsond7619c42009-02-11 14:26:47 +00002445 /* i915 uses fences for GPU access to tiled buffers */
2446 if (IS_I965G(dev) || !old_obj_priv->active)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002447 break;
Chris Wilsond7619c42009-02-11 14:26:47 +00002448
Eric Anholta09ba7f2009-08-29 12:49:51 -07002449 /* This brings the object to the head of the LRU if it
2450 * had been written to. The only way this should
2451 * result in us waiting longer than the expected
2452 * optimal amount of time is if there was a
2453 * fence-using buffer later that was read-only.
2454 */
2455 i915_gem_object_flush_gpu_write_domain(old_obj);
2456 ret = i915_gem_object_wait_rendering(old_obj);
Chris Wilson58c2fb62009-09-01 12:02:39 +01002457 if (ret != 0) {
2458 drm_gem_object_unreference(old_obj);
Chris Wilsond7619c42009-02-11 14:26:47 +00002459 return ret;
Chris Wilson58c2fb62009-09-01 12:02:39 +01002460 }
2461
Eric Anholta09ba7f2009-08-29 12:49:51 -07002462 break;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002463 }
2464
2465 /*
2466 * Zap this virtual mapping so we can set up a fence again
2467 * for this object next time we need it.
2468 */
Chris Wilson58c2fb62009-09-01 12:02:39 +01002469 i915_gem_release_mmap(old_obj);
2470
Eric Anholta09ba7f2009-08-29 12:49:51 -07002471 i = old_obj_priv->fence_reg;
Chris Wilson58c2fb62009-09-01 12:02:39 +01002472 reg = &dev_priv->fence_regs[i];
2473
Jesse Barnesde151cf2008-11-12 10:03:55 -08002474 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002475 list_del_init(&old_obj_priv->fence_list);
Chris Wilson58c2fb62009-09-01 12:02:39 +01002476
Eric Anholta09ba7f2009-08-29 12:49:51 -07002477 drm_gem_object_unreference(old_obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002478 }
2479
2480 obj_priv->fence_reg = i;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002481 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2482
Jesse Barnesde151cf2008-11-12 10:03:55 -08002483 reg->obj = obj;
2484
2485 if (IS_I965G(dev))
2486 i965_write_fence_reg(reg);
2487 else if (IS_I9XX(dev))
2488 i915_write_fence_reg(reg);
2489 else
2490 i830_write_fence_reg(reg);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002491
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002492 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2493
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002494 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002495}
2496
2497/**
2498 * i915_gem_clear_fence_reg - clear out fence register info
2499 * @obj: object to clear
2500 *
2501 * Zeroes out the fence register itself and clears out the associated
2502 * data structures in dev_priv and obj_priv.
2503 */
2504static void
2505i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2506{
2507 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002508 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002509 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2510
2511 if (IS_I965G(dev))
2512 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Eric Anholtdc529a42009-03-10 22:34:49 -07002513 else {
2514 uint32_t fence_reg;
2515
2516 if (obj_priv->fence_reg < 8)
2517 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2518 else
2519 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2520 8) * 4;
2521
2522 I915_WRITE(fence_reg, 0);
2523 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002524
2525 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2526 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholta09ba7f2009-08-29 12:49:51 -07002527 list_del_init(&obj_priv->fence_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002528}
2529
Eric Anholt673a3942008-07-30 12:06:12 -07002530/**
Chris Wilson52dc7d32009-06-06 09:46:01 +01002531 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2532 * to the buffer to finish, and then resets the fence register.
2533 * @obj: tiled object holding a fence register.
2534 *
2535 * Zeroes out the fence register itself and clears out the associated
2536 * data structures in dev_priv and obj_priv.
2537 */
2538int
2539i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2540{
2541 struct drm_device *dev = obj->dev;
2542 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2543
2544 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2545 return 0;
2546
2547 /* On the i915, GPU access to tiled buffers is via a fence,
2548 * therefore we must wait for any outstanding access to complete
2549 * before clearing the fence.
2550 */
2551 if (!IS_I965G(dev)) {
2552 int ret;
2553
2554 i915_gem_object_flush_gpu_write_domain(obj);
2555 i915_gem_object_flush_gtt_write_domain(obj);
2556 ret = i915_gem_object_wait_rendering(obj);
2557 if (ret != 0)
2558 return ret;
2559 }
2560
2561 i915_gem_clear_fence_reg (obj);
2562
2563 return 0;
2564}
2565
2566/**
Eric Anholt673a3942008-07-30 12:06:12 -07002567 * Finds free space in the GTT aperture and binds the object there.
2568 */
2569static int
2570i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2571{
2572 struct drm_device *dev = obj->dev;
2573 drm_i915_private_t *dev_priv = dev->dev_private;
2574 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2575 struct drm_mm_node *free_space;
Chris Wilson4bdadb92010-01-27 13:36:32 +00002576 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
Chris Wilson07f73f62009-09-14 16:50:30 +01002577 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002578
Chris Wilsonbb6baf72009-09-22 14:24:13 +01002579 if (obj_priv->madv != I915_MADV_WILLNEED) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01002580 DRM_ERROR("Attempting to bind a purgeable object\n");
2581 return -EINVAL;
2582 }
2583
Eric Anholt673a3942008-07-30 12:06:12 -07002584 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002585 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002586 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002587 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2588 return -EINVAL;
2589 }
2590
2591 search_free:
2592 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2593 obj->size, alignment, 0);
2594 if (free_space != NULL) {
2595 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2596 alignment);
2597 if (obj_priv->gtt_space != NULL) {
2598 obj_priv->gtt_space->private = obj;
2599 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2600 }
2601 }
2602 if (obj_priv->gtt_space == NULL) {
2603 /* If the gtt is empty and we're still having trouble
2604 * fitting our object in, we're out of memory.
2605 */
2606#if WATCH_LRU
2607 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2608#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002609 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002610 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07002611 return ret;
Chris Wilson97311292009-09-21 00:22:34 +01002612
Eric Anholt673a3942008-07-30 12:06:12 -07002613 goto search_free;
2614 }
2615
2616#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02002617 DRM_INFO("Binding object of size %zd at 0x%08x\n",
Eric Anholt673a3942008-07-30 12:06:12 -07002618 obj->size, obj_priv->gtt_offset);
2619#endif
Chris Wilson4bdadb92010-01-27 13:36:32 +00002620 ret = i915_gem_object_get_pages(obj, gfpmask);
Eric Anholt673a3942008-07-30 12:06:12 -07002621 if (ret) {
2622 drm_mm_put_block(obj_priv->gtt_space);
2623 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002624
2625 if (ret == -ENOMEM) {
2626 /* first try to clear up some space from the GTT */
2627 ret = i915_gem_evict_something(dev, obj->size);
2628 if (ret) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002629 /* now try to shrink everyone else */
Chris Wilson4bdadb92010-01-27 13:36:32 +00002630 if (gfpmask) {
2631 gfpmask = 0;
2632 goto search_free;
Chris Wilson07f73f62009-09-14 16:50:30 +01002633 }
2634
2635 return ret;
2636 }
2637
2638 goto search_free;
2639 }
2640
Eric Anholt673a3942008-07-30 12:06:12 -07002641 return ret;
2642 }
2643
Eric Anholt673a3942008-07-30 12:06:12 -07002644 /* Create an AGP memory structure pointing at our pages, and bind it
2645 * into the GTT.
2646 */
2647 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002648 obj_priv->pages,
Chris Wilson07f73f62009-09-14 16:50:30 +01002649 obj->size >> PAGE_SHIFT,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002650 obj_priv->gtt_offset,
2651 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002652 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002653 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002654 drm_mm_put_block(obj_priv->gtt_space);
2655 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002656
2657 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002658 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002659 return ret;
Chris Wilson07f73f62009-09-14 16:50:30 +01002660
2661 goto search_free;
Eric Anholt673a3942008-07-30 12:06:12 -07002662 }
2663 atomic_inc(&dev->gtt_count);
2664 atomic_add(obj->size, &dev->gtt_memory);
2665
2666 /* Assert that the object is not currently in any GPU domain. As it
2667 * wasn't in the GTT, there shouldn't be any way it could have been in
2668 * a GPU cache
2669 */
Chris Wilson21d509e2009-06-06 09:46:02 +01002670 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2671 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07002672
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002673 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2674
Eric Anholt673a3942008-07-30 12:06:12 -07002675 return 0;
2676}
2677
2678void
2679i915_gem_clflush_object(struct drm_gem_object *obj)
2680{
2681 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2682
2683 /* If we don't have a page list set up, then we're not pinned
2684 * to GPU, and we can ignore the cache flush because it'll happen
2685 * again at bind time.
2686 */
Eric Anholt856fa192009-03-19 14:10:50 -07002687 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002688 return;
2689
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002690 trace_i915_gem_object_clflush(obj);
Eric Anholtcfa16a02009-05-26 18:46:16 -07002691
Eric Anholt856fa192009-03-19 14:10:50 -07002692 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002693}
2694
Eric Anholte47c68e2008-11-14 13:35:19 -08002695/** Flushes any GPU write domain for the object if it's dirty. */
2696static void
2697i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2698{
2699 struct drm_device *dev = obj->dev;
2700 uint32_t seqno;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002701 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002702
2703 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2704 return;
2705
2706 /* Queue the GPU write cache flushing we need. */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002707 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002708 i915_gem_flush(dev, 0, obj->write_domain);
Eric Anholtb9624422009-06-03 07:27:35 +00002709 seqno = i915_add_request(dev, NULL, obj->write_domain);
Daniel Vetter99fcb762010-02-07 16:20:18 +01002710 BUG_ON(obj->write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002711 i915_gem_object_move_to_active(obj, seqno);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002712
2713 trace_i915_gem_object_change_domain(obj,
2714 obj->read_domains,
2715 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002716}
2717
2718/** Flushes the GTT write domain for the object if it's dirty. */
2719static void
2720i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2721{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002722 uint32_t old_write_domain;
2723
Eric Anholte47c68e2008-11-14 13:35:19 -08002724 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2725 return;
2726
2727 /* No actual flushing is required for the GTT write domain. Writes
2728 * to it immediately go to main memory as far as we know, so there's
2729 * no chipset flush. It also doesn't land in render cache.
2730 */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002731 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002732 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002733
2734 trace_i915_gem_object_change_domain(obj,
2735 obj->read_domains,
2736 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002737}
2738
2739/** Flushes the CPU write domain for the object if it's dirty. */
2740static void
2741i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2742{
2743 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002744 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002745
2746 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2747 return;
2748
2749 i915_gem_clflush_object(obj);
2750 drm_agp_chipset_flush(dev);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002751 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002752 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002753
2754 trace_i915_gem_object_change_domain(obj,
2755 obj->read_domains,
2756 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002757}
2758
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002759void
2760i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2761{
2762 switch (obj->write_domain) {
2763 case I915_GEM_DOMAIN_GTT:
2764 i915_gem_object_flush_gtt_write_domain(obj);
2765 break;
2766 case I915_GEM_DOMAIN_CPU:
2767 i915_gem_object_flush_cpu_write_domain(obj);
2768 break;
2769 default:
2770 i915_gem_object_flush_gpu_write_domain(obj);
2771 break;
2772 }
2773}
2774
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002775/**
2776 * Moves a single object to the GTT read, and possibly write domain.
2777 *
2778 * This function returns when the move is complete, including waiting on
2779 * flushes to occur.
2780 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002781int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002782i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2783{
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002784 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002785 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002786 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002787
Eric Anholt02354392008-11-26 13:58:13 -08002788 /* Not valid to be called on unbound objects. */
2789 if (obj_priv->gtt_space == NULL)
2790 return -EINVAL;
2791
Eric Anholte47c68e2008-11-14 13:35:19 -08002792 i915_gem_object_flush_gpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002793 /* Wait on any GPU rendering and flushing to occur. */
Eric Anholte47c68e2008-11-14 13:35:19 -08002794 ret = i915_gem_object_wait_rendering(obj);
2795 if (ret != 0)
2796 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002797
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002798 old_write_domain = obj->write_domain;
2799 old_read_domains = obj->read_domains;
2800
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002801 /* If we're writing through the GTT domain, then CPU and GPU caches
2802 * will need to be invalidated at next use.
2803 */
2804 if (write)
Eric Anholte47c68e2008-11-14 13:35:19 -08002805 obj->read_domains &= I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002806
Eric Anholte47c68e2008-11-14 13:35:19 -08002807 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002808
2809 /* It should now be out of any other write domains, and we can update
2810 * the domain values for our changes.
2811 */
2812 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2813 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002814 if (write) {
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002815 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002816 obj_priv->dirty = 1;
2817 }
2818
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002819 trace_i915_gem_object_change_domain(obj,
2820 old_read_domains,
2821 old_write_domain);
2822
Eric Anholte47c68e2008-11-14 13:35:19 -08002823 return 0;
2824}
2825
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002826/*
2827 * Prepare buffer for display plane. Use uninterruptible for possible flush
2828 * wait, as in modesetting process we're not supposed to be interrupted.
2829 */
2830int
2831i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2832{
2833 struct drm_device *dev = obj->dev;
2834 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2835 uint32_t old_write_domain, old_read_domains;
2836 int ret;
2837
2838 /* Not valid to be called on unbound objects. */
2839 if (obj_priv->gtt_space == NULL)
2840 return -EINVAL;
2841
2842 i915_gem_object_flush_gpu_write_domain(obj);
2843
2844 /* Wait on any GPU rendering and flushing to occur. */
2845 if (obj_priv->active) {
2846#if WATCH_BUF
2847 DRM_INFO("%s: object %p wait for seqno %08x\n",
2848 __func__, obj, obj_priv->last_rendering_seqno);
2849#endif
2850 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2851 if (ret != 0)
2852 return ret;
2853 }
2854
2855 old_write_domain = obj->write_domain;
2856 old_read_domains = obj->read_domains;
2857
2858 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2859
2860 i915_gem_object_flush_cpu_write_domain(obj);
2861
2862 /* It should now be out of any other write domains, and we can update
2863 * the domain values for our changes.
2864 */
2865 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2866 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2867 obj->write_domain = I915_GEM_DOMAIN_GTT;
2868 obj_priv->dirty = 1;
2869
2870 trace_i915_gem_object_change_domain(obj,
2871 old_read_domains,
2872 old_write_domain);
2873
2874 return 0;
2875}
2876
Eric Anholte47c68e2008-11-14 13:35:19 -08002877/**
2878 * Moves a single object to the CPU read, and possibly write domain.
2879 *
2880 * This function returns when the move is complete, including waiting on
2881 * flushes to occur.
2882 */
2883static int
2884i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2885{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002886 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002887 int ret;
2888
2889 i915_gem_object_flush_gpu_write_domain(obj);
2890 /* Wait on any GPU rendering and flushing to occur. */
2891 ret = i915_gem_object_wait_rendering(obj);
2892 if (ret != 0)
2893 return ret;
2894
2895 i915_gem_object_flush_gtt_write_domain(obj);
2896
2897 /* If we have a partially-valid cache of the object in the CPU,
2898 * finish invalidating it and free the per-page flags.
2899 */
2900 i915_gem_object_set_to_full_cpu_read_domain(obj);
2901
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002902 old_write_domain = obj->write_domain;
2903 old_read_domains = obj->read_domains;
2904
Eric Anholte47c68e2008-11-14 13:35:19 -08002905 /* Flush the CPU cache if it's still invalid. */
2906 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2907 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002908
2909 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2910 }
2911
2912 /* It should now be out of any other write domains, and we can update
2913 * the domain values for our changes.
2914 */
2915 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2916
2917 /* If we're writing through the CPU, then the GPU read domains will
2918 * need to be invalidated at next use.
2919 */
2920 if (write) {
2921 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2922 obj->write_domain = I915_GEM_DOMAIN_CPU;
2923 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002924
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002925 trace_i915_gem_object_change_domain(obj,
2926 old_read_domains,
2927 old_write_domain);
2928
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002929 return 0;
2930}
2931
Eric Anholt673a3942008-07-30 12:06:12 -07002932/*
2933 * Set the next domain for the specified object. This
2934 * may not actually perform the necessary flushing/invaliding though,
2935 * as that may want to be batched with other set_domain operations
2936 *
2937 * This is (we hope) the only really tricky part of gem. The goal
2938 * is fairly simple -- track which caches hold bits of the object
2939 * and make sure they remain coherent. A few concrete examples may
2940 * help to explain how it works. For shorthand, we use the notation
2941 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2942 * a pair of read and write domain masks.
2943 *
2944 * Case 1: the batch buffer
2945 *
2946 * 1. Allocated
2947 * 2. Written by CPU
2948 * 3. Mapped to GTT
2949 * 4. Read by GPU
2950 * 5. Unmapped from GTT
2951 * 6. Freed
2952 *
2953 * Let's take these a step at a time
2954 *
2955 * 1. Allocated
2956 * Pages allocated from the kernel may still have
2957 * cache contents, so we set them to (CPU, CPU) always.
2958 * 2. Written by CPU (using pwrite)
2959 * The pwrite function calls set_domain (CPU, CPU) and
2960 * this function does nothing (as nothing changes)
2961 * 3. Mapped by GTT
2962 * This function asserts that the object is not
2963 * currently in any GPU-based read or write domains
2964 * 4. Read by GPU
2965 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2966 * As write_domain is zero, this function adds in the
2967 * current read domains (CPU+COMMAND, 0).
2968 * flush_domains is set to CPU.
2969 * invalidate_domains is set to COMMAND
2970 * clflush is run to get data out of the CPU caches
2971 * then i915_dev_set_domain calls i915_gem_flush to
2972 * emit an MI_FLUSH and drm_agp_chipset_flush
2973 * 5. Unmapped from GTT
2974 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2975 * flush_domains and invalidate_domains end up both zero
2976 * so no flushing/invalidating happens
2977 * 6. Freed
2978 * yay, done
2979 *
2980 * Case 2: The shared render buffer
2981 *
2982 * 1. Allocated
2983 * 2. Mapped to GTT
2984 * 3. Read/written by GPU
2985 * 4. set_domain to (CPU,CPU)
2986 * 5. Read/written by CPU
2987 * 6. Read/written by GPU
2988 *
2989 * 1. Allocated
2990 * Same as last example, (CPU, CPU)
2991 * 2. Mapped to GTT
2992 * Nothing changes (assertions find that it is not in the GPU)
2993 * 3. Read/written by GPU
2994 * execbuffer calls set_domain (RENDER, RENDER)
2995 * flush_domains gets CPU
2996 * invalidate_domains gets GPU
2997 * clflush (obj)
2998 * MI_FLUSH and drm_agp_chipset_flush
2999 * 4. set_domain (CPU, CPU)
3000 * flush_domains gets GPU
3001 * invalidate_domains gets CPU
3002 * wait_rendering (obj) to make sure all drawing is complete.
3003 * This will include an MI_FLUSH to get the data from GPU
3004 * to memory
3005 * clflush (obj) to invalidate the CPU cache
3006 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3007 * 5. Read/written by CPU
3008 * cache lines are loaded and dirtied
3009 * 6. Read written by GPU
3010 * Same as last GPU access
3011 *
3012 * Case 3: The constant buffer
3013 *
3014 * 1. Allocated
3015 * 2. Written by CPU
3016 * 3. Read by GPU
3017 * 4. Updated (written) by CPU again
3018 * 5. Read by GPU
3019 *
3020 * 1. Allocated
3021 * (CPU, CPU)
3022 * 2. Written by CPU
3023 * (CPU, CPU)
3024 * 3. Read by GPU
3025 * (CPU+RENDER, 0)
3026 * flush_domains = CPU
3027 * invalidate_domains = RENDER
3028 * clflush (obj)
3029 * MI_FLUSH
3030 * drm_agp_chipset_flush
3031 * 4. Updated (written) by CPU again
3032 * (CPU, CPU)
3033 * flush_domains = 0 (no previous write domain)
3034 * invalidate_domains = 0 (no new read domains)
3035 * 5. Read by GPU
3036 * (CPU+RENDER, 0)
3037 * flush_domains = CPU
3038 * invalidate_domains = RENDER
3039 * clflush (obj)
3040 * MI_FLUSH
3041 * drm_agp_chipset_flush
3042 */
Keith Packardc0d90822008-11-20 23:11:08 -08003043static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08003044i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07003045{
3046 struct drm_device *dev = obj->dev;
3047 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3048 uint32_t invalidate_domains = 0;
3049 uint32_t flush_domains = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003050 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003051
Eric Anholt8b0e3782009-02-19 14:40:50 -08003052 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3053 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07003054
Jesse Barnes652c3932009-08-17 13:31:43 -07003055 intel_mark_busy(dev, obj);
3056
Eric Anholt673a3942008-07-30 12:06:12 -07003057#if WATCH_BUF
3058 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3059 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08003060 obj->read_domains, obj->pending_read_domains,
3061 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003062#endif
3063 /*
3064 * If the object isn't moving to a new write domain,
3065 * let the object stay in multiple read domains
3066 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003067 if (obj->pending_write_domain == 0)
3068 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003069 else
3070 obj_priv->dirty = 1;
3071
3072 /*
3073 * Flush the current write domain if
3074 * the new read domains don't match. Invalidate
3075 * any read domains which differ from the old
3076 * write domain
3077 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003078 if (obj->write_domain &&
3079 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07003080 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003081 invalidate_domains |=
3082 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07003083 }
3084 /*
3085 * Invalidate any read caches which may have
3086 * stale data. That is, any new read domains.
3087 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003088 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003089 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3090#if WATCH_BUF
3091 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3092 __func__, flush_domains, invalidate_domains);
3093#endif
Eric Anholt673a3942008-07-30 12:06:12 -07003094 i915_gem_clflush_object(obj);
3095 }
3096
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003097 old_read_domains = obj->read_domains;
3098
Eric Anholtefbeed92009-02-19 14:54:51 -08003099 /* The actual obj->write_domain will be updated with
3100 * pending_write_domain after we emit the accumulated flush for all
3101 * of our domain changes in execbuffers (which clears objects'
3102 * write_domains). So if we have a current write domain that we
3103 * aren't changing, set pending_write_domain to that.
3104 */
3105 if (flush_domains == 0 && obj->pending_write_domain == 0)
3106 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003107 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003108
3109 dev->invalidate_domains |= invalidate_domains;
3110 dev->flush_domains |= flush_domains;
3111#if WATCH_BUF
3112 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3113 __func__,
3114 obj->read_domains, obj->write_domain,
3115 dev->invalidate_domains, dev->flush_domains);
3116#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003117
3118 trace_i915_gem_object_change_domain(obj,
3119 old_read_domains,
3120 obj->write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003121}
3122
3123/**
Eric Anholte47c68e2008-11-14 13:35:19 -08003124 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07003125 *
Eric Anholte47c68e2008-11-14 13:35:19 -08003126 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3127 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3128 */
3129static void
3130i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3131{
Eric Anholte47c68e2008-11-14 13:35:19 -08003132 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3133
3134 if (!obj_priv->page_cpu_valid)
3135 return;
3136
3137 /* If we're partially in the CPU read domain, finish moving it in.
3138 */
3139 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3140 int i;
3141
3142 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3143 if (obj_priv->page_cpu_valid[i])
3144 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07003145 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08003146 }
Eric Anholte47c68e2008-11-14 13:35:19 -08003147 }
3148
3149 /* Free the page_cpu_valid mappings which are now stale, whether
3150 * or not we've got I915_GEM_DOMAIN_CPU.
3151 */
Eric Anholt9a298b22009-03-24 12:23:04 -07003152 kfree(obj_priv->page_cpu_valid);
Eric Anholte47c68e2008-11-14 13:35:19 -08003153 obj_priv->page_cpu_valid = NULL;
3154}
3155
3156/**
3157 * Set the CPU read domain on a range of the object.
3158 *
3159 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3160 * not entirely valid. The page_cpu_valid member of the object flags which
3161 * pages have been flushed, and will be respected by
3162 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3163 * of the whole object.
3164 *
3165 * This function returns when the move is complete, including waiting on
3166 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07003167 */
3168static int
Eric Anholte47c68e2008-11-14 13:35:19 -08003169i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3170 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07003171{
3172 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003173 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003174 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003175
Eric Anholte47c68e2008-11-14 13:35:19 -08003176 if (offset == 0 && size == obj->size)
3177 return i915_gem_object_set_to_cpu_domain(obj, 0);
3178
3179 i915_gem_object_flush_gpu_write_domain(obj);
3180 /* Wait on any GPU rendering and flushing to occur. */
3181 ret = i915_gem_object_wait_rendering(obj);
3182 if (ret != 0)
3183 return ret;
3184 i915_gem_object_flush_gtt_write_domain(obj);
3185
3186 /* If we're already fully in the CPU read domain, we're done. */
3187 if (obj_priv->page_cpu_valid == NULL &&
3188 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003189 return 0;
3190
Eric Anholte47c68e2008-11-14 13:35:19 -08003191 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3192 * newly adding I915_GEM_DOMAIN_CPU
3193 */
Eric Anholt673a3942008-07-30 12:06:12 -07003194 if (obj_priv->page_cpu_valid == NULL) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003195 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3196 GFP_KERNEL);
Eric Anholte47c68e2008-11-14 13:35:19 -08003197 if (obj_priv->page_cpu_valid == NULL)
3198 return -ENOMEM;
3199 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3200 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07003201
3202 /* Flush the cache on any pages that are still invalid from the CPU's
3203 * perspective.
3204 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003205 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3206 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07003207 if (obj_priv->page_cpu_valid[i])
3208 continue;
3209
Eric Anholt856fa192009-03-19 14:10:50 -07003210 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07003211
3212 obj_priv->page_cpu_valid[i] = 1;
3213 }
3214
Eric Anholte47c68e2008-11-14 13:35:19 -08003215 /* It should now be out of any other write domains, and we can update
3216 * the domain values for our changes.
3217 */
3218 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3219
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003220 old_read_domains = obj->read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003221 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3222
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003223 trace_i915_gem_object_change_domain(obj,
3224 old_read_domains,
3225 obj->write_domain);
3226
Eric Anholt673a3942008-07-30 12:06:12 -07003227 return 0;
3228}
3229
3230/**
Eric Anholt673a3942008-07-30 12:06:12 -07003231 * Pin an object to the GTT and evaluate the relocations landing in it.
3232 */
3233static int
3234i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3235 struct drm_file *file_priv,
Jesse Barnes76446ca2009-12-17 22:05:42 -05003236 struct drm_i915_gem_exec_object2 *entry,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003237 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07003238{
3239 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07003240 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003241 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3242 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07003243 void __iomem *reloc_page;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003244 bool need_fence;
3245
3246 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3247 obj_priv->tiling_mode != I915_TILING_NONE;
3248
3249 /* Check fence reg constraints and rebind if necessary */
3250 if (need_fence && !i915_obj_fenceable(dev, obj))
3251 i915_gem_object_unbind(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003252
3253 /* Choose the GTT offset for our buffer and put it there. */
3254 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3255 if (ret)
3256 return ret;
3257
Jesse Barnes76446ca2009-12-17 22:05:42 -05003258 /*
3259 * Pre-965 chips need a fence register set up in order to
3260 * properly handle blits to/from tiled surfaces.
3261 */
3262 if (need_fence) {
3263 ret = i915_gem_object_get_fence_reg(obj);
3264 if (ret != 0) {
3265 if (ret != -EBUSY && ret != -ERESTARTSYS)
3266 DRM_ERROR("Failure to install fence: %d\n",
3267 ret);
3268 i915_gem_object_unpin(obj);
3269 return ret;
3270 }
3271 }
3272
Eric Anholt673a3942008-07-30 12:06:12 -07003273 entry->offset = obj_priv->gtt_offset;
3274
Eric Anholt673a3942008-07-30 12:06:12 -07003275 /* Apply the relocations, using the GTT aperture to avoid cache
3276 * flushing requirements.
3277 */
3278 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003279 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003280 struct drm_gem_object *target_obj;
3281 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07003282 uint32_t reloc_val, reloc_offset;
3283 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07003284
Eric Anholt673a3942008-07-30 12:06:12 -07003285 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003286 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003287 if (target_obj == NULL) {
3288 i915_gem_object_unpin(obj);
3289 return -EBADF;
3290 }
3291 target_obj_priv = target_obj->driver_private;
3292
Chris Wilson8542a0b2009-09-09 21:15:15 +01003293#if WATCH_RELOC
3294 DRM_INFO("%s: obj %p offset %08x target %d "
3295 "read %08x write %08x gtt %08x "
3296 "presumed %08x delta %08x\n",
3297 __func__,
3298 obj,
3299 (int) reloc->offset,
3300 (int) reloc->target_handle,
3301 (int) reloc->read_domains,
3302 (int) reloc->write_domain,
3303 (int) target_obj_priv->gtt_offset,
3304 (int) reloc->presumed_offset,
3305 reloc->delta);
3306#endif
3307
Eric Anholt673a3942008-07-30 12:06:12 -07003308 /* The target buffer should have appeared before us in the
3309 * exec_object list, so it should have a GTT space bound by now.
3310 */
3311 if (target_obj_priv->gtt_space == NULL) {
3312 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003313 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003314 drm_gem_object_unreference(target_obj);
3315 i915_gem_object_unpin(obj);
3316 return -EINVAL;
3317 }
3318
Chris Wilson8542a0b2009-09-09 21:15:15 +01003319 /* Validate that the target is in a valid r/w GPU domain */
3320 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3321 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3322 DRM_ERROR("reloc with read/write CPU domains: "
3323 "obj %p target %d offset %d "
3324 "read %08x write %08x",
3325 obj, reloc->target_handle,
3326 (int) reloc->offset,
3327 reloc->read_domains,
3328 reloc->write_domain);
3329 drm_gem_object_unreference(target_obj);
3330 i915_gem_object_unpin(obj);
3331 return -EINVAL;
3332 }
3333 if (reloc->write_domain && target_obj->pending_write_domain &&
3334 reloc->write_domain != target_obj->pending_write_domain) {
3335 DRM_ERROR("Write domain conflict: "
3336 "obj %p target %d offset %d "
3337 "new %08x old %08x\n",
3338 obj, reloc->target_handle,
3339 (int) reloc->offset,
3340 reloc->write_domain,
3341 target_obj->pending_write_domain);
3342 drm_gem_object_unreference(target_obj);
3343 i915_gem_object_unpin(obj);
3344 return -EINVAL;
3345 }
3346
3347 target_obj->pending_read_domains |= reloc->read_domains;
3348 target_obj->pending_write_domain |= reloc->write_domain;
3349
3350 /* If the relocation already has the right value in it, no
3351 * more work needs to be done.
3352 */
3353 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3354 drm_gem_object_unreference(target_obj);
3355 continue;
3356 }
3357
3358 /* Check that the relocation address is valid... */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003359 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07003360 DRM_ERROR("Relocation beyond object bounds: "
3361 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003362 obj, reloc->target_handle,
3363 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07003364 drm_gem_object_unreference(target_obj);
3365 i915_gem_object_unpin(obj);
3366 return -EINVAL;
3367 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003368 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07003369 DRM_ERROR("Relocation not 4-byte aligned: "
3370 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003371 obj, reloc->target_handle,
3372 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003373 drm_gem_object_unreference(target_obj);
3374 i915_gem_object_unpin(obj);
3375 return -EINVAL;
3376 }
3377
Chris Wilson8542a0b2009-09-09 21:15:15 +01003378 /* and points to somewhere within the target object. */
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003379 if (reloc->delta >= target_obj->size) {
3380 DRM_ERROR("Relocation beyond target object bounds: "
3381 "obj %p target %d delta %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003382 obj, reloc->target_handle,
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003383 (int) reloc->delta, (int) target_obj->size);
Chris Wilson491152b2009-02-11 14:26:32 +00003384 drm_gem_object_unreference(target_obj);
3385 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003386 return -EINVAL;
3387 }
3388
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003389 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3390 if (ret != 0) {
3391 drm_gem_object_unreference(target_obj);
3392 i915_gem_object_unpin(obj);
3393 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07003394 }
3395
3396 /* Map the page containing the relocation we're going to
3397 * perform.
3398 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003399 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07003400 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3401 (reloc_offset &
3402 ~(PAGE_SIZE - 1)));
Eric Anholt3043c602008-10-02 12:24:47 -07003403 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07003404 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003405 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07003406
3407#if WATCH_BUF
3408 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003409 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07003410 readl(reloc_entry), reloc_val);
3411#endif
3412 writel(reloc_val, reloc_entry);
Keith Packard0839ccb2008-10-30 19:38:48 -07003413 io_mapping_unmap_atomic(reloc_page);
Eric Anholt673a3942008-07-30 12:06:12 -07003414
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003415 /* The updated presumed offset for this entry will be
3416 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07003417 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003418 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003419
3420 drm_gem_object_unreference(target_obj);
3421 }
3422
Eric Anholt673a3942008-07-30 12:06:12 -07003423#if WATCH_BUF
3424 if (0)
3425 i915_gem_dump_object(obj, 128, __func__, ~0);
3426#endif
3427 return 0;
3428}
3429
3430/** Dispatch a batchbuffer to the ring
3431 */
3432static int
3433i915_dispatch_gem_execbuffer(struct drm_device *dev,
Jesse Barnes76446ca2009-12-17 22:05:42 -05003434 struct drm_i915_gem_execbuffer2 *exec,
Eric Anholt201361a2009-03-11 12:30:04 -07003435 struct drm_clip_rect *cliprects,
Eric Anholt673a3942008-07-30 12:06:12 -07003436 uint64_t exec_offset)
3437{
3438 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003439 int nbox = exec->num_cliprects;
3440 int i = 0, count;
Chris Wilson83d60792009-06-06 09:45:57 +01003441 uint32_t exec_start, exec_len;
Eric Anholt673a3942008-07-30 12:06:12 -07003442 RING_LOCALS;
3443
3444 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3445 exec_len = (uint32_t) exec->batch_len;
3446
Chris Wilson8f0dc5b2009-09-24 00:43:17 +01003447 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003448
Eric Anholt673a3942008-07-30 12:06:12 -07003449 count = nbox ? nbox : 1;
3450
3451 for (i = 0; i < count; i++) {
3452 if (i < nbox) {
Eric Anholt201361a2009-03-11 12:30:04 -07003453 int ret = i915_emit_box(dev, cliprects, i,
Eric Anholt673a3942008-07-30 12:06:12 -07003454 exec->DR1, exec->DR4);
3455 if (ret)
3456 return ret;
3457 }
3458
3459 if (IS_I830(dev) || IS_845G(dev)) {
3460 BEGIN_LP_RING(4);
3461 OUT_RING(MI_BATCH_BUFFER);
3462 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3463 OUT_RING(exec_start + exec_len - 4);
3464 OUT_RING(0);
3465 ADVANCE_LP_RING();
3466 } else {
3467 BEGIN_LP_RING(2);
3468 if (IS_I965G(dev)) {
3469 OUT_RING(MI_BATCH_BUFFER_START |
3470 (2 << 6) |
3471 MI_BATCH_NON_SECURE_I965);
3472 OUT_RING(exec_start);
3473 } else {
3474 OUT_RING(MI_BATCH_BUFFER_START |
3475 (2 << 6));
3476 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3477 }
3478 ADVANCE_LP_RING();
3479 }
3480 }
3481
3482 /* XXX breadcrumb */
3483 return 0;
3484}
3485
3486/* Throttle our rendering by waiting until the ring has completed our requests
3487 * emitted over 20 msec ago.
3488 *
Eric Anholtb9624422009-06-03 07:27:35 +00003489 * Note that if we were to use the current jiffies each time around the loop,
3490 * we wouldn't escape the function with any frames outstanding if the time to
3491 * render a frame was over 20ms.
3492 *
Eric Anholt673a3942008-07-30 12:06:12 -07003493 * This should get us reasonable parallelism between CPU and GPU but also
3494 * relatively low latency when blocking on a particular request to finish.
3495 */
3496static int
3497i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3498{
3499 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3500 int ret = 0;
Eric Anholtb9624422009-06-03 07:27:35 +00003501 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
Eric Anholt673a3942008-07-30 12:06:12 -07003502
3503 mutex_lock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003504 while (!list_empty(&i915_file_priv->mm.request_list)) {
3505 struct drm_i915_gem_request *request;
3506
3507 request = list_first_entry(&i915_file_priv->mm.request_list,
3508 struct drm_i915_gem_request,
3509 client_list);
3510
3511 if (time_after_eq(request->emitted_jiffies, recent_enough))
3512 break;
3513
3514 ret = i915_wait_request(dev, request->seqno);
3515 if (ret != 0)
3516 break;
3517 }
Eric Anholt673a3942008-07-30 12:06:12 -07003518 mutex_unlock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003519
Eric Anholt673a3942008-07-30 12:06:12 -07003520 return ret;
3521}
3522
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003523static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003524i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003525 uint32_t buffer_count,
3526 struct drm_i915_gem_relocation_entry **relocs)
3527{
3528 uint32_t reloc_count = 0, reloc_index = 0, i;
3529 int ret;
3530
3531 *relocs = NULL;
3532 for (i = 0; i < buffer_count; i++) {
3533 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3534 return -EINVAL;
3535 reloc_count += exec_list[i].relocation_count;
3536 }
3537
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003538 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
Jesse Barnes76446ca2009-12-17 22:05:42 -05003539 if (*relocs == NULL) {
3540 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003541 return -ENOMEM;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003542 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003543
3544 for (i = 0; i < buffer_count; i++) {
3545 struct drm_i915_gem_relocation_entry __user *user_relocs;
3546
3547 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3548
3549 ret = copy_from_user(&(*relocs)[reloc_index],
3550 user_relocs,
3551 exec_list[i].relocation_count *
3552 sizeof(**relocs));
3553 if (ret != 0) {
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003554 drm_free_large(*relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003555 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003556 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003557 }
3558
3559 reloc_index += exec_list[i].relocation_count;
3560 }
3561
Florian Mickler2bc43b52009-04-06 22:55:41 +02003562 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003563}
3564
3565static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003566i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003567 uint32_t buffer_count,
3568 struct drm_i915_gem_relocation_entry *relocs)
3569{
3570 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003571 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003572
Chris Wilson93533c22010-01-31 10:40:48 +00003573 if (relocs == NULL)
3574 return 0;
3575
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003576 for (i = 0; i < buffer_count; i++) {
3577 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003578 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003579
3580 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3581
Florian Mickler2bc43b52009-04-06 22:55:41 +02003582 unwritten = copy_to_user(user_relocs,
3583 &relocs[reloc_count],
3584 exec_list[i].relocation_count *
3585 sizeof(*relocs));
3586
3587 if (unwritten) {
3588 ret = -EFAULT;
3589 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003590 }
3591
3592 reloc_count += exec_list[i].relocation_count;
3593 }
3594
Florian Mickler2bc43b52009-04-06 22:55:41 +02003595err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003596 drm_free_large(relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003597
3598 return ret;
3599}
3600
Chris Wilson83d60792009-06-06 09:45:57 +01003601static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003602i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
Chris Wilson83d60792009-06-06 09:45:57 +01003603 uint64_t exec_offset)
3604{
3605 uint32_t exec_start, exec_len;
3606
3607 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3608 exec_len = (uint32_t) exec->batch_len;
3609
3610 if ((exec_start | exec_len) & 0x7)
3611 return -EINVAL;
3612
3613 if (!exec_start)
3614 return -EINVAL;
3615
3616 return 0;
3617}
3618
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003619static int
3620i915_gem_wait_for_pending_flip(struct drm_device *dev,
3621 struct drm_gem_object **object_list,
3622 int count)
3623{
3624 drm_i915_private_t *dev_priv = dev->dev_private;
3625 struct drm_i915_gem_object *obj_priv;
3626 DEFINE_WAIT(wait);
3627 int i, ret = 0;
3628
3629 for (;;) {
3630 prepare_to_wait(&dev_priv->pending_flip_queue,
3631 &wait, TASK_INTERRUPTIBLE);
3632 for (i = 0; i < count; i++) {
3633 obj_priv = object_list[i]->driver_private;
3634 if (atomic_read(&obj_priv->pending_flip) > 0)
3635 break;
3636 }
3637 if (i == count)
3638 break;
3639
3640 if (!signal_pending(current)) {
3641 mutex_unlock(&dev->struct_mutex);
3642 schedule();
3643 mutex_lock(&dev->struct_mutex);
3644 continue;
3645 }
3646 ret = -ERESTARTSYS;
3647 break;
3648 }
3649 finish_wait(&dev_priv->pending_flip_queue, &wait);
3650
3651 return ret;
3652}
3653
Eric Anholt673a3942008-07-30 12:06:12 -07003654int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003655i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3656 struct drm_file *file_priv,
3657 struct drm_i915_gem_execbuffer2 *args,
3658 struct drm_i915_gem_exec_object2 *exec_list)
Eric Anholt673a3942008-07-30 12:06:12 -07003659{
3660 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003661 struct drm_gem_object **object_list = NULL;
3662 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003663 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003664 struct drm_clip_rect *cliprects = NULL;
Chris Wilson93533c22010-01-31 10:40:48 +00003665 struct drm_i915_gem_relocation_entry *relocs = NULL;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003666 int ret = 0, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003667 uint64_t exec_offset;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003668 uint32_t seqno, flush_domains, reloc_index;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003669 int pin_tries, flips;
Eric Anholt673a3942008-07-30 12:06:12 -07003670
3671#if WATCH_EXEC
3672 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3673 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3674#endif
3675
Eric Anholt4f481ed2008-09-10 14:22:49 -07003676 if (args->buffer_count < 1) {
3677 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3678 return -EINVAL;
3679 }
Eric Anholtc8e0f932009-11-22 03:49:37 +01003680 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003681 if (object_list == NULL) {
3682 DRM_ERROR("Failed to allocate object list for %d buffers\n",
Eric Anholt673a3942008-07-30 12:06:12 -07003683 args->buffer_count);
3684 ret = -ENOMEM;
3685 goto pre_mutex_err;
3686 }
Eric Anholt673a3942008-07-30 12:06:12 -07003687
Eric Anholt201361a2009-03-11 12:30:04 -07003688 if (args->num_cliprects != 0) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003689 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3690 GFP_KERNEL);
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003691 if (cliprects == NULL) {
3692 ret = -ENOMEM;
Eric Anholt201361a2009-03-11 12:30:04 -07003693 goto pre_mutex_err;
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003694 }
Eric Anholt201361a2009-03-11 12:30:04 -07003695
3696 ret = copy_from_user(cliprects,
3697 (struct drm_clip_rect __user *)
3698 (uintptr_t) args->cliprects_ptr,
3699 sizeof(*cliprects) * args->num_cliprects);
3700 if (ret != 0) {
3701 DRM_ERROR("copy %d cliprects failed: %d\n",
3702 args->num_cliprects, ret);
3703 goto pre_mutex_err;
3704 }
3705 }
3706
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003707 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3708 &relocs);
3709 if (ret != 0)
3710 goto pre_mutex_err;
3711
Eric Anholt673a3942008-07-30 12:06:12 -07003712 mutex_lock(&dev->struct_mutex);
3713
3714 i915_verify_inactive(dev, __FILE__, __LINE__);
3715
Ben Gamariba1234d2009-09-14 17:48:47 -04003716 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07003717 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003718 ret = -EIO;
3719 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003720 }
3721
3722 if (dev_priv->mm.suspended) {
Eric Anholt673a3942008-07-30 12:06:12 -07003723 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003724 ret = -EBUSY;
3725 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003726 }
3727
Keith Packardac94a962008-11-20 23:30:27 -08003728 /* Look up object handles */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003729 flips = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003730 for (i = 0; i < args->buffer_count; i++) {
3731 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3732 exec_list[i].handle);
3733 if (object_list[i] == NULL) {
3734 DRM_ERROR("Invalid object handle %d at index %d\n",
3735 exec_list[i].handle, i);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003736 /* prevent error path from reading uninitialized data */
3737 args->buffer_count = i + 1;
Eric Anholt673a3942008-07-30 12:06:12 -07003738 ret = -EBADF;
3739 goto err;
3740 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003741
3742 obj_priv = object_list[i]->driver_private;
3743 if (obj_priv->in_execbuffer) {
3744 DRM_ERROR("Object %p appears more than once in object list\n",
3745 object_list[i]);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003746 /* prevent error path from reading uninitialized data */
3747 args->buffer_count = i + 1;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003748 ret = -EBADF;
3749 goto err;
3750 }
3751 obj_priv->in_execbuffer = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003752 flips += atomic_read(&obj_priv->pending_flip);
3753 }
3754
3755 if (flips > 0) {
3756 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3757 args->buffer_count);
3758 if (ret)
3759 goto err;
Keith Packardac94a962008-11-20 23:30:27 -08003760 }
Eric Anholt673a3942008-07-30 12:06:12 -07003761
Keith Packardac94a962008-11-20 23:30:27 -08003762 /* Pin and relocate */
3763 for (pin_tries = 0; ; pin_tries++) {
3764 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003765 reloc_index = 0;
3766
Keith Packardac94a962008-11-20 23:30:27 -08003767 for (i = 0; i < args->buffer_count; i++) {
3768 object_list[i]->pending_read_domains = 0;
3769 object_list[i]->pending_write_domain = 0;
3770 ret = i915_gem_object_pin_and_relocate(object_list[i],
3771 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003772 &exec_list[i],
3773 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003774 if (ret)
3775 break;
3776 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003777 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003778 }
3779 /* success */
3780 if (ret == 0)
3781 break;
3782
3783 /* error other than GTT full, or we've already tried again */
Chris Wilson2939e1f2009-06-06 09:46:03 +01003784 if (ret != -ENOSPC || pin_tries >= 1) {
Chris Wilson07f73f62009-09-14 16:50:30 +01003785 if (ret != -ERESTARTSYS) {
3786 unsigned long long total_size = 0;
3787 for (i = 0; i < args->buffer_count; i++)
3788 total_size += object_list[i]->size;
3789 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3790 pinned+1, args->buffer_count,
3791 total_size, ret);
3792 DRM_ERROR("%d objects [%d pinned], "
3793 "%d object bytes [%d pinned], "
3794 "%d/%d gtt bytes\n",
3795 atomic_read(&dev->object_count),
3796 atomic_read(&dev->pin_count),
3797 atomic_read(&dev->object_memory),
3798 atomic_read(&dev->pin_memory),
3799 atomic_read(&dev->gtt_memory),
3800 dev->gtt_total);
3801 }
Eric Anholt673a3942008-07-30 12:06:12 -07003802 goto err;
3803 }
Keith Packardac94a962008-11-20 23:30:27 -08003804
3805 /* unpin all of our buffers */
3806 for (i = 0; i < pinned; i++)
3807 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003808 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003809
3810 /* evict everyone we can from the aperture */
3811 ret = i915_gem_evict_everything(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01003812 if (ret && ret != -ENOSPC)
Keith Packardac94a962008-11-20 23:30:27 -08003813 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003814 }
3815
3816 /* Set the pending read domains for the batch buffer to COMMAND */
3817 batch_obj = object_list[args->buffer_count-1];
Chris Wilson5f26a2c2009-06-06 09:45:58 +01003818 if (batch_obj->pending_write_domain) {
3819 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3820 ret = -EINVAL;
3821 goto err;
3822 }
3823 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
Eric Anholt673a3942008-07-30 12:06:12 -07003824
Chris Wilson83d60792009-06-06 09:45:57 +01003825 /* Sanity check the batch buffer, prior to moving objects */
3826 exec_offset = exec_list[args->buffer_count - 1].offset;
3827 ret = i915_gem_check_execbuffer (args, exec_offset);
3828 if (ret != 0) {
3829 DRM_ERROR("execbuf with invalid offset/length\n");
3830 goto err;
3831 }
3832
Eric Anholt673a3942008-07-30 12:06:12 -07003833 i915_verify_inactive(dev, __FILE__, __LINE__);
3834
Keith Packard646f0f62008-11-20 23:23:03 -08003835 /* Zero the global flush/invalidate flags. These
3836 * will be modified as new domains are computed
3837 * for each object
3838 */
3839 dev->invalidate_domains = 0;
3840 dev->flush_domains = 0;
3841
Eric Anholt673a3942008-07-30 12:06:12 -07003842 for (i = 0; i < args->buffer_count; i++) {
3843 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003844
Keith Packard646f0f62008-11-20 23:23:03 -08003845 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003846 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003847 }
3848
3849 i915_verify_inactive(dev, __FILE__, __LINE__);
3850
Keith Packard646f0f62008-11-20 23:23:03 -08003851 if (dev->invalidate_domains | dev->flush_domains) {
3852#if WATCH_EXEC
3853 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3854 __func__,
3855 dev->invalidate_domains,
3856 dev->flush_domains);
3857#endif
3858 i915_gem_flush(dev,
3859 dev->invalidate_domains,
3860 dev->flush_domains);
Daniel Vetter99fcb762010-02-07 16:20:18 +01003861 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
Eric Anholtb9624422009-06-03 07:27:35 +00003862 (void)i915_add_request(dev, file_priv,
3863 dev->flush_domains);
Keith Packard646f0f62008-11-20 23:23:03 -08003864 }
Eric Anholt673a3942008-07-30 12:06:12 -07003865
Eric Anholtefbeed92009-02-19 14:54:51 -08003866 for (i = 0; i < args->buffer_count; i++) {
3867 struct drm_gem_object *obj = object_list[i];
Daniel Vetter99fcb762010-02-07 16:20:18 +01003868 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003869 uint32_t old_write_domain = obj->write_domain;
Eric Anholtefbeed92009-02-19 14:54:51 -08003870
3871 obj->write_domain = obj->pending_write_domain;
Daniel Vetter99fcb762010-02-07 16:20:18 +01003872 if (obj->write_domain)
3873 list_move_tail(&obj_priv->gpu_write_list,
3874 &dev_priv->mm.gpu_write_list);
3875 else
3876 list_del_init(&obj_priv->gpu_write_list);
3877
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003878 trace_i915_gem_object_change_domain(obj,
3879 obj->read_domains,
3880 old_write_domain);
Eric Anholtefbeed92009-02-19 14:54:51 -08003881 }
3882
Eric Anholt673a3942008-07-30 12:06:12 -07003883 i915_verify_inactive(dev, __FILE__, __LINE__);
3884
3885#if WATCH_COHERENCY
3886 for (i = 0; i < args->buffer_count; i++) {
3887 i915_gem_object_check_coherency(object_list[i],
3888 exec_list[i].handle);
3889 }
3890#endif
3891
Eric Anholt673a3942008-07-30 12:06:12 -07003892#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003893 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003894 args->batch_len,
3895 __func__,
3896 ~0);
3897#endif
3898
Eric Anholt673a3942008-07-30 12:06:12 -07003899 /* Exec the batchbuffer */
Eric Anholt201361a2009-03-11 12:30:04 -07003900 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003901 if (ret) {
3902 DRM_ERROR("dispatch failed %d\n", ret);
3903 goto err;
3904 }
3905
3906 /*
3907 * Ensure that the commands in the batch buffer are
3908 * finished before the interrupt fires
3909 */
3910 flush_domains = i915_retire_commands(dev);
3911
3912 i915_verify_inactive(dev, __FILE__, __LINE__);
3913
3914 /*
3915 * Get a seqno representing the execution of the current buffer,
3916 * which we can wait on. We would like to mitigate these interrupts,
3917 * likely by only creating seqnos occasionally (so that we have
3918 * *some* interrupts representing completion of buffers that we can
3919 * wait on when trying to clear up gtt space).
3920 */
Eric Anholtb9624422009-06-03 07:27:35 +00003921 seqno = i915_add_request(dev, file_priv, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07003922 BUG_ON(seqno == 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003923 for (i = 0; i < args->buffer_count; i++) {
3924 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003925
Eric Anholtce44b0e2008-11-06 16:00:31 -08003926 i915_gem_object_move_to_active(obj, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07003927#if WATCH_LRU
3928 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3929#endif
3930 }
3931#if WATCH_LRU
3932 i915_dump_lru(dev, __func__);
3933#endif
3934
3935 i915_verify_inactive(dev, __FILE__, __LINE__);
3936
Eric Anholt673a3942008-07-30 12:06:12 -07003937err:
Julia Lawallaad87df2008-12-21 16:28:47 +01003938 for (i = 0; i < pinned; i++)
3939 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07003940
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003941 for (i = 0; i < args->buffer_count; i++) {
3942 if (object_list[i]) {
3943 obj_priv = object_list[i]->driver_private;
3944 obj_priv->in_execbuffer = false;
3945 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003946 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003947 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003948
Eric Anholt673a3942008-07-30 12:06:12 -07003949 mutex_unlock(&dev->struct_mutex);
3950
Chris Wilson93533c22010-01-31 10:40:48 +00003951pre_mutex_err:
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003952 /* Copy the updated relocations out regardless of current error
3953 * state. Failure to update the relocs would mean that the next
3954 * time userland calls execbuf, it would do so with presumed offset
3955 * state that didn't match the actual object state.
3956 */
3957 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3958 relocs);
3959 if (ret2 != 0) {
3960 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3961
3962 if (ret == 0)
3963 ret = ret2;
3964 }
3965
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003966 drm_free_large(object_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07003967 kfree(cliprects);
Eric Anholt673a3942008-07-30 12:06:12 -07003968
3969 return ret;
3970}
3971
Jesse Barnes76446ca2009-12-17 22:05:42 -05003972/*
3973 * Legacy execbuffer just creates an exec2 list from the original exec object
3974 * list array and passes it to the real function.
3975 */
3976int
3977i915_gem_execbuffer(struct drm_device *dev, void *data,
3978 struct drm_file *file_priv)
3979{
3980 struct drm_i915_gem_execbuffer *args = data;
3981 struct drm_i915_gem_execbuffer2 exec2;
3982 struct drm_i915_gem_exec_object *exec_list = NULL;
3983 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3984 int ret, i;
3985
3986#if WATCH_EXEC
3987 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3988 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3989#endif
3990
3991 if (args->buffer_count < 1) {
3992 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3993 return -EINVAL;
3994 }
3995
3996 /* Copy in the exec list from userland */
3997 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3998 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3999 if (exec_list == NULL || exec2_list == NULL) {
4000 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4001 args->buffer_count);
4002 drm_free_large(exec_list);
4003 drm_free_large(exec2_list);
4004 return -ENOMEM;
4005 }
4006 ret = copy_from_user(exec_list,
4007 (struct drm_i915_relocation_entry __user *)
4008 (uintptr_t) args->buffers_ptr,
4009 sizeof(*exec_list) * args->buffer_count);
4010 if (ret != 0) {
4011 DRM_ERROR("copy %d exec entries failed %d\n",
4012 args->buffer_count, ret);
4013 drm_free_large(exec_list);
4014 drm_free_large(exec2_list);
4015 return -EFAULT;
4016 }
4017
4018 for (i = 0; i < args->buffer_count; i++) {
4019 exec2_list[i].handle = exec_list[i].handle;
4020 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4021 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4022 exec2_list[i].alignment = exec_list[i].alignment;
4023 exec2_list[i].offset = exec_list[i].offset;
4024 if (!IS_I965G(dev))
4025 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4026 else
4027 exec2_list[i].flags = 0;
4028 }
4029
4030 exec2.buffers_ptr = args->buffers_ptr;
4031 exec2.buffer_count = args->buffer_count;
4032 exec2.batch_start_offset = args->batch_start_offset;
4033 exec2.batch_len = args->batch_len;
4034 exec2.DR1 = args->DR1;
4035 exec2.DR4 = args->DR4;
4036 exec2.num_cliprects = args->num_cliprects;
4037 exec2.cliprects_ptr = args->cliprects_ptr;
4038 exec2.flags = 0;
4039
4040 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4041 if (!ret) {
4042 /* Copy the new buffer offsets back to the user's exec list. */
4043 for (i = 0; i < args->buffer_count; i++)
4044 exec_list[i].offset = exec2_list[i].offset;
4045 /* ... and back out to userspace */
4046 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4047 (uintptr_t) args->buffers_ptr,
4048 exec_list,
4049 sizeof(*exec_list) * args->buffer_count);
4050 if (ret) {
4051 ret = -EFAULT;
4052 DRM_ERROR("failed to copy %d exec entries "
4053 "back to user (%d)\n",
4054 args->buffer_count, ret);
4055 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004056 }
4057
4058 drm_free_large(exec_list);
4059 drm_free_large(exec2_list);
4060 return ret;
4061}
4062
4063int
4064i915_gem_execbuffer2(struct drm_device *dev, void *data,
4065 struct drm_file *file_priv)
4066{
4067 struct drm_i915_gem_execbuffer2 *args = data;
4068 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4069 int ret;
4070
4071#if WATCH_EXEC
4072 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4073 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4074#endif
4075
4076 if (args->buffer_count < 1) {
4077 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4078 return -EINVAL;
4079 }
4080
4081 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4082 if (exec2_list == NULL) {
4083 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4084 args->buffer_count);
4085 return -ENOMEM;
4086 }
4087 ret = copy_from_user(exec2_list,
4088 (struct drm_i915_relocation_entry __user *)
4089 (uintptr_t) args->buffers_ptr,
4090 sizeof(*exec2_list) * args->buffer_count);
4091 if (ret != 0) {
4092 DRM_ERROR("copy %d exec entries failed %d\n",
4093 args->buffer_count, ret);
4094 drm_free_large(exec2_list);
4095 return -EFAULT;
4096 }
4097
4098 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4099 if (!ret) {
4100 /* Copy the new buffer offsets back to the user's exec list. */
4101 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4102 (uintptr_t) args->buffers_ptr,
4103 exec2_list,
4104 sizeof(*exec2_list) * args->buffer_count);
4105 if (ret) {
4106 ret = -EFAULT;
4107 DRM_ERROR("failed to copy %d exec entries "
4108 "back to user (%d)\n",
4109 args->buffer_count, ret);
4110 }
4111 }
4112
4113 drm_free_large(exec2_list);
4114 return ret;
4115}
4116
Eric Anholt673a3942008-07-30 12:06:12 -07004117int
4118i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4119{
4120 struct drm_device *dev = obj->dev;
4121 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4122 int ret;
4123
4124 i915_verify_inactive(dev, __FILE__, __LINE__);
4125 if (obj_priv->gtt_space == NULL) {
4126 ret = i915_gem_object_bind_to_gtt(obj, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01004127 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07004128 return ret;
Chris Wilson22c344e2009-02-11 14:26:45 +00004129 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004130
Eric Anholt673a3942008-07-30 12:06:12 -07004131 obj_priv->pin_count++;
4132
4133 /* If the object is not active and not pending a flush,
4134 * remove it from the inactive list
4135 */
4136 if (obj_priv->pin_count == 1) {
4137 atomic_inc(&dev->pin_count);
4138 atomic_add(obj->size, &dev->pin_memory);
4139 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004140 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
Eric Anholt673a3942008-07-30 12:06:12 -07004141 !list_empty(&obj_priv->list))
4142 list_del_init(&obj_priv->list);
4143 }
4144 i915_verify_inactive(dev, __FILE__, __LINE__);
4145
4146 return 0;
4147}
4148
4149void
4150i915_gem_object_unpin(struct drm_gem_object *obj)
4151{
4152 struct drm_device *dev = obj->dev;
4153 drm_i915_private_t *dev_priv = dev->dev_private;
4154 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4155
4156 i915_verify_inactive(dev, __FILE__, __LINE__);
4157 obj_priv->pin_count--;
4158 BUG_ON(obj_priv->pin_count < 0);
4159 BUG_ON(obj_priv->gtt_space == NULL);
4160
4161 /* If the object is no longer pinned, and is
4162 * neither active nor being flushed, then stick it on
4163 * the inactive list
4164 */
4165 if (obj_priv->pin_count == 0) {
4166 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004167 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004168 list_move_tail(&obj_priv->list,
4169 &dev_priv->mm.inactive_list);
4170 atomic_dec(&dev->pin_count);
4171 atomic_sub(obj->size, &dev->pin_memory);
4172 }
4173 i915_verify_inactive(dev, __FILE__, __LINE__);
4174}
4175
4176int
4177i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4178 struct drm_file *file_priv)
4179{
4180 struct drm_i915_gem_pin *args = data;
4181 struct drm_gem_object *obj;
4182 struct drm_i915_gem_object *obj_priv;
4183 int ret;
4184
4185 mutex_lock(&dev->struct_mutex);
4186
4187 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4188 if (obj == NULL) {
4189 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4190 args->handle);
4191 mutex_unlock(&dev->struct_mutex);
4192 return -EBADF;
4193 }
4194 obj_priv = obj->driver_private;
4195
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004196 if (obj_priv->madv != I915_MADV_WILLNEED) {
4197 DRM_ERROR("Attempting to pin a purgeable buffer\n");
Chris Wilson3ef94da2009-09-14 16:50:29 +01004198 drm_gem_object_unreference(obj);
4199 mutex_unlock(&dev->struct_mutex);
4200 return -EINVAL;
4201 }
4202
Jesse Barnes79e53942008-11-07 14:24:08 -08004203 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4204 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4205 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00004206 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004207 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004208 return -EINVAL;
4209 }
4210
4211 obj_priv->user_pin_count++;
4212 obj_priv->pin_filp = file_priv;
4213 if (obj_priv->user_pin_count == 1) {
4214 ret = i915_gem_object_pin(obj, args->alignment);
4215 if (ret != 0) {
4216 drm_gem_object_unreference(obj);
4217 mutex_unlock(&dev->struct_mutex);
4218 return ret;
4219 }
Eric Anholt673a3942008-07-30 12:06:12 -07004220 }
4221
4222 /* XXX - flush the CPU caches for pinned objects
4223 * as the X server doesn't manage domains yet
4224 */
Eric Anholte47c68e2008-11-14 13:35:19 -08004225 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004226 args->offset = obj_priv->gtt_offset;
4227 drm_gem_object_unreference(obj);
4228 mutex_unlock(&dev->struct_mutex);
4229
4230 return 0;
4231}
4232
4233int
4234i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4235 struct drm_file *file_priv)
4236{
4237 struct drm_i915_gem_pin *args = data;
4238 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08004239 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07004240
4241 mutex_lock(&dev->struct_mutex);
4242
4243 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4244 if (obj == NULL) {
4245 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4246 args->handle);
4247 mutex_unlock(&dev->struct_mutex);
4248 return -EBADF;
4249 }
4250
Jesse Barnes79e53942008-11-07 14:24:08 -08004251 obj_priv = obj->driver_private;
4252 if (obj_priv->pin_filp != file_priv) {
4253 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4254 args->handle);
4255 drm_gem_object_unreference(obj);
4256 mutex_unlock(&dev->struct_mutex);
4257 return -EINVAL;
4258 }
4259 obj_priv->user_pin_count--;
4260 if (obj_priv->user_pin_count == 0) {
4261 obj_priv->pin_filp = NULL;
4262 i915_gem_object_unpin(obj);
4263 }
Eric Anholt673a3942008-07-30 12:06:12 -07004264
4265 drm_gem_object_unreference(obj);
4266 mutex_unlock(&dev->struct_mutex);
4267 return 0;
4268}
4269
4270int
4271i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4272 struct drm_file *file_priv)
4273{
4274 struct drm_i915_gem_busy *args = data;
4275 struct drm_gem_object *obj;
4276 struct drm_i915_gem_object *obj_priv;
4277
Eric Anholt673a3942008-07-30 12:06:12 -07004278 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4279 if (obj == NULL) {
4280 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4281 args->handle);
Eric Anholt673a3942008-07-30 12:06:12 -07004282 return -EBADF;
4283 }
4284
Chris Wilsonb1ce7862009-06-06 09:46:00 +01004285 mutex_lock(&dev->struct_mutex);
Eric Anholtf21289b2009-02-18 09:44:56 -08004286 /* Update the active list for the hardware's current position.
4287 * Otherwise this only updates on a delayed timer or when irqs are
4288 * actually unmasked, and our working set ends up being larger than
4289 * required.
4290 */
4291 i915_gem_retire_requests(dev);
4292
Eric Anholt673a3942008-07-30 12:06:12 -07004293 obj_priv = obj->driver_private;
Eric Anholtc4de0a52008-12-14 19:05:04 -08004294 /* Don't count being on the flushing list against the object being
4295 * done. Otherwise, a buffer left on the flushing list but not getting
4296 * flushed (because nobody's flushing that domain) won't ever return
4297 * unbusy and get reused by libdrm's bo cache. The other expected
4298 * consumer of this interface, OpenGL's occlusion queries, also specs
4299 * that the objects get unbusy "eventually" without any interference.
4300 */
4301 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004302
4303 drm_gem_object_unreference(obj);
4304 mutex_unlock(&dev->struct_mutex);
4305 return 0;
4306}
4307
4308int
4309i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4310 struct drm_file *file_priv)
4311{
4312 return i915_gem_ring_throttle(dev, file_priv);
4313}
4314
Chris Wilson3ef94da2009-09-14 16:50:29 +01004315int
4316i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4317 struct drm_file *file_priv)
4318{
4319 struct drm_i915_gem_madvise *args = data;
4320 struct drm_gem_object *obj;
4321 struct drm_i915_gem_object *obj_priv;
4322
4323 switch (args->madv) {
4324 case I915_MADV_DONTNEED:
4325 case I915_MADV_WILLNEED:
4326 break;
4327 default:
4328 return -EINVAL;
4329 }
4330
4331 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4332 if (obj == NULL) {
4333 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4334 args->handle);
4335 return -EBADF;
4336 }
4337
4338 mutex_lock(&dev->struct_mutex);
4339 obj_priv = obj->driver_private;
4340
4341 if (obj_priv->pin_count) {
4342 drm_gem_object_unreference(obj);
4343 mutex_unlock(&dev->struct_mutex);
4344
4345 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4346 return -EINVAL;
4347 }
4348
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004349 if (obj_priv->madv != __I915_MADV_PURGED)
4350 obj_priv->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004351
Chris Wilson2d7ef392009-09-20 23:13:10 +01004352 /* if the object is no longer bound, discard its backing storage */
4353 if (i915_gem_object_is_purgeable(obj_priv) &&
4354 obj_priv->gtt_space == NULL)
4355 i915_gem_object_truncate(obj);
4356
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004357 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4358
Chris Wilson3ef94da2009-09-14 16:50:29 +01004359 drm_gem_object_unreference(obj);
4360 mutex_unlock(&dev->struct_mutex);
4361
4362 return 0;
4363}
4364
Eric Anholt673a3942008-07-30 12:06:12 -07004365int i915_gem_init_object(struct drm_gem_object *obj)
4366{
4367 struct drm_i915_gem_object *obj_priv;
4368
Eric Anholt9a298b22009-03-24 12:23:04 -07004369 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07004370 if (obj_priv == NULL)
4371 return -ENOMEM;
4372
4373 /*
4374 * We've just allocated pages from the kernel,
4375 * so they've just been written by the CPU with
4376 * zeros. They'll need to be clflushed before we
4377 * use them with the GPU.
4378 */
4379 obj->write_domain = I915_GEM_DOMAIN_CPU;
4380 obj->read_domains = I915_GEM_DOMAIN_CPU;
4381
Keith Packardba1eb1d2008-10-14 19:55:10 -07004382 obj_priv->agp_type = AGP_USER_MEMORY;
4383
Eric Anholt673a3942008-07-30 12:06:12 -07004384 obj->driver_private = obj_priv;
4385 obj_priv->obj = obj;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004386 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholt673a3942008-07-30 12:06:12 -07004387 INIT_LIST_HEAD(&obj_priv->list);
Daniel Vetter99fcb762010-02-07 16:20:18 +01004388 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004389 INIT_LIST_HEAD(&obj_priv->fence_list);
Chris Wilson3ef94da2009-09-14 16:50:29 +01004390 obj_priv->madv = I915_MADV_WILLNEED;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004391
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004392 trace_i915_gem_object_create(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004393
4394 return 0;
4395}
4396
4397void i915_gem_free_object(struct drm_gem_object *obj)
4398{
Jesse Barnesde151cf2008-11-12 10:03:55 -08004399 struct drm_device *dev = obj->dev;
Eric Anholt673a3942008-07-30 12:06:12 -07004400 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4401
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004402 trace_i915_gem_object_destroy(obj);
4403
Eric Anholt673a3942008-07-30 12:06:12 -07004404 while (obj_priv->pin_count > 0)
4405 i915_gem_object_unpin(obj);
4406
Dave Airlie71acb5e2008-12-30 20:31:46 +10004407 if (obj_priv->phys_obj)
4408 i915_gem_detach_phys_object(dev, obj);
4409
Eric Anholt673a3942008-07-30 12:06:12 -07004410 i915_gem_object_unbind(obj);
4411
Chris Wilson7e616152009-09-10 08:53:04 +01004412 if (obj_priv->mmap_offset)
4413 i915_gem_free_mmap_offset(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08004414
Eric Anholt9a298b22009-03-24 12:23:04 -07004415 kfree(obj_priv->page_cpu_valid);
Eric Anholt280b7132009-03-12 16:56:27 -07004416 kfree(obj_priv->bit_17);
Eric Anholt9a298b22009-03-24 12:23:04 -07004417 kfree(obj->driver_private);
Eric Anholt673a3942008-07-30 12:06:12 -07004418}
4419
Chris Wilsonab5ee572009-09-20 19:25:47 +01004420/** Unbinds all inactive objects. */
Eric Anholt673a3942008-07-30 12:06:12 -07004421static int
Chris Wilsonab5ee572009-09-20 19:25:47 +01004422i915_gem_evict_from_inactive_list(struct drm_device *dev)
Eric Anholt673a3942008-07-30 12:06:12 -07004423{
Chris Wilsonab5ee572009-09-20 19:25:47 +01004424 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07004425
Chris Wilsonab5ee572009-09-20 19:25:47 +01004426 while (!list_empty(&dev_priv->mm.inactive_list)) {
4427 struct drm_gem_object *obj;
4428 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004429
Chris Wilsonab5ee572009-09-20 19:25:47 +01004430 obj = list_first_entry(&dev_priv->mm.inactive_list,
4431 struct drm_i915_gem_object,
4432 list)->obj;
Eric Anholt673a3942008-07-30 12:06:12 -07004433
4434 ret = i915_gem_object_unbind(obj);
4435 if (ret != 0) {
Chris Wilsonab5ee572009-09-20 19:25:47 +01004436 DRM_ERROR("Error unbinding object: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004437 return ret;
4438 }
4439 }
4440
Eric Anholt673a3942008-07-30 12:06:12 -07004441 return 0;
4442}
4443
Chris Wilson29105cc2010-01-07 10:39:13 +00004444static int
4445i915_gpu_idle(struct drm_device *dev)
4446{
4447 drm_i915_private_t *dev_priv = dev->dev_private;
4448 bool lists_empty;
4449 uint32_t seqno;
4450
4451 spin_lock(&dev_priv->mm.active_list_lock);
4452 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4453 list_empty(&dev_priv->mm.active_list);
4454 spin_unlock(&dev_priv->mm.active_list_lock);
4455
4456 if (lists_empty)
4457 return 0;
4458
4459 /* Flush everything onto the inactive list. */
4460 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4461 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4462 if (seqno == 0)
4463 return -ENOMEM;
4464
4465 return i915_wait_request(dev, seqno);
4466}
4467
Jesse Barnes5669fca2009-02-17 15:13:31 -08004468int
Eric Anholt673a3942008-07-30 12:06:12 -07004469i915_gem_idle(struct drm_device *dev)
4470{
4471 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson29105cc2010-01-07 10:39:13 +00004472 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004473
Keith Packard6dbe2772008-10-14 21:41:13 -07004474 mutex_lock(&dev->struct_mutex);
4475
4476 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4477 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004478 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07004479 }
Eric Anholt673a3942008-07-30 12:06:12 -07004480
Chris Wilson29105cc2010-01-07 10:39:13 +00004481 ret = i915_gpu_idle(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004482 if (ret) {
4483 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004484 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07004485 }
Eric Anholt673a3942008-07-30 12:06:12 -07004486
Chris Wilson29105cc2010-01-07 10:39:13 +00004487 /* Under UMS, be paranoid and evict. */
4488 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4489 ret = i915_gem_evict_from_inactive_list(dev);
4490 if (ret) {
4491 mutex_unlock(&dev->struct_mutex);
4492 return ret;
4493 }
4494 }
4495
4496 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4497 * We need to replace this with a semaphore, or something.
4498 * And not confound mm.suspended!
4499 */
4500 dev_priv->mm.suspended = 1;
4501 del_timer(&dev_priv->hangcheck_timer);
4502
4503 i915_kernel_lost_context(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004504 i915_gem_cleanup_ringbuffer(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004505
Keith Packard6dbe2772008-10-14 21:41:13 -07004506 mutex_unlock(&dev->struct_mutex);
4507
Chris Wilson29105cc2010-01-07 10:39:13 +00004508 /* Cancel the retire work handler, which should be idle now. */
4509 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4510
Eric Anholt673a3942008-07-30 12:06:12 -07004511 return 0;
4512}
4513
4514static int
4515i915_gem_init_hws(struct drm_device *dev)
4516{
4517 drm_i915_private_t *dev_priv = dev->dev_private;
4518 struct drm_gem_object *obj;
4519 struct drm_i915_gem_object *obj_priv;
4520 int ret;
4521
4522 /* If we need a physical address for the status page, it's already
4523 * initialized at driver load time.
4524 */
4525 if (!I915_NEED_GFX_HWS(dev))
4526 return 0;
4527
4528 obj = drm_gem_object_alloc(dev, 4096);
4529 if (obj == NULL) {
4530 DRM_ERROR("Failed to allocate status page\n");
4531 return -ENOMEM;
4532 }
4533 obj_priv = obj->driver_private;
Keith Packardba1eb1d2008-10-14 19:55:10 -07004534 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
Eric Anholt673a3942008-07-30 12:06:12 -07004535
4536 ret = i915_gem_object_pin(obj, 4096);
4537 if (ret != 0) {
4538 drm_gem_object_unreference(obj);
4539 return ret;
4540 }
4541
4542 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07004543
Eric Anholt856fa192009-03-19 14:10:50 -07004544 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
Keith Packardba1eb1d2008-10-14 19:55:10 -07004545 if (dev_priv->hw_status_page == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07004546 DRM_ERROR("Failed to map status page.\n");
4547 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
Chris Wilson3eb2ee72009-02-11 14:26:34 +00004548 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004549 drm_gem_object_unreference(obj);
4550 return -EINVAL;
4551 }
4552 dev_priv->hws_obj = obj;
Eric Anholt673a3942008-07-30 12:06:12 -07004553 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4554 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
Keith Packardba1eb1d2008-10-14 19:55:10 -07004555 I915_READ(HWS_PGA); /* posting read */
Zhao Yakui44d98a62009-10-09 11:39:40 +08004556 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
Eric Anholt673a3942008-07-30 12:06:12 -07004557
4558 return 0;
4559}
4560
Chris Wilson85a7bb92009-02-11 14:52:44 +00004561static void
4562i915_gem_cleanup_hws(struct drm_device *dev)
4563{
4564 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004565 struct drm_gem_object *obj;
4566 struct drm_i915_gem_object *obj_priv;
Chris Wilson85a7bb92009-02-11 14:52:44 +00004567
4568 if (dev_priv->hws_obj == NULL)
4569 return;
4570
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004571 obj = dev_priv->hws_obj;
4572 obj_priv = obj->driver_private;
4573
Eric Anholt856fa192009-03-19 14:10:50 -07004574 kunmap(obj_priv->pages[0]);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004575 i915_gem_object_unpin(obj);
4576 drm_gem_object_unreference(obj);
4577 dev_priv->hws_obj = NULL;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00004578
Chris Wilson85a7bb92009-02-11 14:52:44 +00004579 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4580 dev_priv->hw_status_page = NULL;
4581
4582 /* Write high address into HWS_PGA when disabling. */
4583 I915_WRITE(HWS_PGA, 0x1ffff000);
4584}
4585
Jesse Barnes79e53942008-11-07 14:24:08 -08004586int
Eric Anholt673a3942008-07-30 12:06:12 -07004587i915_gem_init_ringbuffer(struct drm_device *dev)
4588{
4589 drm_i915_private_t *dev_priv = dev->dev_private;
4590 struct drm_gem_object *obj;
4591 struct drm_i915_gem_object *obj_priv;
Jesse Barnes79e53942008-11-07 14:24:08 -08004592 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
Eric Anholt673a3942008-07-30 12:06:12 -07004593 int ret;
Keith Packard50aa2532008-10-14 17:20:35 -07004594 u32 head;
Eric Anholt673a3942008-07-30 12:06:12 -07004595
4596 ret = i915_gem_init_hws(dev);
4597 if (ret != 0)
4598 return ret;
4599
4600 obj = drm_gem_object_alloc(dev, 128 * 1024);
4601 if (obj == NULL) {
4602 DRM_ERROR("Failed to allocate ringbuffer\n");
Chris Wilson85a7bb92009-02-11 14:52:44 +00004603 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004604 return -ENOMEM;
4605 }
4606 obj_priv = obj->driver_private;
4607
4608 ret = i915_gem_object_pin(obj, 4096);
4609 if (ret != 0) {
4610 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004611 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004612 return ret;
4613 }
4614
4615 /* Set up the kernel mapping for the ring. */
Jesse Barnes79e53942008-11-07 14:24:08 -08004616 ring->Size = obj->size;
Eric Anholt673a3942008-07-30 12:06:12 -07004617
Jesse Barnes79e53942008-11-07 14:24:08 -08004618 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4619 ring->map.size = obj->size;
4620 ring->map.type = 0;
4621 ring->map.flags = 0;
4622 ring->map.mtrr = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004623
Jesse Barnes79e53942008-11-07 14:24:08 -08004624 drm_core_ioremap_wc(&ring->map, dev);
4625 if (ring->map.handle == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07004626 DRM_ERROR("Failed to map ringbuffer.\n");
4627 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
Chris Wilson47ed1852009-02-11 14:26:33 +00004628 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004629 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00004630 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004631 return -EINVAL;
4632 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004633 ring->ring_obj = obj;
4634 ring->virtual_start = ring->map.handle;
Eric Anholt673a3942008-07-30 12:06:12 -07004635
4636 /* Stop the ring if it's running. */
4637 I915_WRITE(PRB0_CTL, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004638 I915_WRITE(PRB0_TAIL, 0);
Keith Packard50aa2532008-10-14 17:20:35 -07004639 I915_WRITE(PRB0_HEAD, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004640
4641 /* Initialize the ring. */
4642 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
Keith Packard50aa2532008-10-14 17:20:35 -07004643 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4644
4645 /* G45 ring initialization fails to reset head to zero */
4646 if (head != 0) {
4647 DRM_ERROR("Ring head not reset to zero "
4648 "ctl %08x head %08x tail %08x start %08x\n",
4649 I915_READ(PRB0_CTL),
4650 I915_READ(PRB0_HEAD),
4651 I915_READ(PRB0_TAIL),
4652 I915_READ(PRB0_START));
4653 I915_WRITE(PRB0_HEAD, 0);
4654
4655 DRM_ERROR("Ring head forced to zero "
4656 "ctl %08x head %08x tail %08x start %08x\n",
4657 I915_READ(PRB0_CTL),
4658 I915_READ(PRB0_HEAD),
4659 I915_READ(PRB0_TAIL),
4660 I915_READ(PRB0_START));
4661 }
4662
Eric Anholt673a3942008-07-30 12:06:12 -07004663 I915_WRITE(PRB0_CTL,
4664 ((obj->size - 4096) & RING_NR_PAGES) |
4665 RING_NO_REPORT |
4666 RING_VALID);
4667
Keith Packard50aa2532008-10-14 17:20:35 -07004668 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4669
4670 /* If the head is still not zero, the ring is dead */
4671 if (head != 0) {
4672 DRM_ERROR("Ring initialization failed "
4673 "ctl %08x head %08x tail %08x start %08x\n",
4674 I915_READ(PRB0_CTL),
4675 I915_READ(PRB0_HEAD),
4676 I915_READ(PRB0_TAIL),
4677 I915_READ(PRB0_START));
4678 return -EIO;
4679 }
4680
Eric Anholt673a3942008-07-30 12:06:12 -07004681 /* Update our cache of the ring state */
Jesse Barnes79e53942008-11-07 14:24:08 -08004682 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4683 i915_kernel_lost_context(dev);
4684 else {
4685 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4686 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4687 ring->space = ring->head - (ring->tail + 8);
4688 if (ring->space < 0)
4689 ring->space += ring->Size;
4690 }
Eric Anholt673a3942008-07-30 12:06:12 -07004691
4692 return 0;
4693}
4694
Jesse Barnes79e53942008-11-07 14:24:08 -08004695void
Eric Anholt673a3942008-07-30 12:06:12 -07004696i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4697{
4698 drm_i915_private_t *dev_priv = dev->dev_private;
4699
4700 if (dev_priv->ring.ring_obj == NULL)
4701 return;
4702
4703 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4704
4705 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4706 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4707 dev_priv->ring.ring_obj = NULL;
4708 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4709
Chris Wilson85a7bb92009-02-11 14:52:44 +00004710 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004711}
4712
4713int
4714i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4715 struct drm_file *file_priv)
4716{
4717 drm_i915_private_t *dev_priv = dev->dev_private;
4718 int ret;
4719
Jesse Barnes79e53942008-11-07 14:24:08 -08004720 if (drm_core_check_feature(dev, DRIVER_MODESET))
4721 return 0;
4722
Ben Gamariba1234d2009-09-14 17:48:47 -04004723 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07004724 DRM_ERROR("Reenabling wedged hardware, good luck\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004725 atomic_set(&dev_priv->mm.wedged, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004726 }
4727
Eric Anholt673a3942008-07-30 12:06:12 -07004728 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004729 dev_priv->mm.suspended = 0;
4730
4731 ret = i915_gem_init_ringbuffer(dev);
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004732 if (ret != 0) {
4733 mutex_unlock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004734 return ret;
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004735 }
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004736
Carl Worth5e118f42009-03-20 11:54:25 -07004737 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004738 BUG_ON(!list_empty(&dev_priv->mm.active_list));
Carl Worth5e118f42009-03-20 11:54:25 -07004739 spin_unlock(&dev_priv->mm.active_list_lock);
4740
Eric Anholt673a3942008-07-30 12:06:12 -07004741 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4742 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4743 BUG_ON(!list_empty(&dev_priv->mm.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004744 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004745
4746 drm_irq_install(dev);
4747
Eric Anholt673a3942008-07-30 12:06:12 -07004748 return 0;
4749}
4750
4751int
4752i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4753 struct drm_file *file_priv)
4754{
Jesse Barnes79e53942008-11-07 14:24:08 -08004755 if (drm_core_check_feature(dev, DRIVER_MODESET))
4756 return 0;
4757
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004758 drm_irq_uninstall(dev);
Linus Torvaldse6890f62009-09-08 17:09:24 -07004759 return i915_gem_idle(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004760}
4761
4762void
4763i915_gem_lastclose(struct drm_device *dev)
4764{
4765 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004766
Eric Anholte806b492009-01-22 09:56:58 -08004767 if (drm_core_check_feature(dev, DRIVER_MODESET))
4768 return;
4769
Keith Packard6dbe2772008-10-14 21:41:13 -07004770 ret = i915_gem_idle(dev);
4771 if (ret)
4772 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004773}
4774
4775void
4776i915_gem_load(struct drm_device *dev)
4777{
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004778 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07004779 drm_i915_private_t *dev_priv = dev->dev_private;
4780
Carl Worth5e118f42009-03-20 11:54:25 -07004781 spin_lock_init(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004782 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4783 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
Daniel Vetter99fcb762010-02-07 16:20:18 +01004784 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004785 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4786 INIT_LIST_HEAD(&dev_priv->mm.request_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004787 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004788 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4789 i915_gem_retire_work_handler);
Eric Anholt673a3942008-07-30 12:06:12 -07004790 dev_priv->mm.next_gem_seqno = 1;
4791
Chris Wilson31169712009-09-14 16:50:28 +01004792 spin_lock(&shrink_list_lock);
4793 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4794 spin_unlock(&shrink_list_lock);
4795
Jesse Barnesde151cf2008-11-12 10:03:55 -08004796 /* Old X drivers will take 0-2 for front, back, depth buffers */
4797 dev_priv->fence_reg_start = 3;
4798
Jesse Barnes0f973f22009-01-26 17:10:45 -08004799 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004800 dev_priv->num_fence_regs = 16;
4801 else
4802 dev_priv->num_fence_regs = 8;
4803
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004804 /* Initialize fence registers to zero */
4805 if (IS_I965G(dev)) {
4806 for (i = 0; i < 16; i++)
4807 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4808 } else {
4809 for (i = 0; i < 8; i++)
4810 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4811 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4812 for (i = 0; i < 8; i++)
4813 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4814 }
Eric Anholt673a3942008-07-30 12:06:12 -07004815 i915_gem_detect_bit_6_swizzle(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004816 init_waitqueue_head(&dev_priv->pending_flip_queue);
Eric Anholt673a3942008-07-30 12:06:12 -07004817}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004818
4819/*
4820 * Create a physically contiguous memory object for this object
4821 * e.g. for cursor + overlay regs
4822 */
4823int i915_gem_init_phys_object(struct drm_device *dev,
4824 int id, int size)
4825{
4826 drm_i915_private_t *dev_priv = dev->dev_private;
4827 struct drm_i915_gem_phys_object *phys_obj;
4828 int ret;
4829
4830 if (dev_priv->mm.phys_objs[id - 1] || !size)
4831 return 0;
4832
Eric Anholt9a298b22009-03-24 12:23:04 -07004833 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004834 if (!phys_obj)
4835 return -ENOMEM;
4836
4837 phys_obj->id = id;
4838
Zhenyu Wange6be8d92010-01-05 11:25:05 +08004839 phys_obj->handle = drm_pci_alloc(dev, size, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004840 if (!phys_obj->handle) {
4841 ret = -ENOMEM;
4842 goto kfree_obj;
4843 }
4844#ifdef CONFIG_X86
4845 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4846#endif
4847
4848 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4849
4850 return 0;
4851kfree_obj:
Eric Anholt9a298b22009-03-24 12:23:04 -07004852 kfree(phys_obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004853 return ret;
4854}
4855
4856void i915_gem_free_phys_object(struct drm_device *dev, int id)
4857{
4858 drm_i915_private_t *dev_priv = dev->dev_private;
4859 struct drm_i915_gem_phys_object *phys_obj;
4860
4861 if (!dev_priv->mm.phys_objs[id - 1])
4862 return;
4863
4864 phys_obj = dev_priv->mm.phys_objs[id - 1];
4865 if (phys_obj->cur_obj) {
4866 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4867 }
4868
4869#ifdef CONFIG_X86
4870 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4871#endif
4872 drm_pci_free(dev, phys_obj->handle);
4873 kfree(phys_obj);
4874 dev_priv->mm.phys_objs[id - 1] = NULL;
4875}
4876
4877void i915_gem_free_all_phys_object(struct drm_device *dev)
4878{
4879 int i;
4880
Dave Airlie260883c2009-01-22 17:58:49 +10004881 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004882 i915_gem_free_phys_object(dev, i);
4883}
4884
4885void i915_gem_detach_phys_object(struct drm_device *dev,
4886 struct drm_gem_object *obj)
4887{
4888 struct drm_i915_gem_object *obj_priv;
4889 int i;
4890 int ret;
4891 int page_count;
4892
4893 obj_priv = obj->driver_private;
4894 if (!obj_priv->phys_obj)
4895 return;
4896
Chris Wilson4bdadb92010-01-27 13:36:32 +00004897 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004898 if (ret)
4899 goto out;
4900
4901 page_count = obj->size / PAGE_SIZE;
4902
4903 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004904 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004905 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4906
4907 memcpy(dst, src, PAGE_SIZE);
4908 kunmap_atomic(dst, KM_USER0);
4909 }
Eric Anholt856fa192009-03-19 14:10:50 -07004910 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004911 drm_agp_chipset_flush(dev);
Chris Wilsond78b47b2009-06-17 21:52:49 +01004912
4913 i915_gem_object_put_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004914out:
4915 obj_priv->phys_obj->cur_obj = NULL;
4916 obj_priv->phys_obj = NULL;
4917}
4918
4919int
4920i915_gem_attach_phys_object(struct drm_device *dev,
4921 struct drm_gem_object *obj, int id)
4922{
4923 drm_i915_private_t *dev_priv = dev->dev_private;
4924 struct drm_i915_gem_object *obj_priv;
4925 int ret = 0;
4926 int page_count;
4927 int i;
4928
4929 if (id > I915_MAX_PHYS_OBJECT)
4930 return -EINVAL;
4931
4932 obj_priv = obj->driver_private;
4933
4934 if (obj_priv->phys_obj) {
4935 if (obj_priv->phys_obj->id == id)
4936 return 0;
4937 i915_gem_detach_phys_object(dev, obj);
4938 }
4939
4940
4941 /* create a new object */
4942 if (!dev_priv->mm.phys_objs[id - 1]) {
4943 ret = i915_gem_init_phys_object(dev, id,
4944 obj->size);
4945 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004946 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004947 goto out;
4948 }
4949 }
4950
4951 /* bind to the object */
4952 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4953 obj_priv->phys_obj->cur_obj = obj;
4954
Chris Wilson4bdadb92010-01-27 13:36:32 +00004955 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004956 if (ret) {
4957 DRM_ERROR("failed to get page list\n");
4958 goto out;
4959 }
4960
4961 page_count = obj->size / PAGE_SIZE;
4962
4963 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004964 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004965 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4966
4967 memcpy(dst, src, PAGE_SIZE);
4968 kunmap_atomic(src, KM_USER0);
4969 }
4970
Chris Wilsond78b47b2009-06-17 21:52:49 +01004971 i915_gem_object_put_pages(obj);
4972
Dave Airlie71acb5e2008-12-30 20:31:46 +10004973 return 0;
4974out:
4975 return ret;
4976}
4977
4978static int
4979i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4980 struct drm_i915_gem_pwrite *args,
4981 struct drm_file *file_priv)
4982{
4983 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4984 void *obj_addr;
4985 int ret;
4986 char __user *user_data;
4987
4988 user_data = (char __user *) (uintptr_t) args->data_ptr;
4989 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4990
Zhao Yakui44d98a62009-10-09 11:39:40 +08004991 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004992 ret = copy_from_user(obj_addr, user_data, args->size);
4993 if (ret)
4994 return -EFAULT;
4995
4996 drm_agp_chipset_flush(dev);
4997 return 0;
4998}
Eric Anholtb9624422009-06-03 07:27:35 +00004999
5000void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5001{
5002 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5003
5004 /* Clean up our request list when the client is going away, so that
5005 * later retire_requests won't dereference our soon-to-be-gone
5006 * file_priv.
5007 */
5008 mutex_lock(&dev->struct_mutex);
5009 while (!list_empty(&i915_file_priv->mm.request_list))
5010 list_del_init(i915_file_priv->mm.request_list.next);
5011 mutex_unlock(&dev->struct_mutex);
5012}
Chris Wilson31169712009-09-14 16:50:28 +01005013
Chris Wilson31169712009-09-14 16:50:28 +01005014static int
5015i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5016{
5017 drm_i915_private_t *dev_priv, *next_dev;
5018 struct drm_i915_gem_object *obj_priv, *next_obj;
5019 int cnt = 0;
5020 int would_deadlock = 1;
5021
5022 /* "fast-path" to count number of available objects */
5023 if (nr_to_scan == 0) {
5024 spin_lock(&shrink_list_lock);
5025 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5026 struct drm_device *dev = dev_priv->dev;
5027
5028 if (mutex_trylock(&dev->struct_mutex)) {
5029 list_for_each_entry(obj_priv,
5030 &dev_priv->mm.inactive_list,
5031 list)
5032 cnt++;
5033 mutex_unlock(&dev->struct_mutex);
5034 }
5035 }
5036 spin_unlock(&shrink_list_lock);
5037
5038 return (cnt / 100) * sysctl_vfs_cache_pressure;
5039 }
5040
5041 spin_lock(&shrink_list_lock);
5042
5043 /* first scan for clean buffers */
5044 list_for_each_entry_safe(dev_priv, next_dev,
5045 &shrink_list, mm.shrink_list) {
5046 struct drm_device *dev = dev_priv->dev;
5047
5048 if (! mutex_trylock(&dev->struct_mutex))
5049 continue;
5050
5051 spin_unlock(&shrink_list_lock);
5052
5053 i915_gem_retire_requests(dev);
5054
5055 list_for_each_entry_safe(obj_priv, next_obj,
5056 &dev_priv->mm.inactive_list,
5057 list) {
5058 if (i915_gem_object_is_purgeable(obj_priv)) {
Chris Wilson963b4832009-09-20 23:03:54 +01005059 i915_gem_object_unbind(obj_priv->obj);
Chris Wilson31169712009-09-14 16:50:28 +01005060 if (--nr_to_scan <= 0)
5061 break;
5062 }
5063 }
5064
5065 spin_lock(&shrink_list_lock);
5066 mutex_unlock(&dev->struct_mutex);
5067
Chris Wilson963b4832009-09-20 23:03:54 +01005068 would_deadlock = 0;
5069
Chris Wilson31169712009-09-14 16:50:28 +01005070 if (nr_to_scan <= 0)
5071 break;
5072 }
5073
5074 /* second pass, evict/count anything still on the inactive list */
5075 list_for_each_entry_safe(dev_priv, next_dev,
5076 &shrink_list, mm.shrink_list) {
5077 struct drm_device *dev = dev_priv->dev;
5078
5079 if (! mutex_trylock(&dev->struct_mutex))
5080 continue;
5081
5082 spin_unlock(&shrink_list_lock);
5083
5084 list_for_each_entry_safe(obj_priv, next_obj,
5085 &dev_priv->mm.inactive_list,
5086 list) {
5087 if (nr_to_scan > 0) {
Chris Wilson963b4832009-09-20 23:03:54 +01005088 i915_gem_object_unbind(obj_priv->obj);
Chris Wilson31169712009-09-14 16:50:28 +01005089 nr_to_scan--;
5090 } else
5091 cnt++;
5092 }
5093
5094 spin_lock(&shrink_list_lock);
5095 mutex_unlock(&dev->struct_mutex);
5096
5097 would_deadlock = 0;
5098 }
5099
5100 spin_unlock(&shrink_list_lock);
5101
5102 if (would_deadlock)
5103 return -1;
5104 else if (cnt > 0)
5105 return (cnt / 100) * sysctl_vfs_cache_pressure;
5106 else
5107 return 0;
5108}
5109
5110static struct shrinker shrinker = {
5111 .shrink = i915_gem_shrink,
5112 .seeks = DEFAULT_SEEKS,
5113};
5114
5115__init void
5116i915_gem_shrinker_init(void)
5117{
5118 register_shrinker(&shrinker);
5119}
5120
5121__exit void
5122i915_gem_shrinker_exit(void)
5123{
5124 unregister_shrinker(&shrinker);
5125}