Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/list.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/msm_rotator.h> |
| 18 | #include <linux/clkdev.h> |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 19 | #include <linux/dma-mapping.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <mach/irqs-8064.h> |
| 21 | #include <mach/board.h> |
| 22 | #include <mach/msm_iomap.h> |
Yan He | 06913ce | 2011-08-26 16:33:46 -0700 | [diff] [blame] | 23 | #include <mach/usbdiag.h> |
| 24 | #include <mach/msm_sps.h> |
Jeff Ohlstein | 905f1ce | 2011-09-07 18:50:18 -0700 | [diff] [blame] | 25 | #include <mach/dma.h> |
Bharath Ramachandramurthy | b8e797f | 2011-11-30 12:08:42 -0800 | [diff] [blame] | 26 | #include <sound/msm-dai-q6.h> |
| 27 | #include <sound/apr_audio.h> |
Gagan Mac | 8a7a5d3 | 2011-11-11 16:43:06 -0700 | [diff] [blame] | 28 | #include <mach/msm_bus_board.h> |
Praveen Chidambaram | 7849901 | 2011-11-01 17:15:17 -0600 | [diff] [blame] | 29 | #include <mach/rpm.h> |
Joel King | dacbc82 | 2012-01-25 13:30:57 -0800 | [diff] [blame] | 30 | #include <mach/mdm2.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 31 | #include "clock.h" |
| 32 | #include "devices.h" |
Jeff Ohlstein | 7e66855 | 2011-10-06 16:17:25 -0700 | [diff] [blame] | 33 | #include "msm_watchdog.h" |
Praveen Chidambaram | 7849901 | 2011-11-01 17:15:17 -0600 | [diff] [blame] | 34 | #include "rpm_stats.h" |
| 35 | #include "rpm_log.h" |
| 36 | #include "mpm.h" |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 37 | |
| 38 | /* Address of GSBI blocks */ |
Stepan Moskovchenko | 2701a44 | 2011-08-19 13:47:22 -0700 | [diff] [blame] | 39 | #define MSM_GSBI1_PHYS 0x12440000 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 40 | #define MSM_GSBI3_PHYS 0x16200000 |
Harini Jayaraman | c4c5869 | 2011-07-19 14:50:10 -0600 | [diff] [blame] | 41 | #define MSM_GSBI4_PHYS 0x16300000 |
| 42 | #define MSM_GSBI5_PHYS 0x1A200000 |
| 43 | #define MSM_GSBI6_PHYS 0x16500000 |
| 44 | #define MSM_GSBI7_PHYS 0x16600000 |
| 45 | |
Kenneth Heitke | 748593a | 2011-07-15 15:45:11 -0600 | [diff] [blame] | 46 | /* GSBI UART devices */ |
Stepan Moskovchenko | 2701a44 | 2011-08-19 13:47:22 -0700 | [diff] [blame] | 47 | #define MSM_UART1DM_PHYS (MSM_GSBI1_PHYS + 0x10000) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 48 | #define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000) |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame^] | 49 | #define MSM_UART7DM_PHYS (MSM_GSBI7_PHYS + 0x40000) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 50 | |
Harini Jayaraman | c4c5869 | 2011-07-19 14:50:10 -0600 | [diff] [blame] | 51 | /* GSBI QUP devices */ |
| 52 | #define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000) |
| 53 | #define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000) |
| 54 | #define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000) |
| 55 | #define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000) |
| 56 | #define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000) |
| 57 | #define MSM_QUP_SIZE SZ_4K |
| 58 | |
Kenneth Heitke | 36920d3 | 2011-07-20 16:44:30 -0600 | [diff] [blame] | 59 | /* Address of SSBI CMD */ |
| 60 | #define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000 |
| 61 | #define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000 |
| 62 | #define MSM_PMIC_SSBI_SIZE SZ_4K |
Harini Jayaraman | c4c5869 | 2011-07-19 14:50:10 -0600 | [diff] [blame] | 63 | |
Hemant Kumar | caa0909 | 2011-07-30 00:26:33 -0700 | [diff] [blame] | 64 | /* Address of HS USBOTG1 */ |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 65 | #define MSM_HSUSB1_PHYS 0x12500000 |
| 66 | #define MSM_HSUSB1_SIZE SZ_4K |
Hemant Kumar | caa0909 | 2011-07-30 00:26:33 -0700 | [diff] [blame] | 67 | |
Jeff Ohlstein | 7e66855 | 2011-10-06 16:17:25 -0700 | [diff] [blame] | 68 | static struct msm_watchdog_pdata msm_watchdog_pdata = { |
| 69 | .pet_time = 10000, |
| 70 | .bark_time = 11000, |
| 71 | .has_secure = true, |
| 72 | }; |
| 73 | |
| 74 | struct platform_device msm8064_device_watchdog = { |
| 75 | .name = "msm_watchdog", |
| 76 | .id = -1, |
| 77 | .dev = { |
| 78 | .platform_data = &msm_watchdog_pdata, |
| 79 | }, |
| 80 | }; |
| 81 | |
Joel King | 0581896d | 2011-07-19 16:43:28 -0700 | [diff] [blame] | 82 | static struct resource msm_dmov_resource[] = { |
| 83 | { |
Jeff Ohlstein | 4af7269 | 2011-11-07 15:59:17 -0800 | [diff] [blame] | 84 | .start = ADM_0_SCSS_1_IRQ, |
Joel King | 0581896d | 2011-07-19 16:43:28 -0700 | [diff] [blame] | 85 | .flags = IORESOURCE_IRQ, |
| 86 | }, |
Jeff Ohlstein | 905f1ce | 2011-09-07 18:50:18 -0700 | [diff] [blame] | 87 | { |
Jeff Ohlstein | 4af7269 | 2011-11-07 15:59:17 -0800 | [diff] [blame] | 88 | .start = 0x18320000, |
| 89 | .end = 0x18320000 + SZ_1M - 1, |
Jeff Ohlstein | 905f1ce | 2011-09-07 18:50:18 -0700 | [diff] [blame] | 90 | .flags = IORESOURCE_MEM, |
| 91 | }, |
| 92 | }; |
| 93 | |
| 94 | static struct msm_dmov_pdata msm_dmov_pdata = { |
Jeff Ohlstein | 4af7269 | 2011-11-07 15:59:17 -0800 | [diff] [blame] | 95 | .sd = 1, |
Jeff Ohlstein | 905f1ce | 2011-09-07 18:50:18 -0700 | [diff] [blame] | 96 | .sd_size = 0x800, |
Joel King | 0581896d | 2011-07-19 16:43:28 -0700 | [diff] [blame] | 97 | }; |
| 98 | |
Stepan Moskovchenko | df13d34 | 2011-08-03 19:01:25 -0700 | [diff] [blame] | 99 | struct platform_device apq8064_device_dmov = { |
Joel King | 0581896d | 2011-07-19 16:43:28 -0700 | [diff] [blame] | 100 | .name = "msm_dmov", |
| 101 | .id = -1, |
| 102 | .resource = msm_dmov_resource, |
| 103 | .num_resources = ARRAY_SIZE(msm_dmov_resource), |
Jeff Ohlstein | 905f1ce | 2011-09-07 18:50:18 -0700 | [diff] [blame] | 104 | .dev = { |
| 105 | .platform_data = &msm_dmov_pdata, |
| 106 | }, |
Joel King | 0581896d | 2011-07-19 16:43:28 -0700 | [diff] [blame] | 107 | }; |
| 108 | |
Stepan Moskovchenko | 2701a44 | 2011-08-19 13:47:22 -0700 | [diff] [blame] | 109 | static struct resource resources_uart_gsbi1[] = { |
| 110 | { |
| 111 | .start = APQ8064_GSBI1_UARTDM_IRQ, |
| 112 | .end = APQ8064_GSBI1_UARTDM_IRQ, |
| 113 | .flags = IORESOURCE_IRQ, |
| 114 | }, |
| 115 | { |
| 116 | .start = MSM_UART1DM_PHYS, |
| 117 | .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1, |
| 118 | .name = "uartdm_resource", |
| 119 | .flags = IORESOURCE_MEM, |
| 120 | }, |
| 121 | { |
| 122 | .start = MSM_GSBI1_PHYS, |
| 123 | .end = MSM_GSBI1_PHYS + PAGE_SIZE - 1, |
| 124 | .name = "gsbi_resource", |
| 125 | .flags = IORESOURCE_MEM, |
| 126 | }, |
| 127 | }; |
| 128 | |
| 129 | struct platform_device apq8064_device_uart_gsbi1 = { |
| 130 | .name = "msm_serial_hsl", |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame^] | 131 | .id = 1, |
Stepan Moskovchenko | 2701a44 | 2011-08-19 13:47:22 -0700 | [diff] [blame] | 132 | .num_resources = ARRAY_SIZE(resources_uart_gsbi1), |
| 133 | .resource = resources_uart_gsbi1, |
| 134 | }; |
| 135 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 136 | static struct resource resources_uart_gsbi3[] = { |
| 137 | { |
| 138 | .start = GSBI3_UARTDM_IRQ, |
| 139 | .end = GSBI3_UARTDM_IRQ, |
| 140 | .flags = IORESOURCE_IRQ, |
| 141 | }, |
| 142 | { |
| 143 | .start = MSM_UART3DM_PHYS, |
| 144 | .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1, |
| 145 | .name = "uartdm_resource", |
| 146 | .flags = IORESOURCE_MEM, |
| 147 | }, |
| 148 | { |
| 149 | .start = MSM_GSBI3_PHYS, |
| 150 | .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1, |
| 151 | .name = "gsbi_resource", |
| 152 | .flags = IORESOURCE_MEM, |
| 153 | }, |
| 154 | }; |
| 155 | |
| 156 | struct platform_device apq8064_device_uart_gsbi3 = { |
| 157 | .name = "msm_serial_hsl", |
| 158 | .id = 0, |
| 159 | .num_resources = ARRAY_SIZE(resources_uart_gsbi3), |
| 160 | .resource = resources_uart_gsbi3, |
| 161 | }; |
| 162 | |
Kenneth Heitke | 748593a | 2011-07-15 15:45:11 -0600 | [diff] [blame] | 163 | static struct resource resources_qup_i2c_gsbi4[] = { |
| 164 | { |
| 165 | .name = "gsbi_qup_i2c_addr", |
| 166 | .start = MSM_GSBI4_PHYS, |
Harini Jayaraman | e1554a9 | 2011-09-15 14:43:02 -0600 | [diff] [blame] | 167 | .end = MSM_GSBI4_PHYS + 4 - 1, |
Kenneth Heitke | 748593a | 2011-07-15 15:45:11 -0600 | [diff] [blame] | 168 | .flags = IORESOURCE_MEM, |
| 169 | }, |
| 170 | { |
| 171 | .name = "qup_phys_addr", |
| 172 | .start = MSM_GSBI4_QUP_PHYS, |
Harini Jayaraman | e1554a9 | 2011-09-15 14:43:02 -0600 | [diff] [blame] | 173 | .end = MSM_GSBI4_QUP_PHYS + MSM_QUP_SIZE - 1, |
Kenneth Heitke | 748593a | 2011-07-15 15:45:11 -0600 | [diff] [blame] | 174 | .flags = IORESOURCE_MEM, |
| 175 | }, |
| 176 | { |
| 177 | .name = "qup_err_intr", |
| 178 | .start = GSBI4_QUP_IRQ, |
| 179 | .end = GSBI4_QUP_IRQ, |
| 180 | .flags = IORESOURCE_IRQ, |
| 181 | }, |
| 182 | }; |
| 183 | |
| 184 | struct platform_device apq8064_device_qup_i2c_gsbi4 = { |
| 185 | .name = "qup_i2c", |
| 186 | .id = 4, |
| 187 | .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4), |
| 188 | .resource = resources_qup_i2c_gsbi4, |
| 189 | }; |
| 190 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 191 | static struct resource resources_qup_spi_gsbi5[] = { |
| 192 | { |
| 193 | .name = "spi_base", |
| 194 | .start = MSM_GSBI5_QUP_PHYS, |
| 195 | .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1, |
| 196 | .flags = IORESOURCE_MEM, |
| 197 | }, |
| 198 | { |
| 199 | .name = "gsbi_base", |
| 200 | .start = MSM_GSBI5_PHYS, |
| 201 | .end = MSM_GSBI5_PHYS + 4 - 1, |
| 202 | .flags = IORESOURCE_MEM, |
| 203 | }, |
| 204 | { |
| 205 | .name = "spi_irq_in", |
| 206 | .start = GSBI5_QUP_IRQ, |
| 207 | .end = GSBI5_QUP_IRQ, |
| 208 | .flags = IORESOURCE_IRQ, |
| 209 | }, |
| 210 | }; |
| 211 | |
| 212 | struct platform_device apq8064_device_qup_spi_gsbi5 = { |
| 213 | .name = "spi_qsd", |
| 214 | .id = 0, |
| 215 | .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5), |
| 216 | .resource = resources_qup_spi_gsbi5, |
| 217 | }; |
| 218 | |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame^] | 219 | static struct resource resources_uart_gsbi7[] = { |
| 220 | { |
| 221 | .start = GSBI7_UARTDM_IRQ, |
| 222 | .end = GSBI7_UARTDM_IRQ, |
| 223 | .flags = IORESOURCE_IRQ, |
| 224 | }, |
| 225 | { |
| 226 | .start = MSM_UART7DM_PHYS, |
| 227 | .end = MSM_UART7DM_PHYS + PAGE_SIZE - 1, |
| 228 | .name = "uartdm_resource", |
| 229 | .flags = IORESOURCE_MEM, |
| 230 | }, |
| 231 | { |
| 232 | .start = MSM_GSBI7_PHYS, |
| 233 | .end = MSM_GSBI7_PHYS + PAGE_SIZE - 1, |
| 234 | .name = "gsbi_resource", |
| 235 | .flags = IORESOURCE_MEM, |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | struct platform_device apq8064_device_uart_gsbi7 = { |
| 240 | .name = "msm_serial_hsl", |
| 241 | .id = 0, |
| 242 | .num_resources = ARRAY_SIZE(resources_uart_gsbi7), |
| 243 | .resource = resources_uart_gsbi7, |
| 244 | }; |
| 245 | |
Bharath Ramachandramurthy | b8e797f | 2011-11-30 12:08:42 -0800 | [diff] [blame] | 246 | struct platform_device apq_pcm = { |
| 247 | .name = "msm-pcm-dsp", |
| 248 | .id = -1, |
| 249 | }; |
| 250 | |
| 251 | struct platform_device apq_pcm_routing = { |
| 252 | .name = "msm-pcm-routing", |
| 253 | .id = -1, |
| 254 | }; |
| 255 | |
| 256 | struct platform_device apq_cpudai0 = { |
| 257 | .name = "msm-dai-q6", |
| 258 | .id = 0x4000, |
| 259 | }; |
| 260 | |
| 261 | struct platform_device apq_cpudai1 = { |
| 262 | .name = "msm-dai-q6", |
| 263 | .id = 0x4001, |
| 264 | }; |
| 265 | |
| 266 | struct platform_device apq_cpudai_hdmi_rx = { |
| 267 | .name = "msm-dai-q6", |
| 268 | .id = 8, |
| 269 | }; |
| 270 | |
| 271 | struct platform_device apq_cpudai_bt_rx = { |
| 272 | .name = "msm-dai-q6", |
| 273 | .id = 0x3000, |
| 274 | }; |
| 275 | |
| 276 | struct platform_device apq_cpudai_bt_tx = { |
| 277 | .name = "msm-dai-q6", |
| 278 | .id = 0x3001, |
| 279 | }; |
| 280 | |
| 281 | struct platform_device apq_cpudai_fm_rx = { |
| 282 | .name = "msm-dai-q6", |
| 283 | .id = 0x3004, |
| 284 | }; |
| 285 | |
| 286 | struct platform_device apq_cpudai_fm_tx = { |
| 287 | .name = "msm-dai-q6", |
| 288 | .id = 0x3005, |
| 289 | }; |
| 290 | |
| 291 | /* |
| 292 | * Machine specific data for AUX PCM Interface |
| 293 | * which the driver will be unware of. |
| 294 | */ |
| 295 | struct msm_dai_auxpcm_pdata apq_auxpcm_rx_pdata = { |
| 296 | .clk = "pcm_clk", |
| 297 | .mode = AFE_PCM_CFG_MODE_PCM, |
| 298 | .sync = AFE_PCM_CFG_SYNC_INT, |
| 299 | .frame = AFE_PCM_CFG_FRM_256BPF, |
| 300 | .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD, |
| 301 | .slot = 0, |
| 302 | .data = AFE_PCM_CFG_CDATAOE_MASTER, |
| 303 | .pcm_clk_rate = 2048000, |
| 304 | }; |
| 305 | |
| 306 | struct platform_device apq_cpudai_auxpcm_rx = { |
| 307 | .name = "msm-dai-q6", |
| 308 | .id = 2, |
| 309 | .dev = { |
| 310 | .platform_data = &apq_auxpcm_rx_pdata, |
| 311 | }, |
| 312 | }; |
| 313 | |
| 314 | struct platform_device apq_cpudai_auxpcm_tx = { |
| 315 | .name = "msm-dai-q6", |
| 316 | .id = 3, |
| 317 | }; |
| 318 | |
| 319 | struct platform_device apq_cpu_fe = { |
| 320 | .name = "msm-dai-fe", |
| 321 | .id = -1, |
| 322 | }; |
| 323 | |
| 324 | struct platform_device apq_stub_codec = { |
| 325 | .name = "msm-stub-codec", |
| 326 | .id = 1, |
| 327 | }; |
| 328 | |
| 329 | struct platform_device apq_voice = { |
| 330 | .name = "msm-pcm-voice", |
| 331 | .id = -1, |
| 332 | }; |
| 333 | |
| 334 | struct platform_device apq_voip = { |
| 335 | .name = "msm-voip-dsp", |
| 336 | .id = -1, |
| 337 | }; |
| 338 | |
| 339 | struct platform_device apq_lpa_pcm = { |
| 340 | .name = "msm-pcm-lpa", |
| 341 | .id = -1, |
| 342 | }; |
| 343 | |
| 344 | struct platform_device apq_pcm_hostless = { |
| 345 | .name = "msm-pcm-hostless", |
| 346 | .id = -1, |
| 347 | }; |
| 348 | |
| 349 | struct platform_device apq_cpudai_afe_01_rx = { |
| 350 | .name = "msm-dai-q6", |
| 351 | .id = 0xE0, |
| 352 | }; |
| 353 | |
| 354 | struct platform_device apq_cpudai_afe_01_tx = { |
| 355 | .name = "msm-dai-q6", |
| 356 | .id = 0xF0, |
| 357 | }; |
| 358 | |
| 359 | struct platform_device apq_cpudai_afe_02_rx = { |
| 360 | .name = "msm-dai-q6", |
| 361 | .id = 0xF1, |
| 362 | }; |
| 363 | |
| 364 | struct platform_device apq_cpudai_afe_02_tx = { |
| 365 | .name = "msm-dai-q6", |
| 366 | .id = 0xE1, |
| 367 | }; |
| 368 | |
| 369 | struct platform_device apq_pcm_afe = { |
| 370 | .name = "msm-pcm-afe", |
| 371 | .id = -1, |
| 372 | }; |
| 373 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 374 | static struct resource resources_ssbi_pmic1[] = { |
| 375 | { |
| 376 | .start = MSM_PMIC1_SSBI_CMD_PHYS, |
| 377 | .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1, |
| 378 | .flags = IORESOURCE_MEM, |
| 379 | }, |
| 380 | }; |
| 381 | |
Sagar Dharia | 8bdcdaf | 2011-09-16 16:01:15 -0600 | [diff] [blame] | 382 | #define LPASS_SLIMBUS_PHYS 0x28080000 |
| 383 | #define LPASS_SLIMBUS_BAM_PHYS 0x28084000 |
| 384 | /* Board info for the slimbus slave device */ |
| 385 | static struct resource slimbus_res[] = { |
| 386 | { |
| 387 | .start = LPASS_SLIMBUS_PHYS, |
| 388 | .end = LPASS_SLIMBUS_PHYS + 8191, |
| 389 | .flags = IORESOURCE_MEM, |
| 390 | .name = "slimbus_physical", |
| 391 | }, |
| 392 | { |
| 393 | .start = LPASS_SLIMBUS_BAM_PHYS, |
| 394 | .end = LPASS_SLIMBUS_BAM_PHYS + 8191, |
| 395 | .flags = IORESOURCE_MEM, |
| 396 | .name = "slimbus_bam_physical", |
| 397 | }, |
| 398 | { |
| 399 | .start = SLIMBUS0_CORE_EE1_IRQ, |
| 400 | .end = SLIMBUS0_CORE_EE1_IRQ, |
| 401 | .flags = IORESOURCE_IRQ, |
| 402 | .name = "slimbus_irq", |
| 403 | }, |
| 404 | { |
| 405 | .start = SLIMBUS0_BAM_EE1_IRQ, |
| 406 | .end = SLIMBUS0_BAM_EE1_IRQ, |
| 407 | .flags = IORESOURCE_IRQ, |
| 408 | .name = "slimbus_bam_irq", |
| 409 | }, |
| 410 | }; |
| 411 | |
| 412 | struct platform_device apq8064_slim_ctrl = { |
| 413 | .name = "msm_slim_ctrl", |
| 414 | .id = 1, |
| 415 | .num_resources = ARRAY_SIZE(slimbus_res), |
| 416 | .resource = slimbus_res, |
| 417 | .dev = { |
| 418 | .coherent_dma_mask = 0xffffffffULL, |
| 419 | }, |
| 420 | }; |
| 421 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 422 | struct platform_device apq8064_device_ssbi_pmic1 = { |
| 423 | .name = "msm_ssbi", |
| 424 | .id = 0, |
| 425 | .resource = resources_ssbi_pmic1, |
| 426 | .num_resources = ARRAY_SIZE(resources_ssbi_pmic1), |
| 427 | }; |
| 428 | |
| 429 | static struct resource resources_ssbi_pmic2[] = { |
| 430 | { |
| 431 | .start = MSM_PMIC2_SSBI_CMD_PHYS, |
| 432 | .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1, |
| 433 | .flags = IORESOURCE_MEM, |
| 434 | }, |
| 435 | }; |
| 436 | |
| 437 | struct platform_device apq8064_device_ssbi_pmic2 = { |
| 438 | .name = "msm_ssbi", |
| 439 | .id = 1, |
| 440 | .resource = resources_ssbi_pmic2, |
| 441 | .num_resources = ARRAY_SIZE(resources_ssbi_pmic2), |
| 442 | }; |
| 443 | |
| 444 | static struct resource resources_otg[] = { |
| 445 | { |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 446 | .start = MSM_HSUSB1_PHYS, |
| 447 | .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 448 | .flags = IORESOURCE_MEM, |
| 449 | }, |
| 450 | { |
| 451 | .start = USB1_HS_IRQ, |
| 452 | .end = USB1_HS_IRQ, |
| 453 | .flags = IORESOURCE_IRQ, |
| 454 | }, |
| 455 | }; |
| 456 | |
Stepan Moskovchenko | 14aa649 | 2011-08-08 15:15:01 -0700 | [diff] [blame] | 457 | struct platform_device apq8064_device_otg = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 458 | .name = "msm_otg", |
| 459 | .id = -1, |
| 460 | .num_resources = ARRAY_SIZE(resources_otg), |
| 461 | .resource = resources_otg, |
| 462 | .dev = { |
| 463 | .coherent_dma_mask = 0xffffffff, |
| 464 | }, |
| 465 | }; |
| 466 | |
| 467 | static struct resource resources_hsusb[] = { |
| 468 | { |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 469 | .start = MSM_HSUSB1_PHYS, |
| 470 | .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 471 | .flags = IORESOURCE_MEM, |
| 472 | }, |
| 473 | { |
| 474 | .start = USB1_HS_IRQ, |
| 475 | .end = USB1_HS_IRQ, |
| 476 | .flags = IORESOURCE_IRQ, |
| 477 | }, |
| 478 | }; |
| 479 | |
Stepan Moskovchenko | 14aa649 | 2011-08-08 15:15:01 -0700 | [diff] [blame] | 480 | struct platform_device apq8064_device_gadget_peripheral = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 481 | .name = "msm_hsusb", |
| 482 | .id = -1, |
| 483 | .num_resources = ARRAY_SIZE(resources_hsusb), |
| 484 | .resource = resources_hsusb, |
| 485 | .dev = { |
| 486 | .coherent_dma_mask = 0xffffffff, |
| 487 | }, |
| 488 | }; |
| 489 | |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 490 | static struct resource resources_hsusb_host[] = { |
| 491 | { |
| 492 | .start = MSM_HSUSB1_PHYS, |
| 493 | .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1, |
| 494 | .flags = IORESOURCE_MEM, |
| 495 | }, |
| 496 | { |
| 497 | .start = USB1_HS_IRQ, |
| 498 | .end = USB1_HS_IRQ, |
| 499 | .flags = IORESOURCE_IRQ, |
| 500 | }, |
| 501 | }; |
| 502 | |
Hemant Kumar | a945b47 | 2012-01-25 15:08:06 -0800 | [diff] [blame] | 503 | static struct resource resources_hsic_host[] = { |
| 504 | { |
| 505 | .start = 0x12510000, |
| 506 | .end = 0x12510000 + SZ_4K - 1, |
| 507 | .flags = IORESOURCE_MEM, |
| 508 | }, |
| 509 | { |
| 510 | .start = USB2_HSIC_IRQ, |
| 511 | .end = USB2_HSIC_IRQ, |
| 512 | .flags = IORESOURCE_IRQ, |
| 513 | }, |
| 514 | { |
| 515 | .start = MSM_GPIO_TO_INT(49), |
| 516 | .end = MSM_GPIO_TO_INT(49), |
| 517 | .name = "peripheral_status_irq", |
| 518 | .flags = IORESOURCE_IRQ, |
| 519 | }, |
| 520 | }; |
| 521 | |
Hemant Kumar | d86c488 | 2012-01-24 19:39:37 -0800 | [diff] [blame] | 522 | static u64 dma_mask = DMA_BIT_MASK(32); |
| 523 | struct platform_device apq8064_device_hsusb_host = { |
| 524 | .name = "msm_hsusb_host", |
| 525 | .id = -1, |
| 526 | .num_resources = ARRAY_SIZE(resources_hsusb_host), |
| 527 | .resource = resources_hsusb_host, |
| 528 | .dev = { |
| 529 | .dma_mask = &dma_mask, |
| 530 | .coherent_dma_mask = 0xffffffff, |
| 531 | }, |
| 532 | }; |
| 533 | |
Hemant Kumar | a945b47 | 2012-01-25 15:08:06 -0800 | [diff] [blame] | 534 | struct platform_device apq8064_device_hsic_host = { |
| 535 | .name = "msm_hsic_host", |
| 536 | .id = -1, |
| 537 | .num_resources = ARRAY_SIZE(resources_hsic_host), |
| 538 | .resource = resources_hsic_host, |
| 539 | .dev = { |
| 540 | .dma_mask = &dma_mask, |
| 541 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 542 | }, |
| 543 | }; |
| 544 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 545 | #define MSM_SDC1_BASE 0x12400000 |
| 546 | #define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800) |
| 547 | #define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000) |
| 548 | #define MSM_SDC2_BASE 0x12140000 |
| 549 | #define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800) |
| 550 | #define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000) |
| 551 | #define MSM_SDC3_BASE 0x12180000 |
| 552 | #define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800) |
| 553 | #define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000) |
| 554 | #define MSM_SDC4_BASE 0x121C0000 |
| 555 | #define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800) |
| 556 | #define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000) |
| 557 | |
| 558 | static struct resource resources_sdc1[] = { |
| 559 | { |
| 560 | .name = "core_mem", |
| 561 | .flags = IORESOURCE_MEM, |
| 562 | .start = MSM_SDC1_BASE, |
| 563 | .end = MSM_SDC1_DML_BASE - 1, |
| 564 | }, |
| 565 | { |
| 566 | .name = "core_irq", |
| 567 | .flags = IORESOURCE_IRQ, |
| 568 | .start = SDC1_IRQ_0, |
| 569 | .end = SDC1_IRQ_0 |
| 570 | }, |
| 571 | #ifdef CONFIG_MMC_MSM_SPS_SUPPORT |
| 572 | { |
| 573 | .name = "sdcc_dml_addr", |
| 574 | .start = MSM_SDC1_DML_BASE, |
| 575 | .end = MSM_SDC1_BAM_BASE - 1, |
| 576 | .flags = IORESOURCE_MEM, |
| 577 | }, |
| 578 | { |
| 579 | .name = "sdcc_bam_addr", |
| 580 | .start = MSM_SDC1_BAM_BASE, |
| 581 | .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1, |
| 582 | .flags = IORESOURCE_MEM, |
| 583 | }, |
| 584 | { |
| 585 | .name = "sdcc_bam_irq", |
| 586 | .start = SDC1_BAM_IRQ, |
| 587 | .end = SDC1_BAM_IRQ, |
| 588 | .flags = IORESOURCE_IRQ, |
| 589 | }, |
| 590 | #endif |
| 591 | }; |
| 592 | |
| 593 | static struct resource resources_sdc2[] = { |
| 594 | { |
| 595 | .name = "core_mem", |
| 596 | .flags = IORESOURCE_MEM, |
| 597 | .start = MSM_SDC2_BASE, |
| 598 | .end = MSM_SDC2_DML_BASE - 1, |
| 599 | }, |
| 600 | { |
| 601 | .name = "core_irq", |
| 602 | .flags = IORESOURCE_IRQ, |
| 603 | .start = SDC2_IRQ_0, |
| 604 | .end = SDC2_IRQ_0 |
| 605 | }, |
| 606 | #ifdef CONFIG_MMC_MSM_SPS_SUPPORT |
| 607 | { |
| 608 | .name = "sdcc_dml_addr", |
| 609 | .start = MSM_SDC2_DML_BASE, |
| 610 | .end = MSM_SDC2_BAM_BASE - 1, |
| 611 | .flags = IORESOURCE_MEM, |
| 612 | }, |
| 613 | { |
| 614 | .name = "sdcc_bam_addr", |
| 615 | .start = MSM_SDC2_BAM_BASE, |
| 616 | .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1, |
| 617 | .flags = IORESOURCE_MEM, |
| 618 | }, |
| 619 | { |
| 620 | .name = "sdcc_bam_irq", |
| 621 | .start = SDC2_BAM_IRQ, |
| 622 | .end = SDC2_BAM_IRQ, |
| 623 | .flags = IORESOURCE_IRQ, |
| 624 | }, |
| 625 | #endif |
| 626 | }; |
| 627 | |
| 628 | static struct resource resources_sdc3[] = { |
| 629 | { |
| 630 | .name = "core_mem", |
| 631 | .flags = IORESOURCE_MEM, |
| 632 | .start = MSM_SDC3_BASE, |
| 633 | .end = MSM_SDC3_DML_BASE - 1, |
| 634 | }, |
| 635 | { |
| 636 | .name = "core_irq", |
| 637 | .flags = IORESOURCE_IRQ, |
| 638 | .start = SDC3_IRQ_0, |
| 639 | .end = SDC3_IRQ_0 |
| 640 | }, |
| 641 | #ifdef CONFIG_MMC_MSM_SPS_SUPPORT |
| 642 | { |
| 643 | .name = "sdcc_dml_addr", |
| 644 | .start = MSM_SDC3_DML_BASE, |
| 645 | .end = MSM_SDC3_BAM_BASE - 1, |
| 646 | .flags = IORESOURCE_MEM, |
| 647 | }, |
| 648 | { |
| 649 | .name = "sdcc_bam_addr", |
| 650 | .start = MSM_SDC3_BAM_BASE, |
| 651 | .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1, |
| 652 | .flags = IORESOURCE_MEM, |
| 653 | }, |
| 654 | { |
| 655 | .name = "sdcc_bam_irq", |
| 656 | .start = SDC3_BAM_IRQ, |
| 657 | .end = SDC3_BAM_IRQ, |
| 658 | .flags = IORESOURCE_IRQ, |
| 659 | }, |
| 660 | #endif |
| 661 | }; |
| 662 | |
| 663 | static struct resource resources_sdc4[] = { |
| 664 | { |
| 665 | .name = "core_mem", |
| 666 | .flags = IORESOURCE_MEM, |
| 667 | .start = MSM_SDC4_BASE, |
| 668 | .end = MSM_SDC4_DML_BASE - 1, |
| 669 | }, |
| 670 | { |
| 671 | .name = "core_irq", |
| 672 | .flags = IORESOURCE_IRQ, |
| 673 | .start = SDC4_IRQ_0, |
| 674 | .end = SDC4_IRQ_0 |
| 675 | }, |
| 676 | #ifdef CONFIG_MMC_MSM_SPS_SUPPORT |
| 677 | { |
| 678 | .name = "sdcc_dml_addr", |
| 679 | .start = MSM_SDC4_DML_BASE, |
| 680 | .end = MSM_SDC4_BAM_BASE - 1, |
| 681 | .flags = IORESOURCE_MEM, |
| 682 | }, |
| 683 | { |
| 684 | .name = "sdcc_bam_addr", |
| 685 | .start = MSM_SDC4_BAM_BASE, |
| 686 | .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1, |
| 687 | .flags = IORESOURCE_MEM, |
| 688 | }, |
| 689 | { |
| 690 | .name = "sdcc_bam_irq", |
| 691 | .start = SDC4_BAM_IRQ, |
| 692 | .end = SDC4_BAM_IRQ, |
| 693 | .flags = IORESOURCE_IRQ, |
| 694 | }, |
| 695 | #endif |
| 696 | }; |
| 697 | |
| 698 | struct platform_device apq8064_device_sdc1 = { |
| 699 | .name = "msm_sdcc", |
| 700 | .id = 1, |
| 701 | .num_resources = ARRAY_SIZE(resources_sdc1), |
| 702 | .resource = resources_sdc1, |
| 703 | .dev = { |
| 704 | .coherent_dma_mask = 0xffffffff, |
| 705 | }, |
| 706 | }; |
| 707 | |
| 708 | struct platform_device apq8064_device_sdc2 = { |
| 709 | .name = "msm_sdcc", |
| 710 | .id = 2, |
| 711 | .num_resources = ARRAY_SIZE(resources_sdc2), |
| 712 | .resource = resources_sdc2, |
| 713 | .dev = { |
| 714 | .coherent_dma_mask = 0xffffffff, |
| 715 | }, |
| 716 | }; |
| 717 | |
| 718 | struct platform_device apq8064_device_sdc3 = { |
| 719 | .name = "msm_sdcc", |
| 720 | .id = 3, |
| 721 | .num_resources = ARRAY_SIZE(resources_sdc3), |
| 722 | .resource = resources_sdc3, |
| 723 | .dev = { |
| 724 | .coherent_dma_mask = 0xffffffff, |
| 725 | }, |
| 726 | }; |
| 727 | |
| 728 | struct platform_device apq8064_device_sdc4 = { |
| 729 | .name = "msm_sdcc", |
| 730 | .id = 4, |
| 731 | .num_resources = ARRAY_SIZE(resources_sdc4), |
| 732 | .resource = resources_sdc4, |
| 733 | .dev = { |
| 734 | .coherent_dma_mask = 0xffffffff, |
| 735 | }, |
| 736 | }; |
| 737 | |
| 738 | static struct platform_device *apq8064_sdcc_devices[] __initdata = { |
| 739 | &apq8064_device_sdc1, |
| 740 | &apq8064_device_sdc2, |
| 741 | &apq8064_device_sdc3, |
| 742 | &apq8064_device_sdc4, |
| 743 | }; |
| 744 | |
| 745 | int __init apq8064_add_sdcc(unsigned int controller, |
| 746 | struct mmc_platform_data *plat) |
| 747 | { |
| 748 | struct platform_device *pdev; |
| 749 | |
| 750 | if (!plat) |
| 751 | return 0; |
| 752 | if (controller < 1 || controller > 4) |
| 753 | return -EINVAL; |
| 754 | |
| 755 | pdev = apq8064_sdcc_devices[controller-1]; |
| 756 | pdev->dev.platform_data = plat; |
| 757 | return platform_device_register(pdev); |
| 758 | } |
| 759 | |
Yan He | 06913ce | 2011-08-26 16:33:46 -0700 | [diff] [blame] | 760 | static struct resource resources_sps[] = { |
| 761 | { |
| 762 | .name = "pipe_mem", |
| 763 | .start = 0x12800000, |
| 764 | .end = 0x12800000 + 0x4000 - 1, |
| 765 | .flags = IORESOURCE_MEM, |
| 766 | }, |
| 767 | { |
| 768 | .name = "bamdma_dma", |
| 769 | .start = 0x12240000, |
| 770 | .end = 0x12240000 + 0x1000 - 1, |
| 771 | .flags = IORESOURCE_MEM, |
| 772 | }, |
| 773 | { |
| 774 | .name = "bamdma_bam", |
| 775 | .start = 0x12244000, |
| 776 | .end = 0x12244000 + 0x4000 - 1, |
| 777 | .flags = IORESOURCE_MEM, |
| 778 | }, |
| 779 | { |
| 780 | .name = "bamdma_irq", |
| 781 | .start = SPS_BAM_DMA_IRQ, |
| 782 | .end = SPS_BAM_DMA_IRQ, |
| 783 | .flags = IORESOURCE_IRQ, |
| 784 | }, |
| 785 | }; |
| 786 | |
Gagan Mac | 8a7a5d3 | 2011-11-11 16:43:06 -0700 | [diff] [blame] | 787 | struct platform_device msm_bus_8064_sys_fabric = { |
| 788 | .name = "msm_bus_fabric", |
| 789 | .id = MSM_BUS_FAB_SYSTEM, |
| 790 | }; |
| 791 | struct platform_device msm_bus_8064_apps_fabric = { |
| 792 | .name = "msm_bus_fabric", |
| 793 | .id = MSM_BUS_FAB_APPSS, |
| 794 | }; |
| 795 | struct platform_device msm_bus_8064_mm_fabric = { |
| 796 | .name = "msm_bus_fabric", |
| 797 | .id = MSM_BUS_FAB_MMSS, |
| 798 | }; |
| 799 | struct platform_device msm_bus_8064_sys_fpb = { |
| 800 | .name = "msm_bus_fabric", |
| 801 | .id = MSM_BUS_FAB_SYSTEM_FPB, |
| 802 | }; |
| 803 | struct platform_device msm_bus_8064_cpss_fpb = { |
| 804 | .name = "msm_bus_fabric", |
| 805 | .id = MSM_BUS_FAB_CPSS_FPB, |
| 806 | }; |
| 807 | |
Yan He | 06913ce | 2011-08-26 16:33:46 -0700 | [diff] [blame] | 808 | static struct msm_sps_platform_data msm_sps_pdata = { |
| 809 | .bamdma_restricted_pipes = 0x06, |
| 810 | }; |
| 811 | |
| 812 | struct platform_device msm_device_sps_apq8064 = { |
| 813 | .name = "msm_sps", |
| 814 | .id = -1, |
| 815 | .num_resources = ARRAY_SIZE(resources_sps), |
| 816 | .resource = resources_sps, |
| 817 | .dev.platform_data = &msm_sps_pdata, |
| 818 | }; |
| 819 | |
Jeff Hugo | 0c0f5e9 | 2011-09-28 13:55:45 -0600 | [diff] [blame] | 820 | struct platform_device msm_device_smd_apq8064 = { |
| 821 | .name = "msm_smd", |
| 822 | .id = -1, |
| 823 | }; |
| 824 | |
Ramesh Masavarapu | f46be1b | 2011-11-03 11:13:41 -0700 | [diff] [blame] | 825 | #ifdef CONFIG_HW_RANDOM_MSM |
| 826 | /* PRNG device */ |
| 827 | #define MSM_PRNG_PHYS 0x1A500000 |
| 828 | static struct resource rng_resources = { |
| 829 | .flags = IORESOURCE_MEM, |
| 830 | .start = MSM_PRNG_PHYS, |
| 831 | .end = MSM_PRNG_PHYS + SZ_512 - 1, |
| 832 | }; |
| 833 | |
| 834 | struct platform_device apq8064_device_rng = { |
| 835 | .name = "msm_rng", |
| 836 | .id = 0, |
| 837 | .num_resources = 1, |
| 838 | .resource = &rng_resources, |
| 839 | }; |
| 840 | #endif |
| 841 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 842 | static struct resource msm_gss_resources[] = { |
| 843 | { |
| 844 | .start = 0x10000000, |
| 845 | .end = 0x10000000 + SZ_256 - 1, |
| 846 | .flags = IORESOURCE_MEM, |
| 847 | }, |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 848 | { |
| 849 | .start = 0x10008000, |
| 850 | .end = 0x10008000 + SZ_256 - 1, |
| 851 | .flags = IORESOURCE_MEM, |
| 852 | }, |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 853 | }; |
| 854 | |
| 855 | struct platform_device msm_gss = { |
| 856 | .name = "pil_gss", |
| 857 | .id = -1, |
| 858 | .num_resources = ARRAY_SIZE(msm_gss_resources), |
| 859 | .resource = msm_gss_resources, |
| 860 | }; |
| 861 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 862 | static struct clk_lookup msm_clocks_8064_dummy[] = { |
| 863 | CLK_DUMMY("pll2", PLL2, NULL, 0), |
| 864 | CLK_DUMMY("pll8", PLL8, NULL, 0), |
| 865 | CLK_DUMMY("pll4", PLL4, NULL, 0), |
| 866 | |
| 867 | CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0), |
| 868 | CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0), |
| 869 | CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0), |
| 870 | CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0), |
| 871 | CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0), |
| 872 | CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0), |
| 873 | CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0), |
| 874 | CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0), |
| 875 | CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0), |
| 876 | CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0), |
| 877 | CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0), |
| 878 | CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0), |
| 879 | CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0), |
| 880 | CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0), |
| 881 | CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0), |
| 882 | CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0), |
| 883 | |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 884 | CLK_DUMMY("core_clk", GSBI1_UART_CLK, NULL, OFF), |
| 885 | CLK_DUMMY("core_clk", GSBI2_UART_CLK, NULL, OFF), |
| 886 | CLK_DUMMY("core_clk", GSBI3_UART_CLK, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 887 | "msm_serial_hsl.0", OFF), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 888 | CLK_DUMMY("core_clk", GSBI4_UART_CLK, NULL, OFF), |
| 889 | CLK_DUMMY("core_clk", GSBI5_UART_CLK, NULL, OFF), |
| 890 | CLK_DUMMY("core_clk", GSBI6_UART_CLK, NULL, OFF), |
| 891 | CLK_DUMMY("core_clk", GSBI7_UART_CLK, NULL, OFF), |
| 892 | CLK_DUMMY("core_clk", GSBI8_UART_CLK, NULL, OFF), |
| 893 | CLK_DUMMY("core_clk", GSBI9_UART_CLK, NULL, OFF), |
| 894 | CLK_DUMMY("core_clk", GSBI10_UART_CLK, NULL, OFF), |
| 895 | CLK_DUMMY("core_clk", GSBI11_UART_CLK, NULL, OFF), |
| 896 | CLK_DUMMY("core_clk", GSBI12_UART_CLK, NULL, OFF), |
Matt Wagantall | 62cf63e | 2011-08-17 16:34:47 -0700 | [diff] [blame] | 897 | CLK_DUMMY("core_clk", GSBI1_QUP_CLK, NULL, OFF), |
| 898 | CLK_DUMMY("core_clk", GSBI2_QUP_CLK, NULL, OFF), |
| 899 | CLK_DUMMY("core_clk", GSBI3_QUP_CLK, NULL, OFF), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 900 | CLK_DUMMY("core_clk", GSBI4_QUP_CLK, "qup_i2c.4", OFF), |
| 901 | CLK_DUMMY("core_clk", GSBI5_QUP_CLK, "spi_qsd.0", OFF), |
Matt Wagantall | 62cf63e | 2011-08-17 16:34:47 -0700 | [diff] [blame] | 902 | CLK_DUMMY("core_clk", GSBI6_QUP_CLK, NULL, OFF), |
| 903 | CLK_DUMMY("core_clk", GSBI7_QUP_CLK, NULL, OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 904 | CLK_DUMMY("core_clk", PDM_CLK, NULL, OFF), |
Matt Wagantall | d86d683 | 2011-08-17 14:06:55 -0700 | [diff] [blame] | 905 | CLK_DUMMY("mem_clk", PMEM_CLK, NULL, OFF), |
Ramesh Masavarapu | f46be1b | 2011-11-03 11:13:41 -0700 | [diff] [blame] | 906 | CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 907 | CLK_DUMMY("core_clk", SDC1_CLK, NULL, OFF), |
| 908 | CLK_DUMMY("core_clk", SDC2_CLK, NULL, OFF), |
| 909 | CLK_DUMMY("core_clk", SDC3_CLK, NULL, OFF), |
| 910 | CLK_DUMMY("core_clk", SDC4_CLK, NULL, OFF), |
Matt Wagantall | 640e5fd | 2011-08-17 16:08:53 -0700 | [diff] [blame] | 911 | CLK_DUMMY("ref_clk", TSIF_REF_CLK, NULL, OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 912 | CLK_DUMMY("core_clk", TSSC_CLK, NULL, OFF), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 913 | CLK_DUMMY("alt_core_clk", USB_HS1_XCVR_CLK, NULL, OFF), |
| 914 | CLK_DUMMY("alt_core_clk", USB_HS3_XCVR_CLK, NULL, OFF), |
| 915 | CLK_DUMMY("alt_core_clk", USB_HS4_XCVR_CLK, NULL, OFF), |
| 916 | CLK_DUMMY("phy_clk", USB_PHY0_CLK, NULL, OFF), |
| 917 | CLK_DUMMY("src_clk", USB_FS1_SRC_CLK, NULL, OFF), |
| 918 | CLK_DUMMY("alt_core_clk", USB_FS1_XCVR_CLK, NULL, OFF), |
| 919 | CLK_DUMMY("sys_clk", USB_FS1_SYS_CLK, NULL, OFF), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 920 | CLK_DUMMY("core_clk", CE2_CLK, NULL, OFF), |
| 921 | CLK_DUMMY("core_clk", CE1_CORE_CLK, NULL, OFF), |
| 922 | CLK_DUMMY("core_clk", CE3_CORE_CLK, NULL, OFF), |
| 923 | CLK_DUMMY("iface_clk", CE3_P_CLK, NULL, OFF), |
Tianyi Gou | 86bb472 | 2011-08-09 13:28:02 -0700 | [diff] [blame] | 924 | CLK_DUMMY("pcie_pclk", PCIE_P_CLK, NULL, OFF), |
| 925 | CLK_DUMMY("pcie_alt_ref_clk", PCIE_ALT_REF_CLK, NULL, OFF), |
| 926 | CLK_DUMMY("sata_rxoob_clk", SATA_RXOOB_CLK, NULL, OFF), |
| 927 | CLK_DUMMY("sata_pmalive_clk", SATA_PMALIVE_CLK, NULL, OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 928 | CLK_DUMMY("ref_clk", SATA_PHY_REF_CLK, NULL, OFF), |
Matt Wagantall | 62cf63e | 2011-08-17 16:34:47 -0700 | [diff] [blame] | 929 | CLK_DUMMY("iface_clk", GSBI1_P_CLK, NULL, OFF), |
| 930 | CLK_DUMMY("iface_clk", GSBI2_P_CLK, NULL, OFF), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 931 | CLK_DUMMY("iface_clk", GSBI3_P_CLK, "msm_serial_hsl.0", OFF), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 932 | CLK_DUMMY("iface_clk", GSBI4_P_CLK, "qup_i2c.4", OFF), |
| 933 | CLK_DUMMY("iface_clk", GSBI5_P_CLK, "spi_qsd.0", OFF), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 934 | CLK_DUMMY("iface_clk", GSBI6_P_CLK, NULL, OFF), |
Matt Wagantall | 62cf63e | 2011-08-17 16:34:47 -0700 | [diff] [blame] | 935 | CLK_DUMMY("iface_clk", GSBI7_P_CLK, NULL, OFF), |
Matt Wagantall | 640e5fd | 2011-08-17 16:08:53 -0700 | [diff] [blame] | 936 | CLK_DUMMY("iface_clk", TSIF_P_CLK, NULL, OFF), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 937 | CLK_DUMMY("iface_clk", USB_FS1_P_CLK, NULL, OFF), |
| 938 | CLK_DUMMY("iface_clk", USB_HS1_P_CLK, NULL, OFF), |
| 939 | CLK_DUMMY("iface_clk", USB_HS3_P_CLK, NULL, OFF), |
| 940 | CLK_DUMMY("iface_clk", USB_HS4_P_CLK, NULL, OFF), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 941 | CLK_DUMMY("iface_clk", SDC1_P_CLK, NULL, OFF), |
| 942 | CLK_DUMMY("iface_clk", SDC2_P_CLK, NULL, OFF), |
| 943 | CLK_DUMMY("iface_clk", SDC3_P_CLK, NULL, OFF), |
| 944 | CLK_DUMMY("iface_clk", SDC4_P_CLK, NULL, OFF), |
Jin Hong | 01f2dbb | 2011-11-03 22:13:51 -0700 | [diff] [blame] | 945 | CLK_DUMMY("core_clk", ADM0_CLK, "msm_dmov", OFF), |
| 946 | CLK_DUMMY("iface_clk", ADM0_P_CLK, "msm_dmov", OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 947 | CLK_DUMMY("iface_clk", PMIC_ARB0_P_CLK, NULL, OFF), |
| 948 | CLK_DUMMY("iface_clk", PMIC_ARB1_P_CLK, NULL, OFF), |
| 949 | CLK_DUMMY("core_clk", PMIC_SSBI2_CLK, NULL, OFF), |
| 950 | CLK_DUMMY("mem_clk", RPM_MSG_RAM_P_CLK, NULL, OFF), |
| 951 | CLK_DUMMY("core_clk", AMP_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 952 | CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF), |
| 953 | CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF), |
| 954 | CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF), |
| 955 | CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF), |
| 956 | CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF), |
| 957 | CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF), |
| 958 | CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF), |
| 959 | CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF), |
| 960 | CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF), |
| 961 | CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF), |
| 962 | CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF), |
| 963 | CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, NULL, OFF), |
| 964 | CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, NULL, OFF), |
| 965 | CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, NULL, OFF), |
| 966 | CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, NULL, OFF), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 967 | CLK_DUMMY("core_clk", VCAP_CLK, NULL, OFF), |
| 968 | CLK_DUMMY("npl_clk", VCAP_NPL_CLK, NULL, OFF), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 969 | CLK_DUMMY("core_clk", GFX3D_CLK, "kgsl-3d0.0", OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 970 | CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 971 | CLK_DUMMY("mem_clk", IMEM_CLK, NULL, OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 972 | CLK_DUMMY("core_clk", JPEGD_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 973 | CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF), |
| 974 | CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF), |
| 975 | CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 976 | CLK_DUMMY("core_clk", ROT_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 977 | CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF), |
Matt Wagantall | b86ad26 | 2011-10-24 19:50:29 -0700 | [diff] [blame] | 978 | CLK_DUMMY("core_clk", VCODEC_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 979 | CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF), |
Tianyi Gou | 86bb472 | 2011-08-09 13:28:02 -0700 | [diff] [blame] | 980 | CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF), |
| 981 | CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 982 | CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 983 | CLK_DUMMY("core_clk", HDMI_APP_CLK, "hdmi_msm.1", OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 984 | CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF), |
| 985 | CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF), |
| 986 | CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF), |
| 987 | CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF), |
| 988 | CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF), |
| 989 | CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 990 | CLK_DUMMY("bus_clk", ROT_AXI_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 991 | CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF), |
| 992 | CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF), |
| 993 | CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF), |
| 994 | CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 995 | CLK_DUMMY("bus_clk", GFX3D_AXI_CLK, NULL, OFF), |
Tianyi Gou | 86bb472 | 2011-08-09 13:28:02 -0700 | [diff] [blame] | 996 | CLK_DUMMY("vcap_axi_clk", VCAP_AXI_CLK, NULL, OFF), |
| 997 | CLK_DUMMY("vcap_ahb_clk", VCAP_AHB_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 998 | CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF), |
| 999 | CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF), |
| 1000 | CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, NULL, OFF), |
| 1001 | CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, NULL, OFF), |
| 1002 | CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, NULL, OFF), |
| 1003 | CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, NULL, OFF), |
Tianyi Gou | 86bb472 | 2011-08-09 13:28:02 -0700 | [diff] [blame] | 1004 | CLK_DUMMY("lvds_clk", LVDS_CLK, NULL, OFF), |
| 1005 | CLK_DUMMY("mdp_p2clk", MDP_P2CLK, NULL, OFF), |
| 1006 | CLK_DUMMY("dsi2_pixel_clk", DSI2_PIXEL_CLK, NULL, OFF), |
| 1007 | CLK_DUMMY("lvds_ref_clk", LVDS_REF_CLK, NULL, OFF), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 1008 | CLK_DUMMY("iface_clk", GFX3D_P_CLK, "kgsl-3d0.0", OFF), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 1009 | CLK_DUMMY("master_iface_clk", HDMI_M_P_CLK, "hdmi_msm.1", OFF), |
| 1010 | CLK_DUMMY("slave_iface_clk", HDMI_S_P_CLK, "hdmi_msm.1", OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1011 | CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF), |
| 1012 | CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 1013 | CLK_DUMMY("mem_iface_clk", IMEM_P_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1014 | CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 1015 | CLK_DUMMY("iface_clk", SMMU_P_CLK, "msm_smmu", OFF), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 1016 | CLK_DUMMY("iface_clk", ROT_P_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1017 | CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF), |
| 1018 | CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF), |
| 1019 | CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF), |
| 1020 | CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF), |
| 1021 | CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF), |
| 1022 | CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF), |
| 1023 | CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF), |
| 1024 | CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF), |
| 1025 | CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF), |
| 1026 | CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF), |
| 1027 | CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF), |
| 1028 | CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF), |
| 1029 | CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF), |
| 1030 | CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF), |
Tianyi Gou | 142b8db | 2011-09-21 18:01:54 -0700 | [diff] [blame] | 1031 | CLK_DUMMY("audio_slimbus_clk", AUDIO_SLIMBUS_CLK, NULL, OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1032 | |
| 1033 | CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 1034 | CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, NULL, 0), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 1035 | CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0), |
| 1036 | CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0), |
| 1037 | CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0), |
| 1038 | CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1039 | CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0), |
| 1040 | CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0), |
Jin Hong | 01f2dbb | 2011-11-03 22:13:51 -0700 | [diff] [blame] | 1041 | CLK_DUMMY("mem_clk", EBI1_ADM_CLK, "msm_dmov", 0), |
Ramesh Masavarapu | 2831191 | 2011-10-27 11:04:12 -0700 | [diff] [blame] | 1042 | CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qce.0", OFF), |
| 1043 | CLK_DUMMY("ce3_core_src_clk", CE3_SRC_CLK, "qcrypto.0", OFF), |
| 1044 | CLK_DUMMY("core_clk", CE3_CORE_CLK, "qce.0", OFF), |
| 1045 | CLK_DUMMY("core_clk", CE3_CORE_CLK, "qcrypto.0", OFF), |
| 1046 | CLK_DUMMY("iface_clk", CE3_P_CLK, "qce0.0", OFF), |
| 1047 | CLK_DUMMY("iface_clk", CE3_P_CLK, "qcrypto.0", OFF), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1048 | }; |
| 1049 | |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 1050 | struct clock_init_data apq8064_dummy_clock_init_data __initdata = { |
| 1051 | .table = msm_clocks_8064_dummy, |
| 1052 | .size = ARRAY_SIZE(msm_clocks_8064_dummy), |
| 1053 | }; |
Praveen Chidambaram | 7849901 | 2011-11-01 17:15:17 -0600 | [diff] [blame] | 1054 | |
| 1055 | struct msm_rpm_platform_data apq8064_rpm_data __initdata = { |
| 1056 | .reg_base_addrs = { |
| 1057 | [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE, |
| 1058 | [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400, |
| 1059 | [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600, |
| 1060 | [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00, |
| 1061 | }, |
| 1062 | .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ, |
| 1063 | .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008, |
| 1064 | .ipc_rpm_val = 4, |
| 1065 | .target_id = { |
| 1066 | MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4), |
| 1067 | MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4), |
| 1068 | MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8), |
| 1069 | MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1), |
| 1070 | MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1), |
| 1071 | MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1), |
| 1072 | MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1), |
| 1073 | MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1), |
| 1074 | MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1), |
| 1075 | MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1), |
| 1076 | MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1), |
| 1077 | MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1), |
| 1078 | MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1), |
| 1079 | MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1), |
| 1080 | MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1), |
| 1081 | MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1), |
| 1082 | MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0, |
| 1083 | APPS_FABRIC_CFG_HALT, 2), |
| 1084 | MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0, |
| 1085 | APPS_FABRIC_CFG_CLKMOD, 3), |
| 1086 | MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL, |
| 1087 | APPS_FABRIC_CFG_IOCTL, 1), |
| 1088 | MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12), |
| 1089 | MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0, |
| 1090 | SYS_FABRIC_CFG_HALT, 2), |
| 1091 | MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0, |
| 1092 | SYS_FABRIC_CFG_CLKMOD, 3), |
| 1093 | MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL, |
| 1094 | SYS_FABRIC_CFG_IOCTL, 1), |
| 1095 | MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30), |
| 1096 | MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0, |
| 1097 | MMSS_FABRIC_CFG_HALT, 2), |
| 1098 | MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0, |
| 1099 | MMSS_FABRIC_CFG_CLKMOD, 3), |
| 1100 | MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL, |
| 1101 | MMSS_FABRIC_CFG_IOCTL, 1), |
| 1102 | MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21), |
| 1103 | MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2), |
| 1104 | MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2), |
| 1105 | MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2), |
| 1106 | MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2), |
| 1107 | MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2), |
| 1108 | MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2), |
| 1109 | MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2), |
| 1110 | MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2), |
| 1111 | MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2), |
| 1112 | MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2), |
| 1113 | MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2), |
| 1114 | MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2), |
| 1115 | MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2), |
| 1116 | MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2), |
| 1117 | MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2), |
| 1118 | MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2), |
| 1119 | MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2), |
| 1120 | MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2), |
| 1121 | MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2), |
| 1122 | MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2), |
| 1123 | MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2), |
| 1124 | MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2), |
| 1125 | MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2), |
| 1126 | MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2), |
| 1127 | MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2), |
| 1128 | MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2), |
| 1129 | MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2), |
| 1130 | MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2), |
| 1131 | MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2), |
| 1132 | MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2), |
| 1133 | MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2), |
| 1134 | MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2), |
| 1135 | MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2), |
| 1136 | MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2), |
| 1137 | MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2), |
| 1138 | MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2), |
| 1139 | MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2), |
| 1140 | MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2), |
| 1141 | MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2), |
| 1142 | MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1), |
| 1143 | MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1), |
| 1144 | MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1), |
| 1145 | MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1), |
| 1146 | MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1), |
| 1147 | MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1), |
| 1148 | MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1), |
| 1149 | MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2), |
| 1150 | MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2), |
| 1151 | MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2), |
| 1152 | MSM_RPM_MAP(8064, NCP_0, NCP, 2), |
| 1153 | MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1), |
| 1154 | MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1), |
| 1155 | MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1), |
| 1156 | MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2), |
| 1157 | MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1), |
| 1158 | }, |
| 1159 | .target_status = { |
| 1160 | MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR), |
| 1161 | MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR), |
| 1162 | MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD), |
| 1163 | MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0), |
| 1164 | MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1), |
| 1165 | MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2), |
| 1166 | MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0), |
| 1167 | MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE), |
| 1168 | MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL), |
| 1169 | MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK), |
| 1170 | MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK), |
| 1171 | MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK), |
| 1172 | MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK), |
| 1173 | MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK), |
| 1174 | MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK), |
| 1175 | MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK), |
| 1176 | MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK), |
| 1177 | MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK), |
| 1178 | MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK), |
| 1179 | MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT), |
| 1180 | MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD), |
| 1181 | MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL), |
| 1182 | MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB), |
| 1183 | MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT), |
| 1184 | MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD), |
| 1185 | MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL), |
| 1186 | MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB), |
| 1187 | MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT), |
| 1188 | MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD), |
| 1189 | MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL), |
| 1190 | MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB), |
| 1191 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0), |
| 1192 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1), |
| 1193 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0), |
| 1194 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1), |
| 1195 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0), |
| 1196 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1), |
| 1197 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0), |
| 1198 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1), |
| 1199 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0), |
| 1200 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1), |
| 1201 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0), |
| 1202 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1), |
| 1203 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0), |
| 1204 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1), |
| 1205 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0), |
| 1206 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1), |
| 1207 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0), |
| 1208 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1), |
| 1209 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0), |
| 1210 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1), |
| 1211 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0), |
| 1212 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1), |
| 1213 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0), |
| 1214 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1), |
| 1215 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0), |
| 1216 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1), |
| 1217 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0), |
| 1218 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1), |
| 1219 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0), |
| 1220 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1), |
| 1221 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0), |
| 1222 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1), |
| 1223 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0), |
| 1224 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1), |
| 1225 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0), |
| 1226 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1), |
| 1227 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0), |
| 1228 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1), |
| 1229 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0), |
| 1230 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1), |
| 1231 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0), |
| 1232 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1), |
| 1233 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0), |
| 1234 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1), |
| 1235 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0), |
| 1236 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1), |
| 1237 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0), |
| 1238 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1), |
| 1239 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0), |
| 1240 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1), |
| 1241 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0), |
| 1242 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1), |
| 1243 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0), |
| 1244 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1), |
| 1245 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0), |
| 1246 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1), |
| 1247 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0), |
| 1248 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1), |
| 1249 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0), |
| 1250 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1), |
| 1251 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0), |
| 1252 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1), |
| 1253 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0), |
| 1254 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1), |
| 1255 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0), |
| 1256 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1), |
| 1257 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0), |
| 1258 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1), |
| 1259 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0), |
| 1260 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1), |
| 1261 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0), |
| 1262 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1), |
| 1263 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0), |
| 1264 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1), |
| 1265 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0), |
| 1266 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1), |
| 1267 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0), |
| 1268 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1), |
| 1269 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1), |
| 1270 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2), |
| 1271 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3), |
| 1272 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4), |
| 1273 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5), |
| 1274 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6), |
| 1275 | MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7), |
| 1276 | MSM_RPM_STATUS_ID_MAP(8064, NCP_0), |
| 1277 | MSM_RPM_STATUS_ID_MAP(8064, NCP_1), |
| 1278 | MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS), |
| 1279 | MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH), |
| 1280 | MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH), |
| 1281 | MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0), |
| 1282 | MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1), |
| 1283 | MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE), |
| 1284 | MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE), |
| 1285 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0), |
| 1286 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1), |
| 1287 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0), |
| 1288 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1), |
| 1289 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0), |
| 1290 | MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1), |
| 1291 | }, |
| 1292 | .target_ctrl_id = { |
| 1293 | MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR), |
| 1294 | MSM_RPM_CTRL_MAP(8064, VERSION_MINOR), |
| 1295 | MSM_RPM_CTRL_MAP(8064, VERSION_BUILD), |
| 1296 | MSM_RPM_CTRL_MAP(8064, REQ_CTX_0), |
| 1297 | MSM_RPM_CTRL_MAP(8064, REQ_SEL_0), |
| 1298 | MSM_RPM_CTRL_MAP(8064, ACK_CTX_0), |
| 1299 | MSM_RPM_CTRL_MAP(8064, ACK_SEL_0), |
| 1300 | }, |
| 1301 | .sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE, |
| 1302 | .sel_notification = MSM_RPM_8064_SEL_NOTIFICATION, |
| 1303 | .sel_last = MSM_RPM_8064_SEL_LAST, |
| 1304 | .ver = {3, 0, 0}, |
| 1305 | }; |
| 1306 | |
| 1307 | struct platform_device apq8064_rpm_device = { |
| 1308 | .name = "msm_rpm", |
| 1309 | .id = -1, |
| 1310 | }; |
| 1311 | |
| 1312 | static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = { |
| 1313 | .phys_addr_base = 0x0010D204, |
| 1314 | .phys_size = SZ_8K, |
| 1315 | }; |
| 1316 | |
| 1317 | struct platform_device apq8064_rpm_stat_device = { |
| 1318 | .name = "msm_rpm_stat", |
| 1319 | .id = -1, |
| 1320 | .dev = { |
| 1321 | .platform_data = &msm_rpm_stat_pdata, |
| 1322 | }, |
| 1323 | }; |
| 1324 | |
| 1325 | static struct msm_rpm_log_platform_data msm_rpm_log_pdata = { |
| 1326 | .phys_addr_base = 0x0010C000, |
| 1327 | .reg_offsets = { |
| 1328 | [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080, |
| 1329 | [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0, |
| 1330 | }, |
| 1331 | .phys_size = SZ_8K, |
| 1332 | .log_len = 4096, /* log's buffer length in bytes */ |
| 1333 | .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */ |
| 1334 | }; |
| 1335 | |
| 1336 | struct platform_device apq8064_rpm_log_device = { |
| 1337 | .name = "msm_rpm_log", |
| 1338 | .id = -1, |
| 1339 | .dev = { |
| 1340 | .platform_data = &msm_rpm_log_pdata, |
| 1341 | }, |
| 1342 | }; |
| 1343 | |
| 1344 | #ifdef CONFIG_MSM_MPM |
| 1345 | static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = { |
| 1346 | [1] = MSM_GPIO_TO_INT(26), |
| 1347 | [2] = MSM_GPIO_TO_INT(88), |
| 1348 | [4] = MSM_GPIO_TO_INT(73), |
| 1349 | [5] = MSM_GPIO_TO_INT(74), |
| 1350 | [6] = MSM_GPIO_TO_INT(75), |
| 1351 | [7] = MSM_GPIO_TO_INT(76), |
| 1352 | [8] = MSM_GPIO_TO_INT(77), |
| 1353 | [9] = MSM_GPIO_TO_INT(36), |
| 1354 | [10] = MSM_GPIO_TO_INT(84), |
| 1355 | [11] = MSM_GPIO_TO_INT(7), |
| 1356 | [12] = MSM_GPIO_TO_INT(11), |
| 1357 | [13] = MSM_GPIO_TO_INT(52), |
| 1358 | [14] = MSM_GPIO_TO_INT(15), |
| 1359 | [15] = MSM_GPIO_TO_INT(83), |
| 1360 | [16] = USB3_HS_IRQ, |
| 1361 | [19] = MSM_GPIO_TO_INT(61), |
| 1362 | [20] = MSM_GPIO_TO_INT(58), |
| 1363 | [23] = MSM_GPIO_TO_INT(65), |
| 1364 | [24] = MSM_GPIO_TO_INT(63), |
| 1365 | [25] = USB1_HS_IRQ, |
| 1366 | [27] = HDMI_IRQ, |
| 1367 | [29] = MSM_GPIO_TO_INT(22), |
| 1368 | [30] = MSM_GPIO_TO_INT(72), |
| 1369 | [31] = USB4_HS_IRQ, |
| 1370 | [33] = MSM_GPIO_TO_INT(44), |
| 1371 | [34] = MSM_GPIO_TO_INT(39), |
| 1372 | [35] = MSM_GPIO_TO_INT(19), |
| 1373 | [36] = MSM_GPIO_TO_INT(23), |
| 1374 | [37] = MSM_GPIO_TO_INT(41), |
| 1375 | [38] = MSM_GPIO_TO_INT(30), |
| 1376 | [41] = MSM_GPIO_TO_INT(42), |
| 1377 | [42] = MSM_GPIO_TO_INT(56), |
| 1378 | [43] = MSM_GPIO_TO_INT(55), |
| 1379 | [44] = MSM_GPIO_TO_INT(50), |
| 1380 | [45] = MSM_GPIO_TO_INT(49), |
| 1381 | [46] = MSM_GPIO_TO_INT(47), |
| 1382 | [47] = MSM_GPIO_TO_INT(45), |
| 1383 | [48] = MSM_GPIO_TO_INT(38), |
| 1384 | [49] = MSM_GPIO_TO_INT(34), |
| 1385 | [50] = MSM_GPIO_TO_INT(32), |
| 1386 | [51] = MSM_GPIO_TO_INT(29), |
| 1387 | [52] = MSM_GPIO_TO_INT(18), |
| 1388 | [53] = MSM_GPIO_TO_INT(10), |
| 1389 | [54] = MSM_GPIO_TO_INT(81), |
| 1390 | [55] = MSM_GPIO_TO_INT(6), |
| 1391 | }; |
| 1392 | |
| 1393 | static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = { |
| 1394 | TLMM_MSM_SUMMARY_IRQ, |
| 1395 | RPM_APCC_CPU0_GP_HIGH_IRQ, |
| 1396 | RPM_APCC_CPU0_GP_MEDIUM_IRQ, |
| 1397 | RPM_APCC_CPU0_GP_LOW_IRQ, |
| 1398 | RPM_APCC_CPU0_WAKE_UP_IRQ, |
| 1399 | RPM_APCC_CPU1_GP_HIGH_IRQ, |
| 1400 | RPM_APCC_CPU1_GP_MEDIUM_IRQ, |
| 1401 | RPM_APCC_CPU1_GP_LOW_IRQ, |
| 1402 | RPM_APCC_CPU1_WAKE_UP_IRQ, |
| 1403 | MSS_TO_APPS_IRQ_0, |
| 1404 | MSS_TO_APPS_IRQ_1, |
| 1405 | MSS_TO_APPS_IRQ_2, |
| 1406 | MSS_TO_APPS_IRQ_3, |
| 1407 | MSS_TO_APPS_IRQ_4, |
| 1408 | MSS_TO_APPS_IRQ_5, |
| 1409 | MSS_TO_APPS_IRQ_6, |
| 1410 | MSS_TO_APPS_IRQ_7, |
| 1411 | MSS_TO_APPS_IRQ_8, |
| 1412 | MSS_TO_APPS_IRQ_9, |
| 1413 | LPASS_SCSS_GP_LOW_IRQ, |
| 1414 | LPASS_SCSS_GP_MEDIUM_IRQ, |
| 1415 | LPASS_SCSS_GP_HIGH_IRQ, |
| 1416 | SPS_MTI_30, |
| 1417 | SPS_MTI_31, |
| 1418 | RIVA_APSS_SPARE_IRQ, |
| 1419 | RIVA_APPS_WLAN_SMSM_IRQ, |
| 1420 | RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ, |
| 1421 | RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ, |
| 1422 | }; |
| 1423 | |
| 1424 | struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = { |
| 1425 | .irqs_m2a = msm_mpm_irqs_m2a, |
| 1426 | .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a), |
| 1427 | .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs, |
| 1428 | .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs), |
| 1429 | .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8, |
| 1430 | .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8, |
| 1431 | .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008, |
| 1432 | .mpm_apps_ipc_val = BIT(1), |
| 1433 | .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ, |
| 1434 | |
| 1435 | }; |
| 1436 | #endif |
Joel King | dacbc82 | 2012-01-25 13:30:57 -0800 | [diff] [blame] | 1437 | |
| 1438 | #define MDM2AP_ERRFATAL 19 |
| 1439 | #define AP2MDM_ERRFATAL 18 |
| 1440 | #define MDM2AP_STATUS 49 |
| 1441 | #define AP2MDM_STATUS 48 |
| 1442 | #define AP2MDM_PMIC_RESET_N 27 |
| 1443 | |
| 1444 | static struct resource mdm_resources[] = { |
| 1445 | { |
| 1446 | .start = MDM2AP_ERRFATAL, |
| 1447 | .end = MDM2AP_ERRFATAL, |
| 1448 | .name = "MDM2AP_ERRFATAL", |
| 1449 | .flags = IORESOURCE_IO, |
| 1450 | }, |
| 1451 | { |
| 1452 | .start = AP2MDM_ERRFATAL, |
| 1453 | .end = AP2MDM_ERRFATAL, |
| 1454 | .name = "AP2MDM_ERRFATAL", |
| 1455 | .flags = IORESOURCE_IO, |
| 1456 | }, |
| 1457 | { |
| 1458 | .start = MDM2AP_STATUS, |
| 1459 | .end = MDM2AP_STATUS, |
| 1460 | .name = "MDM2AP_STATUS", |
| 1461 | .flags = IORESOURCE_IO, |
| 1462 | }, |
| 1463 | { |
| 1464 | .start = AP2MDM_STATUS, |
| 1465 | .end = AP2MDM_STATUS, |
| 1466 | .name = "AP2MDM_STATUS", |
| 1467 | .flags = IORESOURCE_IO, |
| 1468 | }, |
| 1469 | { |
| 1470 | .start = AP2MDM_PMIC_RESET_N, |
| 1471 | .end = AP2MDM_PMIC_RESET_N, |
| 1472 | .name = "AP2MDM_PMIC_RESET_N", |
| 1473 | .flags = IORESOURCE_IO, |
| 1474 | }, |
| 1475 | }; |
| 1476 | |
| 1477 | struct platform_device mdm_8064_device = { |
| 1478 | .name = "mdm2_modem", |
| 1479 | .id = -1, |
| 1480 | .num_resources = ARRAY_SIZE(mdm_resources), |
| 1481 | .resource = mdm_resources, |
| 1482 | }; |
| 1483 | |