blob: f45f385c84cde98d51a3aee84eee09a4ab343a50 [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010032#include "i915_trace.h"
Jesse Barnes652c3932009-08-17 13:31:43 -070033#include "intel_drv.h"
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Eric Anholt673a3942008-07-30 12:06:12 -070035#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include <linux/pci.h>
Eric Anholt673a3942008-07-30 12:06:12 -070037
Chris Wilson2dafb1e2010-06-07 14:03:05 +010038static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080039static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080041static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070047static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -080048static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
Jesse Barnesde151cf2008-11-12 10:03:55 -080050static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
Chris Wilson07f73f62009-09-14 16:50:30 +010051static int i915_gem_evict_something(struct drm_device *dev, int min_size);
Chris Wilsonab5ee572009-09-20 19:25:47 +010052static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
Dave Airlie71acb5e2008-12-30 20:31:46 +100053static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
Chris Wilsonbe726152010-07-23 23:18:50 +010056static void i915_gem_free_object_tail(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070057
Chris Wilson31169712009-09-14 16:50:28 +010058static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
Jesse Barnes79e53942008-11-07 14:24:08 -080061int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
65
66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
69 return -EINVAL;
70 }
71
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
74
75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
Keith Packard6dbe2772008-10-14 21:41:13 -070079
Eric Anholt673a3942008-07-30 12:06:12 -070080int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
Eric Anholt673a3942008-07-30 12:06:12 -070084 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080085 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070086
87 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080088 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -070089 mutex_unlock(&dev->struct_mutex);
90
Jesse Barnes79e53942008-11-07 14:24:08 -080091 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -070092}
93
Eric Anholt5a125c32008-10-22 21:40:13 -070094int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
Eric Anholt5a125c32008-10-22 21:40:13 -070098 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -070099
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -0800104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700106
107 return 0;
108}
109
Eric Anholt673a3942008-07-30 12:06:12 -0700110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
Pekka Paalanena1a2d1d2009-08-23 12:40:55 +0300120 int ret;
121 u32 handle;
Eric Anholt673a3942008-07-30 12:06:12 -0700122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
Daniel Vetterac52bc52010-04-09 19:05:06 +0000126 obj = i915_gem_alloc_object(dev, args->size);
Eric Anholt673a3942008-07-30 12:06:12 -0700127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
Luca Barbieribc9025b2010-02-09 05:49:12 +0000131 drm_gem_object_handle_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700132
133 if (ret)
134 return ret;
135
136 args->handle = handle;
137
138 return 0;
139}
140
Eric Anholt40123c12009-03-09 13:42:30 -0700141static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700142fast_shmem_read(struct page **pages,
143 loff_t page_base, int page_offset,
144 char __user *data,
145 int length)
146{
147 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200148 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700149
150 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
151 if (vaddr == NULL)
152 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200153 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700154 kunmap_atomic(vaddr, KM_USER0);
155
Florian Mickler2bc43b52009-04-06 22:55:41 +0200156 if (unwritten)
157 return -EFAULT;
158
159 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700160}
161
Eric Anholt280b7132009-03-12 16:56:27 -0700162static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
163{
164 drm_i915_private_t *dev_priv = obj->dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +0100165 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt280b7132009-03-12 16:56:27 -0700166
167 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
168 obj_priv->tiling_mode != I915_TILING_NONE;
169}
170
Chris Wilson99a03df2010-05-27 14:15:34 +0100171static inline void
Eric Anholt40123c12009-03-09 13:42:30 -0700172slow_shmem_copy(struct page *dst_page,
173 int dst_offset,
174 struct page *src_page,
175 int src_offset,
176 int length)
177{
178 char *dst_vaddr, *src_vaddr;
179
Chris Wilson99a03df2010-05-27 14:15:34 +0100180 dst_vaddr = kmap(dst_page);
181 src_vaddr = kmap(src_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700182
183 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
184
Chris Wilson99a03df2010-05-27 14:15:34 +0100185 kunmap(src_page);
186 kunmap(dst_page);
Eric Anholt40123c12009-03-09 13:42:30 -0700187}
188
Chris Wilson99a03df2010-05-27 14:15:34 +0100189static inline void
Eric Anholt280b7132009-03-12 16:56:27 -0700190slow_shmem_bit17_copy(struct page *gpu_page,
191 int gpu_offset,
192 struct page *cpu_page,
193 int cpu_offset,
194 int length,
195 int is_read)
196{
197 char *gpu_vaddr, *cpu_vaddr;
198
199 /* Use the unswizzled path if this page isn't affected. */
200 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
201 if (is_read)
202 return slow_shmem_copy(cpu_page, cpu_offset,
203 gpu_page, gpu_offset, length);
204 else
205 return slow_shmem_copy(gpu_page, gpu_offset,
206 cpu_page, cpu_offset, length);
207 }
208
Chris Wilson99a03df2010-05-27 14:15:34 +0100209 gpu_vaddr = kmap(gpu_page);
210 cpu_vaddr = kmap(cpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700211
212 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
213 * XORing with the other bits (A9 for Y, A9 and A10 for X)
214 */
215 while (length > 0) {
216 int cacheline_end = ALIGN(gpu_offset + 1, 64);
217 int this_length = min(cacheline_end - gpu_offset, length);
218 int swizzled_gpu_offset = gpu_offset ^ 64;
219
220 if (is_read) {
221 memcpy(cpu_vaddr + cpu_offset,
222 gpu_vaddr + swizzled_gpu_offset,
223 this_length);
224 } else {
225 memcpy(gpu_vaddr + swizzled_gpu_offset,
226 cpu_vaddr + cpu_offset,
227 this_length);
228 }
229 cpu_offset += this_length;
230 gpu_offset += this_length;
231 length -= this_length;
232 }
233
Chris Wilson99a03df2010-05-27 14:15:34 +0100234 kunmap(cpu_page);
235 kunmap(gpu_page);
Eric Anholt280b7132009-03-12 16:56:27 -0700236}
237
Eric Anholt673a3942008-07-30 12:06:12 -0700238/**
Eric Anholteb014592009-03-10 11:44:52 -0700239 * This is the fast shmem pread path, which attempts to copy_from_user directly
240 * from the backing pages of the object to the user's address space. On a
241 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
242 */
243static int
244i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
245 struct drm_i915_gem_pread *args,
246 struct drm_file *file_priv)
247{
Daniel Vetter23010e42010-03-08 13:35:02 +0100248 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700249 ssize_t remain;
250 loff_t offset, page_base;
251 char __user *user_data;
252 int page_offset, page_length;
253 int ret;
254
255 user_data = (char __user *) (uintptr_t) args->data_ptr;
256 remain = args->size;
257
258 mutex_lock(&dev->struct_mutex);
259
Chris Wilson4bdadb92010-01-27 13:36:32 +0000260 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholteb014592009-03-10 11:44:52 -0700261 if (ret != 0)
262 goto fail_unlock;
263
264 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
265 args->size);
266 if (ret != 0)
267 goto fail_put_pages;
268
Daniel Vetter23010e42010-03-08 13:35:02 +0100269 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700270 offset = args->offset;
271
272 while (remain > 0) {
273 /* Operation in this page
274 *
275 * page_base = page offset within aperture
276 * page_offset = offset within page
277 * page_length = bytes to copy for this page
278 */
279 page_base = (offset & ~(PAGE_SIZE-1));
280 page_offset = offset & (PAGE_SIZE-1);
281 page_length = remain;
282 if ((page_offset + remain) > PAGE_SIZE)
283 page_length = PAGE_SIZE - page_offset;
284
285 ret = fast_shmem_read(obj_priv->pages,
286 page_base, page_offset,
287 user_data, page_length);
288 if (ret)
289 goto fail_put_pages;
290
291 remain -= page_length;
292 user_data += page_length;
293 offset += page_length;
294 }
295
296fail_put_pages:
297 i915_gem_object_put_pages(obj);
298fail_unlock:
299 mutex_unlock(&dev->struct_mutex);
300
301 return ret;
302}
303
Chris Wilson07f73f62009-09-14 16:50:30 +0100304static int
305i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
306{
307 int ret;
308
Chris Wilson4bdadb92010-01-27 13:36:32 +0000309 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
Chris Wilson07f73f62009-09-14 16:50:30 +0100310
311 /* If we've insufficient memory to map in the pages, attempt
312 * to make some space by throwing out some old buffers.
313 */
314 if (ret == -ENOMEM) {
315 struct drm_device *dev = obj->dev;
Chris Wilson07f73f62009-09-14 16:50:30 +0100316
317 ret = i915_gem_evict_something(dev, obj->size);
318 if (ret)
319 return ret;
320
Chris Wilson4bdadb92010-01-27 13:36:32 +0000321 ret = i915_gem_object_get_pages(obj, 0);
Chris Wilson07f73f62009-09-14 16:50:30 +0100322 }
323
324 return ret;
325}
326
Eric Anholteb014592009-03-10 11:44:52 -0700327/**
328 * This is the fallback shmem pread path, which allocates temporary storage
329 * in kernel space to copy_to_user into outside of the struct_mutex, so we
330 * can copy out of the object's backing pages while holding the struct mutex
331 * and not take page faults.
332 */
333static int
334i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
335 struct drm_i915_gem_pread *args,
336 struct drm_file *file_priv)
337{
Daniel Vetter23010e42010-03-08 13:35:02 +0100338 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700339 struct mm_struct *mm = current->mm;
340 struct page **user_pages;
341 ssize_t remain;
342 loff_t offset, pinned_pages, i;
343 loff_t first_data_page, last_data_page, num_pages;
344 int shmem_page_index, shmem_page_offset;
345 int data_page_index, data_page_offset;
346 int page_length;
347 int ret;
348 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700349 int do_bit17_swizzling;
Eric Anholteb014592009-03-10 11:44:52 -0700350
351 remain = args->size;
352
353 /* Pin the user pages containing the data. We can't fault while
354 * holding the struct mutex, yet we want to hold it while
355 * dereferencing the user data.
356 */
357 first_data_page = data_ptr / PAGE_SIZE;
358 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
359 num_pages = last_data_page - first_data_page + 1;
360
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700361 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholteb014592009-03-10 11:44:52 -0700362 if (user_pages == NULL)
363 return -ENOMEM;
364
365 down_read(&mm->mmap_sem);
366 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700367 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700368 up_read(&mm->mmap_sem);
369 if (pinned_pages < num_pages) {
370 ret = -EFAULT;
371 goto fail_put_user_pages;
372 }
373
Eric Anholt280b7132009-03-12 16:56:27 -0700374 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
375
Eric Anholteb014592009-03-10 11:44:52 -0700376 mutex_lock(&dev->struct_mutex);
377
Chris Wilson07f73f62009-09-14 16:50:30 +0100378 ret = i915_gem_object_get_pages_or_evict(obj);
379 if (ret)
Eric Anholteb014592009-03-10 11:44:52 -0700380 goto fail_unlock;
381
382 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
383 args->size);
384 if (ret != 0)
385 goto fail_put_pages;
386
Daniel Vetter23010e42010-03-08 13:35:02 +0100387 obj_priv = to_intel_bo(obj);
Eric Anholteb014592009-03-10 11:44:52 -0700388 offset = args->offset;
389
390 while (remain > 0) {
391 /* Operation in this page
392 *
393 * shmem_page_index = page number within shmem file
394 * shmem_page_offset = offset within page in shmem file
395 * data_page_index = page number in get_user_pages return
396 * data_page_offset = offset with data_page_index page.
397 * page_length = bytes to copy for this page
398 */
399 shmem_page_index = offset / PAGE_SIZE;
400 shmem_page_offset = offset & ~PAGE_MASK;
401 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
402 data_page_offset = data_ptr & ~PAGE_MASK;
403
404 page_length = remain;
405 if ((shmem_page_offset + page_length) > PAGE_SIZE)
406 page_length = PAGE_SIZE - shmem_page_offset;
407 if ((data_page_offset + page_length) > PAGE_SIZE)
408 page_length = PAGE_SIZE - data_page_offset;
409
Eric Anholt280b7132009-03-12 16:56:27 -0700410 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100411 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700412 shmem_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100413 user_pages[data_page_index],
414 data_page_offset,
415 page_length,
416 1);
417 } else {
418 slow_shmem_copy(user_pages[data_page_index],
419 data_page_offset,
420 obj_priv->pages[shmem_page_index],
421 shmem_page_offset,
422 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700423 }
Eric Anholteb014592009-03-10 11:44:52 -0700424
425 remain -= page_length;
426 data_ptr += page_length;
427 offset += page_length;
428 }
429
430fail_put_pages:
431 i915_gem_object_put_pages(obj);
432fail_unlock:
433 mutex_unlock(&dev->struct_mutex);
434fail_put_user_pages:
435 for (i = 0; i < pinned_pages; i++) {
436 SetPageDirty(user_pages[i]);
437 page_cache_release(user_pages[i]);
438 }
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700439 drm_free_large(user_pages);
Eric Anholteb014592009-03-10 11:44:52 -0700440
441 return ret;
442}
443
Eric Anholt673a3942008-07-30 12:06:12 -0700444/**
445 * Reads data from the object referenced by handle.
446 *
447 * On error, the contents of *data are undefined.
448 */
449int
450i915_gem_pread_ioctl(struct drm_device *dev, void *data,
451 struct drm_file *file_priv)
452{
453 struct drm_i915_gem_pread *args = data;
454 struct drm_gem_object *obj;
455 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700456 int ret;
457
458 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
459 if (obj == NULL)
460 return -EBADF;
Daniel Vetter23010e42010-03-08 13:35:02 +0100461 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700462
463 /* Bounds check source.
464 *
465 * XXX: This could use review for overflow issues...
466 */
467 if (args->offset > obj->size || args->size > obj->size ||
468 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000469 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700470 return -EINVAL;
471 }
472
Eric Anholt280b7132009-03-12 16:56:27 -0700473 if (i915_gem_object_needs_bit17_swizzle(obj)) {
Eric Anholteb014592009-03-10 11:44:52 -0700474 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt280b7132009-03-12 16:56:27 -0700475 } else {
476 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
477 if (ret != 0)
478 ret = i915_gem_shmem_pread_slow(dev, obj, args,
479 file_priv);
480 }
Eric Anholt673a3942008-07-30 12:06:12 -0700481
Luca Barbieribc9025b2010-02-09 05:49:12 +0000482 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700483
Eric Anholteb014592009-03-10 11:44:52 -0700484 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700485}
486
Keith Packard0839ccb2008-10-30 19:38:48 -0700487/* This is the fast write path which cannot handle
488 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700489 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700490
Keith Packard0839ccb2008-10-30 19:38:48 -0700491static inline int
492fast_user_write(struct io_mapping *mapping,
493 loff_t page_base, int page_offset,
494 char __user *user_data,
495 int length)
496{
497 char *vaddr_atomic;
498 unsigned long unwritten;
499
500 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
501 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
502 user_data, length);
503 io_mapping_unmap_atomic(vaddr_atomic);
504 if (unwritten)
505 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700506 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700507}
508
509/* Here's the write path which can sleep for
510 * page faults
511 */
512
Chris Wilsonab34c222010-05-27 14:15:35 +0100513static inline void
Eric Anholt3de09aa2009-03-09 09:42:23 -0700514slow_kernel_write(struct io_mapping *mapping,
515 loff_t gtt_base, int gtt_offset,
516 struct page *user_page, int user_offset,
517 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700518{
Chris Wilsonab34c222010-05-27 14:15:35 +0100519 char __iomem *dst_vaddr;
520 char *src_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700521
Chris Wilsonab34c222010-05-27 14:15:35 +0100522 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
523 src_vaddr = kmap(user_page);
524
525 memcpy_toio(dst_vaddr + gtt_offset,
526 src_vaddr + user_offset,
527 length);
528
529 kunmap(user_page);
530 io_mapping_unmap(dst_vaddr);
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700531}
532
Eric Anholt40123c12009-03-09 13:42:30 -0700533static inline int
534fast_shmem_write(struct page **pages,
535 loff_t page_base, int page_offset,
536 char __user *data,
537 int length)
538{
539 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400540 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700541
542 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
543 if (vaddr == NULL)
544 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400545 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700546 kunmap_atomic(vaddr, KM_USER0);
547
Dave Airlied0088772009-03-28 20:29:48 -0400548 if (unwritten)
549 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700550 return 0;
551}
552
Eric Anholt3de09aa2009-03-09 09:42:23 -0700553/**
554 * This is the fast pwrite path, where we copy the data directly from the
555 * user into the GTT, uncached.
556 */
Eric Anholt673a3942008-07-30 12:06:12 -0700557static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700558i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
559 struct drm_i915_gem_pwrite *args,
560 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700561{
Daniel Vetter23010e42010-03-08 13:35:02 +0100562 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Keith Packard0839ccb2008-10-30 19:38:48 -0700563 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700564 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700565 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700566 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700567 int page_offset, page_length;
568 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700569
570 user_data = (char __user *) (uintptr_t) args->data_ptr;
571 remain = args->size;
572 if (!access_ok(VERIFY_READ, user_data, remain))
573 return -EFAULT;
574
575
576 mutex_lock(&dev->struct_mutex);
577 ret = i915_gem_object_pin(obj, 0);
578 if (ret) {
579 mutex_unlock(&dev->struct_mutex);
580 return ret;
581 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800582 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700583 if (ret)
584 goto fail;
585
Daniel Vetter23010e42010-03-08 13:35:02 +0100586 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700587 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700588
589 while (remain > 0) {
590 /* Operation in this page
591 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700592 * page_base = page offset within aperture
593 * page_offset = offset within page
594 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700595 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700596 page_base = (offset & ~(PAGE_SIZE-1));
597 page_offset = offset & (PAGE_SIZE-1);
598 page_length = remain;
599 if ((page_offset + remain) > PAGE_SIZE)
600 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700601
Keith Packard0839ccb2008-10-30 19:38:48 -0700602 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
603 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700604
Keith Packard0839ccb2008-10-30 19:38:48 -0700605 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700606 * source page isn't available. Return the error and we'll
607 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700608 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700609 if (ret)
610 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700611
Keith Packard0839ccb2008-10-30 19:38:48 -0700612 remain -= page_length;
613 user_data += page_length;
614 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700615 }
Eric Anholt673a3942008-07-30 12:06:12 -0700616
617fail:
618 i915_gem_object_unpin(obj);
619 mutex_unlock(&dev->struct_mutex);
620
621 return ret;
622}
623
Eric Anholt3de09aa2009-03-09 09:42:23 -0700624/**
625 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
626 * the memory and maps it using kmap_atomic for copying.
627 *
628 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
629 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
630 */
Eric Anholt3043c602008-10-02 12:24:47 -0700631static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700632i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
633 struct drm_i915_gem_pwrite *args,
634 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700635{
Daniel Vetter23010e42010-03-08 13:35:02 +0100636 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700637 drm_i915_private_t *dev_priv = dev->dev_private;
638 ssize_t remain;
639 loff_t gtt_page_base, offset;
640 loff_t first_data_page, last_data_page, num_pages;
641 loff_t pinned_pages, i;
642 struct page **user_pages;
643 struct mm_struct *mm = current->mm;
644 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700645 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700646 uint64_t data_ptr = args->data_ptr;
647
648 remain = args->size;
649
650 /* Pin the user pages containing the data. We can't fault while
651 * holding the struct mutex, and all of the pwrite implementations
652 * want to hold it while dereferencing the user data.
653 */
654 first_data_page = data_ptr / PAGE_SIZE;
655 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
656 num_pages = last_data_page - first_data_page + 1;
657
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700658 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt3de09aa2009-03-09 09:42:23 -0700659 if (user_pages == NULL)
660 return -ENOMEM;
661
662 down_read(&mm->mmap_sem);
663 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
664 num_pages, 0, 0, user_pages, NULL);
665 up_read(&mm->mmap_sem);
666 if (pinned_pages < num_pages) {
667 ret = -EFAULT;
668 goto out_unpin_pages;
669 }
670
671 mutex_lock(&dev->struct_mutex);
672 ret = i915_gem_object_pin(obj, 0);
673 if (ret)
674 goto out_unlock;
675
676 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
677 if (ret)
678 goto out_unpin_object;
679
Daniel Vetter23010e42010-03-08 13:35:02 +0100680 obj_priv = to_intel_bo(obj);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700681 offset = obj_priv->gtt_offset + args->offset;
682
683 while (remain > 0) {
684 /* Operation in this page
685 *
686 * gtt_page_base = page offset within aperture
687 * gtt_page_offset = offset within page in aperture
688 * data_page_index = page number in get_user_pages return
689 * data_page_offset = offset with data_page_index page.
690 * page_length = bytes to copy for this page
691 */
692 gtt_page_base = offset & PAGE_MASK;
693 gtt_page_offset = offset & ~PAGE_MASK;
694 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
695 data_page_offset = data_ptr & ~PAGE_MASK;
696
697 page_length = remain;
698 if ((gtt_page_offset + page_length) > PAGE_SIZE)
699 page_length = PAGE_SIZE - gtt_page_offset;
700 if ((data_page_offset + page_length) > PAGE_SIZE)
701 page_length = PAGE_SIZE - data_page_offset;
702
Chris Wilsonab34c222010-05-27 14:15:35 +0100703 slow_kernel_write(dev_priv->mm.gtt_mapping,
704 gtt_page_base, gtt_page_offset,
705 user_pages[data_page_index],
706 data_page_offset,
707 page_length);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700708
709 remain -= page_length;
710 offset += page_length;
711 data_ptr += page_length;
712 }
713
714out_unpin_object:
715 i915_gem_object_unpin(obj);
716out_unlock:
717 mutex_unlock(&dev->struct_mutex);
718out_unpin_pages:
719 for (i = 0; i < pinned_pages; i++)
720 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700721 drm_free_large(user_pages);
Eric Anholt3de09aa2009-03-09 09:42:23 -0700722
723 return ret;
724}
725
Eric Anholt40123c12009-03-09 13:42:30 -0700726/**
727 * This is the fast shmem pwrite path, which attempts to directly
728 * copy_from_user into the kmapped pages backing the object.
729 */
Eric Anholt673a3942008-07-30 12:06:12 -0700730static int
Eric Anholt40123c12009-03-09 13:42:30 -0700731i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
732 struct drm_i915_gem_pwrite *args,
733 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700734{
Daniel Vetter23010e42010-03-08 13:35:02 +0100735 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700736 ssize_t remain;
737 loff_t offset, page_base;
738 char __user *user_data;
739 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700740 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700741
742 user_data = (char __user *) (uintptr_t) args->data_ptr;
743 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700744
745 mutex_lock(&dev->struct_mutex);
746
Chris Wilson4bdadb92010-01-27 13:36:32 +0000747 ret = i915_gem_object_get_pages(obj, 0);
Eric Anholt40123c12009-03-09 13:42:30 -0700748 if (ret != 0)
749 goto fail_unlock;
750
Eric Anholte47c68e2008-11-14 13:35:19 -0800751 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700752 if (ret != 0)
753 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700754
Daniel Vetter23010e42010-03-08 13:35:02 +0100755 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700756 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700757 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700758
Eric Anholt40123c12009-03-09 13:42:30 -0700759 while (remain > 0) {
760 /* Operation in this page
761 *
762 * page_base = page offset within aperture
763 * page_offset = offset within page
764 * page_length = bytes to copy for this page
765 */
766 page_base = (offset & ~(PAGE_SIZE-1));
767 page_offset = offset & (PAGE_SIZE-1);
768 page_length = remain;
769 if ((page_offset + remain) > PAGE_SIZE)
770 page_length = PAGE_SIZE - page_offset;
771
772 ret = fast_shmem_write(obj_priv->pages,
773 page_base, page_offset,
774 user_data, page_length);
775 if (ret)
776 goto fail_put_pages;
777
778 remain -= page_length;
779 user_data += page_length;
780 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700781 }
782
Eric Anholt40123c12009-03-09 13:42:30 -0700783fail_put_pages:
784 i915_gem_object_put_pages(obj);
785fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700786 mutex_unlock(&dev->struct_mutex);
787
Eric Anholt40123c12009-03-09 13:42:30 -0700788 return ret;
789}
790
791/**
792 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
793 * the memory and maps it using kmap_atomic for copying.
794 *
795 * This avoids taking mmap_sem for faulting on the user's address while the
796 * struct_mutex is held.
797 */
798static int
799i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
800 struct drm_i915_gem_pwrite *args,
801 struct drm_file *file_priv)
802{
Daniel Vetter23010e42010-03-08 13:35:02 +0100803 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700804 struct mm_struct *mm = current->mm;
805 struct page **user_pages;
806 ssize_t remain;
807 loff_t offset, pinned_pages, i;
808 loff_t first_data_page, last_data_page, num_pages;
809 int shmem_page_index, shmem_page_offset;
810 int data_page_index, data_page_offset;
811 int page_length;
812 int ret;
813 uint64_t data_ptr = args->data_ptr;
Eric Anholt280b7132009-03-12 16:56:27 -0700814 int do_bit17_swizzling;
Eric Anholt40123c12009-03-09 13:42:30 -0700815
816 remain = args->size;
817
818 /* Pin the user pages containing the data. We can't fault while
819 * holding the struct mutex, and all of the pwrite implementations
820 * want to hold it while dereferencing the user data.
821 */
822 first_data_page = data_ptr / PAGE_SIZE;
823 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
824 num_pages = last_data_page - first_data_page + 1;
825
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700826 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
Eric Anholt40123c12009-03-09 13:42:30 -0700827 if (user_pages == NULL)
828 return -ENOMEM;
829
830 down_read(&mm->mmap_sem);
831 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
832 num_pages, 0, 0, user_pages, NULL);
833 up_read(&mm->mmap_sem);
834 if (pinned_pages < num_pages) {
835 ret = -EFAULT;
836 goto fail_put_user_pages;
837 }
838
Eric Anholt280b7132009-03-12 16:56:27 -0700839 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
840
Eric Anholt40123c12009-03-09 13:42:30 -0700841 mutex_lock(&dev->struct_mutex);
842
Chris Wilson07f73f62009-09-14 16:50:30 +0100843 ret = i915_gem_object_get_pages_or_evict(obj);
844 if (ret)
Eric Anholt40123c12009-03-09 13:42:30 -0700845 goto fail_unlock;
846
847 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
848 if (ret != 0)
849 goto fail_put_pages;
850
Daniel Vetter23010e42010-03-08 13:35:02 +0100851 obj_priv = to_intel_bo(obj);
Eric Anholt40123c12009-03-09 13:42:30 -0700852 offset = args->offset;
853 obj_priv->dirty = 1;
854
855 while (remain > 0) {
856 /* Operation in this page
857 *
858 * shmem_page_index = page number within shmem file
859 * shmem_page_offset = offset within page in shmem file
860 * data_page_index = page number in get_user_pages return
861 * data_page_offset = offset with data_page_index page.
862 * page_length = bytes to copy for this page
863 */
864 shmem_page_index = offset / PAGE_SIZE;
865 shmem_page_offset = offset & ~PAGE_MASK;
866 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
867 data_page_offset = data_ptr & ~PAGE_MASK;
868
869 page_length = remain;
870 if ((shmem_page_offset + page_length) > PAGE_SIZE)
871 page_length = PAGE_SIZE - shmem_page_offset;
872 if ((data_page_offset + page_length) > PAGE_SIZE)
873 page_length = PAGE_SIZE - data_page_offset;
874
Eric Anholt280b7132009-03-12 16:56:27 -0700875 if (do_bit17_swizzling) {
Chris Wilson99a03df2010-05-27 14:15:34 +0100876 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
Eric Anholt280b7132009-03-12 16:56:27 -0700877 shmem_page_offset,
878 user_pages[data_page_index],
879 data_page_offset,
Chris Wilson99a03df2010-05-27 14:15:34 +0100880 page_length,
881 0);
882 } else {
883 slow_shmem_copy(obj_priv->pages[shmem_page_index],
884 shmem_page_offset,
885 user_pages[data_page_index],
886 data_page_offset,
887 page_length);
Eric Anholt280b7132009-03-12 16:56:27 -0700888 }
Eric Anholt40123c12009-03-09 13:42:30 -0700889
890 remain -= page_length;
891 data_ptr += page_length;
892 offset += page_length;
893 }
894
895fail_put_pages:
896 i915_gem_object_put_pages(obj);
897fail_unlock:
898 mutex_unlock(&dev->struct_mutex);
899fail_put_user_pages:
900 for (i = 0; i < pinned_pages; i++)
901 page_cache_release(user_pages[i]);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -0700902 drm_free_large(user_pages);
Eric Anholt40123c12009-03-09 13:42:30 -0700903
904 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700905}
906
907/**
908 * Writes data to the object referenced by handle.
909 *
910 * On error, the contents of the buffer that were to be modified are undefined.
911 */
912int
913i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
914 struct drm_file *file_priv)
915{
916 struct drm_i915_gem_pwrite *args = data;
917 struct drm_gem_object *obj;
918 struct drm_i915_gem_object *obj_priv;
919 int ret = 0;
920
921 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
922 if (obj == NULL)
923 return -EBADF;
Daniel Vetter23010e42010-03-08 13:35:02 +0100924 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700925
926 /* Bounds check destination.
927 *
928 * XXX: This could use review for overflow issues...
929 */
930 if (args->offset > obj->size || args->size > obj->size ||
931 args->offset + args->size > obj->size) {
Luca Barbieribc9025b2010-02-09 05:49:12 +0000932 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700933 return -EINVAL;
934 }
935
936 /* We can only do the GTT pwrite on untiled buffers, as otherwise
937 * it would end up going through the fenced access, and we'll get
938 * different detiling behavior between reading and writing.
939 * pread/pwrite currently are reading and writing from the CPU
940 * perspective, requiring manual detiling by the client.
941 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000942 if (obj_priv->phys_obj)
943 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
944 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Chris Wilson9b8c4a02010-05-27 14:21:01 +0100945 dev->gtt_total != 0 &&
946 obj->write_domain != I915_GEM_DOMAIN_CPU) {
Eric Anholt3de09aa2009-03-09 09:42:23 -0700947 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
948 if (ret == -EFAULT) {
949 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
950 file_priv);
951 }
Eric Anholt280b7132009-03-12 16:56:27 -0700952 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
953 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
Eric Anholt40123c12009-03-09 13:42:30 -0700954 } else {
955 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
956 if (ret == -EFAULT) {
957 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
958 file_priv);
959 }
960 }
Eric Anholt673a3942008-07-30 12:06:12 -0700961
962#if WATCH_PWRITE
963 if (ret)
964 DRM_INFO("pwrite failed %d\n", ret);
965#endif
966
Luca Barbieribc9025b2010-02-09 05:49:12 +0000967 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700968
969 return ret;
970}
971
972/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800973 * Called when user space prepares to use an object with the CPU, either
974 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -0700975 */
976int
977i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
978 struct drm_file *file_priv)
979{
Eric Anholta09ba7f2009-08-29 12:49:51 -0700980 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700981 struct drm_i915_gem_set_domain *args = data;
982 struct drm_gem_object *obj;
Jesse Barnes652c3932009-08-17 13:31:43 -0700983 struct drm_i915_gem_object *obj_priv;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800984 uint32_t read_domains = args->read_domains;
985 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -0700986 int ret;
987
988 if (!(dev->driver->driver_features & DRIVER_GEM))
989 return -ENODEV;
990
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800991 /* Only handle setting domains to types used by the CPU. */
Chris Wilson21d509e2009-06-06 09:46:02 +0100992 if (write_domain & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800993 return -EINVAL;
994
Chris Wilson21d509e2009-06-06 09:46:02 +0100995 if (read_domains & I915_GEM_GPU_DOMAINS)
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800996 return -EINVAL;
997
998 /* Having something in the write domain implies it's in the read
999 * domain, and only that read domain. Enforce that in the request.
1000 */
1001 if (write_domain != 0 && read_domains != write_domain)
1002 return -EINVAL;
1003
Eric Anholt673a3942008-07-30 12:06:12 -07001004 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1005 if (obj == NULL)
1006 return -EBADF;
Daniel Vetter23010e42010-03-08 13:35:02 +01001007 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001008
1009 mutex_lock(&dev->struct_mutex);
Jesse Barnes652c3932009-08-17 13:31:43 -07001010
1011 intel_mark_busy(dev, obj);
1012
Eric Anholt673a3942008-07-30 12:06:12 -07001013#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001014 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001015 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07001016#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001017 if (read_domains & I915_GEM_DOMAIN_GTT) {
1018 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -08001019
Eric Anholta09ba7f2009-08-29 12:49:51 -07001020 /* Update the LRU on the fence for the CPU access that's
1021 * about to occur.
1022 */
1023 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001024 struct drm_i915_fence_reg *reg =
1025 &dev_priv->fence_regs[obj_priv->fence_reg];
1026 list_move_tail(&reg->lru_list,
Eric Anholta09ba7f2009-08-29 12:49:51 -07001027 &dev_priv->mm.fence_list);
1028 }
1029
Eric Anholt02354392008-11-26 13:58:13 -08001030 /* Silently promote "you're not bound, there was nothing to do"
1031 * to success, since the client was just asking us to
1032 * make sure everything was done.
1033 */
1034 if (ret == -EINVAL)
1035 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001036 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -08001037 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08001038 }
1039
Eric Anholt673a3942008-07-30 12:06:12 -07001040 drm_gem_object_unreference(obj);
1041 mutex_unlock(&dev->struct_mutex);
1042 return ret;
1043}
1044
1045/**
1046 * Called when user space has done writes to this buffer
1047 */
1048int
1049i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1050 struct drm_file *file_priv)
1051{
1052 struct drm_i915_gem_sw_finish *args = data;
1053 struct drm_gem_object *obj;
1054 struct drm_i915_gem_object *obj_priv;
1055 int ret = 0;
1056
1057 if (!(dev->driver->driver_features & DRIVER_GEM))
1058 return -ENODEV;
1059
1060 mutex_lock(&dev->struct_mutex);
1061 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1062 if (obj == NULL) {
1063 mutex_unlock(&dev->struct_mutex);
1064 return -EBADF;
1065 }
1066
1067#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02001068 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
Eric Anholt673a3942008-07-30 12:06:12 -07001069 __func__, args->handle, obj, obj->size);
1070#endif
Daniel Vetter23010e42010-03-08 13:35:02 +01001071 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001072
1073 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -08001074 if (obj_priv->pin_count)
1075 i915_gem_object_flush_cpu_write_domain(obj);
1076
Eric Anholt673a3942008-07-30 12:06:12 -07001077 drm_gem_object_unreference(obj);
1078 mutex_unlock(&dev->struct_mutex);
1079 return ret;
1080}
1081
1082/**
1083 * Maps the contents of an object, returning the address it is mapped
1084 * into.
1085 *
1086 * While the mapping holds a reference on the contents of the object, it doesn't
1087 * imply a ref on the object itself.
1088 */
1089int
1090i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv)
1092{
1093 struct drm_i915_gem_mmap *args = data;
1094 struct drm_gem_object *obj;
1095 loff_t offset;
1096 unsigned long addr;
1097
1098 if (!(dev->driver->driver_features & DRIVER_GEM))
1099 return -ENODEV;
1100
1101 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1102 if (obj == NULL)
1103 return -EBADF;
1104
1105 offset = args->offset;
1106
1107 down_write(&current->mm->mmap_sem);
1108 addr = do_mmap(obj->filp, 0, args->size,
1109 PROT_READ | PROT_WRITE, MAP_SHARED,
1110 args->offset);
1111 up_write(&current->mm->mmap_sem);
Luca Barbieribc9025b2010-02-09 05:49:12 +00001112 drm_gem_object_unreference_unlocked(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001113 if (IS_ERR((void *)addr))
1114 return addr;
1115
1116 args->addr_ptr = (uint64_t) addr;
1117
1118 return 0;
1119}
1120
Jesse Barnesde151cf2008-11-12 10:03:55 -08001121/**
1122 * i915_gem_fault - fault a page into the GTT
1123 * vma: VMA in question
1124 * vmf: fault info
1125 *
1126 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1127 * from userspace. The fault handler takes care of binding the object to
1128 * the GTT (if needed), allocating and programming a fence register (again,
1129 * only if needed based on whether the old reg is still valid or the object
1130 * is tiled) and inserting a new PTE into the faulting process.
1131 *
1132 * Note that the faulting process may involve evicting existing objects
1133 * from the GTT and/or fence registers to make room. So performance may
1134 * suffer if the GTT working set is large or there are few fence registers
1135 * left.
1136 */
1137int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1138{
1139 struct drm_gem_object *obj = vma->vm_private_data;
1140 struct drm_device *dev = obj->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001142 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001143 pgoff_t page_offset;
1144 unsigned long pfn;
1145 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001146 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001147
1148 /* We don't use vmf->pgoff since that has the fake offset */
1149 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1150 PAGE_SHIFT;
1151
1152 /* Now bind it into the GTT if needed */
1153 mutex_lock(&dev->struct_mutex);
1154 if (!obj_priv->gtt_space) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001155 ret = i915_gem_object_bind_to_gtt(obj, 0);
Chris Wilsonc7150892009-09-23 00:43:56 +01001156 if (ret)
1157 goto unlock;
Kristian Høgsberg07f4f3e2009-05-27 14:37:28 -04001158
Jesse Barnes14b60392009-05-20 16:47:08 -04001159 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001160
1161 ret = i915_gem_object_set_to_gtt_domain(obj, write);
Chris Wilsonc7150892009-09-23 00:43:56 +01001162 if (ret)
1163 goto unlock;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001164 }
1165
1166 /* Need a new fence register? */
Eric Anholta09ba7f2009-08-29 12:49:51 -07001167 if (obj_priv->tiling_mode != I915_TILING_NONE) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001168 ret = i915_gem_object_get_fence_reg(obj);
Chris Wilsonc7150892009-09-23 00:43:56 +01001169 if (ret)
1170 goto unlock;
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001171 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001172
1173 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1174 page_offset;
1175
1176 /* Finally, remap it using the new GTT offset */
1177 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
Chris Wilsonc7150892009-09-23 00:43:56 +01001178unlock:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001179 mutex_unlock(&dev->struct_mutex);
1180
1181 switch (ret) {
Chris Wilsonc7150892009-09-23 00:43:56 +01001182 case 0:
1183 case -ERESTARTSYS:
1184 return VM_FAULT_NOPAGE;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001185 case -ENOMEM:
1186 case -EAGAIN:
1187 return VM_FAULT_OOM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001188 default:
Chris Wilsonc7150892009-09-23 00:43:56 +01001189 return VM_FAULT_SIGBUS;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001190 }
1191}
1192
1193/**
1194 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1195 * @obj: obj in question
1196 *
1197 * GEM memory mapping works by handing back to userspace a fake mmap offset
1198 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1199 * up the object based on the offset and sets up the various memory mapping
1200 * structures.
1201 *
1202 * This routine allocates and attaches a fake offset for @obj.
1203 */
1204static int
1205i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1206{
1207 struct drm_device *dev = obj->dev;
1208 struct drm_gem_mm *mm = dev->mm_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001209 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001210 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001211 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001212 int ret = 0;
1213
1214 /* Set the object up for mmap'ing */
1215 list = &obj->map_list;
Eric Anholt9a298b22009-03-24 12:23:04 -07001216 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001217 if (!list->map)
1218 return -ENOMEM;
1219
1220 map = list->map;
1221 map->type = _DRM_GEM;
1222 map->size = obj->size;
1223 map->handle = obj;
1224
1225 /* Get a DRM GEM mmap offset allocated... */
1226 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1227 obj->size / PAGE_SIZE, 0, 0);
1228 if (!list->file_offset_node) {
1229 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1230 ret = -ENOMEM;
1231 goto out_free_list;
1232 }
1233
1234 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1235 obj->size / PAGE_SIZE, 0);
1236 if (!list->file_offset_node) {
1237 ret = -ENOMEM;
1238 goto out_free_list;
1239 }
1240
1241 list->hash.key = list->file_offset_node->start;
1242 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1243 DRM_ERROR("failed to add to map hash\n");
Chris Wilson5618ca62009-12-02 15:15:30 +00001244 ret = -ENOMEM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001245 goto out_free_mm;
1246 }
1247
1248 /* By now we should be all set, any drm_mmap request on the offset
1249 * below will get to our mmap & fault handler */
1250 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1251
1252 return 0;
1253
1254out_free_mm:
1255 drm_mm_put_block(list->file_offset_node);
1256out_free_list:
Eric Anholt9a298b22009-03-24 12:23:04 -07001257 kfree(list->map);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001258
1259 return ret;
1260}
1261
Chris Wilson901782b2009-07-10 08:18:50 +01001262/**
1263 * i915_gem_release_mmap - remove physical page mappings
1264 * @obj: obj in question
1265 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001266 * Preserve the reservation of the mmapping with the DRM core code, but
Chris Wilson901782b2009-07-10 08:18:50 +01001267 * relinquish ownership of the pages back to the system.
1268 *
1269 * It is vital that we remove the page mapping if we have mapped a tiled
1270 * object through the GTT and then lose the fence register due to
1271 * resource pressure. Similarly if the object has been moved out of the
1272 * aperture, than pages mapped into userspace must be revoked. Removing the
1273 * mapping will then trigger a page fault on the next user access, allowing
1274 * fixup by i915_gem_fault().
1275 */
Eric Anholtd05ca302009-07-10 13:02:26 -07001276void
Chris Wilson901782b2009-07-10 08:18:50 +01001277i915_gem_release_mmap(struct drm_gem_object *obj)
1278{
1279 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001280 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson901782b2009-07-10 08:18:50 +01001281
1282 if (dev->dev_mapping)
1283 unmap_mapping_range(dev->dev_mapping,
1284 obj_priv->mmap_offset, obj->size, 1);
1285}
1286
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001287static void
1288i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1289{
1290 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001292 struct drm_gem_mm *mm = dev->mm_private;
1293 struct drm_map_list *list;
1294
1295 list = &obj->map_list;
1296 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1297
1298 if (list->file_offset_node) {
1299 drm_mm_put_block(list->file_offset_node);
1300 list->file_offset_node = NULL;
1301 }
1302
1303 if (list->map) {
Eric Anholt9a298b22009-03-24 12:23:04 -07001304 kfree(list->map);
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001305 list->map = NULL;
1306 }
1307
1308 obj_priv->mmap_offset = 0;
1309}
1310
Jesse Barnesde151cf2008-11-12 10:03:55 -08001311/**
1312 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1313 * @obj: object to check
1314 *
1315 * Return the required GTT alignment for an object, taking into account
1316 * potential fence register mapping if needed.
1317 */
1318static uint32_t
1319i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1320{
1321 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001323 int start, i;
1324
1325 /*
1326 * Minimum alignment is 4k (GTT page size), but might be greater
1327 * if a fence register is needed for the object.
1328 */
1329 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1330 return 4096;
1331
1332 /*
1333 * Previous chips need to be aligned to the size of the smallest
1334 * fence register that can contain the object.
1335 */
1336 if (IS_I9XX(dev))
1337 start = 1024*1024;
1338 else
1339 start = 512*1024;
1340
1341 for (i = start; i < obj->size; i <<= 1)
1342 ;
1343
1344 return i;
1345}
1346
1347/**
1348 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1349 * @dev: DRM device
1350 * @data: GTT mapping ioctl data
1351 * @file_priv: GEM object info
1352 *
1353 * Simply returns the fake offset to userspace so it can mmap it.
1354 * The mmap call will end up in drm_gem_mmap(), which will set things
1355 * up so we can get faults in the handler above.
1356 *
1357 * The fault handler will take care of binding the object into the GTT
1358 * (since it may have been evicted to make room for something), allocating
1359 * a fence register, and mapping the appropriate aperture address into
1360 * userspace.
1361 */
1362int
1363i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1364 struct drm_file *file_priv)
1365{
1366 struct drm_i915_gem_mmap_gtt *args = data;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 struct drm_gem_object *obj;
1369 struct drm_i915_gem_object *obj_priv;
1370 int ret;
1371
1372 if (!(dev->driver->driver_features & DRIVER_GEM))
1373 return -ENODEV;
1374
1375 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1376 if (obj == NULL)
1377 return -EBADF;
1378
1379 mutex_lock(&dev->struct_mutex);
1380
Daniel Vetter23010e42010-03-08 13:35:02 +01001381 obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001382
Chris Wilsonab182822009-09-22 18:46:17 +01001383 if (obj_priv->madv != I915_MADV_WILLNEED) {
1384 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1385 drm_gem_object_unreference(obj);
1386 mutex_unlock(&dev->struct_mutex);
1387 return -EINVAL;
1388 }
1389
1390
Jesse Barnesde151cf2008-11-12 10:03:55 -08001391 if (!obj_priv->mmap_offset) {
1392 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001393 if (ret) {
1394 drm_gem_object_unreference(obj);
1395 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001396 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001397 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001398 }
1399
1400 args->offset = obj_priv->mmap_offset;
1401
Jesse Barnesde151cf2008-11-12 10:03:55 -08001402 /*
1403 * Pull it into the GTT so that we have a page list (makes the
1404 * initial fault faster and any subsequent flushing possible).
1405 */
1406 if (!obj_priv->agp_mem) {
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001407 ret = i915_gem_object_bind_to_gtt(obj, 0);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001408 if (ret) {
1409 drm_gem_object_unreference(obj);
1410 mutex_unlock(&dev->struct_mutex);
1411 return ret;
1412 }
Jesse Barnes14b60392009-05-20 16:47:08 -04001413 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001414 }
1415
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1418
1419 return 0;
1420}
1421
Ben Gamari6911a9b2009-04-02 11:24:54 -07001422void
Eric Anholt856fa192009-03-19 14:10:50 -07001423i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001424{
Daniel Vetter23010e42010-03-08 13:35:02 +01001425 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001426 int page_count = obj->size / PAGE_SIZE;
1427 int i;
1428
Eric Anholt856fa192009-03-19 14:10:50 -07001429 BUG_ON(obj_priv->pages_refcount == 0);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001430 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
Eric Anholt856fa192009-03-19 14:10:50 -07001431
1432 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001433 return;
1434
Eric Anholt280b7132009-03-12 16:56:27 -07001435 if (obj_priv->tiling_mode != I915_TILING_NONE)
1436 i915_gem_object_save_bit_17_swizzle(obj);
1437
Chris Wilson3ef94da2009-09-14 16:50:29 +01001438 if (obj_priv->madv == I915_MADV_DONTNEED)
Chris Wilson13a05fd2009-09-20 23:03:19 +01001439 obj_priv->dirty = 0;
Chris Wilson3ef94da2009-09-14 16:50:29 +01001440
1441 for (i = 0; i < page_count; i++) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01001442 if (obj_priv->dirty)
1443 set_page_dirty(obj_priv->pages[i]);
1444
1445 if (obj_priv->madv == I915_MADV_WILLNEED)
Eric Anholt856fa192009-03-19 14:10:50 -07001446 mark_page_accessed(obj_priv->pages[i]);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001447
1448 page_cache_release(obj_priv->pages[i]);
1449 }
Eric Anholt673a3942008-07-30 12:06:12 -07001450 obj_priv->dirty = 0;
1451
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07001452 drm_free_large(obj_priv->pages);
Eric Anholt856fa192009-03-19 14:10:50 -07001453 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001454}
1455
1456static void
Zou Nan hai852835f2010-05-21 09:08:56 +08001457i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1458 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001459{
1460 struct drm_device *dev = obj->dev;
1461 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001462 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Zou Nan hai852835f2010-05-21 09:08:56 +08001463 BUG_ON(ring == NULL);
1464 obj_priv->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001465
1466 /* Add a reference if we're newly entering the active list. */
1467 if (!obj_priv->active) {
1468 drm_gem_object_reference(obj);
1469 obj_priv->active = 1;
1470 }
1471 /* Move from whatever list we were on to the tail of execution. */
Carl Worth5e118f42009-03-20 11:54:25 -07001472 spin_lock(&dev_priv->mm.active_list_lock);
Zou Nan hai852835f2010-05-21 09:08:56 +08001473 list_move_tail(&obj_priv->list, &ring->active_list);
Carl Worth5e118f42009-03-20 11:54:25 -07001474 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001475 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001476}
1477
Eric Anholtce44b0e2008-11-06 16:00:31 -08001478static void
1479i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1480{
1481 struct drm_device *dev = obj->dev;
1482 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001484
1485 BUG_ON(!obj_priv->active);
1486 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1487 obj_priv->last_rendering_seqno = 0;
1488}
Eric Anholt673a3942008-07-30 12:06:12 -07001489
Chris Wilson963b4832009-09-20 23:03:54 +01001490/* Immediately discard the backing storage */
1491static void
1492i915_gem_object_truncate(struct drm_gem_object *obj)
1493{
Daniel Vetter23010e42010-03-08 13:35:02 +01001494 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001495 struct inode *inode;
Chris Wilson963b4832009-09-20 23:03:54 +01001496
Chris Wilsonbb6baf72009-09-22 14:24:13 +01001497 inode = obj->filp->f_path.dentry->d_inode;
1498 if (inode->i_op->truncate)
1499 inode->i_op->truncate (inode);
1500
1501 obj_priv->madv = __I915_MADV_PURGED;
Chris Wilson963b4832009-09-20 23:03:54 +01001502}
1503
1504static inline int
1505i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1506{
1507 return obj_priv->madv == I915_MADV_DONTNEED;
1508}
1509
Eric Anholt673a3942008-07-30 12:06:12 -07001510static void
1511i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1512{
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001515 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001516
1517 i915_verify_inactive(dev, __FILE__, __LINE__);
1518 if (obj_priv->pin_count != 0)
1519 list_del_init(&obj_priv->list);
1520 else
1521 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1522
Daniel Vetter99fcb762010-02-07 16:20:18 +01001523 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1524
Eric Anholtce44b0e2008-11-06 16:00:31 -08001525 obj_priv->last_rendering_seqno = 0;
Zou Nan hai852835f2010-05-21 09:08:56 +08001526 obj_priv->ring = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001527 if (obj_priv->active) {
1528 obj_priv->active = 0;
1529 drm_gem_object_unreference(obj);
1530 }
1531 i915_verify_inactive(dev, __FILE__, __LINE__);
1532}
1533
Daniel Vetter63560392010-02-19 11:51:59 +01001534static void
1535i915_gem_process_flushing_list(struct drm_device *dev,
Zou Nan hai852835f2010-05-21 09:08:56 +08001536 uint32_t flush_domains, uint32_t seqno,
1537 struct intel_ring_buffer *ring)
Daniel Vetter63560392010-02-19 11:51:59 +01001538{
1539 drm_i915_private_t *dev_priv = dev->dev_private;
1540 struct drm_i915_gem_object *obj_priv, *next;
1541
1542 list_for_each_entry_safe(obj_priv, next,
1543 &dev_priv->mm.gpu_write_list,
1544 gpu_write_list) {
Daniel Vettera8089e82010-04-09 19:05:09 +00001545 struct drm_gem_object *obj = &obj_priv->base;
Daniel Vetter63560392010-02-19 11:51:59 +01001546
1547 if ((obj->write_domain & flush_domains) ==
Zou Nan hai852835f2010-05-21 09:08:56 +08001548 obj->write_domain &&
1549 obj_priv->ring->ring_flag == ring->ring_flag) {
Daniel Vetter63560392010-02-19 11:51:59 +01001550 uint32_t old_write_domain = obj->write_domain;
1551
1552 obj->write_domain = 0;
1553 list_del_init(&obj_priv->gpu_write_list);
Zou Nan hai852835f2010-05-21 09:08:56 +08001554 i915_gem_object_move_to_active(obj, seqno, ring);
Daniel Vetter63560392010-02-19 11:51:59 +01001555
1556 /* update the fence lru list */
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001557 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1558 struct drm_i915_fence_reg *reg =
1559 &dev_priv->fence_regs[obj_priv->fence_reg];
1560 list_move_tail(&reg->lru_list,
Daniel Vetter63560392010-02-19 11:51:59 +01001561 &dev_priv->mm.fence_list);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02001562 }
Daniel Vetter63560392010-02-19 11:51:59 +01001563
1564 trace_i915_gem_object_change_domain(obj,
1565 obj->read_domains,
1566 old_write_domain);
1567 }
1568 }
1569}
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001570
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001571uint32_t
Eric Anholtb9624422009-06-03 07:27:35 +00001572i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
Zou Nan hai852835f2010-05-21 09:08:56 +08001573 uint32_t flush_domains, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001574{
1575 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00001576 struct drm_i915_file_private *i915_file_priv = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001577 struct drm_i915_gem_request *request;
1578 uint32_t seqno;
1579 int was_empty;
Eric Anholt673a3942008-07-30 12:06:12 -07001580
Eric Anholtb9624422009-06-03 07:27:35 +00001581 if (file_priv != NULL)
1582 i915_file_priv = file_priv->driver_priv;
1583
Eric Anholt9a298b22009-03-24 12:23:04 -07001584 request = kzalloc(sizeof(*request), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07001585 if (request == NULL)
1586 return 0;
1587
Zou Nan hai852835f2010-05-21 09:08:56 +08001588 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001589
1590 request->seqno = seqno;
Zou Nan hai852835f2010-05-21 09:08:56 +08001591 request->ring = ring;
Eric Anholt673a3942008-07-30 12:06:12 -07001592 request->emitted_jiffies = jiffies;
Zou Nan hai852835f2010-05-21 09:08:56 +08001593 was_empty = list_empty(&ring->request_list);
1594 list_add_tail(&request->list, &ring->request_list);
1595
Eric Anholtb9624422009-06-03 07:27:35 +00001596 if (i915_file_priv) {
1597 list_add_tail(&request->client_list,
1598 &i915_file_priv->mm.request_list);
1599 } else {
1600 INIT_LIST_HEAD(&request->client_list);
1601 }
Eric Anholt673a3942008-07-30 12:06:12 -07001602
Eric Anholtce44b0e2008-11-06 16:00:31 -08001603 /* Associate any objects on the flushing list matching the write
1604 * domain we're flushing with our flush.
1605 */
Daniel Vetter63560392010-02-19 11:51:59 +01001606 if (flush_domains != 0)
Zou Nan hai852835f2010-05-21 09:08:56 +08001607 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001608
Ben Gamarif65d9422009-09-14 17:48:44 -04001609 if (!dev_priv->mm.suspended) {
1610 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1611 if (was_empty)
1612 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1613 }
Eric Anholt673a3942008-07-30 12:06:12 -07001614 return seqno;
1615}
1616
1617/**
1618 * Command execution barrier
1619 *
1620 * Ensures that all commands in the ring are finished
1621 * before signalling the CPU
1622 */
Eric Anholt3043c602008-10-02 12:24:47 -07001623static uint32_t
Zou Nan hai852835f2010-05-21 09:08:56 +08001624i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001625{
Eric Anholt673a3942008-07-30 12:06:12 -07001626 uint32_t flush_domains = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001627
1628 /* The sampler always gets flushed on i965 (sigh) */
1629 if (IS_I965G(dev))
1630 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
Zou Nan hai852835f2010-05-21 09:08:56 +08001631
1632 ring->flush(dev, ring,
1633 I915_GEM_DOMAIN_COMMAND, flush_domains);
Eric Anholt673a3942008-07-30 12:06:12 -07001634 return flush_domains;
1635}
1636
1637/**
1638 * Moves buffers associated only with the given active seqno from the active
1639 * to inactive list, potentially freeing them.
1640 */
1641static void
1642i915_gem_retire_request(struct drm_device *dev,
1643 struct drm_i915_gem_request *request)
1644{
1645 drm_i915_private_t *dev_priv = dev->dev_private;
1646
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001647 trace_i915_gem_request_retire(dev, request->seqno);
1648
Eric Anholt673a3942008-07-30 12:06:12 -07001649 /* Move any buffers on the active list that are no longer referenced
1650 * by the ringbuffer to the flushing/inactive lists as appropriate.
1651 */
Carl Worth5e118f42009-03-20 11:54:25 -07001652 spin_lock(&dev_priv->mm.active_list_lock);
Zou Nan hai852835f2010-05-21 09:08:56 +08001653 while (!list_empty(&request->ring->active_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001654 struct drm_gem_object *obj;
1655 struct drm_i915_gem_object *obj_priv;
1656
Zou Nan hai852835f2010-05-21 09:08:56 +08001657 obj_priv = list_first_entry(&request->ring->active_list,
Eric Anholt673a3942008-07-30 12:06:12 -07001658 struct drm_i915_gem_object,
1659 list);
Daniel Vettera8089e82010-04-09 19:05:09 +00001660 obj = &obj_priv->base;
Eric Anholt673a3942008-07-30 12:06:12 -07001661
1662 /* If the seqno being retired doesn't match the oldest in the
1663 * list, then the oldest in the list must still be newer than
1664 * this seqno.
1665 */
1666 if (obj_priv->last_rendering_seqno != request->seqno)
Carl Worth5e118f42009-03-20 11:54:25 -07001667 goto out;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001668
Eric Anholt673a3942008-07-30 12:06:12 -07001669#if WATCH_LRU
1670 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1671 __func__, request->seqno, obj);
1672#endif
1673
Eric Anholtce44b0e2008-11-06 16:00:31 -08001674 if (obj->write_domain != 0)
1675 i915_gem_object_move_to_flushing(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001676 else {
1677 /* Take a reference on the object so it won't be
1678 * freed while the spinlock is held. The list
1679 * protection for this spinlock is safe when breaking
1680 * the lock like this since the next thing we do
1681 * is just get the head of the list again.
1682 */
1683 drm_gem_object_reference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001684 i915_gem_object_move_to_inactive(obj);
Shaohua Li68c84342009-04-08 10:58:23 +08001685 spin_unlock(&dev_priv->mm.active_list_lock);
1686 drm_gem_object_unreference(obj);
1687 spin_lock(&dev_priv->mm.active_list_lock);
1688 }
Eric Anholt673a3942008-07-30 12:06:12 -07001689 }
Carl Worth5e118f42009-03-20 11:54:25 -07001690out:
1691 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001692}
1693
1694/**
1695 * Returns true if seq1 is later than seq2.
1696 */
Ben Gamari22be1722009-09-14 17:48:43 -04001697bool
Eric Anholt673a3942008-07-30 12:06:12 -07001698i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1699{
1700 return (int32_t)(seq1 - seq2) >= 0;
1701}
1702
1703uint32_t
Zou Nan hai852835f2010-05-21 09:08:56 +08001704i915_get_gem_seqno(struct drm_device *dev,
Zou Nan haid1b851f2010-05-21 09:08:57 +08001705 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001706{
Zou Nan hai852835f2010-05-21 09:08:56 +08001707 return ring->get_gem_seqno(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001708}
1709
1710/**
1711 * This function clears the request list as sequence numbers are passed.
1712 */
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001713static void
1714i915_gem_retire_requests_ring(struct drm_device *dev,
1715 struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001716{
1717 drm_i915_private_t *dev_priv = dev->dev_private;
1718 uint32_t seqno;
1719
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001720 if (!ring->status_page.page_addr
Zou Nan hai852835f2010-05-21 09:08:56 +08001721 || list_empty(&ring->request_list))
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001722 return;
1723
Zou Nan hai852835f2010-05-21 09:08:56 +08001724 seqno = i915_get_gem_seqno(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001725
Zou Nan hai852835f2010-05-21 09:08:56 +08001726 while (!list_empty(&ring->request_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001727 struct drm_i915_gem_request *request;
1728 uint32_t retiring_seqno;
1729
Zou Nan hai852835f2010-05-21 09:08:56 +08001730 request = list_first_entry(&ring->request_list,
Eric Anholt673a3942008-07-30 12:06:12 -07001731 struct drm_i915_gem_request,
1732 list);
1733 retiring_seqno = request->seqno;
1734
1735 if (i915_seqno_passed(seqno, retiring_seqno) ||
Ben Gamariba1234d2009-09-14 17:48:47 -04001736 atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07001737 i915_gem_retire_request(dev, request);
1738
1739 list_del(&request->list);
Eric Anholtb9624422009-06-03 07:27:35 +00001740 list_del(&request->client_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07001741 kfree(request);
Eric Anholt673a3942008-07-30 12:06:12 -07001742 } else
1743 break;
1744 }
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001745
1746 if (unlikely (dev_priv->trace_irq_seqno &&
1747 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001748
1749 ring->user_irq_put(dev, ring);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01001750 dev_priv->trace_irq_seqno = 0;
1751 }
Eric Anholt673a3942008-07-30 12:06:12 -07001752}
1753
1754void
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001755i915_gem_retire_requests(struct drm_device *dev)
1756{
1757 drm_i915_private_t *dev_priv = dev->dev_private;
1758
Chris Wilsonbe726152010-07-23 23:18:50 +01001759 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1760 struct drm_i915_gem_object *obj_priv, *tmp;
1761
1762 /* We must be careful that during unbind() we do not
1763 * accidentally infinitely recurse into retire requests.
1764 * Currently:
1765 * retire -> free -> unbind -> wait -> retire_ring
1766 */
1767 list_for_each_entry_safe(obj_priv, tmp,
1768 &dev_priv->mm.deferred_free_list,
1769 list)
1770 i915_gem_free_object_tail(&obj_priv->base);
1771 }
1772
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001773 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1774 if (HAS_BSD(dev))
1775 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1776}
1777
1778void
Eric Anholt673a3942008-07-30 12:06:12 -07001779i915_gem_retire_work_handler(struct work_struct *work)
1780{
1781 drm_i915_private_t *dev_priv;
1782 struct drm_device *dev;
1783
1784 dev_priv = container_of(work, drm_i915_private_t,
1785 mm.retire_work.work);
1786 dev = dev_priv->dev;
1787
1788 mutex_lock(&dev->struct_mutex);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001789 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08001790
Keith Packard6dbe2772008-10-14 21:41:13 -07001791 if (!dev_priv->mm.suspended &&
Zou Nan haid1b851f2010-05-21 09:08:57 +08001792 (!list_empty(&dev_priv->render_ring.request_list) ||
1793 (HAS_BSD(dev) &&
1794 !list_empty(&dev_priv->bsd_ring.request_list))))
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07001795 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
Eric Anholt673a3942008-07-30 12:06:12 -07001796 mutex_unlock(&dev->struct_mutex);
1797}
1798
Daniel Vetter5a5a0c62009-09-15 22:57:36 +02001799int
Zou Nan hai852835f2010-05-21 09:08:56 +08001800i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1801 int interruptible, struct intel_ring_buffer *ring)
Eric Anholt673a3942008-07-30 12:06:12 -07001802{
1803 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001804 u32 ier;
Eric Anholt673a3942008-07-30 12:06:12 -07001805 int ret = 0;
1806
1807 BUG_ON(seqno == 0);
1808
Ben Gamariba1234d2009-09-14 17:48:47 -04001809 if (atomic_read(&dev_priv->mm.wedged))
Ben Gamariffed1d02009-09-14 17:48:41 -04001810 return -EIO;
1811
Zou Nan hai852835f2010-05-21 09:08:56 +08001812 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001813 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001814 ier = I915_READ(DEIER) | I915_READ(GTIER);
1815 else
1816 ier = I915_READ(IER);
Jesse Barnes802c7eb2009-05-05 16:03:48 -07001817 if (!ier) {
1818 DRM_ERROR("something (likely vbetool) disabled "
1819 "interrupts, re-enabling\n");
1820 i915_driver_irq_preinstall(dev);
1821 i915_driver_irq_postinstall(dev);
1822 }
1823
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001824 trace_i915_gem_request_wait_begin(dev, seqno);
1825
Zou Nan hai852835f2010-05-21 09:08:56 +08001826 ring->waiting_gem_seqno = seqno;
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001827 ring->user_irq_get(dev, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001828 if (interruptible)
Zou Nan hai852835f2010-05-21 09:08:56 +08001829 ret = wait_event_interruptible(ring->irq_queue,
1830 i915_seqno_passed(
1831 ring->get_gem_seqno(dev, ring), seqno)
1832 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001833 else
Zou Nan hai852835f2010-05-21 09:08:56 +08001834 wait_event(ring->irq_queue,
1835 i915_seqno_passed(
1836 ring->get_gem_seqno(dev, ring), seqno)
1837 || atomic_read(&dev_priv->mm.wedged));
Daniel Vetter48764bf2009-09-15 22:57:32 +02001838
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001839 ring->user_irq_put(dev, ring);
Zou Nan hai852835f2010-05-21 09:08:56 +08001840 ring->waiting_gem_seqno = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01001841
1842 trace_i915_gem_request_wait_end(dev, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07001843 }
Ben Gamariba1234d2009-09-14 17:48:47 -04001844 if (atomic_read(&dev_priv->mm.wedged))
Eric Anholt673a3942008-07-30 12:06:12 -07001845 ret = -EIO;
1846
1847 if (ret && ret != -ERESTARTSYS)
1848 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
Zou Nan hai852835f2010-05-21 09:08:56 +08001849 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
Eric Anholt673a3942008-07-30 12:06:12 -07001850
1851 /* Directly dispatch request retiring. While we have the work queue
1852 * to handle this, the waiter on a request often wants an associated
1853 * buffer to have made it to the inactive list, and we would need
1854 * a separate wait queue to handle that.
1855 */
1856 if (ret == 0)
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001857 i915_gem_retire_requests_ring(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001858
1859 return ret;
1860}
1861
Daniel Vetter48764bf2009-09-15 22:57:32 +02001862/**
1863 * Waits for a sequence number to be signaled, and cleans up the
1864 * request and object lists appropriately for that event.
1865 */
1866static int
Zou Nan hai852835f2010-05-21 09:08:56 +08001867i915_wait_request(struct drm_device *dev, uint32_t seqno,
1868 struct intel_ring_buffer *ring)
Daniel Vetter48764bf2009-09-15 22:57:32 +02001869{
Zou Nan hai852835f2010-05-21 09:08:56 +08001870 return i915_do_wait_request(dev, seqno, 1, ring);
Daniel Vetter48764bf2009-09-15 22:57:32 +02001871}
1872
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001873static void
1874i915_gem_flush(struct drm_device *dev,
1875 uint32_t invalidate_domains,
1876 uint32_t flush_domains)
1877{
1878 drm_i915_private_t *dev_priv = dev->dev_private;
1879 if (flush_domains & I915_GEM_DOMAIN_CPU)
1880 drm_agp_chipset_flush(dev);
1881 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1882 invalidate_domains,
1883 flush_domains);
Zou Nan haid1b851f2010-05-21 09:08:57 +08001884
1885 if (HAS_BSD(dev))
1886 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1887 invalidate_domains,
1888 flush_domains);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08001889}
1890
Zou Nan hai852835f2010-05-21 09:08:56 +08001891static void
1892i915_gem_flush_ring(struct drm_device *dev,
1893 uint32_t invalidate_domains,
1894 uint32_t flush_domains,
1895 struct intel_ring_buffer *ring)
1896{
1897 if (flush_domains & I915_GEM_DOMAIN_CPU)
1898 drm_agp_chipset_flush(dev);
1899 ring->flush(dev, ring,
1900 invalidate_domains,
1901 flush_domains);
1902}
1903
Eric Anholt673a3942008-07-30 12:06:12 -07001904/**
1905 * Ensures that all rendering to the object has completed and the object is
1906 * safe to unbind from the GTT or access from the CPU.
1907 */
1908static int
1909i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1910{
1911 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01001912 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001913 int ret;
1914
Eric Anholte47c68e2008-11-14 13:35:19 -08001915 /* This function only exists to support waiting for existing rendering,
1916 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001917 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001918 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001919
1920 /* If there is rendering queued on the buffer being evicted, wait for
1921 * it.
1922 */
1923 if (obj_priv->active) {
1924#if WATCH_BUF
1925 DRM_INFO("%s: object %p wait for seqno %08x\n",
1926 __func__, obj, obj_priv->last_rendering_seqno);
1927#endif
Zou Nan hai852835f2010-05-21 09:08:56 +08001928 ret = i915_wait_request(dev,
1929 obj_priv->last_rendering_seqno, obj_priv->ring);
Eric Anholt673a3942008-07-30 12:06:12 -07001930 if (ret != 0)
1931 return ret;
1932 }
1933
1934 return 0;
1935}
1936
1937/**
1938 * Unbinds an object from the GTT aperture.
1939 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001940int
Eric Anholt673a3942008-07-30 12:06:12 -07001941i915_gem_object_unbind(struct drm_gem_object *obj)
1942{
1943 struct drm_device *dev = obj->dev;
Daniel Vetter4a87b8c2010-02-19 11:51:57 +01001944 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01001945 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001946 int ret = 0;
1947
1948#if WATCH_BUF
1949 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1950 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1951#endif
1952 if (obj_priv->gtt_space == NULL)
1953 return 0;
1954
1955 if (obj_priv->pin_count != 0) {
1956 DRM_ERROR("Attempting to unbind pinned buffer\n");
1957 return -EINVAL;
1958 }
1959
Eric Anholt5323fd02009-09-09 11:50:45 -07001960 /* blow away mappings if mapped through GTT */
1961 i915_gem_release_mmap(obj);
1962
Eric Anholt673a3942008-07-30 12:06:12 -07001963 /* Move the object to the CPU domain to ensure that
1964 * any possible CPU writes while it's not in the GTT
1965 * are flushed when we go to remap it. This will
1966 * also ensure that all pending GPU writes are finished
1967 * before we unbind.
1968 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001969 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07001970 if (ret) {
Eric Anholte47c68e2008-11-14 13:35:19 -08001971 if (ret != -ERESTARTSYS)
1972 DRM_ERROR("set_domain failed: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07001973 return ret;
1974 }
1975
Eric Anholt5323fd02009-09-09 11:50:45 -07001976 BUG_ON(obj_priv->active);
1977
Daniel Vetter96b47b62009-12-15 17:50:00 +01001978 /* release the fence reg _after_ flushing */
1979 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1980 i915_gem_clear_fence_reg(obj);
1981
Eric Anholt673a3942008-07-30 12:06:12 -07001982 if (obj_priv->agp_mem != NULL) {
1983 drm_unbind_agp(obj_priv->agp_mem);
1984 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1985 obj_priv->agp_mem = NULL;
1986 }
1987
Eric Anholt856fa192009-03-19 14:10:50 -07001988 i915_gem_object_put_pages(obj);
Chris Wilsona32808c2009-09-20 21:29:47 +01001989 BUG_ON(obj_priv->pages_refcount);
Eric Anholt673a3942008-07-30 12:06:12 -07001990
1991 if (obj_priv->gtt_space) {
1992 atomic_dec(&dev->gtt_count);
1993 atomic_sub(obj->size, &dev->gtt_memory);
1994
1995 drm_mm_put_block(obj_priv->gtt_space);
1996 obj_priv->gtt_space = NULL;
1997 }
1998
1999 /* Remove ourselves from the LRU list if present. */
Daniel Vetter4a87b8c2010-02-19 11:51:57 +01002000 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07002001 if (!list_empty(&obj_priv->list))
2002 list_del_init(&obj_priv->list);
Daniel Vetter4a87b8c2010-02-19 11:51:57 +01002003 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07002004
Chris Wilson963b4832009-09-20 23:03:54 +01002005 if (i915_gem_object_is_purgeable(obj_priv))
2006 i915_gem_object_truncate(obj);
2007
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002008 trace_i915_gem_object_unbind(obj);
2009
Eric Anholt673a3942008-07-30 12:06:12 -07002010 return 0;
2011}
2012
Chris Wilson07f73f62009-09-14 16:50:30 +01002013static struct drm_gem_object *
2014i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2015{
2016 drm_i915_private_t *dev_priv = dev->dev_private;
2017 struct drm_i915_gem_object *obj_priv;
2018 struct drm_gem_object *best = NULL;
2019 struct drm_gem_object *first = NULL;
2020
2021 /* Try to find the smallest clean object */
2022 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
Daniel Vettera8089e82010-04-09 19:05:09 +00002023 struct drm_gem_object *obj = &obj_priv->base;
Chris Wilson07f73f62009-09-14 16:50:30 +01002024 if (obj->size >= min_size) {
Chris Wilson963b4832009-09-20 23:03:54 +01002025 if ((!obj_priv->dirty ||
2026 i915_gem_object_is_purgeable(obj_priv)) &&
Chris Wilson07f73f62009-09-14 16:50:30 +01002027 (!best || obj->size < best->size)) {
2028 best = obj;
2029 if (best->size == min_size)
2030 return best;
2031 }
2032 if (!first)
2033 first = obj;
2034 }
2035 }
2036
2037 return best ? best : first;
2038}
2039
Eric Anholt673a3942008-07-30 12:06:12 -07002040static int
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002041i915_gpu_idle(struct drm_device *dev)
2042{
2043 drm_i915_private_t *dev_priv = dev->dev_private;
2044 bool lists_empty;
Zou Nan haid1b851f2010-05-21 09:08:57 +08002045 uint32_t seqno1, seqno2;
Zou Nan hai852835f2010-05-21 09:08:56 +08002046 int ret;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002047
2048 spin_lock(&dev_priv->mm.active_list_lock);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002049 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2050 list_empty(&dev_priv->render_ring.active_list) &&
2051 (!HAS_BSD(dev) ||
2052 list_empty(&dev_priv->bsd_ring.active_list)));
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002053 spin_unlock(&dev_priv->mm.active_list_lock);
2054
2055 if (lists_empty)
2056 return 0;
2057
2058 /* Flush everything onto the inactive list. */
2059 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002060 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
Zou Nan hai852835f2010-05-21 09:08:56 +08002061 &dev_priv->render_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002062 if (seqno1 == 0)
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002063 return -ENOMEM;
Zou Nan haid1b851f2010-05-21 09:08:57 +08002064 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2065
2066 if (HAS_BSD(dev)) {
2067 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2068 &dev_priv->bsd_ring);
2069 if (seqno2 == 0)
2070 return -ENOMEM;
2071
2072 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2073 if (ret)
2074 return ret;
2075 }
2076
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002077
Zou Nan hai852835f2010-05-21 09:08:56 +08002078 return ret;
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002079}
2080
2081static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002082i915_gem_evict_everything(struct drm_device *dev)
2083{
2084 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson07f73f62009-09-14 16:50:30 +01002085 int ret;
2086 bool lists_empty;
2087
Chris Wilson07f73f62009-09-14 16:50:30 +01002088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
Zou Nan haid1b851f2010-05-21 09:08:57 +08002091 list_empty(&dev_priv->render_ring.active_list) &&
2092 (!HAS_BSD(dev)
2093 || list_empty(&dev_priv->bsd_ring.active_list)));
Chris Wilson07f73f62009-09-14 16:50:30 +01002094 spin_unlock(&dev_priv->mm.active_list_lock);
2095
Chris Wilson97311292009-09-21 00:22:34 +01002096 if (lists_empty)
Chris Wilson07f73f62009-09-14 16:50:30 +01002097 return -ENOSPC;
Chris Wilson07f73f62009-09-14 16:50:30 +01002098
2099 /* Flush everything (on to the inactive lists) and evict */
Daniel Vetter4df2faf2010-02-19 11:52:00 +01002100 ret = i915_gpu_idle(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01002101 if (ret)
2102 return ret;
2103
Daniel Vetter99fcb762010-02-07 16:20:18 +01002104 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2105
Chris Wilsonab5ee572009-09-20 19:25:47 +01002106 ret = i915_gem_evict_from_inactive_list(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01002107 if (ret)
2108 return ret;
2109
2110 spin_lock(&dev_priv->mm.active_list_lock);
2111 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112 list_empty(&dev_priv->mm.flushing_list) &&
Zou Nan haid1b851f2010-05-21 09:08:57 +08002113 list_empty(&dev_priv->render_ring.active_list) &&
2114 (!HAS_BSD(dev)
2115 || list_empty(&dev_priv->bsd_ring.active_list)));
Chris Wilson07f73f62009-09-14 16:50:30 +01002116 spin_unlock(&dev_priv->mm.active_list_lock);
2117 BUG_ON(!lists_empty);
2118
Eric Anholt673a3942008-07-30 12:06:12 -07002119 return 0;
2120}
2121
2122static int
Chris Wilson07f73f62009-09-14 16:50:30 +01002123i915_gem_evict_something(struct drm_device *dev, int min_size)
Eric Anholt673a3942008-07-30 12:06:12 -07002124{
2125 drm_i915_private_t *dev_priv = dev->dev_private;
2126 struct drm_gem_object *obj;
Chris Wilson07f73f62009-09-14 16:50:30 +01002127 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002128
Zou Nan hai852835f2010-05-21 09:08:56 +08002129 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
Zou Nan haid1b851f2010-05-21 09:08:57 +08002130 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
Eric Anholt673a3942008-07-30 12:06:12 -07002131 for (;;) {
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01002132 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08002133
Eric Anholt673a3942008-07-30 12:06:12 -07002134 /* If there's an inactive buffer available now, grab it
2135 * and be done.
2136 */
Chris Wilson07f73f62009-09-14 16:50:30 +01002137 obj = i915_gem_find_inactive_object(dev, min_size);
2138 if (obj) {
2139 struct drm_i915_gem_object *obj_priv;
2140
Eric Anholt673a3942008-07-30 12:06:12 -07002141#if WATCH_LRU
2142 DRM_INFO("%s: evicting %p\n", __func__, obj);
2143#endif
Daniel Vetter23010e42010-03-08 13:35:02 +01002144 obj_priv = to_intel_bo(obj);
Chris Wilson07f73f62009-09-14 16:50:30 +01002145 BUG_ON(obj_priv->pin_count != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07002146 BUG_ON(obj_priv->active);
2147
2148 /* Wait on the rendering and unbind the buffer. */
Chris Wilson07f73f62009-09-14 16:50:30 +01002149 return i915_gem_object_unbind(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002150 }
2151
2152 /* If we didn't get anything, but the ring is still processing
Chris Wilson07f73f62009-09-14 16:50:30 +01002153 * things, wait for the next to finish and hopefully leave us
2154 * a buffer to evict.
Eric Anholt673a3942008-07-30 12:06:12 -07002155 */
Zou Nan hai852835f2010-05-21 09:08:56 +08002156 if (!list_empty(&render_ring->request_list)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002157 struct drm_i915_gem_request *request;
2158
Zou Nan hai852835f2010-05-21 09:08:56 +08002159 request = list_first_entry(&render_ring->request_list,
Eric Anholt673a3942008-07-30 12:06:12 -07002160 struct drm_i915_gem_request,
2161 list);
2162
Zou Nan hai852835f2010-05-21 09:08:56 +08002163 ret = i915_wait_request(dev,
2164 request->seqno, request->ring);
Eric Anholt673a3942008-07-30 12:06:12 -07002165 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002166 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002167
Chris Wilson07f73f62009-09-14 16:50:30 +01002168 continue;
Eric Anholt673a3942008-07-30 12:06:12 -07002169 }
2170
Zou Nan haid1b851f2010-05-21 09:08:57 +08002171 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2172 struct drm_i915_gem_request *request;
2173
2174 request = list_first_entry(&bsd_ring->request_list,
2175 struct drm_i915_gem_request,
2176 list);
2177
2178 ret = i915_wait_request(dev,
2179 request->seqno, request->ring);
2180 if (ret)
2181 return ret;
2182
2183 continue;
2184 }
2185
Eric Anholt673a3942008-07-30 12:06:12 -07002186 /* If we didn't have anything on the request list but there
2187 * are buffers awaiting a flush, emit one and try again.
2188 * When we wait on it, those buffers waiting for that flush
2189 * will get moved to inactive.
2190 */
2191 if (!list_empty(&dev_priv->mm.flushing_list)) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002192 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002193
Chris Wilson9a1e2582009-09-20 20:16:50 +01002194 /* Find an object that we can immediately reuse */
2195 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
Daniel Vettera8089e82010-04-09 19:05:09 +00002196 obj = &obj_priv->base;
Chris Wilson9a1e2582009-09-20 20:16:50 +01002197 if (obj->size >= min_size)
2198 break;
Eric Anholt673a3942008-07-30 12:06:12 -07002199
Chris Wilson9a1e2582009-09-20 20:16:50 +01002200 obj = NULL;
2201 }
Eric Anholt673a3942008-07-30 12:06:12 -07002202
Chris Wilson9a1e2582009-09-20 20:16:50 +01002203 if (obj != NULL) {
2204 uint32_t seqno;
Chris Wilson07f73f62009-09-14 16:50:30 +01002205
Zou Nan hai852835f2010-05-21 09:08:56 +08002206 i915_gem_flush_ring(dev,
Chris Wilson9a1e2582009-09-20 20:16:50 +01002207 obj->write_domain,
Zou Nan hai852835f2010-05-21 09:08:56 +08002208 obj->write_domain,
2209 obj_priv->ring);
2210 seqno = i915_add_request(dev, NULL,
2211 obj->write_domain,
2212 obj_priv->ring);
Chris Wilson9a1e2582009-09-20 20:16:50 +01002213 if (seqno == 0)
2214 return -ENOMEM;
Chris Wilson9a1e2582009-09-20 20:16:50 +01002215 continue;
2216 }
Eric Anholt673a3942008-07-30 12:06:12 -07002217 }
2218
Chris Wilson07f73f62009-09-14 16:50:30 +01002219 /* If we didn't do any of the above, there's no single buffer
2220 * large enough to swap out for the new one, so just evict
2221 * everything and start again. (This should be rare.)
Eric Anholt673a3942008-07-30 12:06:12 -07002222 */
Chris Wilson97311292009-09-21 00:22:34 +01002223 if (!list_empty (&dev_priv->mm.inactive_list))
Chris Wilsonab5ee572009-09-20 19:25:47 +01002224 return i915_gem_evict_from_inactive_list(dev);
Chris Wilson97311292009-09-21 00:22:34 +01002225 else
Chris Wilson07f73f62009-09-14 16:50:30 +01002226 return i915_gem_evict_everything(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002227 }
Keith Packardac94a962008-11-20 23:30:27 -08002228}
2229
Ben Gamari6911a9b2009-04-02 11:24:54 -07002230int
Chris Wilson4bdadb92010-01-27 13:36:32 +00002231i915_gem_object_get_pages(struct drm_gem_object *obj,
2232 gfp_t gfpmask)
Eric Anholt673a3942008-07-30 12:06:12 -07002233{
Daniel Vetter23010e42010-03-08 13:35:02 +01002234 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002235 int page_count, i;
2236 struct address_space *mapping;
2237 struct inode *inode;
2238 struct page *page;
Eric Anholt673a3942008-07-30 12:06:12 -07002239
Daniel Vetter778c3542010-05-13 11:49:44 +02002240 BUG_ON(obj_priv->pages_refcount
2241 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2242
Eric Anholt856fa192009-03-19 14:10:50 -07002243 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002244 return 0;
2245
2246 /* Get the list of pages out of our struct file. They'll be pinned
2247 * at this point until we release them.
2248 */
2249 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07002250 BUG_ON(obj_priv->pages != NULL);
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07002251 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
Eric Anholt856fa192009-03-19 14:10:50 -07002252 if (obj_priv->pages == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002253 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07002254 return -ENOMEM;
2255 }
2256
2257 inode = obj->filp->f_path.dentry->d_inode;
2258 mapping = inode->i_mapping;
2259 for (i = 0; i < page_count; i++) {
Chris Wilson4bdadb92010-01-27 13:36:32 +00002260 page = read_cache_page_gfp(mapping, i,
Linus Torvalds985b8232010-07-02 10:04:42 +10002261 GFP_HIGHUSER |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002262 __GFP_COLD |
Linus Torvaldscd9f0402010-07-18 09:44:37 -07002263 __GFP_RECLAIMABLE |
Chris Wilson4bdadb92010-01-27 13:36:32 +00002264 gfpmask);
Chris Wilson1f2b1012010-03-12 19:52:55 +00002265 if (IS_ERR(page))
2266 goto err_pages;
2267
Eric Anholt856fa192009-03-19 14:10:50 -07002268 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07002269 }
Eric Anholt280b7132009-03-12 16:56:27 -07002270
2271 if (obj_priv->tiling_mode != I915_TILING_NONE)
2272 i915_gem_object_do_bit_17_swizzle(obj);
2273
Eric Anholt673a3942008-07-30 12:06:12 -07002274 return 0;
Chris Wilson1f2b1012010-03-12 19:52:55 +00002275
2276err_pages:
2277 while (i--)
2278 page_cache_release(obj_priv->pages[i]);
2279
2280 drm_free_large(obj_priv->pages);
2281 obj_priv->pages = NULL;
2282 obj_priv->pages_refcount--;
2283 return PTR_ERR(page);
Eric Anholt673a3942008-07-30 12:06:12 -07002284}
2285
Eric Anholt4e901fd2009-10-26 16:44:17 -07002286static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2287{
2288 struct drm_gem_object *obj = reg->obj;
2289 struct drm_device *dev = obj->dev;
2290 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt4e901fd2009-10-26 16:44:17 -07002292 int regnum = obj_priv->fence_reg;
2293 uint64_t val;
2294
2295 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2296 0xfffff000) << 32;
2297 val |= obj_priv->gtt_offset & 0xfffff000;
2298 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2299 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2300
2301 if (obj_priv->tiling_mode == I915_TILING_Y)
2302 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2303 val |= I965_FENCE_REG_VALID;
2304
2305 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2306}
2307
Jesse Barnesde151cf2008-11-12 10:03:55 -08002308static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2309{
2310 struct drm_gem_object *obj = reg->obj;
2311 struct drm_device *dev = obj->dev;
2312 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002313 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002314 int regnum = obj_priv->fence_reg;
2315 uint64_t val;
2316
2317 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2318 0xfffff000) << 32;
2319 val |= obj_priv->gtt_offset & 0xfffff000;
2320 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2321 if (obj_priv->tiling_mode == I915_TILING_Y)
2322 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2323 val |= I965_FENCE_REG_VALID;
2324
2325 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2326}
2327
2328static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2329{
2330 struct drm_gem_object *obj = reg->obj;
2331 struct drm_device *dev = obj->dev;
2332 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002333 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002334 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08002335 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07002336 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002337 uint32_t pitch_val;
2338
2339 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2340 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08002341 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002342 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002343 return;
2344 }
2345
Jesse Barnes0f973f22009-01-26 17:10:45 -08002346 if (obj_priv->tiling_mode == I915_TILING_Y &&
2347 HAS_128_BYTE_Y_TILING(dev))
2348 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002349 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08002350 tile_width = 512;
2351
2352 /* Note: pitch better be a power of two tile widths */
2353 pitch_val = obj_priv->stride / tile_width;
2354 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002355
Daniel Vetterc36a2a62010-04-17 15:12:03 +02002356 if (obj_priv->tiling_mode == I915_TILING_Y &&
2357 HAS_128_BYTE_Y_TILING(dev))
2358 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2359 else
2360 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2361
Jesse Barnesde151cf2008-11-12 10:03:55 -08002362 val = obj_priv->gtt_offset;
2363 if (obj_priv->tiling_mode == I915_TILING_Y)
2364 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2365 val |= I915_FENCE_SIZE_BITS(obj->size);
2366 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2367 val |= I830_FENCE_REG_VALID;
2368
Eric Anholtdc529a42009-03-10 22:34:49 -07002369 if (regnum < 8)
2370 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2371 else
2372 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2373 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002374}
2375
2376static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2377{
2378 struct drm_gem_object *obj = reg->obj;
2379 struct drm_device *dev = obj->dev;
2380 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002381 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002382 int regnum = obj_priv->fence_reg;
2383 uint32_t val;
2384 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002385 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002386
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002387 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002388 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002389 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002390 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002391 return;
2392 }
2393
Eric Anholte76a16d2009-05-26 17:44:56 -07002394 pitch_val = obj_priv->stride / 128;
2395 pitch_val = ffs(pitch_val) - 1;
2396 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2397
Jesse Barnesde151cf2008-11-12 10:03:55 -08002398 val = obj_priv->gtt_offset;
2399 if (obj_priv->tiling_mode == I915_TILING_Y)
2400 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002401 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2402 WARN_ON(fence_size_bits & ~0x00000f00);
2403 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002404 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2405 val |= I830_FENCE_REG_VALID;
2406
2407 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002408}
2409
Daniel Vetterae3db242010-02-19 11:51:58 +01002410static int i915_find_fence_reg(struct drm_device *dev)
2411{
2412 struct drm_i915_fence_reg *reg = NULL;
2413 struct drm_i915_gem_object *obj_priv = NULL;
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 struct drm_gem_object *obj = NULL;
2416 int i, avail, ret;
2417
2418 /* First try to find a free reg */
2419 avail = 0;
2420 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2421 reg = &dev_priv->fence_regs[i];
2422 if (!reg->obj)
2423 return i;
2424
Daniel Vetter23010e42010-03-08 13:35:02 +01002425 obj_priv = to_intel_bo(reg->obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002426 if (!obj_priv->pin_count)
2427 avail++;
2428 }
2429
2430 if (avail == 0)
2431 return -ENOSPC;
2432
2433 /* None available, try to steal one or wait for a user to finish */
2434 i = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002435 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2436 lru_list) {
2437 obj = reg->obj;
2438 obj_priv = to_intel_bo(obj);
Daniel Vetterae3db242010-02-19 11:51:58 +01002439
2440 if (obj_priv->pin_count)
2441 continue;
2442
2443 /* found one! */
2444 i = obj_priv->fence_reg;
2445 break;
2446 }
2447
2448 BUG_ON(i == I915_FENCE_REG_NONE);
2449
2450 /* We only have a reference on obj from the active list. put_fence_reg
2451 * might drop that one, causing a use-after-free in it. So hold a
2452 * private reference to obj like the other callers of put_fence_reg
2453 * (set_tiling ioctl) do. */
2454 drm_gem_object_reference(obj);
2455 ret = i915_gem_object_put_fence_reg(obj);
2456 drm_gem_object_unreference(obj);
2457 if (ret != 0)
2458 return ret;
2459
2460 return i;
2461}
2462
Jesse Barnesde151cf2008-11-12 10:03:55 -08002463/**
2464 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2465 * @obj: object to map through a fence reg
2466 *
2467 * When mapping objects through the GTT, userspace wants to be able to write
2468 * to them without having to worry about swizzling if the object is tiled.
2469 *
2470 * This function walks the fence regs looking for a free one for @obj,
2471 * stealing one if it can't find any.
2472 *
2473 * It then sets up the reg based on the object's properties: address, pitch
2474 * and tiling format.
2475 */
Chris Wilson8c4b8c32009-06-17 22:08:52 +01002476int
2477i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002478{
2479 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002480 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002481 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002482 struct drm_i915_fence_reg *reg = NULL;
Daniel Vetterae3db242010-02-19 11:51:58 +01002483 int ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002484
Eric Anholta09ba7f2009-08-29 12:49:51 -07002485 /* Just update our place in the LRU if our fence is getting used. */
2486 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002487 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2488 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002489 return 0;
2490 }
2491
Jesse Barnesde151cf2008-11-12 10:03:55 -08002492 switch (obj_priv->tiling_mode) {
2493 case I915_TILING_NONE:
2494 WARN(1, "allocating a fence for non-tiled object?\n");
2495 break;
2496 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002497 if (!obj_priv->stride)
2498 return -EINVAL;
2499 WARN((obj_priv->stride & (512 - 1)),
2500 "object 0x%08x is X tiled but has non-512B pitch\n",
2501 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002502 break;
2503 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002504 if (!obj_priv->stride)
2505 return -EINVAL;
2506 WARN((obj_priv->stride & (128 - 1)),
2507 "object 0x%08x is Y tiled but has non-128B pitch\n",
2508 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002509 break;
2510 }
2511
Daniel Vetterae3db242010-02-19 11:51:58 +01002512 ret = i915_find_fence_reg(dev);
2513 if (ret < 0)
2514 return ret;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002515
Daniel Vetterae3db242010-02-19 11:51:58 +01002516 obj_priv->fence_reg = ret;
2517 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002518 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07002519
Jesse Barnesde151cf2008-11-12 10:03:55 -08002520 reg->obj = obj;
2521
Eric Anholt4e901fd2009-10-26 16:44:17 -07002522 if (IS_GEN6(dev))
2523 sandybridge_write_fence_reg(reg);
2524 else if (IS_I965G(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08002525 i965_write_fence_reg(reg);
2526 else if (IS_I9XX(dev))
2527 i915_write_fence_reg(reg);
2528 else
2529 i830_write_fence_reg(reg);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002530
Daniel Vetterae3db242010-02-19 11:51:58 +01002531 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2532 obj_priv->tiling_mode);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002533
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002534 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002535}
2536
2537/**
2538 * i915_gem_clear_fence_reg - clear out fence register info
2539 * @obj: object to clear
2540 *
2541 * Zeroes out the fence register itself and clears out the associated
2542 * data structures in dev_priv and obj_priv.
2543 */
2544static void
2545i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2546{
2547 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002548 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002549 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002550 struct drm_i915_fence_reg *reg =
2551 &dev_priv->fence_regs[obj_priv->fence_reg];
Jesse Barnesde151cf2008-11-12 10:03:55 -08002552
Eric Anholt4e901fd2009-10-26 16:44:17 -07002553 if (IS_GEN6(dev)) {
2554 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2555 (obj_priv->fence_reg * 8), 0);
2556 } else if (IS_I965G(dev)) {
Jesse Barnesde151cf2008-11-12 10:03:55 -08002557 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Eric Anholt4e901fd2009-10-26 16:44:17 -07002558 } else {
Eric Anholtdc529a42009-03-10 22:34:49 -07002559 uint32_t fence_reg;
2560
2561 if (obj_priv->fence_reg < 8)
2562 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2563 else
2564 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2565 8) * 4;
2566
2567 I915_WRITE(fence_reg, 0);
2568 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002569
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002570 reg->obj = NULL;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002571 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Daniel Vetter007cc8a2010-04-28 11:02:31 +02002572 list_del_init(&reg->lru_list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002573}
2574
Eric Anholt673a3942008-07-30 12:06:12 -07002575/**
Chris Wilson52dc7d32009-06-06 09:46:01 +01002576 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577 * to the buffer to finish, and then resets the fence register.
2578 * @obj: tiled object holding a fence register.
2579 *
2580 * Zeroes out the fence register itself and clears out the associated
2581 * data structures in dev_priv and obj_priv.
2582 */
2583int
2584i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2585{
2586 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01002587 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002588
2589 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2590 return 0;
2591
Daniel Vetter10ae9bd2010-02-01 13:59:17 +01002592 /* If we've changed tiling, GTT-mappings of the object
2593 * need to re-fault to ensure that the correct fence register
2594 * setup is in place.
2595 */
2596 i915_gem_release_mmap(obj);
2597
Chris Wilson52dc7d32009-06-06 09:46:01 +01002598 /* On the i915, GPU access to tiled buffers is via a fence,
2599 * therefore we must wait for any outstanding access to complete
2600 * before clearing the fence.
2601 */
2602 if (!IS_I965G(dev)) {
2603 int ret;
2604
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002605 ret = i915_gem_object_flush_gpu_write_domain(obj);
2606 if (ret != 0)
2607 return ret;
2608
Chris Wilson52dc7d32009-06-06 09:46:01 +01002609 ret = i915_gem_object_wait_rendering(obj);
2610 if (ret != 0)
2611 return ret;
2612 }
2613
Daniel Vetter4a726612010-02-01 13:59:16 +01002614 i915_gem_object_flush_gtt_write_domain(obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +01002615 i915_gem_clear_fence_reg (obj);
2616
2617 return 0;
2618}
2619
2620/**
Eric Anholt673a3942008-07-30 12:06:12 -07002621 * Finds free space in the GTT aperture and binds the object there.
2622 */
2623static int
2624i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2625{
2626 struct drm_device *dev = obj->dev;
2627 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01002628 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002629 struct drm_mm_node *free_space;
Chris Wilson4bdadb92010-01-27 13:36:32 +00002630 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
Chris Wilson07f73f62009-09-14 16:50:30 +01002631 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002632
Chris Wilsonbb6baf72009-09-22 14:24:13 +01002633 if (obj_priv->madv != I915_MADV_WILLNEED) {
Chris Wilson3ef94da2009-09-14 16:50:29 +01002634 DRM_ERROR("Attempting to bind a purgeable object\n");
2635 return -EINVAL;
2636 }
2637
Eric Anholt673a3942008-07-30 12:06:12 -07002638 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002639 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002640 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002641 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2642 return -EINVAL;
2643 }
2644
Chris Wilson654fc602010-05-27 13:18:21 +01002645 /* If the object is bigger than the entire aperture, reject it early
2646 * before evicting everything in a vain attempt to find space.
2647 */
2648 if (obj->size > dev->gtt_total) {
2649 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2650 return -E2BIG;
2651 }
2652
Eric Anholt673a3942008-07-30 12:06:12 -07002653 search_free:
2654 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2655 obj->size, alignment, 0);
2656 if (free_space != NULL) {
2657 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2658 alignment);
Daniel Vetterdb3307a2010-07-02 15:02:12 +01002659 if (obj_priv->gtt_space != NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002660 obj_priv->gtt_offset = obj_priv->gtt_space->start;
Eric Anholt673a3942008-07-30 12:06:12 -07002661 }
2662 if (obj_priv->gtt_space == NULL) {
2663 /* If the gtt is empty and we're still having trouble
2664 * fitting our object in, we're out of memory.
2665 */
2666#if WATCH_LRU
2667 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2668#endif
Chris Wilson07f73f62009-09-14 16:50:30 +01002669 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002670 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07002671 return ret;
Chris Wilson97311292009-09-21 00:22:34 +01002672
Eric Anholt673a3942008-07-30 12:06:12 -07002673 goto search_free;
2674 }
2675
2676#if WATCH_BUF
Krzysztof Halasacfd43c02009-06-20 00:31:28 +02002677 DRM_INFO("Binding object of size %zd at 0x%08x\n",
Eric Anholt673a3942008-07-30 12:06:12 -07002678 obj->size, obj_priv->gtt_offset);
2679#endif
Chris Wilson4bdadb92010-01-27 13:36:32 +00002680 ret = i915_gem_object_get_pages(obj, gfpmask);
Eric Anholt673a3942008-07-30 12:06:12 -07002681 if (ret) {
2682 drm_mm_put_block(obj_priv->gtt_space);
2683 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002684
2685 if (ret == -ENOMEM) {
2686 /* first try to clear up some space from the GTT */
2687 ret = i915_gem_evict_something(dev, obj->size);
2688 if (ret) {
Chris Wilson07f73f62009-09-14 16:50:30 +01002689 /* now try to shrink everyone else */
Chris Wilson4bdadb92010-01-27 13:36:32 +00002690 if (gfpmask) {
2691 gfpmask = 0;
2692 goto search_free;
Chris Wilson07f73f62009-09-14 16:50:30 +01002693 }
2694
2695 return ret;
2696 }
2697
2698 goto search_free;
2699 }
2700
Eric Anholt673a3942008-07-30 12:06:12 -07002701 return ret;
2702 }
2703
Eric Anholt673a3942008-07-30 12:06:12 -07002704 /* Create an AGP memory structure pointing at our pages, and bind it
2705 * into the GTT.
2706 */
2707 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002708 obj_priv->pages,
Chris Wilson07f73f62009-09-14 16:50:30 +01002709 obj->size >> PAGE_SHIFT,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002710 obj_priv->gtt_offset,
2711 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002712 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002713 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002714 drm_mm_put_block(obj_priv->gtt_space);
2715 obj_priv->gtt_space = NULL;
Chris Wilson07f73f62009-09-14 16:50:30 +01002716
2717 ret = i915_gem_evict_something(dev, obj->size);
Chris Wilson97311292009-09-21 00:22:34 +01002718 if (ret)
Chris Wilson07f73f62009-09-14 16:50:30 +01002719 return ret;
Chris Wilson07f73f62009-09-14 16:50:30 +01002720
2721 goto search_free;
Eric Anholt673a3942008-07-30 12:06:12 -07002722 }
2723 atomic_inc(&dev->gtt_count);
2724 atomic_add(obj->size, &dev->gtt_memory);
2725
2726 /* Assert that the object is not currently in any GPU domain. As it
2727 * wasn't in the GTT, there shouldn't be any way it could have been in
2728 * a GPU cache
2729 */
Chris Wilson21d509e2009-06-06 09:46:02 +01002730 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2731 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
Eric Anholt673a3942008-07-30 12:06:12 -07002732
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002733 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2734
Eric Anholt673a3942008-07-30 12:06:12 -07002735 return 0;
2736}
2737
2738void
2739i915_gem_clflush_object(struct drm_gem_object *obj)
2740{
Daniel Vetter23010e42010-03-08 13:35:02 +01002741 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002742
2743 /* If we don't have a page list set up, then we're not pinned
2744 * to GPU, and we can ignore the cache flush because it'll happen
2745 * again at bind time.
2746 */
Eric Anholt856fa192009-03-19 14:10:50 -07002747 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002748 return;
2749
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002750 trace_i915_gem_object_clflush(obj);
Eric Anholtcfa16a02009-05-26 18:46:16 -07002751
Eric Anholt856fa192009-03-19 14:10:50 -07002752 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002753}
2754
Eric Anholte47c68e2008-11-14 13:35:19 -08002755/** Flushes any GPU write domain for the object if it's dirty. */
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002756static int
Eric Anholte47c68e2008-11-14 13:35:19 -08002757i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2758{
2759 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002760 uint32_t old_write_domain;
Zou Nan hai852835f2010-05-21 09:08:56 +08002761 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002762
2763 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002764 return 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002765
2766 /* Queue the GPU write cache flushing we need. */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002767 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002768 i915_gem_flush(dev, 0, obj->write_domain);
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002769 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2770 return -ENOMEM;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002771
2772 trace_i915_gem_object_change_domain(obj,
2773 obj->read_domains,
2774 old_write_domain);
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002775 return 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002776}
2777
2778/** Flushes the GTT write domain for the object if it's dirty. */
2779static void
2780i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2781{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002782 uint32_t old_write_domain;
2783
Eric Anholte47c68e2008-11-14 13:35:19 -08002784 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2785 return;
2786
2787 /* No actual flushing is required for the GTT write domain. Writes
2788 * to it immediately go to main memory as far as we know, so there's
2789 * no chipset flush. It also doesn't land in render cache.
2790 */
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002791 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002792 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002793
2794 trace_i915_gem_object_change_domain(obj,
2795 obj->read_domains,
2796 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002797}
2798
2799/** Flushes the CPU write domain for the object if it's dirty. */
2800static void
2801i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2802{
2803 struct drm_device *dev = obj->dev;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002804 uint32_t old_write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002805
2806 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2807 return;
2808
2809 i915_gem_clflush_object(obj);
2810 drm_agp_chipset_flush(dev);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002811 old_write_domain = obj->write_domain;
Eric Anholte47c68e2008-11-14 13:35:19 -08002812 obj->write_domain = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002813
2814 trace_i915_gem_object_change_domain(obj,
2815 obj->read_domains,
2816 old_write_domain);
Eric Anholte47c68e2008-11-14 13:35:19 -08002817}
2818
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002819int
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002820i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2821{
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002822 int ret = 0;
2823
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002824 switch (obj->write_domain) {
2825 case I915_GEM_DOMAIN_GTT:
2826 i915_gem_object_flush_gtt_write_domain(obj);
2827 break;
2828 case I915_GEM_DOMAIN_CPU:
2829 i915_gem_object_flush_cpu_write_domain(obj);
2830 break;
2831 default:
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002832 ret = i915_gem_object_flush_gpu_write_domain(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002833 break;
2834 }
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002835
2836 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002837}
2838
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002839/**
2840 * Moves a single object to the GTT read, and possibly write domain.
2841 *
2842 * This function returns when the move is complete, including waiting on
2843 * flushes to occur.
2844 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002845int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002846i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2847{
Daniel Vetter23010e42010-03-08 13:35:02 +01002848 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002849 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002850 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002851
Eric Anholt02354392008-11-26 13:58:13 -08002852 /* Not valid to be called on unbound objects. */
2853 if (obj_priv->gtt_space == NULL)
2854 return -EINVAL;
2855
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002856 ret = i915_gem_object_flush_gpu_write_domain(obj);
2857 if (ret != 0)
2858 return ret;
2859
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002860 /* Wait on any GPU rendering and flushing to occur. */
Eric Anholte47c68e2008-11-14 13:35:19 -08002861 ret = i915_gem_object_wait_rendering(obj);
2862 if (ret != 0)
2863 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002864
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002865 old_write_domain = obj->write_domain;
2866 old_read_domains = obj->read_domains;
2867
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002868 /* If we're writing through the GTT domain, then CPU and GPU caches
2869 * will need to be invalidated at next use.
2870 */
2871 if (write)
Eric Anholte47c68e2008-11-14 13:35:19 -08002872 obj->read_domains &= I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002873
Eric Anholte47c68e2008-11-14 13:35:19 -08002874 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002875
2876 /* It should now be out of any other write domains, and we can update
2877 * the domain values for our changes.
2878 */
2879 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2880 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002881 if (write) {
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002882 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002883 obj_priv->dirty = 1;
2884 }
2885
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002886 trace_i915_gem_object_change_domain(obj,
2887 old_read_domains,
2888 old_write_domain);
2889
Eric Anholte47c68e2008-11-14 13:35:19 -08002890 return 0;
2891}
2892
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002893/*
2894 * Prepare buffer for display plane. Use uninterruptible for possible flush
2895 * wait, as in modesetting process we're not supposed to be interrupted.
2896 */
2897int
2898i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2899{
2900 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01002901 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002902 uint32_t old_write_domain, old_read_domains;
2903 int ret;
2904
2905 /* Not valid to be called on unbound objects. */
2906 if (obj_priv->gtt_space == NULL)
2907 return -EINVAL;
2908
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002909 ret = i915_gem_object_flush_gpu_write_domain(obj);
2910 if (ret)
2911 return ret;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002912
2913 /* Wait on any GPU rendering and flushing to occur. */
2914 if (obj_priv->active) {
2915#if WATCH_BUF
2916 DRM_INFO("%s: object %p wait for seqno %08x\n",
2917 __func__, obj, obj_priv->last_rendering_seqno);
2918#endif
Zou Nan hai852835f2010-05-21 09:08:56 +08002919 ret = i915_do_wait_request(dev,
2920 obj_priv->last_rendering_seqno,
2921 0,
2922 obj_priv->ring);
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002923 if (ret != 0)
2924 return ret;
2925 }
2926
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002927 i915_gem_object_flush_cpu_write_domain(obj);
2928
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002929 old_write_domain = obj->write_domain;
2930 old_read_domains = obj->read_domains;
2931
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002932 /* It should now be out of any other write domains, and we can update
2933 * the domain values for our changes.
2934 */
2935 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
Chris Wilsonb118c1e2010-05-27 13:18:14 +01002936 obj->read_domains = I915_GEM_DOMAIN_GTT;
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08002937 obj->write_domain = I915_GEM_DOMAIN_GTT;
2938 obj_priv->dirty = 1;
2939
2940 trace_i915_gem_object_change_domain(obj,
2941 old_read_domains,
2942 old_write_domain);
2943
2944 return 0;
2945}
2946
Eric Anholte47c68e2008-11-14 13:35:19 -08002947/**
2948 * Moves a single object to the CPU read, and possibly write domain.
2949 *
2950 * This function returns when the move is complete, including waiting on
2951 * flushes to occur.
2952 */
2953static int
2954i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2955{
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002956 uint32_t old_write_domain, old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08002957 int ret;
2958
Chris Wilson2dafb1e2010-06-07 14:03:05 +01002959 ret = i915_gem_object_flush_gpu_write_domain(obj);
2960 if (ret)
2961 return ret;
2962
Eric Anholte47c68e2008-11-14 13:35:19 -08002963 /* Wait on any GPU rendering and flushing to occur. */
2964 ret = i915_gem_object_wait_rendering(obj);
2965 if (ret != 0)
2966 return ret;
2967
2968 i915_gem_object_flush_gtt_write_domain(obj);
2969
2970 /* If we have a partially-valid cache of the object in the CPU,
2971 * finish invalidating it and free the per-page flags.
2972 */
2973 i915_gem_object_set_to_full_cpu_read_domain(obj);
2974
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002975 old_write_domain = obj->write_domain;
2976 old_read_domains = obj->read_domains;
2977
Eric Anholte47c68e2008-11-14 13:35:19 -08002978 /* Flush the CPU cache if it's still invalid. */
2979 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2980 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002981
2982 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2983 }
2984
2985 /* It should now be out of any other write domains, and we can update
2986 * the domain values for our changes.
2987 */
2988 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2989
2990 /* If we're writing through the CPU, then the GPU read domains will
2991 * need to be invalidated at next use.
2992 */
2993 if (write) {
2994 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2995 obj->write_domain = I915_GEM_DOMAIN_CPU;
2996 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002997
Chris Wilson1c5d22f2009-08-25 11:15:50 +01002998 trace_i915_gem_object_change_domain(obj,
2999 old_read_domains,
3000 old_write_domain);
3001
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003002 return 0;
3003}
3004
Eric Anholt673a3942008-07-30 12:06:12 -07003005/*
3006 * Set the next domain for the specified object. This
3007 * may not actually perform the necessary flushing/invaliding though,
3008 * as that may want to be batched with other set_domain operations
3009 *
3010 * This is (we hope) the only really tricky part of gem. The goal
3011 * is fairly simple -- track which caches hold bits of the object
3012 * and make sure they remain coherent. A few concrete examples may
3013 * help to explain how it works. For shorthand, we use the notation
3014 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3015 * a pair of read and write domain masks.
3016 *
3017 * Case 1: the batch buffer
3018 *
3019 * 1. Allocated
3020 * 2. Written by CPU
3021 * 3. Mapped to GTT
3022 * 4. Read by GPU
3023 * 5. Unmapped from GTT
3024 * 6. Freed
3025 *
3026 * Let's take these a step at a time
3027 *
3028 * 1. Allocated
3029 * Pages allocated from the kernel may still have
3030 * cache contents, so we set them to (CPU, CPU) always.
3031 * 2. Written by CPU (using pwrite)
3032 * The pwrite function calls set_domain (CPU, CPU) and
3033 * this function does nothing (as nothing changes)
3034 * 3. Mapped by GTT
3035 * This function asserts that the object is not
3036 * currently in any GPU-based read or write domains
3037 * 4. Read by GPU
3038 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3039 * As write_domain is zero, this function adds in the
3040 * current read domains (CPU+COMMAND, 0).
3041 * flush_domains is set to CPU.
3042 * invalidate_domains is set to COMMAND
3043 * clflush is run to get data out of the CPU caches
3044 * then i915_dev_set_domain calls i915_gem_flush to
3045 * emit an MI_FLUSH and drm_agp_chipset_flush
3046 * 5. Unmapped from GTT
3047 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3048 * flush_domains and invalidate_domains end up both zero
3049 * so no flushing/invalidating happens
3050 * 6. Freed
3051 * yay, done
3052 *
3053 * Case 2: The shared render buffer
3054 *
3055 * 1. Allocated
3056 * 2. Mapped to GTT
3057 * 3. Read/written by GPU
3058 * 4. set_domain to (CPU,CPU)
3059 * 5. Read/written by CPU
3060 * 6. Read/written by GPU
3061 *
3062 * 1. Allocated
3063 * Same as last example, (CPU, CPU)
3064 * 2. Mapped to GTT
3065 * Nothing changes (assertions find that it is not in the GPU)
3066 * 3. Read/written by GPU
3067 * execbuffer calls set_domain (RENDER, RENDER)
3068 * flush_domains gets CPU
3069 * invalidate_domains gets GPU
3070 * clflush (obj)
3071 * MI_FLUSH and drm_agp_chipset_flush
3072 * 4. set_domain (CPU, CPU)
3073 * flush_domains gets GPU
3074 * invalidate_domains gets CPU
3075 * wait_rendering (obj) to make sure all drawing is complete.
3076 * This will include an MI_FLUSH to get the data from GPU
3077 * to memory
3078 * clflush (obj) to invalidate the CPU cache
3079 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3080 * 5. Read/written by CPU
3081 * cache lines are loaded and dirtied
3082 * 6. Read written by GPU
3083 * Same as last GPU access
3084 *
3085 * Case 3: The constant buffer
3086 *
3087 * 1. Allocated
3088 * 2. Written by CPU
3089 * 3. Read by GPU
3090 * 4. Updated (written) by CPU again
3091 * 5. Read by GPU
3092 *
3093 * 1. Allocated
3094 * (CPU, CPU)
3095 * 2. Written by CPU
3096 * (CPU, CPU)
3097 * 3. Read by GPU
3098 * (CPU+RENDER, 0)
3099 * flush_domains = CPU
3100 * invalidate_domains = RENDER
3101 * clflush (obj)
3102 * MI_FLUSH
3103 * drm_agp_chipset_flush
3104 * 4. Updated (written) by CPU again
3105 * (CPU, CPU)
3106 * flush_domains = 0 (no previous write domain)
3107 * invalidate_domains = 0 (no new read domains)
3108 * 5. Read by GPU
3109 * (CPU+RENDER, 0)
3110 * flush_domains = CPU
3111 * invalidate_domains = RENDER
3112 * clflush (obj)
3113 * MI_FLUSH
3114 * drm_agp_chipset_flush
3115 */
Keith Packardc0d90822008-11-20 23:11:08 -08003116static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08003117i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07003118{
3119 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01003120 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003121 uint32_t invalidate_domains = 0;
3122 uint32_t flush_domains = 0;
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003123 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003124
Eric Anholt8b0e3782009-02-19 14:40:50 -08003125 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3126 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07003127
Jesse Barnes652c3932009-08-17 13:31:43 -07003128 intel_mark_busy(dev, obj);
3129
Eric Anholt673a3942008-07-30 12:06:12 -07003130#if WATCH_BUF
3131 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3132 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08003133 obj->read_domains, obj->pending_read_domains,
3134 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003135#endif
3136 /*
3137 * If the object isn't moving to a new write domain,
3138 * let the object stay in multiple read domains
3139 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003140 if (obj->pending_write_domain == 0)
3141 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003142 else
3143 obj_priv->dirty = 1;
3144
3145 /*
3146 * Flush the current write domain if
3147 * the new read domains don't match. Invalidate
3148 * any read domains which differ from the old
3149 * write domain
3150 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003151 if (obj->write_domain &&
3152 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07003153 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003154 invalidate_domains |=
3155 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07003156 }
3157 /*
3158 * Invalidate any read caches which may have
3159 * stale data. That is, any new read domains.
3160 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003161 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003162 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3163#if WATCH_BUF
3164 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3165 __func__, flush_domains, invalidate_domains);
3166#endif
Eric Anholt673a3942008-07-30 12:06:12 -07003167 i915_gem_clflush_object(obj);
3168 }
3169
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003170 old_read_domains = obj->read_domains;
3171
Eric Anholtefbeed92009-02-19 14:54:51 -08003172 /* The actual obj->write_domain will be updated with
3173 * pending_write_domain after we emit the accumulated flush for all
3174 * of our domain changes in execbuffers (which clears objects'
3175 * write_domains). So if we have a current write domain that we
3176 * aren't changing, set pending_write_domain to that.
3177 */
3178 if (flush_domains == 0 && obj->pending_write_domain == 0)
3179 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08003180 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07003181
3182 dev->invalidate_domains |= invalidate_domains;
3183 dev->flush_domains |= flush_domains;
3184#if WATCH_BUF
3185 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3186 __func__,
3187 obj->read_domains, obj->write_domain,
3188 dev->invalidate_domains, dev->flush_domains);
3189#endif
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003190
3191 trace_i915_gem_object_change_domain(obj,
3192 old_read_domains,
3193 obj->write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07003194}
3195
3196/**
Eric Anholte47c68e2008-11-14 13:35:19 -08003197 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07003198 *
Eric Anholte47c68e2008-11-14 13:35:19 -08003199 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3200 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3201 */
3202static void
3203i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3204{
Daniel Vetter23010e42010-03-08 13:35:02 +01003205 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003206
3207 if (!obj_priv->page_cpu_valid)
3208 return;
3209
3210 /* If we're partially in the CPU read domain, finish moving it in.
3211 */
3212 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3213 int i;
3214
3215 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3216 if (obj_priv->page_cpu_valid[i])
3217 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07003218 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08003219 }
Eric Anholte47c68e2008-11-14 13:35:19 -08003220 }
3221
3222 /* Free the page_cpu_valid mappings which are now stale, whether
3223 * or not we've got I915_GEM_DOMAIN_CPU.
3224 */
Eric Anholt9a298b22009-03-24 12:23:04 -07003225 kfree(obj_priv->page_cpu_valid);
Eric Anholte47c68e2008-11-14 13:35:19 -08003226 obj_priv->page_cpu_valid = NULL;
3227}
3228
3229/**
3230 * Set the CPU read domain on a range of the object.
3231 *
3232 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3233 * not entirely valid. The page_cpu_valid member of the object flags which
3234 * pages have been flushed, and will be respected by
3235 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3236 * of the whole object.
3237 *
3238 * This function returns when the move is complete, including waiting on
3239 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07003240 */
3241static int
Eric Anholte47c68e2008-11-14 13:35:19 -08003242i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3243 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07003244{
Daniel Vetter23010e42010-03-08 13:35:02 +01003245 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003246 uint32_t old_read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003247 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07003248
Eric Anholte47c68e2008-11-14 13:35:19 -08003249 if (offset == 0 && size == obj->size)
3250 return i915_gem_object_set_to_cpu_domain(obj, 0);
3251
Chris Wilson2dafb1e2010-06-07 14:03:05 +01003252 ret = i915_gem_object_flush_gpu_write_domain(obj);
3253 if (ret)
3254 return ret;
3255
Eric Anholte47c68e2008-11-14 13:35:19 -08003256 /* Wait on any GPU rendering and flushing to occur. */
3257 ret = i915_gem_object_wait_rendering(obj);
3258 if (ret != 0)
3259 return ret;
3260 i915_gem_object_flush_gtt_write_domain(obj);
3261
3262 /* If we're already fully in the CPU read domain, we're done. */
3263 if (obj_priv->page_cpu_valid == NULL &&
3264 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07003265 return 0;
3266
Eric Anholte47c68e2008-11-14 13:35:19 -08003267 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3268 * newly adding I915_GEM_DOMAIN_CPU
3269 */
Eric Anholt673a3942008-07-30 12:06:12 -07003270 if (obj_priv->page_cpu_valid == NULL) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003271 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3272 GFP_KERNEL);
Eric Anholte47c68e2008-11-14 13:35:19 -08003273 if (obj_priv->page_cpu_valid == NULL)
3274 return -ENOMEM;
3275 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3276 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07003277
3278 /* Flush the cache on any pages that are still invalid from the CPU's
3279 * perspective.
3280 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003281 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3282 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07003283 if (obj_priv->page_cpu_valid[i])
3284 continue;
3285
Eric Anholt856fa192009-03-19 14:10:50 -07003286 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07003287
3288 obj_priv->page_cpu_valid[i] = 1;
3289 }
3290
Eric Anholte47c68e2008-11-14 13:35:19 -08003291 /* It should now be out of any other write domains, and we can update
3292 * the domain values for our changes.
3293 */
3294 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3295
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003296 old_read_domains = obj->read_domains;
Eric Anholte47c68e2008-11-14 13:35:19 -08003297 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3298
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003299 trace_i915_gem_object_change_domain(obj,
3300 old_read_domains,
3301 obj->write_domain);
3302
Eric Anholt673a3942008-07-30 12:06:12 -07003303 return 0;
3304}
3305
3306/**
Eric Anholt673a3942008-07-30 12:06:12 -07003307 * Pin an object to the GTT and evaluate the relocations landing in it.
3308 */
3309static int
3310i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3311 struct drm_file *file_priv,
Jesse Barnes76446ca2009-12-17 22:05:42 -05003312 struct drm_i915_gem_exec_object2 *entry,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003313 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07003314{
3315 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07003316 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01003317 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003318 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07003319 void __iomem *reloc_page;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003320 bool need_fence;
3321
3322 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3323 obj_priv->tiling_mode != I915_TILING_NONE;
3324
3325 /* Check fence reg constraints and rebind if necessary */
Chris Wilson808b24d2010-05-27 13:18:15 +01003326 if (need_fence &&
3327 !i915_gem_object_fence_offset_ok(obj,
3328 obj_priv->tiling_mode)) {
3329 ret = i915_gem_object_unbind(obj);
3330 if (ret)
3331 return ret;
3332 }
Eric Anholt673a3942008-07-30 12:06:12 -07003333
3334 /* Choose the GTT offset for our buffer and put it there. */
3335 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3336 if (ret)
3337 return ret;
3338
Jesse Barnes76446ca2009-12-17 22:05:42 -05003339 /*
3340 * Pre-965 chips need a fence register set up in order to
3341 * properly handle blits to/from tiled surfaces.
3342 */
3343 if (need_fence) {
3344 ret = i915_gem_object_get_fence_reg(obj);
3345 if (ret != 0) {
Jesse Barnes76446ca2009-12-17 22:05:42 -05003346 i915_gem_object_unpin(obj);
3347 return ret;
3348 }
3349 }
3350
Eric Anholt673a3942008-07-30 12:06:12 -07003351 entry->offset = obj_priv->gtt_offset;
3352
Eric Anholt673a3942008-07-30 12:06:12 -07003353 /* Apply the relocations, using the GTT aperture to avoid cache
3354 * flushing requirements.
3355 */
3356 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003357 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003358 struct drm_gem_object *target_obj;
3359 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07003360 uint32_t reloc_val, reloc_offset;
3361 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07003362
Eric Anholt673a3942008-07-30 12:06:12 -07003363 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003364 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003365 if (target_obj == NULL) {
3366 i915_gem_object_unpin(obj);
3367 return -EBADF;
3368 }
Daniel Vetter23010e42010-03-08 13:35:02 +01003369 target_obj_priv = to_intel_bo(target_obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003370
Chris Wilson8542a0b2009-09-09 21:15:15 +01003371#if WATCH_RELOC
3372 DRM_INFO("%s: obj %p offset %08x target %d "
3373 "read %08x write %08x gtt %08x "
3374 "presumed %08x delta %08x\n",
3375 __func__,
3376 obj,
3377 (int) reloc->offset,
3378 (int) reloc->target_handle,
3379 (int) reloc->read_domains,
3380 (int) reloc->write_domain,
3381 (int) target_obj_priv->gtt_offset,
3382 (int) reloc->presumed_offset,
3383 reloc->delta);
3384#endif
3385
Eric Anholt673a3942008-07-30 12:06:12 -07003386 /* The target buffer should have appeared before us in the
3387 * exec_object list, so it should have a GTT space bound by now.
3388 */
3389 if (target_obj_priv->gtt_space == NULL) {
3390 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003391 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07003392 drm_gem_object_unreference(target_obj);
3393 i915_gem_object_unpin(obj);
3394 return -EINVAL;
3395 }
3396
Chris Wilson8542a0b2009-09-09 21:15:15 +01003397 /* Validate that the target is in a valid r/w GPU domain */
Daniel Vetter16edd552010-02-19 11:52:02 +01003398 if (reloc->write_domain & (reloc->write_domain - 1)) {
3399 DRM_ERROR("reloc with multiple write domains: "
3400 "obj %p target %d offset %d "
3401 "read %08x write %08x",
3402 obj, reloc->target_handle,
3403 (int) reloc->offset,
3404 reloc->read_domains,
3405 reloc->write_domain);
3406 return -EINVAL;
3407 }
Chris Wilson8542a0b2009-09-09 21:15:15 +01003408 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3409 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3410 DRM_ERROR("reloc with read/write CPU domains: "
3411 "obj %p target %d offset %d "
3412 "read %08x write %08x",
3413 obj, reloc->target_handle,
3414 (int) reloc->offset,
3415 reloc->read_domains,
3416 reloc->write_domain);
3417 drm_gem_object_unreference(target_obj);
3418 i915_gem_object_unpin(obj);
3419 return -EINVAL;
3420 }
3421 if (reloc->write_domain && target_obj->pending_write_domain &&
3422 reloc->write_domain != target_obj->pending_write_domain) {
3423 DRM_ERROR("Write domain conflict: "
3424 "obj %p target %d offset %d "
3425 "new %08x old %08x\n",
3426 obj, reloc->target_handle,
3427 (int) reloc->offset,
3428 reloc->write_domain,
3429 target_obj->pending_write_domain);
3430 drm_gem_object_unreference(target_obj);
3431 i915_gem_object_unpin(obj);
3432 return -EINVAL;
3433 }
3434
3435 target_obj->pending_read_domains |= reloc->read_domains;
3436 target_obj->pending_write_domain |= reloc->write_domain;
3437
3438 /* If the relocation already has the right value in it, no
3439 * more work needs to be done.
3440 */
3441 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3442 drm_gem_object_unreference(target_obj);
3443 continue;
3444 }
3445
3446 /* Check that the relocation address is valid... */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003447 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07003448 DRM_ERROR("Relocation beyond object bounds: "
3449 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003450 obj, reloc->target_handle,
3451 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07003452 drm_gem_object_unreference(target_obj);
3453 i915_gem_object_unpin(obj);
3454 return -EINVAL;
3455 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003456 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07003457 DRM_ERROR("Relocation not 4-byte aligned: "
3458 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003459 obj, reloc->target_handle,
3460 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003461 drm_gem_object_unreference(target_obj);
3462 i915_gem_object_unpin(obj);
3463 return -EINVAL;
3464 }
3465
Chris Wilson8542a0b2009-09-09 21:15:15 +01003466 /* and points to somewhere within the target object. */
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003467 if (reloc->delta >= target_obj->size) {
3468 DRM_ERROR("Relocation beyond target object bounds: "
3469 "obj %p target %d delta %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003470 obj, reloc->target_handle,
Chris Wilsoncd0b9fb2009-09-15 23:23:18 +01003471 (int) reloc->delta, (int) target_obj->size);
Chris Wilson491152b2009-02-11 14:26:32 +00003472 drm_gem_object_unreference(target_obj);
3473 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08003474 return -EINVAL;
3475 }
3476
Eric Anholt2ef7eea2008-11-10 10:53:25 -08003477 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3478 if (ret != 0) {
3479 drm_gem_object_unreference(target_obj);
3480 i915_gem_object_unpin(obj);
3481 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07003482 }
3483
3484 /* Map the page containing the relocation we're going to
3485 * perform.
3486 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003487 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07003488 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3489 (reloc_offset &
3490 ~(PAGE_SIZE - 1)));
Eric Anholt3043c602008-10-02 12:24:47 -07003491 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07003492 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003493 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07003494
3495#if WATCH_BUF
3496 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003497 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07003498 readl(reloc_entry), reloc_val);
3499#endif
3500 writel(reloc_val, reloc_entry);
Keith Packard0839ccb2008-10-30 19:38:48 -07003501 io_mapping_unmap_atomic(reloc_page);
Eric Anholt673a3942008-07-30 12:06:12 -07003502
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003503 /* The updated presumed offset for this entry will be
3504 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07003505 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003506 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003507
3508 drm_gem_object_unreference(target_obj);
3509 }
3510
Eric Anholt673a3942008-07-30 12:06:12 -07003511#if WATCH_BUF
3512 if (0)
3513 i915_gem_dump_object(obj, 128, __func__, ~0);
3514#endif
3515 return 0;
3516}
3517
Eric Anholt673a3942008-07-30 12:06:12 -07003518/* Throttle our rendering by waiting until the ring has completed our requests
3519 * emitted over 20 msec ago.
3520 *
Eric Anholtb9624422009-06-03 07:27:35 +00003521 * Note that if we were to use the current jiffies each time around the loop,
3522 * we wouldn't escape the function with any frames outstanding if the time to
3523 * render a frame was over 20ms.
3524 *
Eric Anholt673a3942008-07-30 12:06:12 -07003525 * This should get us reasonable parallelism between CPU and GPU but also
3526 * relatively low latency when blocking on a particular request to finish.
3527 */
3528static int
3529i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3530{
3531 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3532 int ret = 0;
Eric Anholtb9624422009-06-03 07:27:35 +00003533 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
Eric Anholt673a3942008-07-30 12:06:12 -07003534
3535 mutex_lock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003536 while (!list_empty(&i915_file_priv->mm.request_list)) {
3537 struct drm_i915_gem_request *request;
3538
3539 request = list_first_entry(&i915_file_priv->mm.request_list,
3540 struct drm_i915_gem_request,
3541 client_list);
3542
3543 if (time_after_eq(request->emitted_jiffies, recent_enough))
3544 break;
3545
Zou Nan hai852835f2010-05-21 09:08:56 +08003546 ret = i915_wait_request(dev, request->seqno, request->ring);
Eric Anholtb9624422009-06-03 07:27:35 +00003547 if (ret != 0)
3548 break;
3549 }
Eric Anholt673a3942008-07-30 12:06:12 -07003550 mutex_unlock(&dev->struct_mutex);
Eric Anholtb9624422009-06-03 07:27:35 +00003551
Eric Anholt673a3942008-07-30 12:06:12 -07003552 return ret;
3553}
3554
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003555static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003556i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003557 uint32_t buffer_count,
3558 struct drm_i915_gem_relocation_entry **relocs)
3559{
3560 uint32_t reloc_count = 0, reloc_index = 0, i;
3561 int ret;
3562
3563 *relocs = NULL;
3564 for (i = 0; i < buffer_count; i++) {
3565 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3566 return -EINVAL;
3567 reloc_count += exec_list[i].relocation_count;
3568 }
3569
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003570 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
Jesse Barnes76446ca2009-12-17 22:05:42 -05003571 if (*relocs == NULL) {
3572 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003573 return -ENOMEM;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003574 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003575
3576 for (i = 0; i < buffer_count; i++) {
3577 struct drm_i915_gem_relocation_entry __user *user_relocs;
3578
3579 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3580
3581 ret = copy_from_user(&(*relocs)[reloc_index],
3582 user_relocs,
3583 exec_list[i].relocation_count *
3584 sizeof(**relocs));
3585 if (ret != 0) {
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003586 drm_free_large(*relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003587 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003588 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003589 }
3590
3591 reloc_index += exec_list[i].relocation_count;
3592 }
3593
Florian Mickler2bc43b52009-04-06 22:55:41 +02003594 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003595}
3596
3597static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003598i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003599 uint32_t buffer_count,
3600 struct drm_i915_gem_relocation_entry *relocs)
3601{
3602 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003603 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003604
Chris Wilson93533c22010-01-31 10:40:48 +00003605 if (relocs == NULL)
3606 return 0;
3607
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003608 for (i = 0; i < buffer_count; i++) {
3609 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003610 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003611
3612 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3613
Florian Mickler2bc43b52009-04-06 22:55:41 +02003614 unwritten = copy_to_user(user_relocs,
3615 &relocs[reloc_count],
3616 exec_list[i].relocation_count *
3617 sizeof(*relocs));
3618
3619 if (unwritten) {
3620 ret = -EFAULT;
3621 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003622 }
3623
3624 reloc_count += exec_list[i].relocation_count;
3625 }
3626
Florian Mickler2bc43b52009-04-06 22:55:41 +02003627err:
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07003628 drm_free_large(relocs);
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003629
3630 return ret;
3631}
3632
Chris Wilson83d60792009-06-06 09:45:57 +01003633static int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003634i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
Chris Wilson83d60792009-06-06 09:45:57 +01003635 uint64_t exec_offset)
3636{
3637 uint32_t exec_start, exec_len;
3638
3639 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3640 exec_len = (uint32_t) exec->batch_len;
3641
3642 if ((exec_start | exec_len) & 0x7)
3643 return -EINVAL;
3644
3645 if (!exec_start)
3646 return -EINVAL;
3647
3648 return 0;
3649}
3650
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003651static int
3652i915_gem_wait_for_pending_flip(struct drm_device *dev,
3653 struct drm_gem_object **object_list,
3654 int count)
3655{
3656 drm_i915_private_t *dev_priv = dev->dev_private;
3657 struct drm_i915_gem_object *obj_priv;
3658 DEFINE_WAIT(wait);
3659 int i, ret = 0;
3660
3661 for (;;) {
3662 prepare_to_wait(&dev_priv->pending_flip_queue,
3663 &wait, TASK_INTERRUPTIBLE);
3664 for (i = 0; i < count; i++) {
Daniel Vetter23010e42010-03-08 13:35:02 +01003665 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003666 if (atomic_read(&obj_priv->pending_flip) > 0)
3667 break;
3668 }
3669 if (i == count)
3670 break;
3671
3672 if (!signal_pending(current)) {
3673 mutex_unlock(&dev->struct_mutex);
3674 schedule();
3675 mutex_lock(&dev->struct_mutex);
3676 continue;
3677 }
3678 ret = -ERESTARTSYS;
3679 break;
3680 }
3681 finish_wait(&dev_priv->pending_flip_queue, &wait);
3682
3683 return ret;
3684}
3685
Chris Wilson43b27f42010-07-02 08:57:15 +01003686
Eric Anholt673a3942008-07-30 12:06:12 -07003687int
Jesse Barnes76446ca2009-12-17 22:05:42 -05003688i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3689 struct drm_file *file_priv,
3690 struct drm_i915_gem_execbuffer2 *args,
3691 struct drm_i915_gem_exec_object2 *exec_list)
Eric Anholt673a3942008-07-30 12:06:12 -07003692{
3693 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07003694 struct drm_gem_object **object_list = NULL;
3695 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003696 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003697 struct drm_clip_rect *cliprects = NULL;
Chris Wilson93533c22010-01-31 10:40:48 +00003698 struct drm_i915_gem_relocation_entry *relocs = NULL;
Jesse Barnes76446ca2009-12-17 22:05:42 -05003699 int ret = 0, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003700 uint64_t exec_offset;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003701 uint32_t seqno, flush_domains, reloc_index;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003702 int pin_tries, flips;
Eric Anholt673a3942008-07-30 12:06:12 -07003703
Zou Nan hai852835f2010-05-21 09:08:56 +08003704 struct intel_ring_buffer *ring = NULL;
3705
Eric Anholt673a3942008-07-30 12:06:12 -07003706#if WATCH_EXEC
3707 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3708 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3709#endif
Zou Nan haid1b851f2010-05-21 09:08:57 +08003710 if (args->flags & I915_EXEC_BSD) {
3711 if (!HAS_BSD(dev)) {
3712 DRM_ERROR("execbuf with wrong flag\n");
3713 return -EINVAL;
3714 }
3715 ring = &dev_priv->bsd_ring;
3716 } else {
3717 ring = &dev_priv->render_ring;
3718 }
3719
Eric Anholt673a3942008-07-30 12:06:12 -07003720
Eric Anholt4f481ed2008-09-10 14:22:49 -07003721 if (args->buffer_count < 1) {
3722 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3723 return -EINVAL;
3724 }
Eric Anholtc8e0f932009-11-22 03:49:37 +01003725 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
Jesse Barnes76446ca2009-12-17 22:05:42 -05003726 if (object_list == NULL) {
3727 DRM_ERROR("Failed to allocate object list for %d buffers\n",
Eric Anholt673a3942008-07-30 12:06:12 -07003728 args->buffer_count);
3729 ret = -ENOMEM;
3730 goto pre_mutex_err;
3731 }
Eric Anholt673a3942008-07-30 12:06:12 -07003732
Eric Anholt201361a2009-03-11 12:30:04 -07003733 if (args->num_cliprects != 0) {
Eric Anholt9a298b22009-03-24 12:23:04 -07003734 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3735 GFP_KERNEL);
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003736 if (cliprects == NULL) {
3737 ret = -ENOMEM;
Eric Anholt201361a2009-03-11 12:30:04 -07003738 goto pre_mutex_err;
Owain Ainswortha40e8d32010-02-09 14:25:55 +00003739 }
Eric Anholt201361a2009-03-11 12:30:04 -07003740
3741 ret = copy_from_user(cliprects,
3742 (struct drm_clip_rect __user *)
3743 (uintptr_t) args->cliprects_ptr,
3744 sizeof(*cliprects) * args->num_cliprects);
3745 if (ret != 0) {
3746 DRM_ERROR("copy %d cliprects failed: %d\n",
3747 args->num_cliprects, ret);
3748 goto pre_mutex_err;
3749 }
3750 }
3751
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003752 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3753 &relocs);
3754 if (ret != 0)
3755 goto pre_mutex_err;
3756
Eric Anholt673a3942008-07-30 12:06:12 -07003757 mutex_lock(&dev->struct_mutex);
3758
3759 i915_verify_inactive(dev, __FILE__, __LINE__);
3760
Ben Gamariba1234d2009-09-14 17:48:47 -04003761 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07003762 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003763 ret = -EIO;
3764 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003765 }
3766
3767 if (dev_priv->mm.suspended) {
Eric Anholt673a3942008-07-30 12:06:12 -07003768 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003769 ret = -EBUSY;
3770 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003771 }
3772
Keith Packardac94a962008-11-20 23:30:27 -08003773 /* Look up object handles */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003774 flips = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003775 for (i = 0; i < args->buffer_count; i++) {
3776 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3777 exec_list[i].handle);
3778 if (object_list[i] == NULL) {
3779 DRM_ERROR("Invalid object handle %d at index %d\n",
3780 exec_list[i].handle, i);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003781 /* prevent error path from reading uninitialized data */
3782 args->buffer_count = i + 1;
Eric Anholt673a3942008-07-30 12:06:12 -07003783 ret = -EBADF;
3784 goto err;
3785 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003786
Daniel Vetter23010e42010-03-08 13:35:02 +01003787 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003788 if (obj_priv->in_execbuffer) {
3789 DRM_ERROR("Object %p appears more than once in object list\n",
3790 object_list[i]);
Chris Wilson0ce907f2010-01-23 20:26:35 +00003791 /* prevent error path from reading uninitialized data */
3792 args->buffer_count = i + 1;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003793 ret = -EBADF;
3794 goto err;
3795 }
3796 obj_priv->in_execbuffer = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05003797 flips += atomic_read(&obj_priv->pending_flip);
3798 }
3799
3800 if (flips > 0) {
3801 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3802 args->buffer_count);
3803 if (ret)
3804 goto err;
Keith Packardac94a962008-11-20 23:30:27 -08003805 }
Eric Anholt673a3942008-07-30 12:06:12 -07003806
Keith Packardac94a962008-11-20 23:30:27 -08003807 /* Pin and relocate */
3808 for (pin_tries = 0; ; pin_tries++) {
3809 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003810 reloc_index = 0;
3811
Keith Packardac94a962008-11-20 23:30:27 -08003812 for (i = 0; i < args->buffer_count; i++) {
3813 object_list[i]->pending_read_domains = 0;
3814 object_list[i]->pending_write_domain = 0;
3815 ret = i915_gem_object_pin_and_relocate(object_list[i],
3816 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003817 &exec_list[i],
3818 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003819 if (ret)
3820 break;
3821 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003822 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003823 }
3824 /* success */
3825 if (ret == 0)
3826 break;
3827
3828 /* error other than GTT full, or we've already tried again */
Chris Wilson2939e1f2009-06-06 09:46:03 +01003829 if (ret != -ENOSPC || pin_tries >= 1) {
Chris Wilson07f73f62009-09-14 16:50:30 +01003830 if (ret != -ERESTARTSYS) {
3831 unsigned long long total_size = 0;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003832 int num_fences = 0;
3833 for (i = 0; i < args->buffer_count; i++) {
Chris Wilson43b27f42010-07-02 08:57:15 +01003834 obj_priv = to_intel_bo(object_list[i]);
Chris Wilson3d1cc472010-05-27 13:18:19 +01003835
Chris Wilson07f73f62009-09-14 16:50:30 +01003836 total_size += object_list[i]->size;
Chris Wilson3d1cc472010-05-27 13:18:19 +01003837 num_fences +=
3838 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3839 obj_priv->tiling_mode != I915_TILING_NONE;
3840 }
3841 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
Chris Wilson07f73f62009-09-14 16:50:30 +01003842 pinned+1, args->buffer_count,
Chris Wilson3d1cc472010-05-27 13:18:19 +01003843 total_size, num_fences,
3844 ret);
Chris Wilson07f73f62009-09-14 16:50:30 +01003845 DRM_ERROR("%d objects [%d pinned], "
3846 "%d object bytes [%d pinned], "
3847 "%d/%d gtt bytes\n",
3848 atomic_read(&dev->object_count),
3849 atomic_read(&dev->pin_count),
3850 atomic_read(&dev->object_memory),
3851 atomic_read(&dev->pin_memory),
3852 atomic_read(&dev->gtt_memory),
3853 dev->gtt_total);
3854 }
Eric Anholt673a3942008-07-30 12:06:12 -07003855 goto err;
3856 }
Keith Packardac94a962008-11-20 23:30:27 -08003857
3858 /* unpin all of our buffers */
3859 for (i = 0; i < pinned; i++)
3860 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003861 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003862
3863 /* evict everyone we can from the aperture */
3864 ret = i915_gem_evict_everything(dev);
Chris Wilson07f73f62009-09-14 16:50:30 +01003865 if (ret && ret != -ENOSPC)
Keith Packardac94a962008-11-20 23:30:27 -08003866 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003867 }
3868
3869 /* Set the pending read domains for the batch buffer to COMMAND */
3870 batch_obj = object_list[args->buffer_count-1];
Chris Wilson5f26a2c2009-06-06 09:45:58 +01003871 if (batch_obj->pending_write_domain) {
3872 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3873 ret = -EINVAL;
3874 goto err;
3875 }
3876 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
Eric Anholt673a3942008-07-30 12:06:12 -07003877
Chris Wilson83d60792009-06-06 09:45:57 +01003878 /* Sanity check the batch buffer, prior to moving objects */
3879 exec_offset = exec_list[args->buffer_count - 1].offset;
3880 ret = i915_gem_check_execbuffer (args, exec_offset);
3881 if (ret != 0) {
3882 DRM_ERROR("execbuf with invalid offset/length\n");
3883 goto err;
3884 }
3885
Eric Anholt673a3942008-07-30 12:06:12 -07003886 i915_verify_inactive(dev, __FILE__, __LINE__);
3887
Keith Packard646f0f62008-11-20 23:23:03 -08003888 /* Zero the global flush/invalidate flags. These
3889 * will be modified as new domains are computed
3890 * for each object
3891 */
3892 dev->invalidate_domains = 0;
3893 dev->flush_domains = 0;
3894
Eric Anholt673a3942008-07-30 12:06:12 -07003895 for (i = 0; i < args->buffer_count; i++) {
3896 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003897
Keith Packard646f0f62008-11-20 23:23:03 -08003898 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003899 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003900 }
3901
3902 i915_verify_inactive(dev, __FILE__, __LINE__);
3903
Keith Packard646f0f62008-11-20 23:23:03 -08003904 if (dev->invalidate_domains | dev->flush_domains) {
3905#if WATCH_EXEC
3906 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3907 __func__,
3908 dev->invalidate_domains,
3909 dev->flush_domains);
3910#endif
3911 i915_gem_flush(dev,
3912 dev->invalidate_domains,
3913 dev->flush_domains);
Zou Nan hai852835f2010-05-21 09:08:56 +08003914 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
Eric Anholtb9624422009-06-03 07:27:35 +00003915 (void)i915_add_request(dev, file_priv,
Zou Nan hai852835f2010-05-21 09:08:56 +08003916 dev->flush_domains,
3917 &dev_priv->render_ring);
3918
Zou Nan haid1b851f2010-05-21 09:08:57 +08003919 if (HAS_BSD(dev))
3920 (void)i915_add_request(dev, file_priv,
3921 dev->flush_domains,
3922 &dev_priv->bsd_ring);
Zou Nan hai852835f2010-05-21 09:08:56 +08003923 }
Keith Packard646f0f62008-11-20 23:23:03 -08003924 }
Eric Anholt673a3942008-07-30 12:06:12 -07003925
Eric Anholtefbeed92009-02-19 14:54:51 -08003926 for (i = 0; i < args->buffer_count; i++) {
3927 struct drm_gem_object *obj = object_list[i];
Daniel Vetter23010e42010-03-08 13:35:02 +01003928 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003929 uint32_t old_write_domain = obj->write_domain;
Eric Anholtefbeed92009-02-19 14:54:51 -08003930
3931 obj->write_domain = obj->pending_write_domain;
Daniel Vetter99fcb762010-02-07 16:20:18 +01003932 if (obj->write_domain)
3933 list_move_tail(&obj_priv->gpu_write_list,
3934 &dev_priv->mm.gpu_write_list);
3935 else
3936 list_del_init(&obj_priv->gpu_write_list);
3937
Chris Wilson1c5d22f2009-08-25 11:15:50 +01003938 trace_i915_gem_object_change_domain(obj,
3939 obj->read_domains,
3940 old_write_domain);
Eric Anholtefbeed92009-02-19 14:54:51 -08003941 }
3942
Eric Anholt673a3942008-07-30 12:06:12 -07003943 i915_verify_inactive(dev, __FILE__, __LINE__);
3944
3945#if WATCH_COHERENCY
3946 for (i = 0; i < args->buffer_count; i++) {
3947 i915_gem_object_check_coherency(object_list[i],
3948 exec_list[i].handle);
3949 }
3950#endif
3951
Eric Anholt673a3942008-07-30 12:06:12 -07003952#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003953 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003954 args->batch_len,
3955 __func__,
3956 ~0);
3957#endif
3958
Eric Anholt673a3942008-07-30 12:06:12 -07003959 /* Exec the batchbuffer */
Zou Nan hai852835f2010-05-21 09:08:56 +08003960 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3961 cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003962 if (ret) {
3963 DRM_ERROR("dispatch failed %d\n", ret);
3964 goto err;
3965 }
3966
3967 /*
3968 * Ensure that the commands in the batch buffer are
3969 * finished before the interrupt fires
3970 */
Zou Nan hai852835f2010-05-21 09:08:56 +08003971 flush_domains = i915_retire_commands(dev, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07003972
3973 i915_verify_inactive(dev, __FILE__, __LINE__);
3974
3975 /*
3976 * Get a seqno representing the execution of the current buffer,
3977 * which we can wait on. We would like to mitigate these interrupts,
3978 * likely by only creating seqnos occasionally (so that we have
3979 * *some* interrupts representing completion of buffers that we can
3980 * wait on when trying to clear up gtt space).
3981 */
Zou Nan hai852835f2010-05-21 09:08:56 +08003982 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07003983 BUG_ON(seqno == 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003984 for (i = 0; i < args->buffer_count; i++) {
3985 struct drm_gem_object *obj = object_list[i];
Zou Nan hai852835f2010-05-21 09:08:56 +08003986 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003987
Zou Nan hai852835f2010-05-21 09:08:56 +08003988 i915_gem_object_move_to_active(obj, seqno, ring);
Eric Anholt673a3942008-07-30 12:06:12 -07003989#if WATCH_LRU
3990 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3991#endif
3992 }
3993#if WATCH_LRU
3994 i915_dump_lru(dev, __func__);
3995#endif
3996
3997 i915_verify_inactive(dev, __FILE__, __LINE__);
3998
Eric Anholt673a3942008-07-30 12:06:12 -07003999err:
Julia Lawallaad87df2008-12-21 16:28:47 +01004000 for (i = 0; i < pinned; i++)
4001 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07004002
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05004003 for (i = 0; i < args->buffer_count; i++) {
4004 if (object_list[i]) {
Daniel Vetter23010e42010-03-08 13:35:02 +01004005 obj_priv = to_intel_bo(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05004006 obj_priv->in_execbuffer = false;
4007 }
Julia Lawallaad87df2008-12-21 16:28:47 +01004008 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05004009 }
Julia Lawallaad87df2008-12-21 16:28:47 +01004010
Eric Anholt673a3942008-07-30 12:06:12 -07004011 mutex_unlock(&dev->struct_mutex);
4012
Chris Wilson93533c22010-01-31 10:40:48 +00004013pre_mutex_err:
Eric Anholt40a5f0d2009-03-12 11:23:52 -07004014 /* Copy the updated relocations out regardless of current error
4015 * state. Failure to update the relocs would mean that the next
4016 * time userland calls execbuf, it would do so with presumed offset
4017 * state that didn't match the actual object state.
4018 */
4019 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4020 relocs);
4021 if (ret2 != 0) {
4022 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4023
4024 if (ret == 0)
4025 ret = ret2;
4026 }
4027
Jesse Barnes8e7d2b22009-05-08 16:13:25 -07004028 drm_free_large(object_list);
Eric Anholt9a298b22009-03-24 12:23:04 -07004029 kfree(cliprects);
Eric Anholt673a3942008-07-30 12:06:12 -07004030
4031 return ret;
4032}
4033
Jesse Barnes76446ca2009-12-17 22:05:42 -05004034/*
4035 * Legacy execbuffer just creates an exec2 list from the original exec object
4036 * list array and passes it to the real function.
4037 */
4038int
4039i915_gem_execbuffer(struct drm_device *dev, void *data,
4040 struct drm_file *file_priv)
4041{
4042 struct drm_i915_gem_execbuffer *args = data;
4043 struct drm_i915_gem_execbuffer2 exec2;
4044 struct drm_i915_gem_exec_object *exec_list = NULL;
4045 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4046 int ret, i;
4047
4048#if WATCH_EXEC
4049 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4050 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4051#endif
4052
4053 if (args->buffer_count < 1) {
4054 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4055 return -EINVAL;
4056 }
4057
4058 /* Copy in the exec list from userland */
4059 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4060 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4061 if (exec_list == NULL || exec2_list == NULL) {
4062 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4063 args->buffer_count);
4064 drm_free_large(exec_list);
4065 drm_free_large(exec2_list);
4066 return -ENOMEM;
4067 }
4068 ret = copy_from_user(exec_list,
4069 (struct drm_i915_relocation_entry __user *)
4070 (uintptr_t) args->buffers_ptr,
4071 sizeof(*exec_list) * args->buffer_count);
4072 if (ret != 0) {
4073 DRM_ERROR("copy %d exec entries failed %d\n",
4074 args->buffer_count, ret);
4075 drm_free_large(exec_list);
4076 drm_free_large(exec2_list);
4077 return -EFAULT;
4078 }
4079
4080 for (i = 0; i < args->buffer_count; i++) {
4081 exec2_list[i].handle = exec_list[i].handle;
4082 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4083 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4084 exec2_list[i].alignment = exec_list[i].alignment;
4085 exec2_list[i].offset = exec_list[i].offset;
4086 if (!IS_I965G(dev))
4087 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4088 else
4089 exec2_list[i].flags = 0;
4090 }
4091
4092 exec2.buffers_ptr = args->buffers_ptr;
4093 exec2.buffer_count = args->buffer_count;
4094 exec2.batch_start_offset = args->batch_start_offset;
4095 exec2.batch_len = args->batch_len;
4096 exec2.DR1 = args->DR1;
4097 exec2.DR4 = args->DR4;
4098 exec2.num_cliprects = args->num_cliprects;
4099 exec2.cliprects_ptr = args->cliprects_ptr;
Zou Nan hai852835f2010-05-21 09:08:56 +08004100 exec2.flags = I915_EXEC_RENDER;
Jesse Barnes76446ca2009-12-17 22:05:42 -05004101
4102 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4103 if (!ret) {
4104 /* Copy the new buffer offsets back to the user's exec list. */
4105 for (i = 0; i < args->buffer_count; i++)
4106 exec_list[i].offset = exec2_list[i].offset;
4107 /* ... and back out to userspace */
4108 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4109 (uintptr_t) args->buffers_ptr,
4110 exec_list,
4111 sizeof(*exec_list) * args->buffer_count);
4112 if (ret) {
4113 ret = -EFAULT;
4114 DRM_ERROR("failed to copy %d exec entries "
4115 "back to user (%d)\n",
4116 args->buffer_count, ret);
4117 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004118 }
4119
4120 drm_free_large(exec_list);
4121 drm_free_large(exec2_list);
4122 return ret;
4123}
4124
4125int
4126i915_gem_execbuffer2(struct drm_device *dev, void *data,
4127 struct drm_file *file_priv)
4128{
4129 struct drm_i915_gem_execbuffer2 *args = data;
4130 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4131 int ret;
4132
4133#if WATCH_EXEC
4134 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4135 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4136#endif
4137
4138 if (args->buffer_count < 1) {
4139 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4140 return -EINVAL;
4141 }
4142
4143 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4144 if (exec2_list == NULL) {
4145 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4146 args->buffer_count);
4147 return -ENOMEM;
4148 }
4149 ret = copy_from_user(exec2_list,
4150 (struct drm_i915_relocation_entry __user *)
4151 (uintptr_t) args->buffers_ptr,
4152 sizeof(*exec2_list) * args->buffer_count);
4153 if (ret != 0) {
4154 DRM_ERROR("copy %d exec entries failed %d\n",
4155 args->buffer_count, ret);
4156 drm_free_large(exec2_list);
4157 return -EFAULT;
4158 }
4159
4160 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4161 if (!ret) {
4162 /* Copy the new buffer offsets back to the user's exec list. */
4163 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4164 (uintptr_t) args->buffers_ptr,
4165 exec2_list,
4166 sizeof(*exec2_list) * args->buffer_count);
4167 if (ret) {
4168 ret = -EFAULT;
4169 DRM_ERROR("failed to copy %d exec entries "
4170 "back to user (%d)\n",
4171 args->buffer_count, ret);
4172 }
4173 }
4174
4175 drm_free_large(exec2_list);
4176 return ret;
4177}
4178
Eric Anholt673a3942008-07-30 12:06:12 -07004179int
4180i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4181{
4182 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004183 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004184 int ret;
4185
Daniel Vetter778c3542010-05-13 11:49:44 +02004186 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4187
Eric Anholt673a3942008-07-30 12:06:12 -07004188 i915_verify_inactive(dev, __FILE__, __LINE__);
Chris Wilsonac0c6b52010-05-27 13:18:18 +01004189
4190 if (obj_priv->gtt_space != NULL) {
4191 if (alignment == 0)
4192 alignment = i915_gem_get_gtt_alignment(obj);
4193 if (obj_priv->gtt_offset & (alignment - 1)) {
4194 ret = i915_gem_object_unbind(obj);
4195 if (ret)
4196 return ret;
4197 }
4198 }
4199
Eric Anholt673a3942008-07-30 12:06:12 -07004200 if (obj_priv->gtt_space == NULL) {
4201 ret = i915_gem_object_bind_to_gtt(obj, alignment);
Chris Wilson97311292009-09-21 00:22:34 +01004202 if (ret)
Eric Anholt673a3942008-07-30 12:06:12 -07004203 return ret;
Chris Wilson22c344e2009-02-11 14:26:45 +00004204 }
Jesse Barnes76446ca2009-12-17 22:05:42 -05004205
Eric Anholt673a3942008-07-30 12:06:12 -07004206 obj_priv->pin_count++;
4207
4208 /* If the object is not active and not pending a flush,
4209 * remove it from the inactive list
4210 */
4211 if (obj_priv->pin_count == 1) {
4212 atomic_inc(&dev->pin_count);
4213 atomic_add(obj->size, &dev->pin_memory);
4214 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004215 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
Eric Anholt673a3942008-07-30 12:06:12 -07004216 !list_empty(&obj_priv->list))
4217 list_del_init(&obj_priv->list);
4218 }
4219 i915_verify_inactive(dev, __FILE__, __LINE__);
4220
4221 return 0;
4222}
4223
4224void
4225i915_gem_object_unpin(struct drm_gem_object *obj)
4226{
4227 struct drm_device *dev = obj->dev;
4228 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter23010e42010-03-08 13:35:02 +01004229 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004230
4231 i915_verify_inactive(dev, __FILE__, __LINE__);
4232 obj_priv->pin_count--;
4233 BUG_ON(obj_priv->pin_count < 0);
4234 BUG_ON(obj_priv->gtt_space == NULL);
4235
4236 /* If the object is no longer pinned, and is
4237 * neither active nor being flushed, then stick it on
4238 * the inactive list
4239 */
4240 if (obj_priv->pin_count == 0) {
4241 if (!obj_priv->active &&
Chris Wilson21d509e2009-06-06 09:46:02 +01004242 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
Eric Anholt673a3942008-07-30 12:06:12 -07004243 list_move_tail(&obj_priv->list,
4244 &dev_priv->mm.inactive_list);
4245 atomic_dec(&dev->pin_count);
4246 atomic_sub(obj->size, &dev->pin_memory);
4247 }
4248 i915_verify_inactive(dev, __FILE__, __LINE__);
4249}
4250
4251int
4252i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4253 struct drm_file *file_priv)
4254{
4255 struct drm_i915_gem_pin *args = data;
4256 struct drm_gem_object *obj;
4257 struct drm_i915_gem_object *obj_priv;
4258 int ret;
4259
4260 mutex_lock(&dev->struct_mutex);
4261
4262 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4263 if (obj == NULL) {
4264 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4265 args->handle);
4266 mutex_unlock(&dev->struct_mutex);
4267 return -EBADF;
4268 }
Daniel Vetter23010e42010-03-08 13:35:02 +01004269 obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004270
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004271 if (obj_priv->madv != I915_MADV_WILLNEED) {
4272 DRM_ERROR("Attempting to pin a purgeable buffer\n");
Chris Wilson3ef94da2009-09-14 16:50:29 +01004273 drm_gem_object_unreference(obj);
4274 mutex_unlock(&dev->struct_mutex);
4275 return -EINVAL;
4276 }
4277
Jesse Barnes79e53942008-11-07 14:24:08 -08004278 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4279 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4280 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00004281 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004282 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08004283 return -EINVAL;
4284 }
4285
4286 obj_priv->user_pin_count++;
4287 obj_priv->pin_filp = file_priv;
4288 if (obj_priv->user_pin_count == 1) {
4289 ret = i915_gem_object_pin(obj, args->alignment);
4290 if (ret != 0) {
4291 drm_gem_object_unreference(obj);
4292 mutex_unlock(&dev->struct_mutex);
4293 return ret;
4294 }
Eric Anholt673a3942008-07-30 12:06:12 -07004295 }
4296
4297 /* XXX - flush the CPU caches for pinned objects
4298 * as the X server doesn't manage domains yet
4299 */
Eric Anholte47c68e2008-11-14 13:35:19 -08004300 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004301 args->offset = obj_priv->gtt_offset;
4302 drm_gem_object_unreference(obj);
4303 mutex_unlock(&dev->struct_mutex);
4304
4305 return 0;
4306}
4307
4308int
4309i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4310 struct drm_file *file_priv)
4311{
4312 struct drm_i915_gem_pin *args = data;
4313 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08004314 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07004315
4316 mutex_lock(&dev->struct_mutex);
4317
4318 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4319 if (obj == NULL) {
4320 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4321 args->handle);
4322 mutex_unlock(&dev->struct_mutex);
4323 return -EBADF;
4324 }
4325
Daniel Vetter23010e42010-03-08 13:35:02 +01004326 obj_priv = to_intel_bo(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08004327 if (obj_priv->pin_filp != file_priv) {
4328 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4329 args->handle);
4330 drm_gem_object_unreference(obj);
4331 mutex_unlock(&dev->struct_mutex);
4332 return -EINVAL;
4333 }
4334 obj_priv->user_pin_count--;
4335 if (obj_priv->user_pin_count == 0) {
4336 obj_priv->pin_filp = NULL;
4337 i915_gem_object_unpin(obj);
4338 }
Eric Anholt673a3942008-07-30 12:06:12 -07004339
4340 drm_gem_object_unreference(obj);
4341 mutex_unlock(&dev->struct_mutex);
4342 return 0;
4343}
4344
4345int
4346i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4347 struct drm_file *file_priv)
4348{
4349 struct drm_i915_gem_busy *args = data;
4350 struct drm_gem_object *obj;
4351 struct drm_i915_gem_object *obj_priv;
4352
Eric Anholt673a3942008-07-30 12:06:12 -07004353 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4354 if (obj == NULL) {
4355 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4356 args->handle);
Eric Anholt673a3942008-07-30 12:06:12 -07004357 return -EBADF;
4358 }
4359
Chris Wilsonb1ce7862009-06-06 09:46:00 +01004360 mutex_lock(&dev->struct_mutex);
Eric Anholtf21289b2009-02-18 09:44:56 -08004361 /* Update the active list for the hardware's current position.
4362 * Otherwise this only updates on a delayed timer or when irqs are
4363 * actually unmasked, and our working set ends up being larger than
4364 * required.
4365 */
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01004366 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004367
Daniel Vetter23010e42010-03-08 13:35:02 +01004368 obj_priv = to_intel_bo(obj);
Eric Anholtc4de0a52008-12-14 19:05:04 -08004369 /* Don't count being on the flushing list against the object being
4370 * done. Otherwise, a buffer left on the flushing list but not getting
4371 * flushed (because nobody's flushing that domain) won't ever return
4372 * unbusy and get reused by libdrm's bo cache. The other expected
4373 * consumer of this interface, OpenGL's occlusion queries, also specs
4374 * that the objects get unbusy "eventually" without any interference.
4375 */
4376 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
Eric Anholt673a3942008-07-30 12:06:12 -07004377
4378 drm_gem_object_unreference(obj);
4379 mutex_unlock(&dev->struct_mutex);
4380 return 0;
4381}
4382
4383int
4384i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4385 struct drm_file *file_priv)
4386{
4387 return i915_gem_ring_throttle(dev, file_priv);
4388}
4389
Chris Wilson3ef94da2009-09-14 16:50:29 +01004390int
4391i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4392 struct drm_file *file_priv)
4393{
4394 struct drm_i915_gem_madvise *args = data;
4395 struct drm_gem_object *obj;
4396 struct drm_i915_gem_object *obj_priv;
4397
4398 switch (args->madv) {
4399 case I915_MADV_DONTNEED:
4400 case I915_MADV_WILLNEED:
4401 break;
4402 default:
4403 return -EINVAL;
4404 }
4405
4406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4407 if (obj == NULL) {
4408 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4409 args->handle);
4410 return -EBADF;
4411 }
4412
4413 mutex_lock(&dev->struct_mutex);
Daniel Vetter23010e42010-03-08 13:35:02 +01004414 obj_priv = to_intel_bo(obj);
Chris Wilson3ef94da2009-09-14 16:50:29 +01004415
4416 if (obj_priv->pin_count) {
4417 drm_gem_object_unreference(obj);
4418 mutex_unlock(&dev->struct_mutex);
4419
4420 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4421 return -EINVAL;
4422 }
4423
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004424 if (obj_priv->madv != __I915_MADV_PURGED)
4425 obj_priv->madv = args->madv;
Chris Wilson3ef94da2009-09-14 16:50:29 +01004426
Chris Wilson2d7ef392009-09-20 23:13:10 +01004427 /* if the object is no longer bound, discard its backing storage */
4428 if (i915_gem_object_is_purgeable(obj_priv) &&
4429 obj_priv->gtt_space == NULL)
4430 i915_gem_object_truncate(obj);
4431
Chris Wilsonbb6baf72009-09-22 14:24:13 +01004432 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4433
Chris Wilson3ef94da2009-09-14 16:50:29 +01004434 drm_gem_object_unreference(obj);
4435 mutex_unlock(&dev->struct_mutex);
4436
4437 return 0;
4438}
4439
Daniel Vetterac52bc52010-04-09 19:05:06 +00004440struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4441 size_t size)
4442{
Daniel Vetterc397b902010-04-09 19:05:07 +00004443 struct drm_i915_gem_object *obj;
4444
4445 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4446 if (obj == NULL)
4447 return NULL;
4448
4449 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4450 kfree(obj);
4451 return NULL;
4452 }
4453
4454 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4455 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4456
4457 obj->agp_type = AGP_USER_MEMORY;
Daniel Vetter62b8b212010-04-09 19:05:08 +00004458 obj->base.driver_private = NULL;
Daniel Vetterc397b902010-04-09 19:05:07 +00004459 obj->fence_reg = I915_FENCE_REG_NONE;
4460 INIT_LIST_HEAD(&obj->list);
4461 INIT_LIST_HEAD(&obj->gpu_write_list);
Daniel Vetterc397b902010-04-09 19:05:07 +00004462 obj->madv = I915_MADV_WILLNEED;
4463
4464 trace_i915_gem_object_create(&obj->base);
4465
4466 return &obj->base;
Daniel Vetterac52bc52010-04-09 19:05:06 +00004467}
4468
Eric Anholt673a3942008-07-30 12:06:12 -07004469int i915_gem_init_object(struct drm_gem_object *obj)
4470{
Daniel Vetterc397b902010-04-09 19:05:07 +00004471 BUG();
Jesse Barnesde151cf2008-11-12 10:03:55 -08004472
Eric Anholt673a3942008-07-30 12:06:12 -07004473 return 0;
4474}
4475
Chris Wilsonbe726152010-07-23 23:18:50 +01004476static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4477{
4478 struct drm_device *dev = obj->dev;
4479 drm_i915_private_t *dev_priv = dev->dev_private;
4480 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4481 int ret;
4482
4483 ret = i915_gem_object_unbind(obj);
4484 if (ret == -ERESTARTSYS) {
4485 list_move(&obj_priv->list,
4486 &dev_priv->mm.deferred_free_list);
4487 return;
4488 }
4489
4490 if (obj_priv->mmap_offset)
4491 i915_gem_free_mmap_offset(obj);
4492
4493 drm_gem_object_release(obj);
4494
4495 kfree(obj_priv->page_cpu_valid);
4496 kfree(obj_priv->bit_17);
4497 kfree(obj_priv);
4498}
4499
Eric Anholt673a3942008-07-30 12:06:12 -07004500void i915_gem_free_object(struct drm_gem_object *obj)
4501{
Jesse Barnesde151cf2008-11-12 10:03:55 -08004502 struct drm_device *dev = obj->dev;
Daniel Vetter23010e42010-03-08 13:35:02 +01004503 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004504
Chris Wilson1c5d22f2009-08-25 11:15:50 +01004505 trace_i915_gem_object_destroy(obj);
4506
Eric Anholt673a3942008-07-30 12:06:12 -07004507 while (obj_priv->pin_count > 0)
4508 i915_gem_object_unpin(obj);
4509
Dave Airlie71acb5e2008-12-30 20:31:46 +10004510 if (obj_priv->phys_obj)
4511 i915_gem_detach_phys_object(dev, obj);
4512
Chris Wilsonbe726152010-07-23 23:18:50 +01004513 i915_gem_free_object_tail(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07004514}
4515
Chris Wilsonab5ee572009-09-20 19:25:47 +01004516/** Unbinds all inactive objects. */
Eric Anholt673a3942008-07-30 12:06:12 -07004517static int
Chris Wilsonab5ee572009-09-20 19:25:47 +01004518i915_gem_evict_from_inactive_list(struct drm_device *dev)
Eric Anholt673a3942008-07-30 12:06:12 -07004519{
Chris Wilsonab5ee572009-09-20 19:25:47 +01004520 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07004521
Chris Wilsonab5ee572009-09-20 19:25:47 +01004522 while (!list_empty(&dev_priv->mm.inactive_list)) {
4523 struct drm_gem_object *obj;
4524 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004525
Daniel Vettera8089e82010-04-09 19:05:09 +00004526 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4527 struct drm_i915_gem_object,
4528 list)->base;
Eric Anholt673a3942008-07-30 12:06:12 -07004529
4530 ret = i915_gem_object_unbind(obj);
4531 if (ret != 0) {
Chris Wilsonab5ee572009-09-20 19:25:47 +01004532 DRM_ERROR("Error unbinding object: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004533 return ret;
4534 }
4535 }
4536
Eric Anholt673a3942008-07-30 12:06:12 -07004537 return 0;
4538}
4539
Jesse Barnes5669fca2009-02-17 15:13:31 -08004540int
Eric Anholt673a3942008-07-30 12:06:12 -07004541i915_gem_idle(struct drm_device *dev)
4542{
4543 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson29105cc2010-01-07 10:39:13 +00004544 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004545
Keith Packard6dbe2772008-10-14 21:41:13 -07004546 mutex_lock(&dev->struct_mutex);
4547
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004548 if (dev_priv->mm.suspended ||
Zou Nan haid1b851f2010-05-21 09:08:57 +08004549 (dev_priv->render_ring.gem_object == NULL) ||
4550 (HAS_BSD(dev) &&
4551 dev_priv->bsd_ring.gem_object == NULL)) {
Keith Packard6dbe2772008-10-14 21:41:13 -07004552 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004553 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07004554 }
Eric Anholt673a3942008-07-30 12:06:12 -07004555
Chris Wilson29105cc2010-01-07 10:39:13 +00004556 ret = i915_gpu_idle(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004557 if (ret) {
4558 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07004559 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07004560 }
Eric Anholt673a3942008-07-30 12:06:12 -07004561
Chris Wilson29105cc2010-01-07 10:39:13 +00004562 /* Under UMS, be paranoid and evict. */
4563 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4564 ret = i915_gem_evict_from_inactive_list(dev);
4565 if (ret) {
4566 mutex_unlock(&dev->struct_mutex);
4567 return ret;
4568 }
4569 }
4570
4571 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4572 * We need to replace this with a semaphore, or something.
4573 * And not confound mm.suspended!
4574 */
4575 dev_priv->mm.suspended = 1;
4576 del_timer(&dev_priv->hangcheck_timer);
4577
4578 i915_kernel_lost_context(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07004579 i915_gem_cleanup_ringbuffer(dev);
Chris Wilson29105cc2010-01-07 10:39:13 +00004580
Keith Packard6dbe2772008-10-14 21:41:13 -07004581 mutex_unlock(&dev->struct_mutex);
4582
Chris Wilson29105cc2010-01-07 10:39:13 +00004583 /* Cancel the retire work handler, which should be idle now. */
4584 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4585
Eric Anholt673a3942008-07-30 12:06:12 -07004586 return 0;
4587}
4588
Jesse Barnese552eb72010-04-21 11:39:23 -07004589/*
4590 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4591 * over cache flushing.
4592 */
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004593static int
Jesse Barnese552eb72010-04-21 11:39:23 -07004594i915_gem_init_pipe_control(struct drm_device *dev)
4595{
4596 drm_i915_private_t *dev_priv = dev->dev_private;
4597 struct drm_gem_object *obj;
4598 struct drm_i915_gem_object *obj_priv;
4599 int ret;
4600
Eric Anholt34dc4d42010-05-07 14:30:03 -07004601 obj = i915_gem_alloc_object(dev, 4096);
Jesse Barnese552eb72010-04-21 11:39:23 -07004602 if (obj == NULL) {
4603 DRM_ERROR("Failed to allocate seqno page\n");
4604 ret = -ENOMEM;
4605 goto err;
4606 }
4607 obj_priv = to_intel_bo(obj);
4608 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4609
4610 ret = i915_gem_object_pin(obj, 4096);
4611 if (ret)
4612 goto err_unref;
4613
4614 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4615 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4616 if (dev_priv->seqno_page == NULL)
4617 goto err_unpin;
4618
4619 dev_priv->seqno_obj = obj;
4620 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4621
4622 return 0;
4623
4624err_unpin:
4625 i915_gem_object_unpin(obj);
4626err_unref:
4627 drm_gem_object_unreference(obj);
4628err:
4629 return ret;
4630}
4631
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004632
4633static void
Jesse Barnese552eb72010-04-21 11:39:23 -07004634i915_gem_cleanup_pipe_control(struct drm_device *dev)
4635{
4636 drm_i915_private_t *dev_priv = dev->dev_private;
4637 struct drm_gem_object *obj;
4638 struct drm_i915_gem_object *obj_priv;
4639
4640 obj = dev_priv->seqno_obj;
4641 obj_priv = to_intel_bo(obj);
4642 kunmap(obj_priv->pages[0]);
4643 i915_gem_object_unpin(obj);
4644 drm_gem_object_unreference(obj);
4645 dev_priv->seqno_obj = NULL;
4646
4647 dev_priv->seqno_page = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07004648}
4649
Eric Anholt673a3942008-07-30 12:06:12 -07004650int
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004651i915_gem_init_ringbuffer(struct drm_device *dev)
4652{
4653 drm_i915_private_t *dev_priv = dev->dev_private;
4654 int ret;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004655
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004656 dev_priv->render_ring = render_ring;
Chris Wilson68f95ba2010-05-27 13:18:22 +01004657
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004658 if (!I915_NEED_GFX_HWS(dev)) {
4659 dev_priv->render_ring.status_page.page_addr
4660 = dev_priv->status_page_dmah->vaddr;
4661 memset(dev_priv->render_ring.status_page.page_addr,
4662 0, PAGE_SIZE);
4663 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004664
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004665 if (HAS_PIPE_CONTROL(dev)) {
4666 ret = i915_gem_init_pipe_control(dev);
4667 if (ret)
4668 return ret;
4669 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004670
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004671 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004672 if (ret)
4673 goto cleanup_pipe_control;
4674
4675 if (HAS_BSD(dev)) {
Zou Nan haid1b851f2010-05-21 09:08:57 +08004676 dev_priv->bsd_ring = bsd_ring;
4677 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
Chris Wilson68f95ba2010-05-27 13:18:22 +01004678 if (ret)
4679 goto cleanup_render_ring;
Zou Nan haid1b851f2010-05-21 09:08:57 +08004680 }
Chris Wilson68f95ba2010-05-27 13:18:22 +01004681
4682 return 0;
4683
4684cleanup_render_ring:
4685 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4686cleanup_pipe_control:
4687 if (HAS_PIPE_CONTROL(dev))
4688 i915_gem_cleanup_pipe_control(dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004689 return ret;
4690}
4691
4692void
4693i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4694{
4695 drm_i915_private_t *dev_priv = dev->dev_private;
4696
4697 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004698 if (HAS_BSD(dev))
4699 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +08004700 if (HAS_PIPE_CONTROL(dev))
4701 i915_gem_cleanup_pipe_control(dev);
4702}
4703
4704int
Eric Anholt673a3942008-07-30 12:06:12 -07004705i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4706 struct drm_file *file_priv)
4707{
4708 drm_i915_private_t *dev_priv = dev->dev_private;
4709 int ret;
4710
Jesse Barnes79e53942008-11-07 14:24:08 -08004711 if (drm_core_check_feature(dev, DRIVER_MODESET))
4712 return 0;
4713
Ben Gamariba1234d2009-09-14 17:48:47 -04004714 if (atomic_read(&dev_priv->mm.wedged)) {
Eric Anholt673a3942008-07-30 12:06:12 -07004715 DRM_ERROR("Reenabling wedged hardware, good luck\n");
Ben Gamariba1234d2009-09-14 17:48:47 -04004716 atomic_set(&dev_priv->mm.wedged, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07004717 }
4718
Eric Anholt673a3942008-07-30 12:06:12 -07004719 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004720 dev_priv->mm.suspended = 0;
4721
4722 ret = i915_gem_init_ringbuffer(dev);
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004723 if (ret != 0) {
4724 mutex_unlock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004725 return ret;
Wu Fengguangd816f6a2009-04-18 10:43:32 +08004726 }
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08004727
Carl Worth5e118f42009-03-20 11:54:25 -07004728 spin_lock(&dev_priv->mm.active_list_lock);
Zou Nan hai852835f2010-05-21 09:08:56 +08004729 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004730 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
Carl Worth5e118f42009-03-20 11:54:25 -07004731 spin_unlock(&dev_priv->mm.active_list_lock);
4732
Eric Anholt673a3942008-07-30 12:06:12 -07004733 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4734 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
Zou Nan hai852835f2010-05-21 09:08:56 +08004735 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
Zou Nan haid1b851f2010-05-21 09:08:57 +08004736 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07004737 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004738
Chris Wilson5f353082010-06-07 14:03:03 +01004739 ret = drm_irq_install(dev);
4740 if (ret)
4741 goto cleanup_ringbuffer;
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004742
Eric Anholt673a3942008-07-30 12:06:12 -07004743 return 0;
Chris Wilson5f353082010-06-07 14:03:03 +01004744
4745cleanup_ringbuffer:
4746 mutex_lock(&dev->struct_mutex);
4747 i915_gem_cleanup_ringbuffer(dev);
4748 dev_priv->mm.suspended = 1;
4749 mutex_unlock(&dev->struct_mutex);
4750
4751 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004752}
4753
4754int
4755i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4756 struct drm_file *file_priv)
4757{
Jesse Barnes79e53942008-11-07 14:24:08 -08004758 if (drm_core_check_feature(dev, DRIVER_MODESET))
4759 return 0;
4760
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004761 drm_irq_uninstall(dev);
Linus Torvaldse6890f62009-09-08 17:09:24 -07004762 return i915_gem_idle(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07004763}
4764
4765void
4766i915_gem_lastclose(struct drm_device *dev)
4767{
4768 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004769
Eric Anholte806b492009-01-22 09:56:58 -08004770 if (drm_core_check_feature(dev, DRIVER_MODESET))
4771 return;
4772
Keith Packard6dbe2772008-10-14 21:41:13 -07004773 ret = i915_gem_idle(dev);
4774 if (ret)
4775 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004776}
4777
4778void
4779i915_gem_load(struct drm_device *dev)
4780{
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004781 int i;
Eric Anholt673a3942008-07-30 12:06:12 -07004782 drm_i915_private_t *dev_priv = dev->dev_private;
4783
Carl Worth5e118f42009-03-20 11:54:25 -07004784 spin_lock_init(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004785 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
Daniel Vetter99fcb762010-02-07 16:20:18 +01004786 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004787 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
Eric Anholta09ba7f2009-08-29 12:49:51 -07004788 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
Chris Wilsonbe726152010-07-23 23:18:50 +01004789 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
Zou Nan hai852835f2010-05-21 09:08:56 +08004790 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4791 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08004792 if (HAS_BSD(dev)) {
4793 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4794 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4795 }
Daniel Vetter007cc8a2010-04-28 11:02:31 +02004796 for (i = 0; i < 16; i++)
4797 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
Eric Anholt673a3942008-07-30 12:06:12 -07004798 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4799 i915_gem_retire_work_handler);
Chris Wilson31169712009-09-14 16:50:28 +01004800 spin_lock(&shrink_list_lock);
4801 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4802 spin_unlock(&shrink_list_lock);
4803
Dave Airlie94400122010-07-20 13:15:31 +10004804 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4805 if (IS_GEN3(dev)) {
4806 u32 tmp = I915_READ(MI_ARB_STATE);
4807 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4808 /* arb state is a masked write, so set bit + bit in mask */
4809 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4810 I915_WRITE(MI_ARB_STATE, tmp);
4811 }
4812 }
4813
Jesse Barnesde151cf2008-11-12 10:03:55 -08004814 /* Old X drivers will take 0-2 for front, back, depth buffers */
Eric Anholtb397c832010-01-26 09:43:10 -08004815 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4816 dev_priv->fence_reg_start = 3;
Jesse Barnesde151cf2008-11-12 10:03:55 -08004817
Jesse Barnes0f973f22009-01-26 17:10:45 -08004818 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004819 dev_priv->num_fence_regs = 16;
4820 else
4821 dev_priv->num_fence_regs = 8;
4822
Grégoire Henryb5aa8a02009-06-23 15:41:02 +02004823 /* Initialize fence registers to zero */
4824 if (IS_I965G(dev)) {
4825 for (i = 0; i < 16; i++)
4826 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4827 } else {
4828 for (i = 0; i < 8; i++)
4829 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4830 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4831 for (i = 0; i < 8; i++)
4832 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4833 }
Eric Anholt673a3942008-07-30 12:06:12 -07004834 i915_gem_detect_bit_6_swizzle(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004835 init_waitqueue_head(&dev_priv->pending_flip_queue);
Eric Anholt673a3942008-07-30 12:06:12 -07004836}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004837
4838/*
4839 * Create a physically contiguous memory object for this object
4840 * e.g. for cursor + overlay regs
4841 */
4842int i915_gem_init_phys_object(struct drm_device *dev,
4843 int id, int size)
4844{
4845 drm_i915_private_t *dev_priv = dev->dev_private;
4846 struct drm_i915_gem_phys_object *phys_obj;
4847 int ret;
4848
4849 if (dev_priv->mm.phys_objs[id - 1] || !size)
4850 return 0;
4851
Eric Anholt9a298b22009-03-24 12:23:04 -07004852 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004853 if (!phys_obj)
4854 return -ENOMEM;
4855
4856 phys_obj->id = id;
4857
Zhenyu Wange6be8d92010-01-05 11:25:05 +08004858 phys_obj->handle = drm_pci_alloc(dev, size, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004859 if (!phys_obj->handle) {
4860 ret = -ENOMEM;
4861 goto kfree_obj;
4862 }
4863#ifdef CONFIG_X86
4864 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4865#endif
4866
4867 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4868
4869 return 0;
4870kfree_obj:
Eric Anholt9a298b22009-03-24 12:23:04 -07004871 kfree(phys_obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004872 return ret;
4873}
4874
4875void i915_gem_free_phys_object(struct drm_device *dev, int id)
4876{
4877 drm_i915_private_t *dev_priv = dev->dev_private;
4878 struct drm_i915_gem_phys_object *phys_obj;
4879
4880 if (!dev_priv->mm.phys_objs[id - 1])
4881 return;
4882
4883 phys_obj = dev_priv->mm.phys_objs[id - 1];
4884 if (phys_obj->cur_obj) {
4885 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4886 }
4887
4888#ifdef CONFIG_X86
4889 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4890#endif
4891 drm_pci_free(dev, phys_obj->handle);
4892 kfree(phys_obj);
4893 dev_priv->mm.phys_objs[id - 1] = NULL;
4894}
4895
4896void i915_gem_free_all_phys_object(struct drm_device *dev)
4897{
4898 int i;
4899
Dave Airlie260883c2009-01-22 17:58:49 +10004900 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004901 i915_gem_free_phys_object(dev, i);
4902}
4903
4904void i915_gem_detach_phys_object(struct drm_device *dev,
4905 struct drm_gem_object *obj)
4906{
4907 struct drm_i915_gem_object *obj_priv;
4908 int i;
4909 int ret;
4910 int page_count;
4911
Daniel Vetter23010e42010-03-08 13:35:02 +01004912 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004913 if (!obj_priv->phys_obj)
4914 return;
4915
Chris Wilson4bdadb92010-01-27 13:36:32 +00004916 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004917 if (ret)
4918 goto out;
4919
4920 page_count = obj->size / PAGE_SIZE;
4921
4922 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004923 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004924 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4925
4926 memcpy(dst, src, PAGE_SIZE);
4927 kunmap_atomic(dst, KM_USER0);
4928 }
Eric Anholt856fa192009-03-19 14:10:50 -07004929 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004930 drm_agp_chipset_flush(dev);
Chris Wilsond78b47b2009-06-17 21:52:49 +01004931
4932 i915_gem_object_put_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004933out:
4934 obj_priv->phys_obj->cur_obj = NULL;
4935 obj_priv->phys_obj = NULL;
4936}
4937
4938int
4939i915_gem_attach_phys_object(struct drm_device *dev,
4940 struct drm_gem_object *obj, int id)
4941{
4942 drm_i915_private_t *dev_priv = dev->dev_private;
4943 struct drm_i915_gem_object *obj_priv;
4944 int ret = 0;
4945 int page_count;
4946 int i;
4947
4948 if (id > I915_MAX_PHYS_OBJECT)
4949 return -EINVAL;
4950
Daniel Vetter23010e42010-03-08 13:35:02 +01004951 obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004952
4953 if (obj_priv->phys_obj) {
4954 if (obj_priv->phys_obj->id == id)
4955 return 0;
4956 i915_gem_detach_phys_object(dev, obj);
4957 }
4958
4959
4960 /* create a new object */
4961 if (!dev_priv->mm.phys_objs[id - 1]) {
4962 ret = i915_gem_init_phys_object(dev, id,
4963 obj->size);
4964 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004965 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004966 goto out;
4967 }
4968 }
4969
4970 /* bind to the object */
4971 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4972 obj_priv->phys_obj->cur_obj = obj;
4973
Chris Wilson4bdadb92010-01-27 13:36:32 +00004974 ret = i915_gem_object_get_pages(obj, 0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004975 if (ret) {
4976 DRM_ERROR("failed to get page list\n");
4977 goto out;
4978 }
4979
4980 page_count = obj->size / PAGE_SIZE;
4981
4982 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004983 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004984 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4985
4986 memcpy(dst, src, PAGE_SIZE);
4987 kunmap_atomic(src, KM_USER0);
4988 }
4989
Chris Wilsond78b47b2009-06-17 21:52:49 +01004990 i915_gem_object_put_pages(obj);
4991
Dave Airlie71acb5e2008-12-30 20:31:46 +10004992 return 0;
4993out:
4994 return ret;
4995}
4996
4997static int
4998i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4999 struct drm_i915_gem_pwrite *args,
5000 struct drm_file *file_priv)
5001{
Daniel Vetter23010e42010-03-08 13:35:02 +01005002 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005003 void *obj_addr;
5004 int ret;
5005 char __user *user_data;
5006
5007 user_data = (char __user *) (uintptr_t) args->data_ptr;
5008 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5009
Zhao Yakui44d98a62009-10-09 11:39:40 +08005010 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005011 ret = copy_from_user(obj_addr, user_data, args->size);
5012 if (ret)
5013 return -EFAULT;
5014
5015 drm_agp_chipset_flush(dev);
5016 return 0;
5017}
Eric Anholtb9624422009-06-03 07:27:35 +00005018
5019void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5020{
5021 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5022
5023 /* Clean up our request list when the client is going away, so that
5024 * later retire_requests won't dereference our soon-to-be-gone
5025 * file_priv.
5026 */
5027 mutex_lock(&dev->struct_mutex);
5028 while (!list_empty(&i915_file_priv->mm.request_list))
5029 list_del_init(i915_file_priv->mm.request_list.next);
5030 mutex_unlock(&dev->struct_mutex);
5031}
Chris Wilson31169712009-09-14 16:50:28 +01005032
Chris Wilson31169712009-09-14 16:50:28 +01005033static int
Chris Wilson1637ef42010-04-20 17:10:35 +01005034i915_gpu_is_active(struct drm_device *dev)
5035{
5036 drm_i915_private_t *dev_priv = dev->dev_private;
5037 int lists_empty;
5038
5039 spin_lock(&dev_priv->mm.active_list_lock);
5040 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
Zou Nan hai852835f2010-05-21 09:08:56 +08005041 list_empty(&dev_priv->render_ring.active_list);
Zou Nan haid1b851f2010-05-21 09:08:57 +08005042 if (HAS_BSD(dev))
5043 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
Chris Wilson1637ef42010-04-20 17:10:35 +01005044 spin_unlock(&dev_priv->mm.active_list_lock);
5045
5046 return !lists_empty;
5047}
5048
5049static int
Dave Chinner7f8275d2010-07-19 14:56:17 +10005050i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
Chris Wilson31169712009-09-14 16:50:28 +01005051{
5052 drm_i915_private_t *dev_priv, *next_dev;
5053 struct drm_i915_gem_object *obj_priv, *next_obj;
5054 int cnt = 0;
5055 int would_deadlock = 1;
5056
5057 /* "fast-path" to count number of available objects */
5058 if (nr_to_scan == 0) {
5059 spin_lock(&shrink_list_lock);
5060 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5061 struct drm_device *dev = dev_priv->dev;
5062
5063 if (mutex_trylock(&dev->struct_mutex)) {
5064 list_for_each_entry(obj_priv,
5065 &dev_priv->mm.inactive_list,
5066 list)
5067 cnt++;
5068 mutex_unlock(&dev->struct_mutex);
5069 }
5070 }
5071 spin_unlock(&shrink_list_lock);
5072
5073 return (cnt / 100) * sysctl_vfs_cache_pressure;
5074 }
5075
5076 spin_lock(&shrink_list_lock);
5077
Chris Wilson1637ef42010-04-20 17:10:35 +01005078rescan:
Chris Wilson31169712009-09-14 16:50:28 +01005079 /* first scan for clean buffers */
5080 list_for_each_entry_safe(dev_priv, next_dev,
5081 &shrink_list, mm.shrink_list) {
5082 struct drm_device *dev = dev_priv->dev;
5083
5084 if (! mutex_trylock(&dev->struct_mutex))
5085 continue;
5086
5087 spin_unlock(&shrink_list_lock);
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01005088 i915_gem_retire_requests(dev);
Zou Nan haid1b851f2010-05-21 09:08:57 +08005089
Chris Wilson31169712009-09-14 16:50:28 +01005090 list_for_each_entry_safe(obj_priv, next_obj,
5091 &dev_priv->mm.inactive_list,
5092 list) {
5093 if (i915_gem_object_is_purgeable(obj_priv)) {
Daniel Vettera8089e82010-04-09 19:05:09 +00005094 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01005095 if (--nr_to_scan <= 0)
5096 break;
5097 }
5098 }
5099
5100 spin_lock(&shrink_list_lock);
5101 mutex_unlock(&dev->struct_mutex);
5102
Chris Wilson963b4832009-09-20 23:03:54 +01005103 would_deadlock = 0;
5104
Chris Wilson31169712009-09-14 16:50:28 +01005105 if (nr_to_scan <= 0)
5106 break;
5107 }
5108
5109 /* second pass, evict/count anything still on the inactive list */
5110 list_for_each_entry_safe(dev_priv, next_dev,
5111 &shrink_list, mm.shrink_list) {
5112 struct drm_device *dev = dev_priv->dev;
5113
5114 if (! mutex_trylock(&dev->struct_mutex))
5115 continue;
5116
5117 spin_unlock(&shrink_list_lock);
5118
5119 list_for_each_entry_safe(obj_priv, next_obj,
5120 &dev_priv->mm.inactive_list,
5121 list) {
5122 if (nr_to_scan > 0) {
Daniel Vettera8089e82010-04-09 19:05:09 +00005123 i915_gem_object_unbind(&obj_priv->base);
Chris Wilson31169712009-09-14 16:50:28 +01005124 nr_to_scan--;
5125 } else
5126 cnt++;
5127 }
5128
5129 spin_lock(&shrink_list_lock);
5130 mutex_unlock(&dev->struct_mutex);
5131
5132 would_deadlock = 0;
5133 }
5134
Chris Wilson1637ef42010-04-20 17:10:35 +01005135 if (nr_to_scan) {
5136 int active = 0;
5137
5138 /*
5139 * We are desperate for pages, so as a last resort, wait
5140 * for the GPU to finish and discard whatever we can.
5141 * This has a dramatic impact to reduce the number of
5142 * OOM-killer events whilst running the GPU aggressively.
5143 */
5144 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5145 struct drm_device *dev = dev_priv->dev;
5146
5147 if (!mutex_trylock(&dev->struct_mutex))
5148 continue;
5149
5150 spin_unlock(&shrink_list_lock);
5151
5152 if (i915_gpu_is_active(dev)) {
5153 i915_gpu_idle(dev);
5154 active++;
5155 }
5156
5157 spin_lock(&shrink_list_lock);
5158 mutex_unlock(&dev->struct_mutex);
5159 }
5160
5161 if (active)
5162 goto rescan;
5163 }
5164
Chris Wilson31169712009-09-14 16:50:28 +01005165 spin_unlock(&shrink_list_lock);
5166
5167 if (would_deadlock)
5168 return -1;
5169 else if (cnt > 0)
5170 return (cnt / 100) * sysctl_vfs_cache_pressure;
5171 else
5172 return 0;
5173}
5174
5175static struct shrinker shrinker = {
5176 .shrink = i915_gem_shrink,
5177 .seeks = DEFAULT_SEEKS,
5178};
5179
5180__init void
5181i915_gem_shrinker_init(void)
5182{
5183 register_shrinker(&shrinker);
5184}
5185
5186__exit void
5187i915_gem_shrinker_exit(void)
5188{
5189 unregister_shrinker(&shrinker);
5190}