blob: 0b13cc04a38db81f2a09cd2c083fecd431c61d97 [file] [log] [blame]
Arnold Schwaighofer373e8652007-10-12 21:30:57 +00001//===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instruction set, defining the instructions, and
11// properties of the instructions which are needed for code generation, machine
12// code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// X86 specific DAG Nodes.
18//
19
20def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
23
24def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
25
Evan Cheng621216e2007-09-29 00:00:36 +000026def SDTX86Cmov : SDTypeProfile<1, 4,
Evan Cheng950aac02007-09-25 01:57:46 +000027 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000029
Dan Gohman99a12192009-03-04 19:44:21 +000030// Unary and binary operator instructions that set EFLAGS as a side-effect.
31def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
32 [SDTCisInt<0>]>;
33def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
34 [SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>,
36 SDTCisInt<0>]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +000037
Evan Cheng621216e2007-09-29 00:00:36 +000038def SDTX86BrCond : SDTypeProfile<0, 3,
Evan Cheng950aac02007-09-25 01:57:46 +000039 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000041
Evan Cheng621216e2007-09-29 00:00:36 +000042def SDTX86SetCC : SDTypeProfile<1, 2,
Evan Cheng950aac02007-09-25 01:57:46 +000043 [SDTCisVT<0, i8>,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000045
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000046def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 SDTCisVT<2, i8>]>;
Andrew Lenharth81580822008-03-05 01:15:49 +000048def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000049
Dale Johannesenf160d802008-10-02 18:53:47 +000050def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
51 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
Chris Lattnerb56cc342008-03-11 03:23:40 +000052def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000053
Bill Wendling7173da52007-11-13 09:19:02 +000054def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
55def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
56 SDTCisVT<1, i32> ]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000057
Dan Gohman3329ffe2008-05-29 19:57:41 +000058def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000059
60def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61
62def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63
64def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65
66def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
67
68def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
69
70def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +000072def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73
Evan Cheng48679f42007-12-14 02:13:44 +000074def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
75def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000076def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
77def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78
Evan Cheng621216e2007-09-29 00:00:36 +000079def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000080
Dan Gohman7fe9b7f2008-12-23 22:45:23 +000081def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82
Evan Cheng621216e2007-09-29 00:00:36 +000083def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000084def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
Evan Cheng950aac02007-09-25 01:57:46 +000085 [SDNPHasChain]>;
Evan Cheng621216e2007-09-29 00:00:36 +000086def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000087
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +000088def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 SDNPMayLoad]>;
Andrew Lenharth81580822008-03-05 01:15:49 +000091def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 SDNPMayLoad]>;
Dale Johannesenf160d802008-10-02 18:53:47 +000094def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
95 [SDNPHasChain, SDNPMayStore,
96 SDNPMayLoad, SDNPMemOperand]>;
97def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
Dale Johannesen51c58ee2008-10-03 22:25:52 +0000112def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000115def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
116 [SDNPHasChain, SDNPOptInFlag]>;
117
118def X86callseq_start :
119 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
120 [SDNPHasChain, SDNPOutFlag]>;
121def X86callseq_end :
122 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000123 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000124
125def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
126 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127
128def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
129 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130
131def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
Chris Lattnerca4e0fe2008-01-10 05:12:37 +0000132 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000133def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
Chris Lattnerca4e0fe2008-01-10 05:12:37 +0000134 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
135 SDNPMayLoad]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000136
137def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000138 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000139
140def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
141def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
142
143def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
Anton Korobeynikov4fbf00b2008-05-04 21:36:32 +0000144 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000145def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
146
147def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
148 [SDNPHasChain]>;
149
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000150def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
151 [SDNPHasChain, SDNPOptInFlag]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000152
Dan Gohman99a12192009-03-04 19:44:21 +0000153def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
154def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
155def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
156def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
157def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
158def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
Bill Wendlingae034ed2008-12-12 00:56:36 +0000159
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000160//===----------------------------------------------------------------------===//
161// X86 Operand Definitions.
162//
163
164// *mem - Operand definitions for the funky X86 addressing mode operands.
165//
166class X86MemOperand<string printMethod> : Operand<iPTR> {
167 let PrintMethod = printMethod;
168 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
169}
170
171def i8mem : X86MemOperand<"printi8mem">;
172def i16mem : X86MemOperand<"printi16mem">;
173def i32mem : X86MemOperand<"printi32mem">;
174def i64mem : X86MemOperand<"printi64mem">;
175def i128mem : X86MemOperand<"printi128mem">;
176def f32mem : X86MemOperand<"printf32mem">;
177def f64mem : X86MemOperand<"printf64mem">;
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000178def f80mem : X86MemOperand<"printf80mem">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000179def f128mem : X86MemOperand<"printf128mem">;
180
181def lea32mem : Operand<i32> {
182 let PrintMethod = "printi32mem";
183 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
184}
185
186def SSECC : Operand<i8> {
187 let PrintMethod = "printSSECC";
188}
189
190def piclabel: Operand<i32> {
191 let PrintMethod = "printPICLabel";
192}
193
194// A couple of more descriptive operand definitions.
195// 16-bits but only 8 bits are significant.
196def i16i8imm : Operand<i16>;
197// 32-bits but only 8 bits are significant.
198def i32i8imm : Operand<i32>;
199
200// Branch targets have OtherVT type.
201def brtarget : Operand<OtherVT>;
202
203//===----------------------------------------------------------------------===//
204// X86 Complex Pattern Definitions.
205//
206
207// Define X86 specific addressing mode.
208def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
209def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
210 [add, mul, shl, or, frameindex], []>;
211
212//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000213// X86 Instruction Predicate Definitions.
214def HasMMX : Predicate<"Subtarget->hasMMX()">;
215def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
216def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
217def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
218def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
Nate Begemanb2975562008-02-03 07:18:54 +0000219def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
220def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
Dale Johannesene0e0fd02007-09-23 14:52:20 +0000221def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
222def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000223def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
224def In64BitMode : Predicate<"Subtarget->is64Bit()">;
225def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
226def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
227def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
Evan Cheng13559d62008-09-26 23:41:32 +0000228def OptForSpeed : Predicate<"!OptForSize">;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000229def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000230
231//===----------------------------------------------------------------------===//
Evan Cheng86ab7d32007-07-31 08:04:03 +0000232// X86 Instruction Format Definitions.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000233//
234
Evan Cheng86ab7d32007-07-31 08:04:03 +0000235include "X86InstrFormats.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000236
237//===----------------------------------------------------------------------===//
238// Pattern fragments...
239//
240
241// X86 specific condition code. These correspond to CondCode in
242// X86InstrInfo.h. They must be kept in synch.
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000243def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
244def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
245def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
246def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
247def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
248def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
249def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
250def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
251def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
252def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000253def X86_COND_NO : PatLeaf<(i8 10)>;
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000254def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000255def X86_COND_NS : PatLeaf<(i8 12)>;
Dan Gohman0fc9ed62009-01-07 00:15:08 +0000256def X86_COND_O : PatLeaf<(i8 13)>;
257def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
258def X86_COND_S : PatLeaf<(i8 15)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000259
260def i16immSExt8 : PatLeaf<(i16 imm), [{
261 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
262 // sign extended field.
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000263 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000264}]>;
265
266def i32immSExt8 : PatLeaf<(i32 imm), [{
267 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
268 // sign extended field.
Dan Gohmanfaeb4a32008-09-12 16:56:44 +0000269 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000270}]>;
271
272// Helper fragments for loads.
Evan Chengb3e25ea2008-05-13 18:59:59 +0000273// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
274// known to be 32-bit aligned or better. Ditto for i8 to i16.
Dan Gohman2a174122008-10-15 06:50:19 +0000275def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
Dan Gohman8335c412008-08-20 15:24:22 +0000276 LoadSDNode *LD = cast<LoadSDNode>(N);
Dan Gohman8335c412008-08-20 15:24:22 +0000277 ISD::LoadExtType ExtType = LD->getExtensionType();
278 if (ExtType == ISD::NON_EXTLOAD)
279 return true;
280 if (ExtType == ISD::EXTLOAD)
281 return LD->getAlignment() >= 2 && !LD->isVolatile();
Evan Cheng8b765e92008-05-13 00:54:02 +0000282 return false;
283}]>;
284
Dan Gohman2a174122008-10-15 06:50:19 +0000285def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Cheng56ec77b2008-09-24 23:27:55 +0000286 LoadSDNode *LD = cast<LoadSDNode>(N);
Evan Cheng56ec77b2008-09-24 23:27:55 +0000287 ISD::LoadExtType ExtType = LD->getExtensionType();
288 if (ExtType == ISD::EXTLOAD)
289 return LD->getAlignment() >= 2 && !LD->isVolatile();
290 return false;
291}]>;
292
Dan Gohman2a174122008-10-15 06:50:19 +0000293def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Dan Gohman8335c412008-08-20 15:24:22 +0000294 LoadSDNode *LD = cast<LoadSDNode>(N);
Dan Gohman8335c412008-08-20 15:24:22 +0000295 ISD::LoadExtType ExtType = LD->getExtensionType();
296 if (ExtType == ISD::NON_EXTLOAD)
297 return true;
298 if (ExtType == ISD::EXTLOAD)
299 return LD->getAlignment() >= 4 && !LD->isVolatile();
Evan Cheng8b765e92008-05-13 00:54:02 +0000300 return false;
301}]>;
302
Dan Gohman2a174122008-10-15 06:50:19 +0000303def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Cheng1e5e5452008-09-29 17:26:18 +0000304 LoadSDNode *LD = cast<LoadSDNode>(N);
305 if (LD->isVolatile())
306 return false;
Evan Cheng1e5e5452008-09-29 17:26:18 +0000307 ISD::LoadExtType ExtType = LD->getExtensionType();
308 if (ExtType == ISD::NON_EXTLOAD)
309 return true;
310 if (ExtType == ISD::EXTLOAD)
311 return LD->getAlignment() >= 4;
312 return false;
313}]>;
314
sampo9cc09a32009-01-26 01:24:32 +0000315def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
316 LoadSDNode *LD = cast<LoadSDNode>(N);
317 const Value *Src = LD->getSrcValue();
318 if (!Src)
319 return false;
320 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
321 return PT->getAddressSpace() == 256;
322 return false;
323}]>;
324
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000325def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000326def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
327
328def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
329def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
Dale Johannesen4ab00bd2007-08-05 18:49:15 +0000330def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000331
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000332def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
333def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
334def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
335
336def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
337def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
338def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
339def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
340def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
341def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
342
343def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
344def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
345def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
346def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
347def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
348def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
349
Chris Lattner21da6382008-02-19 17:37:35 +0000350
351// An 'and' node with a single use.
352def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
Evan Cheng9123cfa2008-03-04 00:40:35 +0000353 return N->hasOneUse();
Chris Lattner21da6382008-02-19 17:37:35 +0000354}]>;
355
Dan Gohman921581d2008-10-17 01:23:35 +0000356// 'shld' and 'shrd' instruction patterns. Note that even though these have
357// the srl and shl in their patterns, the C++ code must still check for them,
358// because predicates are tested before children nodes are explored.
359
360def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
361 (or (srl node:$src1, node:$amt1),
362 (shl node:$src2, node:$amt2)), [{
363 assert(N->getOpcode() == ISD::OR);
364 return N->getOperand(0).getOpcode() == ISD::SRL &&
365 N->getOperand(1).getOpcode() == ISD::SHL &&
366 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
367 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
368 N->getOperand(0).getConstantOperandVal(1) ==
369 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
370}]>;
371
372def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
373 (or (shl node:$src1, node:$amt1),
374 (srl node:$src2, node:$amt2)), [{
375 assert(N->getOpcode() == ISD::OR);
376 return N->getOperand(0).getOpcode() == ISD::SHL &&
377 N->getOperand(1).getOpcode() == ISD::SRL &&
378 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
379 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
380 N->getOperand(0).getConstantOperandVal(1) ==
381 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
382}]>;
383
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000384//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000385// Instruction list...
386//
387
388// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
389// a stack adjustment and the codegen must know that they may modify the stack
390// pointer before prolog-epilog rewriting occurs.
Chris Lattnerb56cc342008-03-11 03:23:40 +0000391// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
392// sub / add which can clobber EFLAGS.
Evan Cheng037364a2007-09-28 01:19:48 +0000393let Defs = [ESP, EFLAGS], Uses = [ESP] in {
Dan Gohman01c9f772008-10-01 18:28:06 +0000394def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
395 "#ADJCALLSTACKDOWN",
Chris Lattnerfe5d4022008-10-11 22:08:30 +0000396 [(X86callseq_start timm:$amt)]>,
Dan Gohman01c9f772008-10-01 18:28:06 +0000397 Requires<[In32BitMode]>;
398def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
399 "#ADJCALLSTACKUP",
Chris Lattnerfe5d4022008-10-11 22:08:30 +0000400 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
Dan Gohman01c9f772008-10-01 18:28:06 +0000401 Requires<[In32BitMode]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000402}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000403
404// Nop
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000405let neverHasSideEffects = 1 in
406 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000407
Evan Cheng0729ccf2008-01-05 00:41:47 +0000408// PIC base
Dan Gohman9499cfe2008-10-01 04:14:30 +0000409let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000410 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
411 "call\t$label\n\tpop{l}\t$reg", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000412
413//===----------------------------------------------------------------------===//
414// Control Flow Instructions...
415//
416
417// Return instructions.
418let isTerminator = 1, isReturn = 1, isBarrier = 1,
Chris Lattnerb56cc342008-03-11 03:23:40 +0000419 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
Dan Gohman2c4be2a2008-05-31 02:11:25 +0000420 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
Chris Lattnerb56cc342008-03-11 03:23:40 +0000421 "ret",
Dan Gohman2c4be2a2008-05-31 02:11:25 +0000422 [(X86retflag 0)]>;
Chris Lattnerb56cc342008-03-11 03:23:40 +0000423 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
424 "ret\t$amt",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000425 [(X86retflag imm:$amt)]>;
426}
427
428// All branches are RawFrm, Void, Branch, and Terminators
Evan Cheng37e7c752007-07-21 00:34:19 +0000429let isBranch = 1, isTerminator = 1 in
Evan Chengb783fa32007-07-19 01:14:50 +0000430 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
431 I<opcode, RawFrm, (outs), ins, asm, pattern>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000432
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000433let isBranch = 1, isBarrier = 1 in
Dan Gohman91888f02007-07-31 20:11:57 +0000434 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000435
Owen Andersonf8053082007-11-12 07:39:39 +0000436// Indirect branches
437let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
Dan Gohman91888f02007-07-31 20:11:57 +0000438 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000439 [(brind GR32:$dst)]>;
Dan Gohman91888f02007-07-31 20:11:57 +0000440 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000441 [(brind (loadi32 addr:$dst))]>;
442}
443
444// Conditional branches
Evan Cheng950aac02007-09-25 01:57:46 +0000445let Uses = [EFLAGS] in {
Dan Gohman91888f02007-07-31 20:11:57 +0000446def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000447 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000448def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000449 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000450def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000451 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000452def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000453 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000454def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000455 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000456def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000457 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000458
Dan Gohman91888f02007-07-31 20:11:57 +0000459def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000460 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000461def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000462 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000463def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000464 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000465def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000466 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000467
Dan Gohman91888f02007-07-31 20:11:57 +0000468def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000469 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000470def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000471 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000472def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000473 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000474def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000475 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000476def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000477 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
Dan Gohman91888f02007-07-31 20:11:57 +0000478def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +0000479 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
Evan Cheng950aac02007-09-25 01:57:46 +0000480} // Uses = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000481
482//===----------------------------------------------------------------------===//
483// Call Instructions...
484//
Evan Cheng37e7c752007-07-21 00:34:19 +0000485let isCall = 1 in
Dan Gohman01c9f772008-10-01 18:28:06 +0000486 // All calls clobber the non-callee saved registers. ESP is marked as
487 // a use to prevent stack-pointer assignments that appear immediately
488 // before calls from potentially appearing dead. Uses for argument
489 // registers are added manually.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000490 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
491 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
Evan Cheng2293b252008-10-17 21:02:22 +0000492 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
493 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
Dan Gohman9499cfe2008-10-01 04:14:30 +0000494 Uses = [ESP] in {
Evan Cheng34f93712007-12-22 02:26:46 +0000495 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
Dan Gohman2fe209e2009-03-11 23:01:47 +0000496 "call\t${dst:call}", []>;
Evan Chengb783fa32007-07-19 01:14:50 +0000497 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
Dan Gohman91888f02007-07-31 20:11:57 +0000498 "call\t{*}$dst", [(X86call GR32:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000499 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
Dan Gohmanea4faba2008-05-29 21:50:34 +0000500 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000501 }
502
503// Tail call stuff.
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000504
Chris Lattnerb56cc342008-03-11 03:23:40 +0000505def TAILCALL : I<0, Pseudo, (outs), (ins),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000506 "#TAILCALL",
507 []>;
508
Evan Cheng37e7c752007-07-21 00:34:19 +0000509let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer6fd37ac2008-03-19 16:39:45 +0000510def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000511 "#TC_RETURN $dst $offset",
512 []>;
513
514let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer6fd37ac2008-03-19 16:39:45 +0000515def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000516 "#TC_RETURN $dst $offset",
517 []>;
518
519let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofera0032722008-04-30 09:16:33 +0000520
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000521 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000522 []>;
Evan Cheng37e7c752007-07-21 00:34:19 +0000523let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000524 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
525 []>;
Evan Cheng37e7c752007-07-21 00:34:19 +0000526let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Evan Chengb783fa32007-07-19 01:14:50 +0000527 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +0000528 "jmp\t{*}$dst # TAILCALL", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000529
530//===----------------------------------------------------------------------===//
531// Miscellaneous Instructions...
532//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000533let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000534def LEAVE : I<0xC9, RawFrm,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000535 (outs), (ins), "leave", []>;
536
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000537let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
538let mayLoad = 1 in
Evan Chengd8434332007-09-26 01:29:06 +0000539def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000540
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000541let mayStore = 1 in
Evan Chengd8434332007-09-26 01:29:06 +0000542def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000543}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000544
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000545let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
Evan Chengf1341312007-09-26 21:28:00 +0000546def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000547let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
Evan Chengf1341312007-09-26 21:28:00 +0000548def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
Evan Chengd8434332007-09-26 01:29:06 +0000549
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000550let isTwoAddress = 1 in // GR32 = bswap GR32
551 def BSWAP32r : I<0xC8, AddRegFrm,
Evan Chengb783fa32007-07-19 01:14:50 +0000552 (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000553 "bswap{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000554 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
555
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000556
Evan Cheng48679f42007-12-14 02:13:44 +0000557// Bit scan instructions.
558let Defs = [EFLAGS] in {
Evan Cheng4e33de92007-12-14 18:49:43 +0000559def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000560 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000561 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000562def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000563 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000564 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
565 (implicit EFLAGS)]>, TB;
Evan Cheng4e33de92007-12-14 18:49:43 +0000566def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000567 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000568 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000569def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000570 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000571 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
572 (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000573
Evan Cheng4e33de92007-12-14 18:49:43 +0000574def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000575 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000576 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000577def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000578 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000579 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
580 (implicit EFLAGS)]>, TB;
Evan Cheng4e33de92007-12-14 18:49:43 +0000581def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000582 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000583 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000584def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohmancdb54c62007-12-14 15:10:00 +0000585 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng7cfbfe32007-12-14 08:30:15 +0000586 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
587 (implicit EFLAGS)]>, TB;
Evan Cheng48679f42007-12-14 02:13:44 +0000588} // Defs = [EFLAGS]
589
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000590let neverHasSideEffects = 1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000591def LEA16r : I<0x8D, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +0000592 (outs GR16:$dst), (ins i32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000593 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
Evan Cheng1ea8e6b2008-03-27 01:41:09 +0000594let isReMaterializable = 1 in
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000595def LEA32r : I<0x8D, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +0000596 (outs GR32:$dst), (ins lea32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000597 "lea{l}\t{$src|$dst}, {$dst|$src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000598 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
599
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000600let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
Evan Chengb783fa32007-07-19 01:14:50 +0000601def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000602 [(X86rep_movs i8)]>, REP;
Evan Chengb783fa32007-07-19 01:14:50 +0000603def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000604 [(X86rep_movs i16)]>, REP, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000605def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000606 [(X86rep_movs i32)]>, REP;
607}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000608
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000609let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000610def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000611 [(X86rep_stos i8)]>, REP;
612let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000613def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000614 [(X86rep_stos i16)]>, REP, OpSize;
615let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
Evan Chengb783fa32007-07-19 01:14:50 +0000616def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000617 [(X86rep_stos i32)]>, REP;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000618
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000619let Defs = [RAX, RDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000620def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000621 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000622
Anton Korobeynikov39d40ba2008-01-15 07:02:33 +0000623let isBarrier = 1, hasCtrlDep = 1 in {
Chris Lattner56b941f2008-01-15 21:58:22 +0000624def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
Anton Korobeynikov39d40ba2008-01-15 07:02:33 +0000625}
626
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000627//===----------------------------------------------------------------------===//
628// Input/Output Instructions...
629//
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000630let Defs = [AL], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000631def IN8rr : I<0xEC, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000632 "in{b}\t{%dx, %al|%AL, %DX}", []>;
633let Defs = [AX], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000634def IN16rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000635 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
636let Defs = [EAX], Uses = [DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000637def IN32rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000638 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000639
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000640let Defs = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000641def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000642 "in{b}\t{$port, %al|%AL, $port}", []>;
643let Defs = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000644def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000645 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
646let Defs = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000647def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000648 "in{l}\t{$port, %eax|%EAX, $port}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000649
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000650let Uses = [DX, AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000651def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000652 "out{b}\t{%al, %dx|%DX, %AL}", []>;
653let Uses = [DX, AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000654def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000655 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
656let Uses = [DX, EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000657def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000658 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000659
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000660let Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000661def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000662 "out{b}\t{%al, $port|$port, %AL}", []>;
663let Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000664def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000665 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
666let Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000667def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000668 "out{l}\t{%eax, $port|$port, %EAX}", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000669
670//===----------------------------------------------------------------------===//
671// Move Instructions...
672//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000673let neverHasSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000674def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000675 "mov{b}\t{$src, $dst|$dst, $src}", []>;
Evan Chengb783fa32007-07-19 01:14:50 +0000676def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000677 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000678def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000679 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000680}
Evan Cheng6f26e8b2008-06-18 08:13:07 +0000681let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000682def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000683 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000684 [(set GR8:$dst, imm:$src)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000685def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000686 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000687 [(set GR16:$dst, imm:$src)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000688def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000689 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000690 [(set GR32:$dst, imm:$src)]>;
691}
Evan Chengb783fa32007-07-19 01:14:50 +0000692def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000693 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000694 [(store (i8 imm:$src), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000695def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000696 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000697 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000698def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000699 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000700 [(store (i32 imm:$src), addr:$dst)]>;
701
Dan Gohman5574cc72008-12-03 18:15:48 +0000702let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +0000703def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000704 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000705 [(set GR8:$dst, (load addr:$src))]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000706def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000707 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000708 [(set GR16:$dst, (load addr:$src))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000709def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000710 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000711 [(set GR32:$dst, (load addr:$src))]>;
Evan Cheng4e84e452007-08-30 05:49:43 +0000712}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000713
Evan Chengb783fa32007-07-19 01:14:50 +0000714def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000715 "mov{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000716 [(store GR8:$src, addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +0000717def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000718 "mov{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000719 [(store GR16:$src, addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +0000720def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000721 "mov{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000722 [(store GR32:$src, addr:$dst)]>;
723
724//===----------------------------------------------------------------------===//
725// Fixed-Register Multiplication and Division Instructions...
726//
727
728// Extra precision multiplication
Evan Cheng55687072007-09-14 21:48:26 +0000729let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Dan Gohman91888f02007-07-31 20:11:57 +0000730def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000731 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
732 // This probably ought to be moved to a def : Pat<> if the
733 // syntax can be accepted.
Bill Wendlingf5399032008-12-12 21:15:41 +0000734 [(set AL, (mul AL, GR8:$src)),
735 (implicit EFLAGS)]>; // AL,AH = AL*GR8
736
Chris Lattnerc7e96e72008-01-11 07:18:17 +0000737let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
Bill Wendlingf5399032008-12-12 21:15:41 +0000738def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
739 "mul{w}\t$src",
740 []>, OpSize; // AX,DX = AX*GR16
741
Chris Lattnerc7e96e72008-01-11 07:18:17 +0000742let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
Bill Wendlingf5399032008-12-12 21:15:41 +0000743def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
744 "mul{l}\t$src",
745 []>; // EAX,EDX = EAX*GR32
746
Evan Cheng55687072007-09-14 21:48:26 +0000747let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000748def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +0000749 "mul{b}\t$src",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000750 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
751 // This probably ought to be moved to a def : Pat<> if the
752 // syntax can be accepted.
Bill Wendlingf5399032008-12-12 21:15:41 +0000753 [(set AL, (mul AL, (loadi8 addr:$src))),
754 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
755
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000756let mayLoad = 1, neverHasSideEffects = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000757let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000758def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
Bill Wendlingf5399032008-12-12 21:15:41 +0000759 "mul{w}\t$src",
760 []>, OpSize; // AX,DX = AX*[mem16]
761
Evan Cheng55687072007-09-14 21:48:26 +0000762let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000763def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
Bill Wendlingf5399032008-12-12 21:15:41 +0000764 "mul{l}\t$src",
765 []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000766}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000767
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000768let neverHasSideEffects = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000769let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000770def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
771 // AL,AH = AL*GR8
Evan Cheng55687072007-09-14 21:48:26 +0000772let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Dan Gohman91888f02007-07-31 20:11:57 +0000773def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000774 OpSize; // AX,DX = AX*GR16
Evan Cheng55687072007-09-14 21:48:26 +0000775let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000776def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
777 // EAX,EDX = EAX*GR32
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000778let mayLoad = 1 in {
Evan Cheng55687072007-09-14 21:48:26 +0000779let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Chengb783fa32007-07-19 01:14:50 +0000780def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000781 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
Evan Cheng55687072007-09-14 21:48:26 +0000782let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000783def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000784 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
785let Defs = [EAX,EDX], Uses = [EAX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000786def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000787 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000788}
Dan Gohmand44572d2008-11-18 21:29:14 +0000789} // neverHasSideEffects
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000790
791// unsigned division/remainder
Dale Johannesend8fd3562008-10-07 18:54:28 +0000792let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000793def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000794 "div{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000795let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000796def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000797 "div{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000798let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000799def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000800 "div{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000801let mayLoad = 1 in {
Dale Johannesend8fd3562008-10-07 18:54:28 +0000802let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000803def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000804 "div{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000805let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000806def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000807 "div{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000808let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000809def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000810 "div{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000811}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000812
813// Signed division/remainder.
Dale Johannesend8fd3562008-10-07 18:54:28 +0000814let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000815def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000816 "idiv{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000817let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000818def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000819 "idiv{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000820let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000821def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000822 "idiv{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000823let mayLoad = 1, mayLoad = 1 in {
Dale Johannesend8fd3562008-10-07 18:54:28 +0000824let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000825def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000826 "idiv{b}\t$src", []>;
Evan Cheng55687072007-09-14 21:48:26 +0000827let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000828def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000829 "idiv{w}\t$src", []>, OpSize;
Evan Cheng55687072007-09-14 21:48:26 +0000830let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Chengb783fa32007-07-19 01:14:50 +0000831def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng6e4d1d92007-09-11 19:55:27 +0000832 "idiv{l}\t$src", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000833}
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000834
835//===----------------------------------------------------------------------===//
Chris Lattnerc90ee9c2008-01-10 07:59:24 +0000836// Two address Instructions.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000837//
838let isTwoAddress = 1 in {
839
840// Conditional moves
Evan Cheng950aac02007-09-25 01:57:46 +0000841let Uses = [EFLAGS] in {
Evan Cheng926658c2007-10-05 23:13:21 +0000842let isCommutable = 1 in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000843def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000844 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000845 "cmovb\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000846 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000847 X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000848 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000849def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000850 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000851 "cmovb\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000852 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000853 X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000854 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000855def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000856 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000857 "cmovae\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000858 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000859 X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000860 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000861def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000862 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000863 "cmovae\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000864 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000865 X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000866 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000867def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000868 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000869 "cmove\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000870 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000871 X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000872 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000873def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000874 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000875 "cmove\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000876 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000877 X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000878 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000879def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000880 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000881 "cmovne\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000882 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000883 X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000884 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000885def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000886 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000887 "cmovne\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000888 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000889 X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000890 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000891def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000892 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000893 "cmovbe\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000894 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000895 X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000896 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000897def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000898 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000899 "cmovbe\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000900 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000901 X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000902 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000903def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000904 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000905 "cmova\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000906 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000907 X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000908 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000909def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000910 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000911 "cmova\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000912 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000913 X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000914 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000915def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000916 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000917 "cmovl\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000918 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000919 X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000920 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000921def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000922 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000923 "cmovl\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000924 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000925 X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000926 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000927def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000928 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000929 "cmovge\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000930 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000931 X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000932 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000933def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000934 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000935 "cmovge\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000936 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000937 X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000938 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000939def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000940 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000941 "cmovle\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000942 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000943 X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000944 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000945def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000946 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000947 "cmovle\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000948 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000949 X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000950 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000951def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000952 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000953 "cmovg\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000954 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000955 X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000956 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000957def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000958 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000959 "cmovg\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000960 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000961 X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000962 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000963def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000964 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000965 "cmovs\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000966 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000967 X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000968 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000969def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000970 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000971 "cmovs\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000972 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000973 X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000974 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000975def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000976 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000977 "cmovns\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000978 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000979 X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000980 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000981def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000982 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000983 "cmovns\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000984 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000985 X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000986 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000987def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +0000988 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000989 "cmovp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000990 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000991 X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000992 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000993def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +0000994 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +0000995 "cmovp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000996 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +0000997 X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000998 TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000999def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
Evan Chengb783fa32007-07-19 01:14:50 +00001000 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001001 "cmovnp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001002 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001003 X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001004 TB, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001005def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
Evan Chengb783fa32007-07-19 01:14:50 +00001006 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001007 "cmovnp\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001008 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Cheng621216e2007-09-29 00:00:36 +00001009 X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001010 TB;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001011def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1012 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1013 "cmovo\t{$src2, $dst|$dst, $src2}",
1014 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1015 X86_COND_O, EFLAGS))]>,
1016 TB, OpSize;
1017def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1018 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1019 "cmovo\t{$src2, $dst|$dst, $src2}",
1020 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1021 X86_COND_O, EFLAGS))]>,
Evan Cheng950aac02007-09-25 01:57:46 +00001022 TB;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001023def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1024 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1025 "cmovno\t{$src2, $dst|$dst, $src2}",
1026 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1027 X86_COND_NO, EFLAGS))]>,
1028 TB, OpSize;
1029def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1030 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1031 "cmovno\t{$src2, $dst|$dst, $src2}",
1032 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1033 X86_COND_NO, EFLAGS))]>,
1034 TB;
1035} // isCommutable = 1
Evan Cheng926658c2007-10-05 23:13:21 +00001036
1037def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1038 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1039 "cmovb\t{$src2, $dst|$dst, $src2}",
1040 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1041 X86_COND_B, EFLAGS))]>,
1042 TB, OpSize;
1043def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1044 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1045 "cmovb\t{$src2, $dst|$dst, $src2}",
1046 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1047 X86_COND_B, EFLAGS))]>,
1048 TB;
1049def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1050 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1051 "cmovae\t{$src2, $dst|$dst, $src2}",
1052 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1053 X86_COND_AE, EFLAGS))]>,
1054 TB, OpSize;
1055def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1056 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1057 "cmovae\t{$src2, $dst|$dst, $src2}",
1058 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1059 X86_COND_AE, EFLAGS))]>,
1060 TB;
1061def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1062 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1063 "cmove\t{$src2, $dst|$dst, $src2}",
1064 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1065 X86_COND_E, EFLAGS))]>,
1066 TB, OpSize;
1067def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1068 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1069 "cmove\t{$src2, $dst|$dst, $src2}",
1070 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1071 X86_COND_E, EFLAGS))]>,
1072 TB;
1073def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1074 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1075 "cmovne\t{$src2, $dst|$dst, $src2}",
1076 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1077 X86_COND_NE, EFLAGS))]>,
1078 TB, OpSize;
1079def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1080 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1081 "cmovne\t{$src2, $dst|$dst, $src2}",
1082 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1083 X86_COND_NE, EFLAGS))]>,
1084 TB;
1085def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1086 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1087 "cmovbe\t{$src2, $dst|$dst, $src2}",
1088 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1089 X86_COND_BE, EFLAGS))]>,
1090 TB, OpSize;
1091def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1092 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1093 "cmovbe\t{$src2, $dst|$dst, $src2}",
1094 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1095 X86_COND_BE, EFLAGS))]>,
1096 TB;
1097def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1098 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1099 "cmova\t{$src2, $dst|$dst, $src2}",
1100 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1101 X86_COND_A, EFLAGS))]>,
1102 TB, OpSize;
1103def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1104 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1105 "cmova\t{$src2, $dst|$dst, $src2}",
1106 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1107 X86_COND_A, EFLAGS))]>,
1108 TB;
1109def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1110 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1111 "cmovl\t{$src2, $dst|$dst, $src2}",
1112 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1113 X86_COND_L, EFLAGS))]>,
1114 TB, OpSize;
1115def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1116 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1117 "cmovl\t{$src2, $dst|$dst, $src2}",
1118 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1119 X86_COND_L, EFLAGS))]>,
1120 TB;
1121def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1122 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1123 "cmovge\t{$src2, $dst|$dst, $src2}",
1124 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1125 X86_COND_GE, EFLAGS))]>,
1126 TB, OpSize;
1127def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1128 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1129 "cmovge\t{$src2, $dst|$dst, $src2}",
1130 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1131 X86_COND_GE, EFLAGS))]>,
1132 TB;
1133def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1134 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1135 "cmovle\t{$src2, $dst|$dst, $src2}",
1136 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1137 X86_COND_LE, EFLAGS))]>,
1138 TB, OpSize;
1139def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1140 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1141 "cmovle\t{$src2, $dst|$dst, $src2}",
1142 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1143 X86_COND_LE, EFLAGS))]>,
1144 TB;
1145def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1146 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1147 "cmovg\t{$src2, $dst|$dst, $src2}",
1148 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1149 X86_COND_G, EFLAGS))]>,
1150 TB, OpSize;
1151def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1152 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1153 "cmovg\t{$src2, $dst|$dst, $src2}",
1154 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1155 X86_COND_G, EFLAGS))]>,
1156 TB;
1157def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1158 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1159 "cmovs\t{$src2, $dst|$dst, $src2}",
1160 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1161 X86_COND_S, EFLAGS))]>,
1162 TB, OpSize;
1163def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1164 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1165 "cmovs\t{$src2, $dst|$dst, $src2}",
1166 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1167 X86_COND_S, EFLAGS))]>,
1168 TB;
1169def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1170 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1171 "cmovns\t{$src2, $dst|$dst, $src2}",
1172 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1173 X86_COND_NS, EFLAGS))]>,
1174 TB, OpSize;
1175def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1176 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1177 "cmovns\t{$src2, $dst|$dst, $src2}",
1178 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1179 X86_COND_NS, EFLAGS))]>,
1180 TB;
1181def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1182 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1183 "cmovp\t{$src2, $dst|$dst, $src2}",
1184 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1185 X86_COND_P, EFLAGS))]>,
1186 TB, OpSize;
1187def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1188 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1189 "cmovp\t{$src2, $dst|$dst, $src2}",
1190 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1191 X86_COND_P, EFLAGS))]>,
1192 TB;
1193def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1194 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1195 "cmovnp\t{$src2, $dst|$dst, $src2}",
1196 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1197 X86_COND_NP, EFLAGS))]>,
1198 TB, OpSize;
Dan Gohman12fd4d72009-01-07 00:35:10 +00001199def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1200 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1201 "cmovnp\t{$src2, $dst|$dst, $src2}",
1202 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1203 X86_COND_NP, EFLAGS))]>,
1204 TB;
1205def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1206 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1207 "cmovo\t{$src2, $dst|$dst, $src2}",
1208 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1209 X86_COND_O, EFLAGS))]>,
1210 TB, OpSize;
1211def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1212 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1213 "cmovo\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1215 X86_COND_O, EFLAGS))]>,
1216 TB;
1217def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1218 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1219 "cmovno\t{$src2, $dst|$dst, $src2}",
1220 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1221 X86_COND_NO, EFLAGS))]>,
1222 TB, OpSize;
1223def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1224 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1225 "cmovno\t{$src2, $dst|$dst, $src2}",
1226 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1227 X86_COND_NO, EFLAGS))]>,
1228 TB;
Evan Cheng950aac02007-09-25 01:57:46 +00001229} // Uses = [EFLAGS]
1230
1231
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001232// unary instructions
1233let CodeSize = 2 in {
Evan Cheng55687072007-09-14 21:48:26 +00001234let Defs = [EFLAGS] in {
Dan Gohman91888f02007-07-31 20:11:57 +00001235def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001236 [(set GR8:$dst, (ineg GR8:$src)),
1237 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001238def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001239 [(set GR16:$dst, (ineg GR16:$src)),
1240 (implicit EFLAGS)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001241def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001242 [(set GR32:$dst, (ineg GR32:$src)),
1243 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001244let isTwoAddress = 0 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001245 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001246 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1247 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001248 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001249 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1250 (implicit EFLAGS)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001251 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001252 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1253 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001254}
Evan Cheng55687072007-09-14 21:48:26 +00001255} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001256
Evan Chengc6cee682009-01-21 02:09:05 +00001257// Match xor -1 to not. Favors these over a move imm + xor to save code size.
1258let AddedComplexity = 15 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001259def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001260 [(set GR8:$dst, (not GR8:$src))]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001261def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001262 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001263def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001264 [(set GR32:$dst, (not GR32:$src))]>;
Evan Chengc6cee682009-01-21 02:09:05 +00001265}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001266let isTwoAddress = 0 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001267 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001268 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001269 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001270 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
Dan Gohman91888f02007-07-31 20:11:57 +00001271 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001272 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1273}
1274} // CodeSize
1275
1276// TODO: inc/dec is slow for P4, but fast for Pentium-M.
Evan Cheng55687072007-09-14 21:48:26 +00001277let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001278let CodeSize = 2 in
Dan Gohman91888f02007-07-31 20:11:57 +00001279def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001280 [(set GR8:$dst, (add GR8:$src, 1)),
1281 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001282let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohman91888f02007-07-31 20:11:57 +00001283def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001284 [(set GR16:$dst, (add GR16:$src, 1)),
1285 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001286 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001287def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001288 [(set GR32:$dst, (add GR32:$src, 1)),
1289 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001290}
1291let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001292 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001293 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1294 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001295 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001296 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1297 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001298 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001299 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001300 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1301 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001302 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001303}
1304
1305let CodeSize = 2 in
Dan Gohman91888f02007-07-31 20:11:57 +00001306def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001307 [(set GR8:$dst, (add GR8:$src, -1)),
1308 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001309let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohman91888f02007-07-31 20:11:57 +00001310def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001311 [(set GR16:$dst, (add GR16:$src, -1)),
1312 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001313 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001314def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001315 [(set GR32:$dst, (add GR32:$src, -1)),
1316 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001317}
1318
1319let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohman91888f02007-07-31 20:11:57 +00001320 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001321 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1322 (implicit EFLAGS)]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001323 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001324 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1325 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001326 OpSize, Requires<[In32BitMode]>;
Dan Gohman91888f02007-07-31 20:11:57 +00001327 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001328 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1329 (implicit EFLAGS)]>,
Evan Cheng4a7e72f2007-10-19 21:23:22 +00001330 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001331}
Evan Cheng55687072007-09-14 21:48:26 +00001332} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001333
1334// Logical operators...
Evan Cheng55687072007-09-14 21:48:26 +00001335let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001336let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1337def AND8rr : I<0x20, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001338 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001339 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001340 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1341 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001342def AND16rr : I<0x21, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001343 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001344 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001345 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1346 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001347def AND32rr : I<0x21, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00001348 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001349 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001350 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1351 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001352}
1353
1354def AND8rm : I<0x22, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001355 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001356 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001357 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
1358 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001359def AND16rm : I<0x23, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001360 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001361 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001362 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
1363 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001364def AND32rm : I<0x23, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001365 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001366 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001367 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2))),
1368 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001369
1370def AND8ri : Ii8<0x80, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001371 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001372 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001373 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1374 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001375def AND16ri : Ii16<0x81, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001376 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001377 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001378 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1379 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001380def AND32ri : Ii32<0x81, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001381 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001382 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001383 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1384 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001385def AND16ri8 : Ii8<0x83, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001386 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001387 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001388 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1389 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001390 OpSize;
1391def AND32ri8 : Ii8<0x83, MRM4r,
Evan Chengb783fa32007-07-19 01:14:50 +00001392 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001393 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001394 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1395 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001396
1397let isTwoAddress = 0 in {
1398 def AND8mr : I<0x20, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001399 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001400 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001401 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1402 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001403 def AND16mr : I<0x21, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001404 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001405 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001406 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1407 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001408 OpSize;
1409 def AND32mr : I<0x21, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001410 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001411 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001412 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1413 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001414 def AND8mi : Ii8<0x80, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001415 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001416 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001417 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1418 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001419 def AND16mi : Ii16<0x81, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001420 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001421 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001422 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1423 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001424 OpSize;
1425 def AND32mi : Ii32<0x81, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001426 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001427 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001428 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1429 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001430 def AND16mi8 : Ii8<0x83, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001431 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001432 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001433 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1434 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001435 OpSize;
1436 def AND32mi8 : Ii8<0x83, MRM4m,
Evan Chengb783fa32007-07-19 01:14:50 +00001437 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001438 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001439 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1440 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001441}
1442
1443
1444let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
Evan Chengb783fa32007-07-19 01:14:50 +00001445def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001446 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001447 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1448 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001449def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001450 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001451 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1452 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001453def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001454 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001455 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1456 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001457}
Evan Chengb783fa32007-07-19 01:14:50 +00001458def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001459 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001460 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1461 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001462def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001463 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001464 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1465 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001466def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001467 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001468 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1469 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001470
Evan Chengb783fa32007-07-19 01:14:50 +00001471def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001472 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001473 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1474 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001475def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001476 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001477 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1478 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001479def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001480 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001481 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1482 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001483
Evan Chengb783fa32007-07-19 01:14:50 +00001484def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001485 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001486 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1487 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001488def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001489 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001490 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1491 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001492let isTwoAddress = 0 in {
Evan Chengb783fa32007-07-19 01:14:50 +00001493 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001494 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001495 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1496 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001497 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001498 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001499 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1500 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001501 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001502 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001503 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1504 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001505 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001506 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001507 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1508 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001509 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001510 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001511 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1512 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001513 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001514 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001515 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001516 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1517 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001518 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001519 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001520 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1521 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001522 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001523 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001524 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001525 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1526 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001527} // isTwoAddress = 0
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001528
1529
Evan Cheng6f26e8b2008-06-18 08:13:07 +00001530let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001531 def XOR8rr : I<0x30, MRMDestReg,
1532 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1533 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001534 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1535 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001536 def XOR16rr : I<0x31, MRMDestReg,
1537 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1538 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001539 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1540 (implicit EFLAGS)]>, OpSize;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001541 def XOR32rr : I<0x31, MRMDestReg,
1542 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1543 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001544 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1545 (implicit EFLAGS)]>;
Evan Cheng6f26e8b2008-06-18 08:13:07 +00001546} // isCommutable = 1
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001547
1548def XOR8rm : I<0x32, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001549 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001550 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001551 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1552 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001553def XOR16rm : I<0x33, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001554 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001555 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001556 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1557 (implicit EFLAGS)]>,
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001558 OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001559def XOR32rm : I<0x33, MRMSrcMem ,
Evan Chengb783fa32007-07-19 01:14:50 +00001560 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001561 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001562 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1563 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001564
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001565def XOR8ri : Ii8<0x80, MRM6r,
1566 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1567 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001568 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1569 (implicit EFLAGS)]>;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001570def XOR16ri : Ii16<0x81, MRM6r,
1571 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1572 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001573 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1574 (implicit EFLAGS)]>, OpSize;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001575def XOR32ri : Ii32<0x81, MRM6r,
1576 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1577 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001578 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1579 (implicit EFLAGS)]>;
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001580def XOR16ri8 : Ii8<0x83, MRM6r,
1581 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1582 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001583 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1584 (implicit EFLAGS)]>,
Bill Wendlingbac38eb2008-05-29 03:46:36 +00001585 OpSize;
1586def XOR32ri8 : Ii8<0x83, MRM6r,
1587 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1588 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001589 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1590 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001591
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001592let isTwoAddress = 0 in {
1593 def XOR8mr : I<0x30, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001594 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001595 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001596 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1597 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001598 def XOR16mr : I<0x31, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001599 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001600 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001601 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1602 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001603 OpSize;
1604 def XOR32mr : I<0x31, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00001605 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001606 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001607 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1608 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001609 def XOR8mi : Ii8<0x80, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001610 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001611 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001612 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1613 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001614 def XOR16mi : Ii16<0x81, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001615 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001616 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001617 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1618 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001619 OpSize;
1620 def XOR32mi : Ii32<0x81, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001621 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001622 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001623 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1624 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001625 def XOR16mi8 : Ii8<0x83, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001626 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001627 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001628 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1629 (implicit EFLAGS)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001630 OpSize;
1631 def XOR32mi8 : Ii8<0x83, MRM6m,
Evan Chengb783fa32007-07-19 01:14:50 +00001632 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001633 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman7b93f1c2009-03-03 19:53:46 +00001634 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1635 (implicit EFLAGS)]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001636} // isTwoAddress = 0
Evan Cheng55687072007-09-14 21:48:26 +00001637} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001638
1639// Shift instructions
Evan Cheng55687072007-09-14 21:48:26 +00001640let Defs = [EFLAGS] in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001641let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001642def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001643 "shl{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001644 [(set GR8:$dst, (shl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001645def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001646 "shl{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001647 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001648def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001649 "shl{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001650 [(set GR32:$dst, (shl GR32:$src, CL))]>;
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001651} // Uses = [CL]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001652
Evan Chengb783fa32007-07-19 01:14:50 +00001653def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001654 "shl{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001655 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1656let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Evan Chengb783fa32007-07-19 01:14:50 +00001657def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001658 "shl{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001659 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001660def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001661 "shl{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001662 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattnerf4005a82008-01-11 18:00:50 +00001663// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1664// cheaper.
Bill Wendlingba5d5b02008-05-29 01:02:09 +00001665} // isConvertibleToThreeAddress = 1
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001666
1667let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001668 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001669 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001670 "shl{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001671 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001672 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001673 "shl{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001674 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001675 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001676 "shl{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001677 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1678 }
Evan Chengb783fa32007-07-19 01:14:50 +00001679 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001680 "shl{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001681 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001682 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001683 "shl{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001684 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1685 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001686 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001687 "shl{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001688 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1689
1690 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001691 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001692 "shl{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001693 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001694 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001695 "shl{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001696 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1697 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001698 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001699 "shl{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001700 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1701}
1702
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001703let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001704def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001705 "shr{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001706 [(set GR8:$dst, (srl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001707def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001708 "shr{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001709 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001710def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001711 "shr{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001712 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1713}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001714
Evan Chengb783fa32007-07-19 01:14:50 +00001715def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001716 "shr{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001717 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001718def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001719 "shr{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001720 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001721def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001722 "shr{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001723 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1724
1725// Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001726def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001727 "shr{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001728 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001729def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001730 "shr{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001731 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001732def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001733 "shr{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001734 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1735
1736let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001737 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001738 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001739 "shr{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001740 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001741 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001742 "shr{w}\t{%cl, $dst|$dst, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001743 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001744 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001745 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001746 "shr{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001747 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1748 }
Evan Chengb783fa32007-07-19 01:14:50 +00001749 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001750 "shr{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001751 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001752 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001753 "shr{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001754 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1755 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001756 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001757 "shr{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001758 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1759
1760 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001761 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001762 "shr{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001763 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001764 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001765 "shr{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001766 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001767 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001768 "shr{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001769 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1770}
1771
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001772let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001773def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001774 "sar{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001775 [(set GR8:$dst, (sra GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001776def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001777 "sar{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001778 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001779def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001780 "sar{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001781 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1782}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001783
Evan Chengb783fa32007-07-19 01:14:50 +00001784def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001785 "sar{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001786 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001787def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001788 "sar{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001789 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1790 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001791def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001792 "sar{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001793 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1794
1795// Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001796def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001797 "sar{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001798 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001799def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001800 "sar{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001801 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001802def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001803 "sar{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001804 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1805
1806let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001807 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001808 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001809 "sar{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001810 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001811 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001812 "sar{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001813 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001814 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001815 "sar{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001816 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1817 }
Evan Chengb783fa32007-07-19 01:14:50 +00001818 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001819 "sar{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001820 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001821 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001822 "sar{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001823 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1824 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001825 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001826 "sar{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001827 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1828
1829 // Shift by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001830 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001831 "sar{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001832 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001833 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001834 "sar{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001835 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1836 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001837 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001838 "sar{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001839 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1840}
1841
1842// Rotate instructions
1843// FIXME: provide shorter instructions when imm8 == 1
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001844let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001845def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001846 "rol{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001847 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001848def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001849 "rol{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001850 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001851def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001852 "rol{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001853 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1854}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001855
Evan Chengb783fa32007-07-19 01:14:50 +00001856def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001857 "rol{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001858 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001859def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001860 "rol{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001861 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001862def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001863 "rol{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001864 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1865
1866// Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001867def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001868 "rol{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001869 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001870def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001871 "rol{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001872 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001873def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001874 "rol{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001875 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1876
1877let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001878 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001879 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001880 "rol{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001881 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001882 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001883 "rol{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001884 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001885 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001886 "rol{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001887 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1888 }
Evan Chengb783fa32007-07-19 01:14:50 +00001889 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001890 "rol{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001891 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001892 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001893 "rol{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001894 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1895 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001896 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001897 "rol{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001898 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1899
1900 // Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001901 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001902 "rol{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001903 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001904 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001905 "rol{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001906 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1907 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001908 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001909 "rol{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001910 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1911}
1912
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001913let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001914def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001915 "ror{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001916 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001917def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001918 "ror{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001919 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001920def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001921 "ror{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001922 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
1923}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001924
Evan Chengb783fa32007-07-19 01:14:50 +00001925def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001926 "ror{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001927 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001928def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001929 "ror{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001930 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001931def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001932 "ror{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001933 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1934
1935// Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001936def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001937 "ror{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001938 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001939def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001940 "ror{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001941 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001942def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohman91888f02007-07-31 20:11:57 +00001943 "ror{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001944 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1945
1946let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001947 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001948 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001949 "ror{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001950 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001951 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001952 "ror{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001953 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001954 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001955 "ror{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001956 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
1957 }
Evan Chengb783fa32007-07-19 01:14:50 +00001958 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001959 "ror{b}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001960 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001961 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001962 "ror{w}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001963 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1964 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001965 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00001966 "ror{l}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001967 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1968
1969 // Rotate by 1
Evan Chengb783fa32007-07-19 01:14:50 +00001970 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001971 "ror{b}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001972 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00001973 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001974 "ror{w}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001975 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1976 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001977 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00001978 "ror{l}\t$dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001979 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1980}
1981
1982
1983
1984// Double shift instructions (generalizations of rotate)
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001985let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00001986def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001987 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001988 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00001989def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001990 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001991 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00001992def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001993 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001994 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001995 TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00001996def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00001997 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001998 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng6e4d1d92007-09-11 19:55:27 +00001999 TB, OpSize;
2000}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002001
2002let isCommutable = 1 in { // These instructions commute to each other.
2003def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002004 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002005 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002006 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2007 (i8 imm:$src3)))]>,
2008 TB;
2009def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002010 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002011 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002012 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2013 (i8 imm:$src3)))]>,
2014 TB;
2015def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002016 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002017 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002018 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2019 (i8 imm:$src3)))]>,
2020 TB, OpSize;
2021def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002022 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002023 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002024 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2025 (i8 imm:$src3)))]>,
2026 TB, OpSize;
2027}
2028
2029let isTwoAddress = 0 in {
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002030 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002031 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002032 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002033 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002034 addr:$dst)]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002035 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002036 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002037 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002038 addr:$dst)]>, TB;
2039 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002040 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002041 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002042 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002043 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2044 (i8 imm:$src3)), addr:$dst)]>,
2045 TB;
2046 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002047 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002048 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002049 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2050 (i8 imm:$src3)), addr:$dst)]>,
2051 TB;
2052
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002053 let Uses = [CL] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002054 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002055 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002056 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002057 addr:$dst)]>, TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002058 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002059 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002060 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002061 addr:$dst)]>, TB, OpSize;
2062 }
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002063 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002064 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002065 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002066 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2067 (i8 imm:$src3)), addr:$dst)]>,
2068 TB, OpSize;
2069 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002070 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohman91888f02007-07-31 20:11:57 +00002071 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002072 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2073 (i8 imm:$src3)), addr:$dst)]>,
2074 TB, OpSize;
2075}
Evan Cheng55687072007-09-14 21:48:26 +00002076} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002077
2078
2079// Arithmetic.
Evan Cheng55687072007-09-14 21:48:26 +00002080let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002081let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
Bill Wendlingae034ed2008-12-12 00:56:36 +00002082// Register-Register Addition
2083def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2084 (ins GR8 :$src1, GR8 :$src2),
2085 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002086 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
Bill Wendlingae034ed2008-12-12 00:56:36 +00002087 (implicit EFLAGS)]>;
2088
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002089let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingae034ed2008-12-12 00:56:36 +00002090// Register-Register Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002091def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2092 (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002093 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002094 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2095 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002096def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2097 (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002098 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002099 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2100 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002101} // end isConvertibleToThreeAddress
2102} // end isCommutable
Bill Wendlingae034ed2008-12-12 00:56:36 +00002103
2104// Register-Memory Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002105def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2106 (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002107 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002108 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2109 (implicit EFLAGS)]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002110def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2111 (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002112 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002113 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2114 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002115def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2116 (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002117 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002118 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2119 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002120
Bill Wendlingae034ed2008-12-12 00:56:36 +00002121// Register-Integer Addition
2122def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2123 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002124 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2125 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002126
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002127let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingae034ed2008-12-12 00:56:36 +00002128// Register-Integer Addition
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002129def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2130 (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002131 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002132 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2133 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002134def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2135 (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002136 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002137 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2138 (implicit EFLAGS)]>;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002139def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2140 (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002141 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002142 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2143 (implicit EFLAGS)]>, OpSize;
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002144def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2145 (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002146 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002147 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2148 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002149}
2150
2151let isTwoAddress = 0 in {
Bill Wendlingae034ed2008-12-12 00:56:36 +00002152 // Memory-Register Addition
Bill Wendlingf5399032008-12-12 21:15:41 +00002153 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002154 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002155 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2156 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002157 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002158 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002159 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2160 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002161 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002162 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002163 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2164 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002165 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002166 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002167 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2168 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002169 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002170 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002171 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2172 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002173 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002174 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002175 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2176 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002177 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002178 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002179 [(store (add (load addr:$dst), i16immSExt8:$src2),
2180 addr:$dst),
2181 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002182 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002183 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002184 [(store (add (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002185 addr:$dst),
2186 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002187}
2188
Evan Cheng259471d2007-10-05 17:59:57 +00002189let Uses = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002190let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
Evan Chengb783fa32007-07-19 01:14:50 +00002191def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002192 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002193 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002194}
Evan Chengb783fa32007-07-19 01:14:50 +00002195def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002196 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002197 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002198def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002199 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002200 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002201def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002202 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002203 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002204
2205let isTwoAddress = 0 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002206 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002207 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002208 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002209 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002210 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingc0ca7f32008-12-01 23:44:08 +00002211 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002212 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002213 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002214 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002215}
Evan Cheng259471d2007-10-05 17:59:57 +00002216} // Uses = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002217
Bill Wendlingae034ed2008-12-12 00:56:36 +00002218// Register-Register Subtraction
2219def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2220 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002221 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2222 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002223def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2224 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002225 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2226 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002227def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2228 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002229 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2230 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002231
2232// Register-Memory Subtraction
2233def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2234 (ins GR8 :$src1, i8mem :$src2),
2235 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002236 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2237 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002238def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2239 (ins GR16:$src1, i16mem:$src2),
2240 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002241 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2242 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002243def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2244 (ins GR32:$src1, i32mem:$src2),
2245 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002246 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2247 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002248
2249// Register-Integer Subtraction
2250def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2251 (ins GR8:$src1, i8imm:$src2),
2252 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002253 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2254 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002255def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2256 (ins GR16:$src1, i16imm:$src2),
2257 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002258 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2259 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002260def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2261 (ins GR32:$src1, i32imm:$src2),
2262 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002263 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2264 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002265def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2266 (ins GR16:$src1, i16i8imm:$src2),
2267 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002268 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2269 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002270def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2271 (ins GR32:$src1, i32i8imm:$src2),
2272 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002273 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2274 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002275
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002276let isTwoAddress = 0 in {
Bill Wendlingae034ed2008-12-12 00:56:36 +00002277 // Memory-Register Subtraction
Evan Chengb783fa32007-07-19 01:14:50 +00002278 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002279 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002280 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2281 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002282 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002283 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002284 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2285 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002286 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002287 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002288 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2289 (implicit EFLAGS)]>;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002290
2291 // Memory-Integer Subtraction
Evan Chengb783fa32007-07-19 01:14:50 +00002292 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002293 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002294 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2295 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002296 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002297 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002298 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2299 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002300 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002301 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002302 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2303 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002304 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002305 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002306 [(store (sub (load addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002307 addr:$dst),
2308 (implicit EFLAGS)]>, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002309 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002310 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002311 [(store (sub (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00002312 addr:$dst),
2313 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002314}
2315
Evan Cheng259471d2007-10-05 17:59:57 +00002316let Uses = [EFLAGS] in {
Evan Chengb783fa32007-07-19 01:14:50 +00002317def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002318 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng55687072007-09-14 21:48:26 +00002319 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002320
2321let isTwoAddress = 0 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002322 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002323 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002324 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002325 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002326 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002327 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002328 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002329 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002330 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002331 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002332 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng55687072007-09-14 21:48:26 +00002333 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002334}
Evan Chengb783fa32007-07-19 01:14:50 +00002335def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002336 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002337 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002338def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002339 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002340 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002341def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002342 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002343 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
Evan Cheng259471d2007-10-05 17:59:57 +00002344} // Uses = [EFLAGS]
Evan Cheng55687072007-09-14 21:48:26 +00002345} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002346
Evan Cheng55687072007-09-14 21:48:26 +00002347let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002348let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
Bill Wendlingf5399032008-12-12 21:15:41 +00002349// Register-Register Signed Integer Multiply
Bill Wendlingae034ed2008-12-12 00:56:36 +00002350def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002351 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002352 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2353 (implicit EFLAGS)]>, TB, OpSize;
Bill Wendlingae034ed2008-12-12 00:56:36 +00002354def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002355 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002356 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2357 (implicit EFLAGS)]>, TB;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002358}
Bill Wendlingae034ed2008-12-12 00:56:36 +00002359
Bill Wendlingf5399032008-12-12 21:15:41 +00002360// Register-Memory Signed Integer Multiply
Bill Wendlingae034ed2008-12-12 00:56:36 +00002361def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2362 (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002363 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002364 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2365 (implicit EFLAGS)]>, TB, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002366def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002367 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002368 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2369 (implicit EFLAGS)]>, TB;
Evan Cheng55687072007-09-14 21:48:26 +00002370} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002371} // end Two Address instructions
2372
2373// Suprisingly enough, these are not two address instructions!
Evan Cheng55687072007-09-14 21:48:26 +00002374let Defs = [EFLAGS] in {
Bill Wendlingf5399032008-12-12 21:15:41 +00002375// Register-Integer Signed Integer Multiply
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002376def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
Evan Chengb783fa32007-07-19 01:14:50 +00002377 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002378 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002379 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2380 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002381def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
Evan Chengb783fa32007-07-19 01:14:50 +00002382 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002383 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002384 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2385 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002386def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002387 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002388 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002389 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2390 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002391def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002392 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002393 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002394 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2395 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002396
Bill Wendlingf5399032008-12-12 21:15:41 +00002397// Memory-Integer Signed Integer Multiply
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002398def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
Evan Chengb783fa32007-07-19 01:14:50 +00002399 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002400 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002401 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2402 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002403def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
Evan Chengb783fa32007-07-19 01:14:50 +00002404 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002405 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingf5399032008-12-12 21:15:41 +00002406 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2407 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002408def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002409 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002410 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002411 [(set GR16:$dst, (mul (load addr:$src1),
Bill Wendlingf5399032008-12-12 21:15:41 +00002412 i16immSExt8:$src2)),
2413 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002414def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
Evan Chengb783fa32007-07-19 01:14:50 +00002415 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002416 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingae034ed2008-12-12 00:56:36 +00002417 [(set GR32:$dst, (mul (load addr:$src1),
Bill Wendlingf5399032008-12-12 21:15:41 +00002418 i32immSExt8:$src2)),
2419 (implicit EFLAGS)]>;
Evan Cheng55687072007-09-14 21:48:26 +00002420} // Defs = [EFLAGS]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002421
2422//===----------------------------------------------------------------------===//
2423// Test instructions are just like AND, except they don't generate a result.
2424//
Evan Cheng950aac02007-09-25 01:57:46 +00002425let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002426let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
Evan Chengb783fa32007-07-19 01:14:50 +00002427def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002428 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002429 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002430 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002431def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002432 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002433 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002434 (implicit EFLAGS)]>,
2435 OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002436def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002437 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002438 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002439 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002440}
2441
Evan Chengb783fa32007-07-19 01:14:50 +00002442def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002443 "test{b}\t{$src2, $src1|$src1, $src2}",
2444 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2445 (implicit EFLAGS)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002446def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002447 "test{w}\t{$src2, $src1|$src1, $src2}",
2448 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2449 (implicit EFLAGS)]>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002450def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
Evan Cheng621216e2007-09-29 00:00:36 +00002451 "test{l}\t{$src2, $src1|$src1, $src2}",
2452 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2453 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002454
2455def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
Evan Chengb783fa32007-07-19 01:14:50 +00002456 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002457 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002458 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002459 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002460def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
Evan Chengb783fa32007-07-19 01:14:50 +00002461 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002462 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002463 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002464 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002465def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
Evan Chengb783fa32007-07-19 01:14:50 +00002466 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002467 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattner21da6382008-02-19 17:37:35 +00002468 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
Evan Cheng621216e2007-09-29 00:00:36 +00002469 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002470
Evan Cheng621216e2007-09-29 00:00:36 +00002471def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
Evan Chengb783fa32007-07-19 01:14:50 +00002472 (outs), (ins i8mem:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002473 "test{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002474 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2475 (implicit EFLAGS)]>;
2476def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
Evan Chengb783fa32007-07-19 01:14:50 +00002477 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002478 "test{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002479 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2480 (implicit EFLAGS)]>, OpSize;
2481def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
Evan Chengb783fa32007-07-19 01:14:50 +00002482 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002483 "test{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002484 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
Evan Cheng950aac02007-09-25 01:57:46 +00002485 (implicit EFLAGS)]>;
2486} // Defs = [EFLAGS]
2487
2488
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002489// Condition code ops, incl. set if equal/not equal/...
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002490let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002491def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002492let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002493def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002494
Evan Cheng950aac02007-09-25 01:57:46 +00002495let Uses = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002496def SETEr : I<0x94, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002497 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002498 "sete\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002499 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002500 TB; // GR8 = ==
2501def SETEm : I<0x94, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002502 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002503 "sete\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002504 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002505 TB; // [mem8] = ==
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002506
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002507def SETNEr : I<0x95, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002508 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002509 "setne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002510 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002511 TB; // GR8 = !=
2512def SETNEm : I<0x95, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002513 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002514 "setne\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002515 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002516 TB; // [mem8] = !=
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002517
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002518def SETLr : I<0x9C, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002519 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002520 "setl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002521 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002522 TB; // GR8 = < signed
2523def SETLm : I<0x9C, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002524 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002525 "setl\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002526 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002527 TB; // [mem8] = < signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002528
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002529def SETGEr : I<0x9D, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002530 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002531 "setge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002532 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002533 TB; // GR8 = >= signed
2534def SETGEm : I<0x9D, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002535 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002536 "setge\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002537 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002538 TB; // [mem8] = >= signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002539
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002540def SETLEr : I<0x9E, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002541 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002542 "setle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002543 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002544 TB; // GR8 = <= signed
2545def SETLEm : I<0x9E, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002546 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002547 "setle\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002548 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002549 TB; // [mem8] = <= signed
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002550
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002551def SETGr : I<0x9F, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002552 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002553 "setg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002554 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002555 TB; // GR8 = > signed
2556def SETGm : I<0x9F, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002557 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002558 "setg\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002559 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002560 TB; // [mem8] = > signed
2561
2562def SETBr : I<0x92, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002563 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002564 "setb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002565 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002566 TB; // GR8 = < unsign
2567def SETBm : I<0x92, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002568 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002569 "setb\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002570 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002571 TB; // [mem8] = < unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002572
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002573def SETAEr : I<0x93, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002574 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002575 "setae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002576 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002577 TB; // GR8 = >= unsign
2578def SETAEm : I<0x93, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002579 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002580 "setae\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002581 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002582 TB; // [mem8] = >= unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002583
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002584def SETBEr : I<0x96, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002585 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002586 "setbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002587 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002588 TB; // GR8 = <= unsign
2589def SETBEm : I<0x96, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002590 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002591 "setbe\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002592 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002593 TB; // [mem8] = <= unsign
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002594
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002595def SETAr : I<0x97, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002596 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002597 "seta\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002598 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002599 TB; // GR8 = > signed
2600def SETAm : I<0x97, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002601 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002602 "seta\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002603 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002604 TB; // [mem8] = > signed
2605
2606def SETSr : I<0x98, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002607 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002608 "sets\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002609 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002610 TB; // GR8 = <sign bit>
2611def SETSm : I<0x98, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002612 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002613 "sets\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002614 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002615 TB; // [mem8] = <sign bit>
2616def SETNSr : I<0x99, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002617 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002618 "setns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002619 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002620 TB; // GR8 = !<sign bit>
2621def SETNSm : I<0x99, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002622 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002623 "setns\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002624 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002625 TB; // [mem8] = !<sign bit>
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002626
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002627def SETPr : I<0x9A, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002628 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002629 "setp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002630 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002631 TB; // GR8 = parity
2632def SETPm : I<0x9A, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002633 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002634 "setp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002635 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002636 TB; // [mem8] = parity
2637def SETNPr : I<0x9B, MRM0r,
Evan Chengb783fa32007-07-19 01:14:50 +00002638 (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002639 "setnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002640 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002641 TB; // GR8 = not parity
2642def SETNPm : I<0x9B, MRM0m,
Evan Chengb783fa32007-07-19 01:14:50 +00002643 (outs), (ins i8mem:$dst),
Dan Gohman91888f02007-07-31 20:11:57 +00002644 "setnp\t$dst",
Evan Cheng621216e2007-09-29 00:00:36 +00002645 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002646 TB; // [mem8] = not parity
Bill Wendling0c52d0a2008-12-02 00:07:05 +00002647
2648def SETOr : I<0x90, MRM0r,
2649 (outs GR8 :$dst), (ins),
2650 "seto\t$dst",
2651 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2652 TB; // GR8 = overflow
2653def SETOm : I<0x90, MRM0m,
2654 (outs), (ins i8mem:$dst),
2655 "seto\t$dst",
2656 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2657 TB; // [mem8] = overflow
2658def SETNOr : I<0x91, MRM0r,
2659 (outs GR8 :$dst), (ins),
2660 "setno\t$dst",
2661 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2662 TB; // GR8 = not overflow
2663def SETNOm : I<0x91, MRM0m,
2664 (outs), (ins i8mem:$dst),
2665 "setno\t$dst",
2666 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2667 TB; // [mem8] = not overflow
Evan Cheng950aac02007-09-25 01:57:46 +00002668} // Uses = [EFLAGS]
2669
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002670
2671// Integer comparisons
Evan Cheng55687072007-09-14 21:48:26 +00002672let Defs = [EFLAGS] in {
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002673def CMP8rr : I<0x38, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002674 (outs), (ins GR8 :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002675 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002676 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002677def CMP16rr : I<0x39, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002678 (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002679 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002680 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002681def CMP32rr : I<0x39, MRMDestReg,
Evan Chengb783fa32007-07-19 01:14:50 +00002682 (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002683 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002684 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002685def CMP8mr : I<0x38, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002686 (outs), (ins i8mem :$src1, GR8 :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002687 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002688 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2689 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002690def CMP16mr : I<0x39, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002691 (outs), (ins i16mem:$src1, GR16:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002692 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002693 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2694 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002695def CMP32mr : I<0x39, MRMDestMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002696 (outs), (ins i32mem:$src1, GR32:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002697 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002698 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2699 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002700def CMP8rm : I<0x3A, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002701 (outs), (ins GR8 :$src1, i8mem :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002702 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002703 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2704 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002705def CMP16rm : I<0x3B, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002706 (outs), (ins GR16:$src1, i16mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002707 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002708 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2709 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002710def CMP32rm : I<0x3B, MRMSrcMem,
Evan Chengb783fa32007-07-19 01:14:50 +00002711 (outs), (ins GR32:$src1, i32mem:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002712 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002713 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2714 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002715def CMP8ri : Ii8<0x80, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002716 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002717 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002718 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002719def CMP16ri : Ii16<0x81, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002720 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002721 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002722 [(X86cmp GR16:$src1, imm:$src2),
2723 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002724def CMP32ri : Ii32<0x81, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002725 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002726 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002727 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002728def CMP8mi : Ii8 <0x80, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002729 (outs), (ins i8mem :$src1, i8imm :$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002730 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002731 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2732 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002733def CMP16mi : Ii16<0x81, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002734 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002735 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002736 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2737 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002738def CMP32mi : Ii32<0x81, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002739 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002740 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002741 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2742 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002743def CMP16ri8 : Ii8<0x83, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002744 (outs), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002745 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002746 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2747 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002748def CMP16mi8 : Ii8<0x83, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002749 (outs), (ins i16mem:$src1, i16i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002750 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002751 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2752 (implicit EFLAGS)]>, OpSize;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002753def CMP32mi8 : Ii8<0x83, MRM7m,
Evan Chengb783fa32007-07-19 01:14:50 +00002754 (outs), (ins i32mem:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002755 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002756 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2757 (implicit EFLAGS)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002758def CMP32ri8 : Ii8<0x83, MRM7r,
Evan Chengb783fa32007-07-19 01:14:50 +00002759 (outs), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohman91888f02007-07-31 20:11:57 +00002760 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Cheng621216e2007-09-29 00:00:36 +00002761 [(X86cmp GR32:$src1, i32immSExt8:$src2),
Evan Cheng950aac02007-09-25 01:57:46 +00002762 (implicit EFLAGS)]>;
2763} // Defs = [EFLAGS]
2764
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00002765// Bit tests.
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00002766// TODO: BTC, BTR, and BTS
2767let Defs = [EFLAGS] in {
Dan Gohmanfc4eddb2009-01-13 20:32:45 +00002768def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00002769 "bt{w}\t{$src2, $src1|$src1, $src2}",
2770 [(X86bt GR16:$src1, GR16:$src2),
Chris Lattner5a95cde2008-12-25 01:32:49 +00002771 (implicit EFLAGS)]>, OpSize, TB;
Dan Gohmanfc4eddb2009-01-13 20:32:45 +00002772def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00002773 "bt{l}\t{$src2, $src1|$src1, $src2}",
2774 [(X86bt GR32:$src1, GR32:$src2),
Chris Lattner5a95cde2008-12-25 01:32:49 +00002775 (implicit EFLAGS)]>, TB;
Dan Gohman85a228c2009-01-13 23:23:30 +00002776
2777// Unlike with the register+register form, the memory+register form of the
2778// bt instruction does not ignore the high bits of the index. From ISel's
2779// perspective, this is pretty bizarre. Disable these instructions for now.
2780//def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2781// "bt{w}\t{$src2, $src1|$src1, $src2}",
2782// [(X86bt (loadi16 addr:$src1), GR16:$src2),
2783// (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2784//def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2785// "bt{l}\t{$src2, $src1|$src1, $src2}",
2786// [(X86bt (loadi32 addr:$src1), GR32:$src2),
2787// (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
Dan Gohman46fb1cf2009-01-13 20:33:23 +00002788
2789def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2790 "bt{w}\t{$src2, $src1|$src1, $src2}",
2791 [(X86bt GR16:$src1, i16immSExt8:$src2),
2792 (implicit EFLAGS)]>, OpSize, TB;
2793def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2794 "bt{l}\t{$src2, $src1|$src1, $src2}",
2795 [(X86bt GR32:$src1, i32immSExt8:$src2),
2796 (implicit EFLAGS)]>, TB;
2797// Note that these instructions don't need FastBTMem because that
2798// only applies when the other operand is in a register. When it's
2799// an immediate, bt is still fast.
2800def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2801 "bt{w}\t{$src2, $src1|$src1, $src2}",
2802 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2803 (implicit EFLAGS)]>, OpSize, TB;
2804def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2805 "bt{l}\t{$src2, $src1|$src1, $src2}",
2806 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2807 (implicit EFLAGS)]>, TB;
Dan Gohman7fe9b7f2008-12-23 22:45:23 +00002808} // Defs = [EFLAGS]
2809
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002810// Sign/Zero extenders
Dan Gohman9203ab42008-07-30 18:09:17 +00002811// Use movsbl intead of movsbw; we don't care about the high 16 bits
2812// of the register here. This has a smaller encoding and avoids a
2813// partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00002814def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00002815 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2816 [(set GR16:$dst, (sext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002817def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00002818 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2819 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002820def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002821 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002822 [(set GR32:$dst, (sext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002823def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002824 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002825 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002826def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002827 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002828 [(set GR32:$dst, (sext GR16:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002829def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002830 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002831 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2832
Dan Gohman9203ab42008-07-30 18:09:17 +00002833// Use movzbl intead of movzbw; we don't care about the high 16 bits
2834// of the register here. This has a smaller encoding and avoids a
2835// partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00002836def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00002837 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2838 [(set GR16:$dst, (zext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002839def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman9203ab42008-07-30 18:09:17 +00002840 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2841 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002842def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002843 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002844 [(set GR32:$dst, (zext GR8:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002845def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002846 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002847 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002848def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002849 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002850 [(set GR32:$dst, (zext GR16:$src))]>, TB;
Evan Chengb783fa32007-07-19 01:14:50 +00002851def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002852 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002853 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2854
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002855let neverHasSideEffects = 1 in {
2856 let Defs = [AX], Uses = [AL] in
2857 def CBW : I<0x98, RawFrm, (outs), (ins),
2858 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2859 let Defs = [EAX], Uses = [AX] in
2860 def CWDE : I<0x98, RawFrm, (outs), (ins),
2861 "{cwtl|cwde}", []>; // EAX = signext(AX)
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002862
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002863 let Defs = [AX,DX], Uses = [AX] in
2864 def CWD : I<0x99, RawFrm, (outs), (ins),
2865 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2866 let Defs = [EAX,EDX], Uses = [EAX] in
2867 def CDQ : I<0x99, RawFrm, (outs), (ins),
2868 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2869}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002870
2871//===----------------------------------------------------------------------===//
2872// Alias Instructions
2873//===----------------------------------------------------------------------===//
2874
2875// Alias instructions that map movr0 to xor.
2876// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
Bill Wendlingba5d5b02008-05-29 01:02:09 +00002877let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002878def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002879 "xor{b}\t$dst, $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002880 [(set GR8:$dst, 0)]>;
Dan Gohman9203ab42008-07-30 18:09:17 +00002881// Use xorl instead of xorw since we don't care about the high 16 bits,
2882// it's smaller, and it avoids a partial-register update.
Evan Chengb783fa32007-07-19 01:14:50 +00002883def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
Dan Gohman9203ab42008-07-30 18:09:17 +00002884 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2885 [(set GR16:$dst, 0)]>;
Evan Chengb783fa32007-07-19 01:14:50 +00002886def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002887 "xor{l}\t$dst, $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002888 [(set GR32:$dst, 0)]>;
Dan Gohman8aef09b2007-09-07 21:32:51 +00002889}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002890
2891// Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2892// those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
Evan Chengbd0ca9c2009-02-05 08:42:55 +00002893let neverHasSideEffects = 1, isAsCheapAsAMove = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002894def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002895 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002896def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002897 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002898
Evan Chengb783fa32007-07-19 01:14:50 +00002899def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002900 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002901def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002902 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002903} // neverHasSideEffects
2904
Dan Gohman5574cc72008-12-03 18:15:48 +00002905let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002906def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002907 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002908def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002909 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Evan Cheng4e84e452007-08-30 05:49:43 +00002910}
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002911let mayStore = 1, neverHasSideEffects = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002912def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002913 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Chengb783fa32007-07-19 01:14:50 +00002914def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002915 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerc90ee9c2008-01-10 07:59:24 +00002916}
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002917
2918//===----------------------------------------------------------------------===//
2919// Thread Local Storage Instructions
2920//
2921
Evan Cheng6e4d1d92007-09-11 19:55:27 +00002922let Uses = [EBX] in
Anton Korobeynikov4fbf00b2008-05-04 21:36:32 +00002923def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2924 "leal\t${sym:mem}(,%ebx,1), $dst",
2925 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002926
2927let AddedComplexity = 10 in
Anton Korobeynikov4fbf00b2008-05-04 21:36:32 +00002928def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002929 "movl\t%gs:($src), $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002930 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2931
2932let AddedComplexity = 15 in
Nicolas Geoffray81580792008-10-25 15:22:06 +00002933def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
Dan Gohman91888f02007-07-31 20:11:57 +00002934 "movl\t%gs:${src:mem}, $dst",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002935 [(set GR32:$dst,
Nicolas Geoffray81580792008-10-25 15:22:06 +00002936 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
2937 SegGS;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002938
Rafael Espindola53ec6be2009-03-11 22:40:04 +00002939let AddedComplexity = 15 in
2940def TLS_ext16_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2941 "movzwl\t%gs:${src:mem}, $dst",
2942 [(set GR32:$dst,
2943 (extloadi32i16
2944 (add X86TLStp,
2945 (X86Wrapper tglobaltlsaddr:$src))))]>,
2946 SegGS;
2947
2948let AddedComplexity = 15 in
2949def TLS_ext8_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2950 "movzbl\t%gs:${src:mem}, $dst",
2951 [(set GR32:$dst,
2952 (extloadi32i8
2953 (add X86TLStp,
2954 (X86Wrapper tglobaltlsaddr:$src))))]>,
2955 SegGS;
2956
Nicolas Geoffray81580792008-10-25 15:22:06 +00002957def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
Dan Gohman91888f02007-07-31 20:11:57 +00002958 "movl\t%gs:0, $dst",
Nicolas Geoffray81580792008-10-25 15:22:06 +00002959 [(set GR32:$dst, X86TLStp)]>, SegGS;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002960
sampo9cc09a32009-01-26 01:24:32 +00002961let AddedComplexity = 5 in
2962def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2963 "movl\t%gs:$src, $dst",
2964 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
2965
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002966//===----------------------------------------------------------------------===//
2967// DWARF Pseudo Instructions
2968//
2969
Evan Chengb783fa32007-07-19 01:14:50 +00002970def DWARF_LOC : I<0, Pseudo, (outs),
2971 (ins i32imm:$line, i32imm:$col, i32imm:$file),
Dan Gohman77af4a82007-09-24 19:25:06 +00002972 ".loc\t${file:debug} ${line:debug} ${col:debug}",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002973 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2974 (i32 imm:$file))]>;
2975
2976//===----------------------------------------------------------------------===//
2977// EH Pseudo Instructions
2978//
2979let isTerminator = 1, isReturn = 1, isBarrier = 1,
Evan Cheng37e7c752007-07-21 00:34:19 +00002980 hasCtrlDep = 1 in {
Evan Chengb783fa32007-07-19 01:14:50 +00002981def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
Dan Gohman91888f02007-07-31 20:11:57 +00002982 "ret\t#eh_return, addr: $addr",
Dan Gohmanf17a25c2007-07-18 16:29:46 +00002983 [(X86ehret GR32:$addr)]>;
2984
2985}
2986
2987//===----------------------------------------------------------------------===//
Andrew Lenharthe44f3902008-02-21 06:45:13 +00002988// Atomic support
2989//
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00002990
Evan Cheng3e171562008-04-19 01:20:30 +00002991// Atomic swap. These are just normal xchg instructions. But since a memory
2992// operand is referenced, the atomicity is ensured.
Dan Gohmana41a1c092008-08-06 15:52:50 +00002993let Constraints = "$val = $dst" in {
Evan Cheng3e171562008-04-19 01:20:30 +00002994def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
2995 "xchg{l}\t{$val, $ptr|$ptr, $val}",
2996 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
2997def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
2998 "xchg{w}\t{$val, $ptr|$ptr, $val}",
2999 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3000 OpSize;
3001def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3002 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3003 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3004}
3005
Evan Chengd49dbb82008-04-18 20:55:36 +00003006// Atomic compare and swap.
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003007let Defs = [EAX, EFLAGS], Uses = [EAX] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003008def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
Dale Johannesend20e4452008-08-19 18:47:28 +00003009 "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003010 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003011}
Dale Johannesenf160d802008-10-02 18:53:47 +00003012let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
Anton Korobeynikovc4067392008-07-22 16:22:48 +00003013def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
Dale Johannesend20e4452008-08-19 18:47:28 +00003014 "lock\n\tcmpxchg8b\t$ptr",
Andrew Lenharth81580822008-03-05 01:15:49 +00003015 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3016}
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003017
3018let Defs = [AX, EFLAGS], Uses = [AX] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003019def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
Dale Johannesend20e4452008-08-19 18:47:28 +00003020 "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003021 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003022}
Andrew Lenharth7dfe23f2008-03-01 21:52:34 +00003023let Defs = [AL, EFLAGS], Uses = [AL] in {
Evan Chengd49dbb82008-04-18 20:55:36 +00003024def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
Dale Johannesend20e4452008-08-19 18:47:28 +00003025 "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng09fbdee2008-03-04 03:20:06 +00003026 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003027}
3028
Evan Chengd49dbb82008-04-18 20:55:36 +00003029// Atomic exchange and add
3030let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3031def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Dale Johannesend20e4452008-08-19 18:47:28 +00003032 "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003033 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003034 TB, LOCK;
3035def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Dale Johannesend20e4452008-08-19 18:47:28 +00003036 "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003037 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003038 TB, OpSize, LOCK;
3039def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
Dale Johannesend20e4452008-08-19 18:47:28 +00003040 "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}",
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003041 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
Evan Chengd49dbb82008-04-18 20:55:36 +00003042 TB, LOCK;
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +00003043}
3044
Mon P Wang6bde9ec2008-06-25 08:15:39 +00003045// Atomic exchange, and, or, xor
Mon P Wang078a62d2008-05-05 19:05:59 +00003046let Constraints = "$val = $dst", Defs = [EFLAGS],
3047 usesCustomDAGSchedInserter = 1 in {
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003048def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003049 "#ATOMAND32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003050 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003051def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003052 "#ATOMOR32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003053 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003054def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003055 "#ATOMXOR32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003056 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
Andrew Lenharthaf02d592008-06-14 05:48:15 +00003057def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003058 "#ATOMNAND32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003059 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003060def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003061 "#ATOMMIN32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003062 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003063def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003064 "#ATOMMAX32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003065 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003066def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003067 "#ATOMUMIN32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003068 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
Dan Gohman8aeb61f2008-05-12 20:22:45 +00003069def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003070 "#ATOMUMAX32 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003071 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003072
3073def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003074 "#ATOMAND16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003075 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003076def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003077 "#ATOMOR16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003078 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003079def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003080 "#ATOMXOR16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003081 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003082def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003083 "#ATOMNAND16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003084 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003085def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003086 "#ATOMMIN16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003087 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003088def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003089 "#ATOMMAX16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003090 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003091def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003092 "#ATOMUMIN16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003093 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003094def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003095 "#ATOMUMAX16 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003096 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003097
3098def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003099 "#ATOMAND8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003100 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003101def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003102 "#ATOMOR8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003103 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003104def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003105 "#ATOMXOR8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003106 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
Dale Johannesend20e4452008-08-19 18:47:28 +00003107def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003108 "#ATOMNAND8 PSEUDO!",
Dale Johannesenbc187662008-08-28 02:44:49 +00003109 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
Mon P Wang078a62d2008-05-05 19:05:59 +00003110}
3111
Dale Johannesenf160d802008-10-02 18:53:47 +00003112let Constraints = "$val1 = $dst1, $val2 = $dst2",
3113 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3114 Uses = [EAX, EBX, ECX, EDX],
Dale Johannesen44eb5372008-10-03 19:41:08 +00003115 mayLoad = 1, mayStore = 1,
Dale Johannesenf160d802008-10-02 18:53:47 +00003116 usesCustomDAGSchedInserter = 1 in {
3117def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3118 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003119 "#ATOMAND6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003120def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3121 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003122 "#ATOMOR6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003123def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3124 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003125 "#ATOMXOR6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003126def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3127 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003128 "#ATOMNAND6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003129def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3130 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003131 "#ATOMADD6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003132def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3133 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003134 "#ATOMSUB6432 PSEUDO!", []>;
Dale Johannesen51c58ee2008-10-03 22:25:52 +00003135def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3136 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewyckybfb9fd22008-12-07 03:49:52 +00003137 "#ATOMSWAP6432 PSEUDO!", []>;
Dale Johannesenf160d802008-10-02 18:53:47 +00003138}
3139
Andrew Lenharthe44f3902008-02-21 06:45:13 +00003140//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003141// Non-Instruction Patterns
3142//===----------------------------------------------------------------------===//
3143
Bill Wendlingfef06052008-09-16 21:48:12 +00003144// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003145def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3146def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
Nate Begemanb52948972008-04-12 00:47:57 +00003147def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003148def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3149def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3150
3151def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3152 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3153def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3154 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3155def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3156 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3157def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3158 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3159
3160def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3161 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3162def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3163 (MOV32mi addr:$dst, texternalsym:$src)>;
3164
3165// Calls
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003166// tailcall stuff
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003167def : Pat<(X86tailcall GR32:$dst),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003168 (TAILCALL)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003169
3170def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003171 (TAILCALL)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003172def : Pat<(X86tailcall (i32 texternalsym:$dst)),
Arnold Schwaighofere2d6bbb2007-10-11 19:40:01 +00003173 (TAILCALL)>;
3174
3175def : Pat<(X86tcret GR32:$dst, imm:$off),
3176 (TCRETURNri GR32:$dst, imm:$off)>;
3177
3178def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3179 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3180
3181def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3182 (TCRETURNdi texternalsym:$dst, imm:$off)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003183
3184def : Pat<(X86call (i32 tglobaladdr:$dst)),
3185 (CALLpcrel32 tglobaladdr:$dst)>;
3186def : Pat<(X86call (i32 texternalsym:$dst)),
3187 (CALLpcrel32 texternalsym:$dst)>;
3188
3189// X86 specific add which produces a flag.
3190def : Pat<(addc GR32:$src1, GR32:$src2),
3191 (ADD32rr GR32:$src1, GR32:$src2)>;
3192def : Pat<(addc GR32:$src1, (load addr:$src2)),
3193 (ADD32rm GR32:$src1, addr:$src2)>;
3194def : Pat<(addc GR32:$src1, imm:$src2),
3195 (ADD32ri GR32:$src1, imm:$src2)>;
3196def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3197 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3198
3199def : Pat<(subc GR32:$src1, GR32:$src2),
3200 (SUB32rr GR32:$src1, GR32:$src2)>;
3201def : Pat<(subc GR32:$src1, (load addr:$src2)),
3202 (SUB32rm GR32:$src1, addr:$src2)>;
3203def : Pat<(subc GR32:$src1, imm:$src2),
3204 (SUB32ri GR32:$src1, imm:$src2)>;
3205def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3206 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3207
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003208// Comparisons.
3209
3210// TEST R,R is smaller than CMP R,0
Evan Cheng621216e2007-09-29 00:00:36 +00003211def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003212 (TEST8rr GR8:$src1, GR8:$src1)>;
Evan Cheng621216e2007-09-29 00:00:36 +00003213def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003214 (TEST16rr GR16:$src1, GR16:$src1)>;
Evan Cheng621216e2007-09-29 00:00:36 +00003215def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003216 (TEST32rr GR32:$src1, GR32:$src1)>;
3217
Dan Gohman0a3c5222009-01-07 01:00:24 +00003218// Conditional moves with folded loads with operands swapped and conditions
3219// inverted.
3220def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3221 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3222def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3223 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3224def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3225 (CMOVB16rm GR16:$src2, addr:$src1)>;
3226def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3227 (CMOVB32rm GR32:$src2, addr:$src1)>;
3228def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3229 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3230def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3231 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3232def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3233 (CMOVE16rm GR16:$src2, addr:$src1)>;
3234def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3235 (CMOVE32rm GR32:$src2, addr:$src1)>;
3236def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3237 (CMOVA16rm GR16:$src2, addr:$src1)>;
3238def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3239 (CMOVA32rm GR32:$src2, addr:$src1)>;
3240def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3241 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3242def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3243 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3244def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3245 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3246def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3247 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3248def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3249 (CMOVL16rm GR16:$src2, addr:$src1)>;
3250def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3251 (CMOVL32rm GR32:$src2, addr:$src1)>;
3252def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3253 (CMOVG16rm GR16:$src2, addr:$src1)>;
3254def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3255 (CMOVG32rm GR32:$src2, addr:$src1)>;
3256def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3257 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3258def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3259 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3260def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3261 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3262def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3263 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3264def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3265 (CMOVP16rm GR16:$src2, addr:$src1)>;
3266def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3267 (CMOVP32rm GR32:$src2, addr:$src1)>;
3268def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3269 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3270def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3271 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3272def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3273 (CMOVS16rm GR16:$src2, addr:$src1)>;
3274def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3275 (CMOVS32rm GR32:$src2, addr:$src1)>;
3276def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3277 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3278def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3279 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3280def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3281 (CMOVO16rm GR16:$src2, addr:$src1)>;
3282def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3283 (CMOVO32rm GR32:$src2, addr:$src1)>;
3284
Duncan Sands082524c2008-01-23 20:39:46 +00003285// zextload bool -> zextload byte
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003286def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3287def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3288def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3289
3290// extload bool -> extload byte
3291def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003292def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3293 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003294def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003295def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3296 Requires<[In32BitMode]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003297def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3298def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3299
Dan Gohmandd612bb2008-08-20 21:27:32 +00003300// anyext
Bill Wendlingce1c5c12008-08-22 20:51:05 +00003301def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3302 Requires<[In32BitMode]>;
3303def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3304 Requires<[In32BitMode]>;
Dan Gohmandd612bb2008-08-20 21:27:32 +00003305def : Pat<(i32 (anyext GR16:$src)),
3306 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003307
Evan Chengf2abee72007-12-13 00:43:27 +00003308// (and (i32 load), 255) -> (zextload i8)
Evan Cheng1e5e5452008-09-29 17:26:18 +00003309def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3310 (MOVZX32rm8 addr:$src)>;
3311def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3312 (MOVZX32rm16 addr:$src)>;
Evan Chengf2abee72007-12-13 00:43:27 +00003313
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003314//===----------------------------------------------------------------------===//
3315// Some peepholes
3316//===----------------------------------------------------------------------===//
3317
Dan Gohman5a5e6e92008-10-17 01:33:43 +00003318// Odd encoding trick: -128 fits into an 8-bit immediate field while
3319// +128 doesn't, so in this special case use a sub instead of an add.
3320def : Pat<(add GR16:$src1, 128),
3321 (SUB16ri8 GR16:$src1, -128)>;
3322def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3323 (SUB16mi8 addr:$dst, -128)>;
3324def : Pat<(add GR32:$src1, 128),
3325 (SUB32ri8 GR32:$src1, -128)>;
3326def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3327 (SUB32mi8 addr:$dst, -128)>;
3328
Dan Gohman9203ab42008-07-30 18:09:17 +00003329// r & (2^16-1) ==> movz
3330def : Pat<(and GR32:$src1, 0xffff),
Dan Gohmandd612bb2008-08-20 21:27:32 +00003331 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003332// r & (2^8-1) ==> movz
3333def : Pat<(and GR32:$src1, 0xff),
Dan Gohmandd612bb2008-08-20 21:27:32 +00003334 (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
3335 x86_subreg_8bit)))>,
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003336 Requires<[In32BitMode]>;
3337// r & (2^8-1) ==> movz
3338def : Pat<(and GR16:$src1, 0xff),
Dan Gohmandd612bb2008-08-20 21:27:32 +00003339 (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
3340 x86_subreg_8bit)))>,
3341 Requires<[In32BitMode]>;
3342
3343// sext_inreg patterns
3344def : Pat<(sext_inreg GR32:$src, i16),
3345 (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>;
3346def : Pat<(sext_inreg GR32:$src, i8),
3347 (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src),
3348 x86_subreg_8bit)))>,
3349 Requires<[In32BitMode]>;
3350def : Pat<(sext_inreg GR16:$src, i8),
3351 (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src),
3352 x86_subreg_8bit)))>,
3353 Requires<[In32BitMode]>;
3354
3355// trunc patterns
3356def : Pat<(i16 (trunc GR32:$src)),
3357 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3358def : Pat<(i8 (trunc GR32:$src)),
3359 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>,
3360 Requires<[In32BitMode]>;
3361def : Pat<(i8 (trunc GR16:$src)),
3362 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>,
Dan Gohman5beb1ff2008-08-06 18:27:21 +00003363 Requires<[In32BitMode]>;
Dan Gohman9203ab42008-07-30 18:09:17 +00003364
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003365// (shl x, 1) ==> (add x, x)
3366def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3367def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3368def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3369
Evan Cheng76a64c72008-08-30 02:03:58 +00003370// (shl x (and y, 31)) ==> (shl x, y)
3371def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3372 (SHL8rCL GR8:$src1)>;
3373def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3374 (SHL16rCL GR16:$src1)>;
3375def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3376 (SHL32rCL GR32:$src1)>;
3377def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3378 (SHL8mCL addr:$dst)>;
3379def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3380 (SHL16mCL addr:$dst)>;
3381def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3382 (SHL32mCL addr:$dst)>;
3383
3384def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3385 (SHR8rCL GR8:$src1)>;
3386def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3387 (SHR16rCL GR16:$src1)>;
3388def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3389 (SHR32rCL GR32:$src1)>;
3390def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3391 (SHR8mCL addr:$dst)>;
3392def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3393 (SHR16mCL addr:$dst)>;
3394def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3395 (SHR32mCL addr:$dst)>;
3396
3397def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3398 (SAR8rCL GR8:$src1)>;
3399def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3400 (SAR16rCL GR16:$src1)>;
3401def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3402 (SAR32rCL GR32:$src1)>;
3403def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3404 (SAR8mCL addr:$dst)>;
3405def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3406 (SAR16mCL addr:$dst)>;
3407def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3408 (SAR32mCL addr:$dst)>;
3409
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003410// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3411def : Pat<(or (srl GR32:$src1, CL:$amt),
3412 (shl GR32:$src2, (sub 32, CL:$amt))),
3413 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3414
3415def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3416 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3417 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3418
Dan Gohman921581d2008-10-17 01:23:35 +00003419def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3420 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3421 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3422
3423def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3424 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3425 addr:$dst),
3426 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3427
3428def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3429 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3430
3431def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3432 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3433 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3434
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003435// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3436def : Pat<(or (shl GR32:$src1, CL:$amt),
3437 (srl GR32:$src2, (sub 32, CL:$amt))),
3438 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3439
3440def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3441 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3442 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3443
Dan Gohman921581d2008-10-17 01:23:35 +00003444def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3445 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3446 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3447
3448def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3449 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3450 addr:$dst),
3451 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3452
3453def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3454 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3455
3456def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3457 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3458 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3459
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003460// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3461def : Pat<(or (srl GR16:$src1, CL:$amt),
3462 (shl GR16:$src2, (sub 16, CL:$amt))),
3463 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3464
3465def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3466 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3467 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3468
Dan Gohman921581d2008-10-17 01:23:35 +00003469def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3470 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3471 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3472
3473def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3474 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3475 addr:$dst),
3476 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3477
3478def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3479 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3480
3481def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3482 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3483 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3484
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003485// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3486def : Pat<(or (shl GR16:$src1, CL:$amt),
3487 (srl GR16:$src2, (sub 16, CL:$amt))),
3488 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3489
3490def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3491 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3492 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3493
Dan Gohman921581d2008-10-17 01:23:35 +00003494def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3495 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3496 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3497
3498def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3499 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3500 addr:$dst),
3501 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3502
3503def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3504 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3505
3506def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3507 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3508 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3509
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003510//===----------------------------------------------------------------------===//
Dan Gohman99a12192009-03-04 19:44:21 +00003511// EFLAGS-defining Patterns
Bill Wendlingf5399032008-12-12 21:15:41 +00003512//===----------------------------------------------------------------------===//
3513
Dan Gohman99a12192009-03-04 19:44:21 +00003514// Register-Register Addition with EFLAGS result
3515def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003516 (implicit EFLAGS)),
3517 (ADD8rr GR8:$src1, GR8:$src2)>;
3518
Dan Gohman99a12192009-03-04 19:44:21 +00003519// Register-Register Addition with EFLAGS result
3520def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003521 (implicit EFLAGS)),
3522 (ADD16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003523def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003524 (implicit EFLAGS)),
3525 (ADD32rr GR32:$src1, GR32:$src2)>;
3526
Dan Gohman99a12192009-03-04 19:44:21 +00003527// Register-Memory Addition with EFLAGS result
3528def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003529 (implicit EFLAGS)),
3530 (ADD8rm GR8:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003531def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003532 (implicit EFLAGS)),
3533 (ADD16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003534def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003535 (implicit EFLAGS)),
3536 (ADD32rm GR32:$src1, addr:$src2)>;
3537
Dan Gohman99a12192009-03-04 19:44:21 +00003538// Register-Integer Addition with EFLAGS result
3539def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003540 (implicit EFLAGS)),
3541 (ADD8ri GR8:$src1, imm:$src2)>;
3542
Dan Gohman99a12192009-03-04 19:44:21 +00003543// Register-Integer Addition with EFLAGS result
3544def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003545 (implicit EFLAGS)),
3546 (ADD16ri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003547def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003548 (implicit EFLAGS)),
3549 (ADD32ri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003550def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003551 (implicit EFLAGS)),
3552 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003553def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003554 (implicit EFLAGS)),
3555 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3556
Dan Gohman99a12192009-03-04 19:44:21 +00003557// Memory-Register Addition with EFLAGS result
3558def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003559 addr:$dst),
3560 (implicit EFLAGS)),
3561 (ADD8mr addr:$dst, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003562def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003563 addr:$dst),
3564 (implicit EFLAGS)),
3565 (ADD16mr addr:$dst, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003566def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003567 addr:$dst),
3568 (implicit EFLAGS)),
3569 (ADD32mr addr:$dst, GR32:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003570def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003571 addr:$dst),
3572 (implicit EFLAGS)),
3573 (ADD8mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003574def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003575 addr:$dst),
3576 (implicit EFLAGS)),
3577 (ADD16mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003578def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003579 addr:$dst),
3580 (implicit EFLAGS)),
3581 (ADD32mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003582def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003583 addr:$dst),
3584 (implicit EFLAGS)),
3585 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003586def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003587 addr:$dst),
3588 (implicit EFLAGS)),
3589 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3590
Dan Gohman99a12192009-03-04 19:44:21 +00003591// Register-Register Subtraction with EFLAGS result
3592def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003593 (implicit EFLAGS)),
3594 (SUB8rr GR8:$src1, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003595def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003596 (implicit EFLAGS)),
3597 (SUB16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003598def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003599 (implicit EFLAGS)),
3600 (SUB32rr GR32:$src1, GR32:$src2)>;
3601
Dan Gohman99a12192009-03-04 19:44:21 +00003602// Register-Memory Subtraction with EFLAGS result
3603def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003604 (implicit EFLAGS)),
3605 (SUB8rm GR8:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003606def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003607 (implicit EFLAGS)),
3608 (SUB16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003609def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003610 (implicit EFLAGS)),
3611 (SUB32rm GR32:$src1, addr:$src2)>;
3612
Dan Gohman99a12192009-03-04 19:44:21 +00003613// Register-Integer Subtraction with EFLAGS result
3614def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003615 (implicit EFLAGS)),
3616 (SUB8ri GR8:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003617def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003618 (implicit EFLAGS)),
3619 (SUB16ri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003620def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003621 (implicit EFLAGS)),
3622 (SUB32ri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003623def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003624 (implicit EFLAGS)),
3625 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003626def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003627 (implicit EFLAGS)),
3628 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3629
Dan Gohman99a12192009-03-04 19:44:21 +00003630// Memory-Register Subtraction with EFLAGS result
3631def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003632 addr:$dst),
3633 (implicit EFLAGS)),
3634 (SUB8mr addr:$dst, GR8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003635def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003636 addr:$dst),
3637 (implicit EFLAGS)),
3638 (SUB16mr addr:$dst, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003639def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003640 addr:$dst),
3641 (implicit EFLAGS)),
3642 (SUB32mr addr:$dst, GR32:$src2)>;
3643
Dan Gohman99a12192009-03-04 19:44:21 +00003644// Memory-Integer Subtraction with EFLAGS result
3645def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003646 addr:$dst),
3647 (implicit EFLAGS)),
3648 (SUB8mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003649def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003650 addr:$dst),
3651 (implicit EFLAGS)),
3652 (SUB16mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003653def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003654 addr:$dst),
3655 (implicit EFLAGS)),
3656 (SUB32mi addr:$dst, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003657def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003658 addr:$dst),
3659 (implicit EFLAGS)),
3660 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003661def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003662 addr:$dst),
3663 (implicit EFLAGS)),
3664 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3665
3666
Dan Gohman99a12192009-03-04 19:44:21 +00003667// Register-Register Signed Integer Multiply with EFLAGS result
3668def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003669 (implicit EFLAGS)),
3670 (IMUL16rr GR16:$src1, GR16:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003671def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003672 (implicit EFLAGS)),
3673 (IMUL32rr GR32:$src1, GR32:$src2)>;
3674
Dan Gohman99a12192009-03-04 19:44:21 +00003675// Register-Memory Signed Integer Multiply with EFLAGS result
3676def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003677 (implicit EFLAGS)),
3678 (IMUL16rm GR16:$src1, addr:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003679def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingf5399032008-12-12 21:15:41 +00003680 (implicit EFLAGS)),
3681 (IMUL32rm GR32:$src1, addr:$src2)>;
3682
Dan Gohman99a12192009-03-04 19:44:21 +00003683// Register-Integer Signed Integer Multiply with EFLAGS result
3684def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003685 (implicit EFLAGS)),
3686 (IMUL16rri GR16:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003687def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003688 (implicit EFLAGS)),
3689 (IMUL32rri GR32:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003690def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003691 (implicit EFLAGS)),
3692 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003693def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003694 (implicit EFLAGS)),
3695 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3696
Dan Gohman99a12192009-03-04 19:44:21 +00003697// Memory-Integer Signed Integer Multiply with EFLAGS result
3698def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003699 (implicit EFLAGS)),
3700 (IMUL16rmi addr:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003701def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003702 (implicit EFLAGS)),
3703 (IMUL32rmi addr:$src1, imm:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003704def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003705 (implicit EFLAGS)),
3706 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
Dan Gohman99a12192009-03-04 19:44:21 +00003707def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
Bill Wendlingf5399032008-12-12 21:15:41 +00003708 (implicit EFLAGS)),
3709 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3710
Dan Gohman99a12192009-03-04 19:44:21 +00003711// Optimize multiply by 2 with EFLAGS result.
Evan Cheng00cf7932009-01-27 03:30:42 +00003712let AddedComplexity = 2 in {
Dan Gohman99a12192009-03-04 19:44:21 +00003713def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
Evan Cheng00cf7932009-01-27 03:30:42 +00003714 (implicit EFLAGS)),
3715 (ADD16rr GR16:$src1, GR16:$src1)>;
3716
Dan Gohman99a12192009-03-04 19:44:21 +00003717def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
Evan Cheng00cf7932009-01-27 03:30:42 +00003718 (implicit EFLAGS)),
3719 (ADD32rr GR32:$src1, GR32:$src1)>;
3720}
3721
Dan Gohman99a12192009-03-04 19:44:21 +00003722// INC and DEC with EFLAGS result. Note that these do not set CF.
3723def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3724 (INC8r GR8:$src)>;
3725def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3726 (implicit EFLAGS)),
3727 (INC8m addr:$dst)>;
3728def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3729 (DEC8r GR8:$src)>;
3730def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3731 (implicit EFLAGS)),
3732 (DEC8m addr:$dst)>;
3733
3734def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003735 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003736def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3737 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003738 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003739def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003740 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003741def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3742 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003743 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003744
3745def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003746 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003747def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3748 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003749 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003750def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003751 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003752def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3753 (implicit EFLAGS)),
Dan Gohmaneebcac72009-03-05 21:32:23 +00003754 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman99a12192009-03-04 19:44:21 +00003755
Bill Wendlingf5399032008-12-12 21:15:41 +00003756//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003757// Floating Point Stack Support
3758//===----------------------------------------------------------------------===//
3759
3760include "X86InstrFPStack.td"
3761
3762//===----------------------------------------------------------------------===//
Evan Cheng86ab7d32007-07-31 08:04:03 +00003763// X86-64 Support
3764//===----------------------------------------------------------------------===//
3765
Chris Lattner2de8d2b2008-01-10 05:50:42 +00003766include "X86Instr64bit.td"
Evan Cheng86ab7d32007-07-31 08:04:03 +00003767
3768//===----------------------------------------------------------------------===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +00003769// XMM Floating point support (requires SSE / SSE2)
3770//===----------------------------------------------------------------------===//
3771
3772include "X86InstrSSE.td"
Evan Cheng5e4d1e72008-04-25 18:19:54 +00003773
3774//===----------------------------------------------------------------------===//
3775// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3776//===----------------------------------------------------------------------===//
3777
3778include "X86InstrMMX.td"