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3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]61 <li><a href="#codeemit">Code Emission</a>
62 <ul>
63 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
64 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
65 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]66 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]67 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]68 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]69 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]70 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]71 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]72 </li>
73
74</ol>
75
76<div class="doc_author">
77 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
78</div>
79
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]80<div class="doc_warning">
81 <p>Warning: This is a work in progress.</p>
82</div>
83
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]84<!-- *********************************************************************** -->
85<div class="doc_section">
86 <a name="introduction">Introduction</a>
87</div>
88<!-- *********************************************************************** -->
89
90<div class="doc_text">
91
92<p>The LLVM target-independent code generator is a framework that provides a
93suite of reusable components for translating the LLVM internal representation to
94the machine code for a specified target -- either in assembly form (suitable for
95a static compiler) or in binary machine code format (usable for a JIT compiler).
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]96The LLVM target-independent code generator consists of five main components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]97
98<ol>
99<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]100capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]101of how they will be used. These interfaces are defined in
102<tt>include/llvm/Target/</tt>.</li>
103
104<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]105generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]106represent the machine code for <i>any</i> target machine. These classes are
107defined in <tt>include/llvm/CodeGen/</tt>.</li>
108
109<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
110various phases of native code generation (register allocation, scheduling, stack
111frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
112
113<li><a href="#targetimpls">Implementations of the abstract target description
114interfaces</a> for particular targets. These machine descriptions make use of
115the components provided by LLVM, and can optionally provide custom
116target-specific passes, to build complete code generators for a specific target.
117Target descriptions live in <tt>lib/Target/</tt>.</li>
118
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]119<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
120completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
121interface for target-specific issues. The code for the target-independent
122JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
123
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]124</ol>
125
126<p>
127Depending on which part of the code generator you are interested in working on,
128different pieces of this will be useful to you. In any case, you should be
129familiar with the <a href="#targetdesc">target description</a> and <a
130href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]131a backend for a new target, you will need to <a href="#targetimpls">implement the
132target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]133href="LangRef.html">LLVM code representation</a>. If you are interested in
134implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
135should only depend on the target-description and machine code representation
136classes, ensuring that it is portable.
137</p>
138
139</div>
140
141<!-- ======================================================================= -->
142<div class="doc_subsection">
143 <a name="required">Required components in the code generator</a>
144</div>
145
146<div class="doc_text">
147
148<p>The two pieces of the LLVM code generator are the high-level interface to the
149code generator and the set of reusable components that can be used to build
150target-specific backends. The two most important interfaces (<a
151href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]152href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]153required to be defined for a backend to fit into the LLVM system, but the others
154must be defined if the reusable code generator components are going to be
155used.</p>
156
157<p>This design has two important implications. The first is that LLVM can
158support completely non-traditional code generation targets. For example, the C
159backend does not require register allocation, instruction selection, or any of
160the other standard components provided by the system. As such, it only
161implements these two interfaces, and does its own thing. Another example of a
162code generator like this is a (purely hypothetical) backend that converts LLVM
163to the GCC RTL form and uses GCC to emit machine code for a target.</p>
164
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]165<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]166implement radically different code generators in the LLVM system that do not
167make use of any of the built-in components. Doing so is not recommended at all,
168but could be required for radically different targets that do not fit into the
169LLVM machine description model: programmable FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]170
171<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
172generator uses almost entirely different code paths than described in this
173document. For this reason, there are some deprecated interfaces (such as
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]174<tt>TargetSchedInfo</tt>), which are only used by the
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]175V9 backend and should not be used by any other targets. Also, all code in the
176<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
177deprecated, and should not be used as the basis for future code generator work.
Misha Brukmanf3709d62004-06-03 16:55:57 +0000[diff] [blame]178The SparcV9 backend is slowly being merged into the rest of the
179target-independent code generators, but this is a low-priority process with no
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]180predictable completion date.</p>
181
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]182</div>
183
184<!-- ======================================================================= -->
185<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]186 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]187</div>
188
189<div class="doc_text">
190
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]191<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]192quality code generation for standard register-based microprocessors. Code
193generation in this model is divided into the following stages:</p>
194
195<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]196<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
197determines an efficient way to express the input LLVM code in the target
198instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]199This stage produces the initial code for the program in the target instruction
200set, then makes use of virtual registers in SSA form and physical registers that
201represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]202conventions. This step turns the LLVM code into a DAG of target
203instructions.</li>
204
205<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
206phase takes the DAG of target instructions produced by the instruction selection
207phase, determines an ordering of the instructions, then emits the instructions
208as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
209</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]210
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]211<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
212optional stage consists of a series of machine-code optimizations that
213operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]214like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]215</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]216
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]217<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]218target code is transformed from an infinite virtual register file in SSA form
219to the concrete register file used by the target. This phase introduces spill
220code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]221
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]222<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]223machine code has been generated for the function and the amount of stack space
224required is known (used for LLVM alloca's and spill slots), the prolog and
225epilog code for the function can be inserted and "abstract stack location
226references" can be eliminated. This stage is responsible for implementing
227optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]228
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]229<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]230that operate on "final" machine code can go here, such as spill code scheduling
231and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]232
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]233<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]234puts out the code for the current function, either in the target assembler
235format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]236
237</ol>
238
239<p>
240The code generator is based on the assumption that the instruction selector will
241use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]242native instructions. Alternative code generator designs based on pattern
243expansion and
244aggressive iterative peephole optimization are much slower. This design
245permits efficient compilation (important for JIT environments) and
246aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]247components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]248compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]249
250<p>
251In addition to these stages, target implementations can insert arbitrary
252target-specific passes into the flow. For example, the X86 target uses a
253special pass to handle the 80x87 floating point stack architecture. Other
254targets with unusual requirements can be supported with custom passes as needed.
255</p>
256
257</div>
258
259
260<!-- ======================================================================= -->
261<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]262 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]263</div>
264
265<div class="doc_text">
266
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]267<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]268architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]269information (e.g., an <tt>add</tt> instruction is almost identical to a
270<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]271In order to allow the maximum amount of commonality to be factored out, the LLVM
272code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]273describe big chunks of the target machine, which allows the use of
274domain-specific and target-specific abstractions to reduce the amount of
275repetition.
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]276</p>
277
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]278<p>As LLVM continues to be developed and refined, we plan to move more and more
279of the target description to be in <tt>.td</tt> form. Doing so gives us a
280number of advantages. The most important is that it makes it easier to port
281LLVM, because it reduces the amount of C++ code that has to be written and the
282surface area of the code generator that needs to be understood before someone
283can get in an get something working. Second, it is also important to us because
284it makes it easier to change things: in particular, if tables and other things
285are all emitted by tblgen, we only need to change one place (tblgen) to update
286all of the targets to a new interface.</p>
287
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]288</div>
289
290<!-- *********************************************************************** -->
291<div class="doc_section">
292 <a name="targetdesc">Target description classes</a>
293</div>
294<!-- *********************************************************************** -->
295
296<div class="doc_text">
297
298<p>The LLVM target description classes (which are located in the
299<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]300target machine; independent of any particular client. These classes are
301designed to capture the <i>abstract</i> properties of the target (such as the
302instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]303of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]304
305<p>All of the target description classes (except the <tt><a
306href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
307the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]308get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]309href="#targetmachine">TargetMachine</a></tt> class provides accessors that
310should be implemented by the target.</p>
311
312</div>
313
314<!-- ======================================================================= -->
315<div class="doc_subsection">
316 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
317</div>
318
319<div class="doc_text">
320
321<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
322access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]323classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
324<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
325designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]326a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
327implements the various virtual methods. The only required target description
328class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
329code generator components are to be used, the other interfaces should be
330implemented as well.</p>
331
332</div>
333
334
335<!-- ======================================================================= -->
336<div class="doc_subsection">
337 <a name="targetdata">The <tt>TargetData</tt> class</a>
338</div>
339
340<div class="doc_text">
341
342<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]343and it is the only class that is not extensible (you cannot derived a new
344class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]345lays out memory for structures, the alignment requirements for various data
346types, the size of pointers in the target, and whether the target is
347little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]348
349</div>
350
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]351<!-- ======================================================================= -->
352<div class="doc_subsection">
353 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
354</div>
355
356<div class="doc_text">
357
358<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
359selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]360operations. Among other things, this class indicates:
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]361<ul><li>an initial register class to use for various ValueTypes</li>
362 <li>which operations are natively supported by the target machine</li>
363 <li>the return type of setcc operations</li>
364 <li>the type to use for shift amounts</li>
365 <li>various high-level characteristics, like whether it is profitable to turn
366 division by a constant into a multiplication sequence</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]367</ol></p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]368
369</div>
370
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]371<!-- ======================================================================= -->
372<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]373 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]374</div>
375
376<div class="doc_text">
377
378<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
379<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
380target and any interactions between the registers.</p>
381
382<p>Registers in the code generator are represented in the code generator by
383unsigned numbers. Physical registers (those that actually exist in the target
384description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]385large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]386
387<p>Each register in the processor description has an associated
Chris Lattner88a06d22005-09-30 17:46:55 +0000[diff] [blame]388<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the register
389(used for assembly output and debugging dumps) and a set of aliases (used to
390indicate that one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]391</p>
392
393<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
394exposes a set of processor specific register classes (instances of the
395<tt>TargetRegisterClass</tt> class). Each register class contains sets of
396registers that have the same properties (for example, they are all 32-bit
397integer registers). Each SSA virtual register created by the instruction
398selector has an associated register class. When the register allocator runs, it
399replaces virtual registers with a physical register in the set.</p>
400
401<p>
402The target-specific implementations of these classes is auto-generated from a <a
403href="TableGenFundamentals.html">TableGen</a> description of the register file.
404</p>
405
406</div>
407
408<!-- ======================================================================= -->
409<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]410 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]411</div>
412
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]413<div class="doc_text">
414 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
415 instructions supported by the target. It is essentially an array of
416 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
417 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]418 for the opcode, the number of operands, the list of implicit register uses
419 and defs, whether the instruction has certain target-independent properties
420 (accesses memory, is commutable, etc), and holds any target-specific flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]421</div>
422
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]423<!-- ======================================================================= -->
424<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]425 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]426</div>
427
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]428<div class="doc_text">
429 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
430 stack frame layout of the target. It holds the direction of stack growth,
431 the known stack alignment on entry to each function, and the offset to the
432 locals area. The offset to the local area is the offset from the stack
433 pointer on function entry to the first location where function data (local
434 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]435</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]436
437<!-- ======================================================================= -->
438<div class="doc_subsection">
439 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
440</div>
441
442<div class="doc_text">
443 <p>
444 TODO
445 </p>
446</div>
447
448
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]449<!-- ======================================================================= -->
450<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]451 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]452</div>
453
454<!-- *********************************************************************** -->
455<div class="doc_section">
456 <a name="codegendesc">Machine code description classes</a>
457</div>
458<!-- *********************************************************************** -->
459
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]460<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]461
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]462<p>
463At the high-level, LLVM code is translated to a machine specific representation
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]464formed out of <a href="#machinefunction">MachineFunction</a>,
465<a href="#machinebasicblock">MachineBasicBlock</a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]466href="#machineinstr"><tt>MachineInstr</tt></a> instances
467(defined in include/llvm/CodeGen). This representation is completely target
468agnostic, representing instructions in their most abstract form: an opcode and a
469series of operands. This representation is designed to support both SSA
470representation for machine code, as well as a register allocated, non-SSA form.
471</p>
472
473</div>
474
475<!-- ======================================================================= -->
476<div class="doc_subsection">
477 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
478</div>
479
480<div class="doc_text">
481
482<p>Target machine instructions are represented as instances of the
483<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]484representing machine instructions. In particular, it only keeps track of
485an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]486
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]487<p>The opcode number is a simple unsigned number that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]488specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]489the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]490are auto-generated from this description. The <tt>MachineInstr</tt> class does
491not have any information about how to interpret the instruction (i.e., what the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]492semantics of the instruction are): for that you must refer to the
493<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
494
495<p>The operands of a machine instruction can be of several different types:
496they can be a register reference, constant integer, basic block reference, etc.
497In addition, a machine operand should be marked as a def or a use of the value
498(though only registers are allowed to be defs).</p>
499
500<p>By convention, the LLVM code generator orders instruction operands so that
501all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]502that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]503instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
504and stores the result into the "%i3" register. In the LLVM code generator,
505the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
506first.</p>
507
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]508<p>Keeping destination (definition) operands at the beginning of the operand
509list has several advantages. In particular, the debugging printer will print
510the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]511
512<pre>
513 %r3 = add %i1, %i2
514</pre>
515
516<p>If the first operand is a def, and it is also easier to <a
517href="#buildmi">create instructions</a> whose only def is the first
518operand.</p>
519
520</div>
521
522<!-- _______________________________________________________________________ -->
523<div class="doc_subsubsection">
524 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
525</div>
526
527<div class="doc_text">
528
529<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
530located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
531<tt>BuildMI</tt> functions make it easy to build arbitrary machine
532instructions. Usage of the <tt>BuildMI</tt> functions look like this:
533</p>
534
535<pre>
536 // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
537 // instruction. The '1' specifies how many operands will be added.
538 MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
539
540 // Create the same instr, but insert it at the end of a basic block.
541 MachineBasicBlock &amp;MBB = ...
542 BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
543
544 // Create the same instr, but insert it before a specified iterator point.
545 MachineBasicBlock::iterator MBBI = ...
546 BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
547
548 // Create a 'cmp Reg, 0' instruction, no destination reg.
549 MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
550 // Create an 'sahf' instruction which takes no operands and stores nothing.
551 MI = BuildMI(X86::SAHF, 0);
552
553 // Create a self looping branch instruction.
554 BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
555</pre>
556
557<p>
558The key thing to remember with the <tt>BuildMI</tt> functions is that you have
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]559to specify the number of operands that the machine instruction will take. This
560allows for efficient memory allocation. You also need to specify if operands
561default to be uses of values, not definitions. If you need to add a definition
562operand (other than the optional destination register), you must explicitly
563mark it as such.
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]564</p>
565
566</div>
567
568<!-- _______________________________________________________________________ -->
569<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]570 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]571</div>
572
573<div class="doc_text">
574
575<p>One important issue that the code generator needs to be aware of is the
576presence of fixed registers. In particular, there are often places in the
577instruction stream where the register allocator <em>must</em> arrange for a
578particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]579limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]580with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
581conventions. In any case, the instruction selector should emit code that
582copies a virtual register into or out of a physical register when needed.</p>
583
584<p>For example, consider this simple LLVM example:</p>
585
586<pre>
587 int %test(int %X, int %Y) {
588 %Z = div int %X, %Y
589 ret int %Z
590 }
591</pre>
592
593<p>The X86 instruction selector produces this machine code for the div
594and ret (use
595"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
596
597<pre>
598 ;; Start of div
599 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
600 %reg1027 = sar %reg1024, 31
601 %EDX = mov %reg1027 ;; Sign extend X into EDX
602 idiv %reg1025 ;; Divide by Y (in reg1025)
603 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
604
605 ;; Start of ret
606 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
607 ret
608</pre>
609
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]610<p>By the end of code generation, the register allocator has coalesced
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]611the registers and deleted the resultant identity moves, producing the
612following code:</p>
613
614<pre>
615 ;; X is in EAX, Y is in ECX
616 mov %EAX, %EDX
617 sar %EDX, 31
618 idiv %ECX
619 ret
620</pre>
621
622<p>This approach is extremely general (if it can handle the X86 architecture,
623it can handle anything!) and allows all of the target specific
624knowledge about the instruction stream to be isolated in the instruction
625selector. Note that physical registers should have a short lifetime for good
626code generation, and all physical registers are assumed dead on entry and
627exit of basic blocks (before register allocation). Thus if you need a value
628to be live across basic block boundaries, it <em>must</em> live in a virtual
629register.</p>
630
631</div>
632
633<!-- _______________________________________________________________________ -->
634<div class="doc_subsubsection">
635 <a name="ssa">Machine code SSA form</a>
636</div>
637
638<div class="doc_text">
639
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]640<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]641are maintained in SSA-form until register allocation happens. For the most
642part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
643become machine code PHI nodes, and virtual registers are only allowed to have a
644single definition.</p>
645
646<p>After register allocation, machine code is no longer in SSA-form, as there
647are no virtual registers left in the code.</p>
648
649</div>
650
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]651<!-- ======================================================================= -->
652<div class="doc_subsection">
653 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
654</div>
655
656<div class="doc_text">
657
658<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
659(<a href="#machineinstr">MachineInstr</a> instances). It roughly corresponds to
660the LLVM code input to the instruction selector, but there can be a one-to-many
661mapping (i.e. one LLVM basic block can map to multiple machine basic blocks).
662The MachineBasicBlock class has a "<tt>getBasicBlock</tt>" method, which returns
663the LLVM basic block that it comes from.
664</p>
665
666</div>
667
668<!-- ======================================================================= -->
669<div class="doc_subsection">
670 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
671</div>
672
673<div class="doc_text">
674
675<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
676(<a href="#machinebasicblock">MachineBasicBlock</a> instances). It corresponds
677one-to-one with the LLVM function input to the instruction selector. In
678addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
679the MachineConstantPool, MachineFrameInfo, MachineFunctionInfo,
680SSARegMap, and a set of live in and live out registers for the function. See
681<tt>MachineFunction.h</tt> for more information.
682</p>
683
684</div>
685
686
687
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]688<!-- *********************************************************************** -->
689<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]690 <a name="codegenalgs">Target-independent code generation algorithms</a>
691</div>
692<!-- *********************************************************************** -->
693
694<div class="doc_text">
695
696<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]697href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]698explains how they work and some of the rationale behind their design.</p>
699
700</div>
701
702<!-- ======================================================================= -->
703<div class="doc_subsection">
704 <a name="instselect">Instruction Selection</a>
705</div>
706
707<div class="doc_text">
708<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]709Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]710code generator into target-specific machine instructions. There are several
711well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]712the SelectionDAG based instruction selector framework and an old-style 'simple'
713instruction selector (which effectively peephole selects each LLVM instruction
714into a series of machine instructions). We recommend that all targets use the
715SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]716</p>
717
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]718<p>Portions of the DAG instruction selector are generated from the target
719description files (<tt>*.td</tt>) files. Eventually, we aim for the entire
720instruction selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]721</div>
722
723<!-- _______________________________________________________________________ -->
724<div class="doc_subsubsection">
725 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
726</div>
727
728<div class="doc_text">
729
730<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]731The SelectionDAG provides an abstraction for code representation in a way that
732is amenable to instruction selection using automatic techniques
733(e.g. dynamic-programming based optimal pattern matching selectors), It is also
734well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
735large variety of very-low-level (but target-independent)
736<a href="#selectiondag_optimize">optimizations</a> may be
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]737performed: ones which require extensive information about the instructions
738efficiently supported by the target.
739</p>
740
741<p>
742The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]743<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
744operation code (Opcode) that indicates what operation the node performs.
745The various operation node types are described at the top of the
746<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
747operation, nodes may contain additional information (e.g. the condition code
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]748for a SETCC node) contained in a derived class.</p>
749
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]750<p>Although most operations define a single value, each node in the graph may
751define multiple values. For example, a combined div/rem operation will define
752both the dividend and the remainder. Many other situations require multiple
753values as well. Each node also has some number of operands, which are edges
754to the node defining the used value. Because nodes may define multiple values,
755edges are represented by instances of the <tt>SDOperand</tt> class, which is
756a &lt;SDNode, unsigned&gt; pair, indicating the node and result
757value being used, respectively. Each value produced by an SDNode has an
758associated MVT::ValueType, indicating what type the value is.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]759</p>
760
761<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]762SelectionDAGs contain two different kinds of values: those that represent data
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]763flow and those that represent control flow dependencies. Data values are simple
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]764edges with an integer or floating point value type. Control edges are
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]765represented as "chain" edges which are of type MVT::Other. These edges provide
766an ordering between nodes that have side effects (such as
767loads/stores/calls/return/etc). All nodes that have side effects should take a
768token chain as input and produce a new one as output. By convention, token
769chain inputs are always operand #0, and chain results are always the last
770value produced by an operation.</p>
771
772<p>
773A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Chris Lattnere0c13172005-05-09 15:41:03 +0000[diff] [blame]774always a marker node with an Opcode of ISD::EntryToken. The Root node is the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]775final side-effecting node in the token chain. For example, in a single basic
776block function, this would be the return node.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]777</p>
778
779<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]780One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]781DAG. A legal DAG for a target is one that only uses supported operations and
782supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
783or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]784phase is responsible for turning an illegal DAG into a legal DAG.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]785</p>
786</div>
787
788<!-- _______________________________________________________________________ -->
789<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]790 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]791</div>
792
793<div class="doc_text">
794
795<p>
796SelectionDAG-based instruction selection consists of the following steps:
797</p>
798
799<ol>
800<li><a href="#selectiondag_build">Build initial DAG</a> - This stage performs
801 a simple translation from the input LLVM code to an illegal SelectionDAG.
802 </li>
803<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
804 performs simple optimizations on the SelectionDAG to simplify it and
805 recognize meta instructions (like rotates and div/rem pairs) for
806 targets that support these meta operations. This makes the resultant code
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]807 more efficient and the 'select instructions from DAG' phase (below) simpler.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]808</li>
809<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
810 converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
811 unsupported operations and data types.</li>
812<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
813 second run of the SelectionDAG optimized the newly legalized DAG, to
814 eliminate inefficiencies introduced by legalization.</li>
815<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
816 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]817 instructions. This process translates the target-independent input DAG into
818 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]819<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]820 - The last phase assigns a linear order to the instructions in the
821 target-instruction DAG and emits them into the MachineFunction being
822 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]823</ol>
824
825<p>After all of these steps are complete, the SelectionDAG is destroyed and the
826rest of the code generation passes are run.</p>
827
828</div>
829
830<!-- _______________________________________________________________________ -->
831<div class="doc_subsubsection">
832 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
833</div>
834
835<div class="doc_text">
836
837<p>
838The initial SelectionDAG is naively peephole expanded from the LLVM input by
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]839the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
840intent of this pass is to expose as much low-level, target-specific details
841to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
842add turns into an SDNode add while a geteelementptr is expanded into the obvious
843arithmetic). This pass requires target-specific hooks to lower calls and
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]844returns, varargs, etc. For these features, the TargetLowering interface is
845used.
846</p>
847
848</div>
849
850<!-- _______________________________________________________________________ -->
851<div class="doc_subsubsection">
852 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
853</div>
854
855<div class="doc_text">
856
857<p>The Legalize phase is in charge of converting a DAG to only use the types and
858operations that are natively supported by the target. This involves two major
859tasks:</p>
860
861<ol>
862<li><p>Convert values of unsupported types to values of supported types.</p>
863 <p>There are two main ways of doing this: promoting a small type to a larger
Chris Lattnerfd84c2d2005-04-25 00:38:52 +0000[diff] [blame]864 type (e.g. f32 -&gt; f64, or i16 -&gt; i32), and breaking up large
865 integer types
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]866 to smaller ones (e.g. implementing i64 with i32 operations where
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]867 possible). Type conversions can insert sign and zero extensions as
868 needed to make sure that the final code has the same behavior as the
869 input.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]870</li>
871
872<li><p>Eliminate operations that are not supported by the target in a supported
873 type.</p>
874 <p>Targets often have wierd constraints, such as not supporting every
875 operation on every supported datatype (e.g. X86 does not support byte
876 conditional moves). Legalize takes care of either open-coding another
877 sequence of operations to emulate the operation (this is known as
878 expansion), promoting to a larger type that supports the operation
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]879 (promotion), or using a target-specific hook to implement the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]880 legalization.</p>
881</li>
882</ol>
883
884<p>
885Instead of using a Legalize pass, we could require that every target-specific
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]886<a href="#selectiondag_optimize">selector</a> supports and expands every
887operator and type even if they are not supported and may require many
888instructions to implement (in fact, this is the approach taken by the
889"simple" selectors). However, using a Legalize pass allows all of the
890cannonicalization patterns to be shared across targets which makes it very
891easy to optimize the cannonicalized code because it is still in the form of
892a DAG.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]893</p>
894
895</div>
896
897<!-- _______________________________________________________________________ -->
898<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]899 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
900 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]901</div>
902
903<div class="doc_text">
904
905<p>
906The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]907immediately after the DAG is built and once after legalization. The first run
908of the pass allows the initial code to be cleaned up (e.g. performing
909optimizations that depend on knowing that the operators have restricted type
910inputs). The second run of the pass cleans up the messy code generated by the
911Legalize pass, allowing Legalize to be very simple since it can ignore many
912special cases.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]913</p>
914
915<p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]916One important class of optimizations performed is optimizing inserted sign and
917zero extension instructions. We currently use ad-hoc techniques, but could move
918to more rigorous techniques in the future. Here are some good
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]919papers on the subject:</p>
920
921<p>
922"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
923integer arithmetic</a>"<br>
924Kevin Redwine and Norman Ramsey<br>
925International Conference on Compiler Construction (CC) 2004
926</p>
927
928
929<p>
930 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
931 sign extension elimination</a>"<br>
932 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
933 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
934 and Implementation.
935</p>
936
937</div>
938
939<!-- _______________________________________________________________________ -->
940<div class="doc_subsubsection">
941 <a name="selectiondag_select">SelectionDAG Select Phase</a>
942</div>
943
944<div class="doc_text">
945
946<p>The Select phase is the bulk of the target-specific code for instruction
947selection. This phase takes a legal SelectionDAG as input, and does simple
948pattern matching on the DAG to generate code. In time, the Select phase will
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]949be automatically generated from the target's InstrInfo.td file, which is why we
950want to make the Select phase as simple and mechanical as possible.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]951
952</div>
953
954<!-- _______________________________________________________________________ -->
955<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]956 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]957</div>
958
959<div class="doc_text">
960
961<p>The scheduling phase takes the DAG of target instructions from the selection
962phase and assigns an order. The scheduler can pick an order depending on
963various constraints of the machines (i.e. order for minimal register pressure or
964try to cover instruction latencies). Once an order is established, the DAG is
965converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
966Selection DAG is destroyed.
967</p>
968
969</div>
970
971<!-- _______________________________________________________________________ -->
972<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]973 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
974</div>
975
976<div class="doc_text">
977
978<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]979<li>Optional function-at-a-time selection.</li>
980<li>Auto-generate entire selector from .td file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]981</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]982</ol>
983
984</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]985
986<!-- ======================================================================= -->
987<div class="doc_subsection">
988 <a name="ssamco">SSA-based Machine Code Optimizations</a>
989</div>
990<div class="doc_text"><p>To Be Written</p></div>
991<!-- ======================================================================= -->
992<div class="doc_subsection">
993 <a name="regalloc">Register Allocation</a>
994</div>
995<div class="doc_text"><p>To Be Written</p></div>
996<!-- ======================================================================= -->
997<div class="doc_subsection">
998 <a name="proepicode">Prolog/Epilog Code Insertion</a>
999</div>
1000<div class="doc_text"><p>To Be Written</p></div>
1001<!-- ======================================================================= -->
1002<div class="doc_subsection">
1003 <a name="latemco">Late Machine Code Optimizations</a>
1004</div>
1005<div class="doc_text"><p>To Be Written</p></div>
1006<!-- ======================================================================= -->
1007<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]1008 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1009</div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1010
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]1011
1012<!-- _______________________________________________________________________ -->
1013<div class="doc_subsubsection">
1014 <a name="codeemit_asm">Generating Assembly Code</a>
1015</div>
1016
1017<div class="doc_text">
1018
1019</div>
1020
1021
1022<!-- _______________________________________________________________________ -->
1023<div class="doc_subsubsection">
1024 <a name="codeemit_bin">Generating Binary Machine Code</a>
1025</div>
1026
1027<div class="doc_text">
1028 <p>For the JIT or .o file writer</p>
1029</div>
1030
1031
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1032<!-- *********************************************************************** -->
1033<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]1034 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1035</div>
1036<!-- *********************************************************************** -->
1037
1038<div class="doc_text">
1039
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1040<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1041are specific to the code generator for a particular target.</p>
1042
1043</div>
1044
1045
1046<!-- ======================================================================= -->
1047<div class="doc_subsection">
1048 <a name="x86">The X86 backend</a>
1049</div>
1050
1051<div class="doc_text">
1052
1053<p>
1054The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
1055code generator currently targets a generic P6-like processor. As such, it
1056produces a few P6-and-above instructions (like conditional moves), but it does
1057not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1058will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1059implementations.</p>
1060
1061</div>
1062
1063<!-- _______________________________________________________________________ -->
1064<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1065 <a name="x86_tt">X86 Target Triples Supported</a>
1066</div>
1067
1068<div class="doc_text">
1069<p>
1070The following are the known target triples that are supported by the X86
1071backend. This is not an exhaustive list, but it would be useful to add those
1072that people test.
1073</p>
1074
1075<ul>
1076<li><b>i686-pc-linux-gnu</b> - Linux</li>
1077<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1078<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1079<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame^]1080<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1081</ul>
1082
1083</div>
1084
1085<!-- _______________________________________________________________________ -->
1086<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1087 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1088</div>
1089
1090<div class="doc_text">
1091
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1092<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1093forming memory addresses of the following expression directly in integer
1094instructions (which use ModR/M addressing):</p>
1095
1096<pre>
1097 Base+[1,2,4,8]*IndexReg+Disp32
1098</pre>
1099
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1100<p>In order to represent this, LLVM tracks no less than 4 operands for each
1101memory operand of this form. This means that the "load" form of 'mov' has the
1102following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1103
1104<pre>
1105Index: 0 | 1 2 3 4
1106Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1107OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1108</pre>
1109
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1110<p>Stores, and all other instructions, treat the four memory operands in the
1111same way, in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1112
1113</div>
1114
1115<!-- _______________________________________________________________________ -->
1116<div class="doc_subsubsection">
1117 <a name="x86_names">Instruction naming</a>
1118</div>
1119
1120<div class="doc_text">
1121
1122<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1123An instruction name consists of the base name, a default operand size, and a
1124a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1125
1126<p>
1127<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1128<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1129<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1130<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1131</p>
1132
1133</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1134
1135<!-- *********************************************************************** -->
1136<hr>
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1142
1143 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
1144 <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
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