Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
Chris Lattner | 74c8d67 | 2010-03-24 00:47:47 +0000 | [diff] [blame] | 31 | def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, |
| 32 | [SDTCisInt<0>, SDTCisVT<1, i32>]>; |
| 33 | |
Chris Lattner | 1aec4d7 | 2010-03-24 00:49:29 +0000 | [diff] [blame] | 34 | def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, |
| 35 | [SDTCisSameAs<0, 2>, |
| 36 | SDTCisSameAs<0, 3>, |
| 37 | SDTCisInt<0>, SDTCisVT<1, i32>]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 38 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 39 | [SDTCisVT<0, OtherVT>, |
| 40 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 41 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 42 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 43 | [SDTCisVT<0, i8>, |
| 44 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 45 | def SDTX86SetCC_C : SDTypeProfile<1, 2, |
| 46 | [SDTCisInt<0>, |
| 47 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 48 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 49 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 50 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 51 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 52 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 53 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 54 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 55 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 56 | |
Sean Callanan | 1c97ceb | 2009-06-23 23:25:37 +0000 | [diff] [blame] | 57 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 58 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 59 | SDTCisVT<1, i32>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 60 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 61 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 62 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 63 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, |
| 64 | SDTCisVT<1, iPTR>, |
| 65 | SDTCisVT<2, iPTR>]>; |
| 66 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 67 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 68 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 69 | def SDTX86Void : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 70 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 71 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 72 | |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 73 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 74 | |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 75 | def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
| 76 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 77 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 78 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 79 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 80 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 81 | def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; |
| 82 | def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 83 | |
| 84 | def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, |
| 85 | [SDNPHasChain]>; |
| 86 | def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE, |
| 87 | [SDNPHasChain]>; |
| 88 | def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, |
| 89 | [SDNPHasChain]>; |
| 90 | def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, |
| 91 | [SDNPHasChain]>; |
| 92 | def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, |
| 93 | [SDNPHasChain]>; |
| 94 | |
| 95 | |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 96 | def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; |
| 97 | def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 98 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 99 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 100 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 101 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 102 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 103 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 104 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 105 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 106 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 107 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 108 | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 109 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 110 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 111 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 112 | SDNPMayLoad, SDNPMemOperand]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 113 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 114 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 115 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 116 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 117 | [SDNPHasChain, SDNPMayStore, |
| 118 | SDNPMayLoad, SDNPMemOperand]>; |
| 119 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 120 | [SDNPHasChain, SDNPMayStore, |
| 121 | SDNPMayLoad, SDNPMemOperand]>; |
| 122 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 123 | [SDNPHasChain, SDNPMayStore, |
| 124 | SDNPMayLoad, SDNPMemOperand]>; |
| 125 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 126 | [SDNPHasChain, SDNPMayStore, |
| 127 | SDNPMayLoad, SDNPMemOperand]>; |
| 128 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 129 | [SDNPHasChain, SDNPMayStore, |
| 130 | SDNPMayLoad, SDNPMemOperand]>; |
| 131 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 132 | [SDNPHasChain, SDNPMayStore, |
| 133 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 134 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 135 | [SDNPHasChain, SDNPMayStore, |
| 136 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 137 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 138 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 139 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 140 | def X86vastart_save_xmm_regs : |
| 141 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", |
| 142 | SDT_X86VASTART_SAVE_XMM_REGS, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 143 | [SDNPHasChain, SDNPVariadic]>; |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 144 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 145 | def X86callseq_start : |
| 146 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 147 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 148 | def X86callseq_end : |
| 149 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 150 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 151 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 152 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 153 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag, |
| 154 | SDNPVariadic]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 155 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 156 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 157 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 158 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 159 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 160 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 161 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 162 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 163 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 164 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 165 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 166 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 167 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 168 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 169 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 170 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 171 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 172 | [SDNPHasChain]>; |
| 173 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 174 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 175 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 176 | |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 177 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 178 | [SDNPCommutative]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 179 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 180 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 181 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 182 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 183 | [SDNPCommutative]>; |
Chris Lattner | 74c8d67 | 2010-03-24 00:47:47 +0000 | [diff] [blame] | 184 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 185 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 186 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 187 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 188 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 189 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 190 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 191 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 192 | [SDNPCommutative]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 193 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 194 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 195 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 196 | def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void, |
| 197 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 198 | |
| 199 | def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, |
| 200 | []>; |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 201 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 202 | //===----------------------------------------------------------------------===// |
| 203 | // X86 Operand Definitions. |
| 204 | // |
| 205 | |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 206 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for |
| 207 | // the index operand of an address, to conform to x86 encoding restrictions. |
| 208 | def ptr_rc_nosp : PointerLikeRegClass<1>; |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 209 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 210 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 211 | // |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 212 | def X86MemAsmOperand : AsmOperandClass { |
| 213 | let Name = "Mem"; |
Daniel Dunbar | 54ddf3d | 2010-05-22 21:02:29 +0000 | [diff] [blame] | 214 | let SuperClasses = []; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 215 | } |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 216 | def X86AbsMemAsmOperand : AsmOperandClass { |
| 217 | let Name = "AbsMem"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 218 | let SuperClasses = [X86MemAsmOperand]; |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 219 | } |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 220 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 221 | let PrintMethod = printMethod; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 222 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 223 | let ParserMatchClass = X86MemAsmOperand; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 224 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 225 | |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 226 | def opaque32mem : X86MemOperand<"printopaquemem">; |
| 227 | def opaque48mem : X86MemOperand<"printopaquemem">; |
| 228 | def opaque80mem : X86MemOperand<"printopaquemem">; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 229 | def opaque512mem : X86MemOperand<"printopaquemem">; |
| 230 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 231 | def i8mem : X86MemOperand<"printi8mem">; |
| 232 | def i16mem : X86MemOperand<"printi16mem">; |
| 233 | def i32mem : X86MemOperand<"printi32mem">; |
| 234 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 235 | def i128mem : X86MemOperand<"printi128mem">; |
Bruno Cardoso Lopes | 94143ee | 2010-07-19 23:32:44 +0000 | [diff] [blame] | 236 | def i256mem : X86MemOperand<"printi256mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 237 | def f32mem : X86MemOperand<"printf32mem">; |
| 238 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 239 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 240 | def f128mem : X86MemOperand<"printf128mem">; |
Bruno Cardoso Lopes | e86b01c | 2010-07-09 18:27:43 +0000 | [diff] [blame] | 241 | def f256mem : X86MemOperand<"printf256mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 242 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 243 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 244 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 245 | def i8mem_NOREX : Operand<i64> { |
| 246 | let PrintMethod = "printi8mem"; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 247 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 248 | let ParserMatchClass = X86MemAsmOperand; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 249 | } |
| 250 | |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 251 | // Special i32mem for addresses of load folding tail calls. These are not |
| 252 | // allowed to use callee-saved registers since they must be scheduled |
| 253 | // after callee-saved register are popped. |
| 254 | def i32mem_TC : Operand<i32> { |
| 255 | let PrintMethod = "printi32mem"; |
| 256 | let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm); |
| 257 | let ParserMatchClass = X86MemAsmOperand; |
| 258 | } |
| 259 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 260 | |
Daniel Dunbar | b834f5d | 2010-01-30 01:02:48 +0000 | [diff] [blame] | 261 | let ParserMatchClass = X86AbsMemAsmOperand, |
| 262 | PrintMethod = "print_pcrel_imm" in { |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 263 | def i32imm_pcrel : Operand<i32>; |
Chris Lattner | 9fc0522 | 2010-07-07 22:27:31 +0000 | [diff] [blame] | 264 | def i16imm_pcrel : Operand<i16>; |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 265 | |
| 266 | def offset8 : Operand<i64>; |
| 267 | def offset16 : Operand<i64>; |
| 268 | def offset32 : Operand<i64>; |
| 269 | def offset64 : Operand<i64>; |
| 270 | |
| 271 | // Branch targets have OtherVT type and print as pc-relative values. |
| 272 | def brtarget : Operand<OtherVT>; |
| 273 | def brtarget8 : Operand<OtherVT>; |
| 274 | |
| 275 | } |
| 276 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 277 | def SSECC : Operand<i8> { |
| 278 | let PrintMethod = "printSSECC"; |
| 279 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 280 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 281 | class ImmSExtAsmOperandClass : AsmOperandClass { |
Daniel Dunbar | 54ddf3d | 2010-05-22 21:02:29 +0000 | [diff] [blame] | 282 | let SuperClasses = [ImmAsmOperand]; |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 283 | let RenderMethod = "addImmOperands"; |
Daniel Dunbar | 1fe591d | 2010-05-20 20:20:39 +0000 | [diff] [blame] | 284 | } |
| 285 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 286 | // Sign-extended immediate classes. We don't need to define the full lattice |
| 287 | // here because there is no instruction with an ambiguity between ImmSExti64i32 |
| 288 | // and ImmSExti32i8. |
| 289 | // |
| 290 | // The strange ranges come from the fact that the assembler always works with |
| 291 | // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" |
| 292 | // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). |
| 293 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 294 | // [0, 0x7FFFFFFF] | |
| 295 | // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 296 | def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { |
| 297 | let Name = "ImmSExti64i32"; |
| 298 | } |
| 299 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 300 | // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | |
| 301 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 302 | def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { |
| 303 | let Name = "ImmSExti16i8"; |
| 304 | let SuperClasses = [ImmSExti64i32AsmOperand]; |
| 305 | } |
| 306 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 307 | // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | |
| 308 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 309 | def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { |
| 310 | let Name = "ImmSExti32i8"; |
| 311 | } |
| 312 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 313 | // [0, 0x0000007F] | |
| 314 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 315 | def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { |
| 316 | let Name = "ImmSExti64i8"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 317 | let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, |
| 318 | ImmSExti64i32AsmOperand]; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 319 | } |
| 320 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 321 | // A couple of more descriptive operand definitions. |
| 322 | // 16-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 323 | def i16i8imm : Operand<i16> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 324 | let ParserMatchClass = ImmSExti16i8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 325 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 326 | // 32-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 327 | def i32i8imm : Operand<i32> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 328 | let ParserMatchClass = ImmSExti32i8AsmOperand; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 329 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 330 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 331 | //===----------------------------------------------------------------------===// |
| 332 | // X86 Complex Pattern Definitions. |
| 333 | // |
| 334 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 335 | // Define X86 specific addressing mode. |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 336 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 337 | def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", |
Dan Gohman | a98634b | 2009-08-02 16:09:17 +0000 | [diff] [blame] | 338 | [add, sub, mul, X86mul_imm, shl, or, frameindex], |
| 339 | []>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 340 | def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 341 | [tglobaltlsaddr], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 342 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 343 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 344 | // X86 Instruction Predicate Definitions. |
Chris Lattner | 314a113 | 2010-03-14 18:31:44 +0000 | [diff] [blame] | 345 | def HasCMov : Predicate<"Subtarget->hasCMov()">; |
| 346 | def NoCMov : Predicate<"!Subtarget->hasCMov()">; |
Bruno Cardoso Lopes | 3c45734 | 2010-07-26 21:01:18 +0000 | [diff] [blame] | 347 | |
| 348 | // FIXME: temporary hack to let codegen assert or generate poor code in case |
| 349 | // no AVX version of the desired intructions is present, this is better for |
| 350 | // incremental dev (without fallbacks it's easier to spot what's missing) |
Bruno Cardoso Lopes | 5b7dab8 | 2010-07-30 19:41:24 +0000 | [diff] [blame] | 351 | def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">; |
Chris Lattner | 548abfc | 2010-10-03 18:08:05 +0000 | [diff] [blame] | 352 | def Has3DNow : Predicate<"Subtarget->has3DNow()">; |
| 353 | def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; |
Bruno Cardoso Lopes | 5b7dab8 | 2010-07-30 19:41:24 +0000 | [diff] [blame] | 354 | def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; |
| 355 | def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; |
| 356 | def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; |
| 357 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; |
| 358 | def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; |
| 359 | def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; |
| 360 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">; |
Bruno Cardoso Lopes | 3c45734 | 2010-07-26 21:01:18 +0000 | [diff] [blame] | 361 | |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 362 | def HasAVX : Predicate<"Subtarget->hasAVX()">; |
Bruno Cardoso Lopes | cdae7e8 | 2010-07-23 01:17:51 +0000 | [diff] [blame] | 363 | def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 364 | def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; |
| 365 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 366 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 367 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 368 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 369 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
Anton Korobeynikov | cf6b739 | 2009-08-03 08:12:53 +0000 | [diff] [blame] | 370 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; |
| 371 | def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 372 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 373 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; |
| 374 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" |
Anton Korobeynikov | 186fa1d | 2009-08-06 09:11:19 +0000 | [diff] [blame] | 375 | "TM.getCodeModel() != CodeModel::Kernel">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 376 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" |
| 377 | "TM.getCodeModel() == CodeModel::Kernel">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 378 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | cb0f06e | 2010-03-25 00:10:31 +0000 | [diff] [blame] | 379 | def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; |
Evan Cheng | b1f4981 | 2009-12-22 17:47:23 +0000 | [diff] [blame] | 380 | def OptForSize : Predicate<"OptForSize">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 381 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 382 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 383 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 384 | def HasAES : Predicate<"Subtarget->hasAES()">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 385 | |
| 386 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 387 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 388 | // |
| 389 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 390 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 391 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 392 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 393 | // Pattern fragments... |
| 394 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 395 | |
| 396 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 397 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 398 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 399 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 400 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 401 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 402 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 403 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 404 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 405 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 406 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 407 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 408 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 409 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 410 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 411 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 412 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 413 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 414 | |
Jakob Stoklund Olesen | 3061c44 | 2010-09-03 00:35:18 +0000 | [diff] [blame] | 415 | def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>; |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 416 | |
Chris Lattner | 1840991 | 2010-03-03 01:45:01 +0000 | [diff] [blame] | 417 | def i16immSExt8 : PatLeaf<(i16 immSext8)>; |
| 418 | def i32immSExt8 : PatLeaf<(i32 immSext8)>; |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 419 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 420 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 421 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 422 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 423 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 424 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 425 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 426 | if (ExtType == ISD::NON_EXTLOAD) |
| 427 | return true; |
| 428 | if (ExtType == ISD::EXTLOAD) |
| 429 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 430 | return false; |
| 431 | }]>; |
| 432 | |
Chris Lattner | f85eff7 | 2010-03-03 01:52:59 +0000 | [diff] [blame] | 433 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 434 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 435 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 436 | if (ExtType == ISD::EXTLOAD) |
| 437 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 438 | return false; |
| 439 | }]>; |
| 440 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 441 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 442 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 443 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 444 | if (ExtType == ISD::NON_EXTLOAD) |
| 445 | return true; |
| 446 | if (ExtType == ISD::EXTLOAD) |
| 447 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 448 | return false; |
| 449 | }]>; |
| 450 | |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 451 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 452 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; |
| 453 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 454 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
| 455 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 456 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 457 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 458 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 459 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 460 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 461 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 462 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 463 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 464 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 465 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 466 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 467 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 468 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 469 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 470 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 471 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 472 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 473 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 474 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 475 | |
| 476 | // An 'and' node with a single use. |
| 477 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 478 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 479 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 480 | // An 'srl' node with a single use. |
| 481 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 482 | return N->hasOneUse(); |
| 483 | }]>; |
| 484 | // An 'trunc' node with a single use. |
| 485 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 486 | return N->hasOneUse(); |
| 487 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 488 | |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 489 | // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. |
| 490 | def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ |
| 491 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) |
| 492 | return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); |
Chris Lattner | fdac0b6 | 2010-03-24 00:12:57 +0000 | [diff] [blame] | 493 | |
| 494 | unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); |
| 495 | APInt Mask = APInt::getAllOnesValue(BitWidth); |
| 496 | APInt KnownZero0, KnownOne0; |
| 497 | CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0); |
| 498 | APInt KnownZero1, KnownOne1; |
| 499 | CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0); |
| 500 | return (~KnownZero0 & ~KnownZero1) == 0; |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 501 | }]>; |
Evan Cheng | 4b0345b | 2010-01-11 17:03:47 +0000 | [diff] [blame] | 502 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 503 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 504 | // Instruction list. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 505 | // |
| 506 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 507 | // Nop |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 508 | let neverHasSideEffects = 1 in { |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 509 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 510 | def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), |
| 511 | "nop{w}\t$zero", []>, TB, OpSize; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 512 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 513 | "nop{l}\t$zero", []>, TB; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 514 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 515 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 516 | |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 517 | // Constructing a stack frame. |
Chris Lattner | 40cc3f8 | 2010-09-17 18:02:29 +0000 | [diff] [blame] | 518 | def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), |
| 519 | "enter\t$len, $lvl", []>; |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 520 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 521 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 522 | def LEAVE : I<0xC9, RawFrm, |
Daniel Dunbar | df4c47b | 2010-07-19 07:21:01 +0000 | [diff] [blame] | 523 | (outs), (ins), "leave", []>, Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 524 | |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 525 | //===----------------------------------------------------------------------===// |
| 526 | // Miscellaneous Instructions... |
| 527 | // |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 528 | def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 529 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS; |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 530 | let mayLoad = 1 in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 531 | def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 532 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS; |
| 533 | def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 534 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS; |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 535 | let mayLoad = 1 in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 536 | def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 537 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS; |
| 538 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 539 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 540 | let mayLoad = 1 in { |
| 541 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 542 | OpSize; |
| 543 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 544 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, |
| 545 | OpSize; |
| 546 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, |
| 547 | OpSize; |
| 548 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
| 549 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; |
| 550 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 551 | |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 552 | let mayStore = 1 in { |
| 553 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 554 | OpSize; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 555 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 556 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, |
| 557 | OpSize; |
| 558 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, |
| 559 | OpSize; |
| 560 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
| 561 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; |
| 562 | } |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 563 | } |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 564 | |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 565 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in { |
Kevin Enderby | 3c979b0 | 2010-05-03 20:45:05 +0000 | [diff] [blame] | 566 | def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 567 | "push{l}\t$imm", []>; |
Kevin Enderby | 3c979b0 | 2010-05-03 20:45:05 +0000 | [diff] [blame] | 568 | def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
| 569 | "push{w}\t$imm", []>, OpSize; |
| 570 | def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), |
Bill Wendling | 927788c | 2009-06-15 20:59:31 +0000 | [diff] [blame] | 571 | "push{l}\t$imm", []>; |
Bill Wendling | 453eb26 | 2009-06-15 19:39:04 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 574 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in { |
Dan Gohman | e5e4ff9 | 2010-05-20 16:16:00 +0000 | [diff] [blame] | 575 | def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize; |
| 576 | def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, |
| 577 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 578 | } |
| 579 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in { |
Dan Gohman | e5e4ff9 | 2010-05-20 16:16:00 +0000 | [diff] [blame] | 580 | def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize; |
| 581 | def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, |
| 582 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 583 | } |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 584 | |
Nico Weber | 50b9efc | 2010-06-23 20:00:58 +0000 | [diff] [blame] | 585 | let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], |
| 586 | mayLoad=1, neverHasSideEffects=1 in { |
| 587 | def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>, |
| 588 | Requires<[In32BitMode]>; |
| 589 | } |
| 590 | let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], |
| 591 | mayStore=1, neverHasSideEffects=1 in { |
| 592 | def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>, |
| 593 | Requires<[In32BitMode]>; |
| 594 | } |
| 595 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 596 | let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 597 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 598 | (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 599 | "bswap{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 600 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 601 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 602 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 603 | // Bit scan instructions. |
| 604 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 605 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 606 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 607 | [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 608 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 609 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 610 | [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB, |
| 611 | OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 612 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 613 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 614 | [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 615 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 616 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 617 | [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 618 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 619 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 620 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 621 | [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 622 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 623 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 624 | [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB, |
| 625 | OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 626 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 627 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 628 | [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 629 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 630 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 631 | [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 632 | } // Defs = [EFLAGS] |
| 633 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 634 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 635 | def LEA16r : I<0x8D, MRMSrcMem, |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 636 | (outs GR16:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 637 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 638 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 639 | def LEA32r : I<0x8D, MRMSrcMem, |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 640 | (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 641 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 642 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 643 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 644 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 645 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 646 | let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { |
| 647 | def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>; |
| 648 | def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize; |
| 649 | def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 650 | def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 651 | } |
| 652 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 653 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 654 | let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in |
| 655 | def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>; |
| 656 | let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in |
| 657 | def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize; |
| 658 | let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in |
| 659 | def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 660 | let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in |
| 661 | def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 662 | |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 663 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>; |
| 664 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize; |
| 665 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 666 | def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>; |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 667 | |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 668 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>; |
| 669 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize; |
| 670 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 671 | def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>; |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 672 | |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 673 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 674 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 675 | // Move Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 676 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 677 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 678 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 679 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 680 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 681 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 682 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 683 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 684 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 685 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 686 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 687 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 688 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 689 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 690 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 691 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 692 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 693 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 694 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 695 | } |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 696 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 697 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 698 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 699 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 700 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 701 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 702 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 703 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 704 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 705 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 706 | |
Chris Lattner | b5505d0 | 2010-05-13 00:02:47 +0000 | [diff] [blame] | 707 | /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a |
| 708 | /// 32-bit offset from the PC. These are only valid in x86-32 mode. |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 709 | def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 710 | "mov{b}\t{$src, %al|%al, $src}", []>, |
| 711 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 712 | def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 713 | "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize, |
| 714 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 715 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 716 | "mov{l}\t{$src, %eax|%eax, $src}", []>, |
| 717 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 718 | def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 719 | "mov{b}\t{%al, $dst|$dst, %al}", []>, |
| 720 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 721 | def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 722 | "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize, |
| 723 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 724 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 725 | "mov{l}\t{%eax, $dst|$dst, %eax}", []>, |
| 726 | Requires<[In32BitMode]>; |
Chris Lattner | b5505d0 | 2010-05-13 00:02:47 +0000 | [diff] [blame] | 727 | |
Sean Callanan | 38fee0e | 2009-09-15 18:47:29 +0000 | [diff] [blame] | 728 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 729 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 730 | def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), |
| 731 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
| 732 | def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 733 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
| 734 | def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 735 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 736 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 737 | |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 738 | let canFoldAsLoad = 1, isReMaterializable = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 739 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 740 | "mov{b}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 741 | [(set GR8:$dst, (loadi8 addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 742 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 743 | "mov{w}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 744 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 745 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 746 | "mov{l}\t{$src, $dst|$dst, $src}", |
Chris Lattner | c2406f2 | 2009-04-10 00:16:23 +0000 | [diff] [blame] | 747 | [(set GR32:$dst, (loadi32 addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 748 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 749 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 750 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 751 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 752 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 753 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 754 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 755 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 756 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 757 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 758 | [(store GR32:$src, addr:$dst)]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 759 | |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 760 | /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC. |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 761 | let isCodeGenOnly = 1 in { |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 762 | let neverHasSideEffects = 1 in |
| 763 | def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src), |
| 764 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
| 765 | |
| 766 | let mayLoad = 1, |
| 767 | canFoldAsLoad = 1, isReMaterializable = 1 in |
| 768 | def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src), |
| 769 | "mov{l}\t{$src, $dst|$dst, $src}", |
| 770 | []>; |
| 771 | |
| 772 | let mayStore = 1 in |
| 773 | def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src), |
| 774 | "mov{l}\t{$src, $dst|$dst, $src}", |
| 775 | []>; |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 776 | } |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 777 | |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 778 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so |
| 779 | // that they can be used for copying and storing h registers, which can't be |
| 780 | // encoded when a REX prefix is present. |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 781 | let isCodeGenOnly = 1 in { |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 782 | let neverHasSideEffects = 1 in |
Dan Gohman | df7dfc7 | 2009-04-15 19:48:57 +0000 | [diff] [blame] | 783 | def MOV8rr_NOREX : I<0x88, MRMDestReg, |
| 784 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 785 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 786 | let mayStore = 1 in |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 787 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 788 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
| 789 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 790 | let mayLoad = 1, |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 791 | canFoldAsLoad = 1, isReMaterializable = 1 in |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 792 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, |
| 793 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), |
| 794 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 795 | } |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 796 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 797 | //===----------------------------------------------------------------------===// |
| 798 | // Fixed-Register Multiplication and Division Instructions... |
| 799 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 800 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 801 | // Extra precision multiplication |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 802 | |
Eric Christopher | 5cb33a3 | 2010-08-09 22:52:47 +0000 | [diff] [blame] | 803 | // AL is really implied by AX, but the registers in Defs must match the |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 804 | // SDNode results (i8, i32). |
| 805 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 806 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 807 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 808 | // This probably ought to be moved to a def : Pat<> if the |
| 809 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 810 | [(set AL, (mul AL, GR8:$src)), |
| 811 | (implicit EFLAGS)]>; // AL,AH = AL*GR8 |
| 812 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 813 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 814 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
| 815 | "mul{w}\t$src", |
| 816 | []>, OpSize; // AX,DX = AX*GR16 |
| 817 | |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 818 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 819 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
| 820 | "mul{l}\t$src", |
| 821 | []>; // EAX,EDX = EAX*GR32 |
| 822 | |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 823 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 824 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 825 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 826 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 827 | // This probably ought to be moved to a def : Pat<> if the |
| 828 | // syntax can be accepted. |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 829 | [(set AL, (mul AL, (loadi8 addr:$src))), |
| 830 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8] |
| 831 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 832 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 833 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 834 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 835 | "mul{w}\t$src", |
| 836 | []>, OpSize; // AX,DX = AX*[mem16] |
| 837 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 838 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 839 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 840 | "mul{l}\t$src", |
| 841 | []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 842 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 843 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 844 | let neverHasSideEffects = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 845 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 846 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 847 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 848 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 849 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 850 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 851 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 852 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 853 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 854 | let mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 855 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 856 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 857 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 858 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 859 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 860 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
Eli Friedman | ba7b1c4 | 2009-12-26 20:08:30 +0000 | [diff] [blame] | 861 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 862 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 863 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 864 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 865 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 866 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 867 | // unsigned division/remainder |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 868 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 869 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 870 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 871 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 872 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 873 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 874 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 875 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 876 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 877 | let mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 878 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 879 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 880 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 881 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 882 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 883 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 884 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 885 | // EDX:EAX/[mem32] = EAX,EDX |
| 886 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 887 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 888 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 889 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 890 | // Signed division/remainder. |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 891 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 892 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 893 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 894 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 895 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 896 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 897 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 898 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 899 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 900 | let mayLoad = 1, mayLoad = 1 in { |
Jakob Stoklund Olesen | 3cfe010 | 2010-03-04 20:42:07 +0000 | [diff] [blame] | 901 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 902 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 903 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 904 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 905 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 906 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 907 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 908 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), |
| 909 | // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 910 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 911 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 912 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 913 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 914 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 915 | // |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 916 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 917 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 918 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 919 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 920 | let Defs = [EFLAGS] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 921 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 922 | "neg{b}\t$dst", |
| 923 | [(set GR8:$dst, (ineg GR8:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 924 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 925 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
| 926 | "neg{w}\t$dst", |
| 927 | [(set GR16:$dst, (ineg GR16:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 928 | (implicit EFLAGS)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 929 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
| 930 | "neg{l}\t$dst", |
| 931 | [(set GR32:$dst, (ineg GR32:$src1)), |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 932 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 933 | |
| 934 | let Constraints = "" in { |
| 935 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), |
| 936 | "neg{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 937 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
| 938 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 939 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), |
| 940 | "neg{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 941 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
| 942 | (implicit EFLAGS)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 943 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), |
| 944 | "neg{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 945 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
| 946 | (implicit EFLAGS)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 947 | } // Constraints = "" |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 948 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 949 | |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 950 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 951 | let AddedComplexity = 15 in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 952 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 953 | "not{b}\t$dst", |
| 954 | [(set GR8:$dst, (not GR8:$src1))]>; |
| 955 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
| 956 | "not{w}\t$dst", |
| 957 | [(set GR16:$dst, (not GR16:$src1))]>, OpSize; |
| 958 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
| 959 | "not{l}\t$dst", |
| 960 | [(set GR32:$dst, (not GR32:$src1))]>; |
Evan Cheng | aaf414c | 2009-01-21 02:09:05 +0000 | [diff] [blame] | 961 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 962 | let Constraints = "" in { |
| 963 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), |
| 964 | "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 965 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 966 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), |
| 967 | "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 968 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 969 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), |
| 970 | "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 971 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 972 | } // Constraints = "" |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 973 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 974 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 975 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 976 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 977 | let CodeSize = 2 in |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 978 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 979 | "inc{b}\t$dst", |
| 980 | [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>; |
Chris Lattner | c54a2f1 | 2010-03-24 01:02:12 +0000 | [diff] [blame] | 981 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 982 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 983 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 984 | "inc{w}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 985 | [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 986 | OpSize, Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 987 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 988 | "inc{l}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 989 | [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>, |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 990 | Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 991 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 992 | let Constraints = "", CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 993 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 994 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
| 995 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 996 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 997 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
| 998 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 999 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1000 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1001 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
| 1002 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1003 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1004 | } // Constraints = "", CodeSize = 2 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1005 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1006 | let CodeSize = 2 in |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1007 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 1008 | "dec{b}\t$dst", |
| 1009 | [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1010 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1011 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1012 | "dec{w}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1013 | [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1014 | OpSize, Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1015 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1016 | "dec{l}\t$dst", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1017 | [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>, |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1018 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1019 | } // CodeSize = 2 |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1020 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1021 | let Constraints = "", CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1022 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1023 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
| 1024 | (implicit EFLAGS)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1025 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1026 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
| 1027 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1028 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1029 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1030 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
| 1031 | (implicit EFLAGS)]>, |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1032 | Requires<[In32BitMode]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1033 | } // Constraints = "", CodeSize = 2 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1034 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1035 | |
| 1036 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1037 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1038 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1039 | def AND8rr : I<0x20, MRMDestReg, |
| 1040 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1041 | "and{b}\t{$src2, $dst|$dst, $src2}", |
| 1042 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>; |
| 1043 | def AND16rr : I<0x21, MRMDestReg, |
| 1044 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1045 | "and{w}\t{$src2, $dst|$dst, $src2}", |
| 1046 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1047 | GR16:$src2))]>, OpSize; |
| 1048 | def AND32rr : I<0x21, MRMDestReg, |
| 1049 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1050 | "and{l}\t{$src2, $dst|$dst, $src2}", |
| 1051 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1052 | GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1053 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1054 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1055 | // AND instructions with the destination register in REG and the source register |
| 1056 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1057 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1058 | def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1059 | "and{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1060 | def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst), |
| 1061 | (ins GR16:$src1, GR16:$src2), |
| 1062 | "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1063 | def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst), |
| 1064 | (ins GR32:$src1, GR32:$src2), |
| 1065 | "and{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1066 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1067 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1068 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1069 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1070 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1071 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, |
| 1072 | (loadi8 addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1073 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1074 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1075 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1076 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1077 | (loadi16 addr:$src2)))]>, |
| 1078 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1079 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1080 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1081 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1082 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1083 | (loadi32 addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1084 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1085 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1086 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1087 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1088 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, |
| 1089 | imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1090 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1091 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1092 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1093 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1094 | imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1095 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1096 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1097 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1098 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1099 | imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1100 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1101 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1102 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1103 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1, |
| 1104 | i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1105 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1106 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1107 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1108 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1109 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1, |
| 1110 | i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1111 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1112 | let Constraints = "" in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1113 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1114 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1115 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1116 | [(store (and (load addr:$dst), GR8:$src), addr:$dst), |
| 1117 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1118 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1119 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1120 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1121 | [(store (and (load addr:$dst), GR16:$src), addr:$dst), |
| 1122 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1123 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1124 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1125 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1126 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1127 | [(store (and (load addr:$dst), GR32:$src), addr:$dst), |
| 1128 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1129 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1130 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1131 | "and{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1132 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1133 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1134 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1135 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1136 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1137 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1138 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1139 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1140 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1141 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1142 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1143 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1144 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1145 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1146 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1147 | "and{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1148 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1149 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1150 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1151 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1152 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1153 | "and{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1154 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1155 | (implicit EFLAGS)]>; |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1156 | |
| 1157 | def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src), |
| 1158 | "and{b}\t{$src, %al|%al, $src}", []>; |
| 1159 | def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src), |
| 1160 | "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1161 | def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src), |
| 1162 | "and{l}\t{$src, %eax|%eax, $src}", []>; |
| 1163 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1164 | } // Constraints = "" |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1165 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1166 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1167 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1168 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), |
| 1169 | (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1170 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1171 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1172 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), |
| 1173 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1174 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1175 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>, |
| 1176 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1177 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), |
| 1178 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1179 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1180 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1181 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1182 | |
| 1183 | // OR instructions with the destination register in REG and the source register |
| 1184 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1185 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1186 | def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1187 | "or{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1188 | def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst), |
| 1189 | (ins GR16:$src1, GR16:$src2), |
| 1190 | "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1191 | def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst), |
| 1192 | (ins GR32:$src1, GR32:$src2), |
| 1193 | "or{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1194 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1195 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1196 | def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1197 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1198 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1199 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, |
| 1200 | (load addr:$src2)))]>; |
| 1201 | def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1202 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1203 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1204 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1205 | (load addr:$src2)))]>, |
| 1206 | OpSize; |
| 1207 | def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1208 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1209 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1210 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1211 | (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1212 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1213 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), |
| 1214 | (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1215 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1216 | [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1217 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), |
| 1218 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1219 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1220 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1221 | imm:$src2))]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1222 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), |
| 1223 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1224 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1225 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1226 | imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1227 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1228 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), |
| 1229 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1230 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1231 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1, |
| 1232 | i16immSExt8:$src2))]>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1233 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), |
| 1234 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1235 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1236 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1, |
| 1237 | i32immSExt8:$src2))]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1238 | let Constraints = "" in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1239 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1240 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1241 | [(store (or (load addr:$dst), GR8:$src), addr:$dst), |
| 1242 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1243 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1244 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1245 | [(store (or (load addr:$dst), GR16:$src), addr:$dst), |
| 1246 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1247 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1248 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1249 | [(store (or (load addr:$dst), GR32:$src), addr:$dst), |
| 1250 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1251 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1252 | "or{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1253 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1254 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1255 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1256 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1257 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1258 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1259 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1260 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1261 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1262 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1263 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1264 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1265 | "or{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1266 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1267 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1268 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1269 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1270 | "or{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1271 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1272 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 1273 | |
| 1274 | def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src), |
| 1275 | "or{b}\t{$src, %al|%al, $src}", []>; |
| 1276 | def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src), |
| 1277 | "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1278 | def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src), |
| 1279 | "or{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1280 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1281 | |
| 1282 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1283 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1284 | def XOR8rr : I<0x30, MRMDestReg, |
| 1285 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1286 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1287 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, |
| 1288 | GR8:$src2))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1289 | def XOR16rr : I<0x31, MRMDestReg, |
| 1290 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1291 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1292 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1293 | GR16:$src2))]>, OpSize; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1294 | def XOR32rr : I<0x31, MRMDestReg, |
| 1295 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1296 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1297 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1298 | GR32:$src2))]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1299 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1300 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1301 | // XOR instructions with the destination register in REG and the source register |
| 1302 | // in R/M. Included for the disassembler. |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1303 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1304 | def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1305 | "xor{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1306 | def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst), |
| 1307 | (ins GR16:$src1, GR16:$src2), |
| 1308 | "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 1309 | def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst), |
| 1310 | (ins GR32:$src1, GR32:$src2), |
| 1311 | "xor{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1312 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1313 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1314 | def XOR8rm : I<0x32, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1315 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1316 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1317 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, |
| 1318 | (load addr:$src2)))]>; |
| 1319 | def XOR16rm : I<0x33, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1320 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1321 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1322 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1323 | (load addr:$src2)))]>, |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1324 | OpSize; |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1325 | def XOR32rm : I<0x33, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1326 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1327 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1328 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1329 | (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1330 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1331 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1332 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1333 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
| 1334 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>; |
| 1335 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1336 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 1337 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
| 1338 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1339 | imm:$src2))]>, OpSize; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1340 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1341 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 1342 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1343 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1344 | imm:$src2))]>; |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1345 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 1346 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 1347 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1348 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1, |
| 1349 | i16immSExt8:$src2))]>, |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1350 | OpSize; |
| 1351 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 1352 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 1353 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1354 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1, |
| 1355 | i32immSExt8:$src2))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1356 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1357 | let Constraints = "" in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1358 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1359 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1360 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1361 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst), |
| 1362 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1363 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1364 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1365 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1366 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst), |
| 1367 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1368 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1369 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1370 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1371 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1372 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst), |
| 1373 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1374 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1375 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1376 | "xor{b}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1377 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst), |
| 1378 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1379 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1380 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1381 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1382 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst), |
| 1383 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1384 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1385 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1386 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1387 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1388 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst), |
| 1389 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1390 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1391 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1392 | "xor{w}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1393 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst), |
| 1394 | (implicit EFLAGS)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1395 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1396 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1397 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1398 | "xor{l}\t{$src, $dst|$dst, $src}", |
Dan Gohman | 09a2609e | 2009-03-03 19:53:46 +0000 | [diff] [blame] | 1399 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst), |
| 1400 | (implicit EFLAGS)]>; |
Sean Callanan | 7893ec6 | 2009-09-10 19:52:26 +0000 | [diff] [blame] | 1401 | |
Chris Lattner | 589ad5d | 2010-03-25 05:44:01 +0000 | [diff] [blame] | 1402 | def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src), |
| 1403 | "xor{b}\t{$src, %al|%al, $src}", []>; |
| 1404 | def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src), |
| 1405 | "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 1406 | def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src), |
| 1407 | "xor{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1408 | } // Constraints = "" |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1409 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1410 | |
| 1411 | // Shift instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1412 | let Defs = [EFLAGS] in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1413 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1414 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1415 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1416 | [(set GR8:$dst, (shl GR8:$src1, CL))]>; |
| 1417 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1418 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1419 | [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize; |
| 1420 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1421 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1422 | [(set GR32:$dst, (shl GR32:$src1, CL))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1423 | } // Uses = [CL] |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1424 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1425 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1426 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1427 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1428 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1429 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1430 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1431 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1432 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1433 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1434 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1435 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Sean Callanan | 13cf8e9 | 2009-09-16 02:28:43 +0000 | [diff] [blame] | 1436 | |
| 1437 | // NOTE: We don't include patterns for shifts of a register by one, because |
| 1438 | // 'add reg,reg' is cheaper. |
| 1439 | |
| 1440 | def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), |
| 1441 | "shl{b}\t$dst", []>; |
| 1442 | def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
| 1443 | "shl{w}\t$dst", []>, OpSize; |
| 1444 | def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
| 1445 | "shl{l}\t$dst", []>; |
| 1446 | |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1447 | } // isConvertibleToThreeAddress = 1 |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1448 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1449 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1450 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1451 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1452 | "shl{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1453 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1454 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1455 | "shl{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1456 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1457 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1458 | "shl{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1459 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1460 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1461 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1462 | "shl{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1463 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1464 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1465 | "shl{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1466 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1467 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1468 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1469 | "shl{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1470 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1471 | |
| 1472 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1473 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1474 | "shl{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1475 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1476 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1477 | "shl{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1478 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1479 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1480 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1481 | "shl{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1482 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1483 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1484 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1485 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1486 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1487 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1488 | [(set GR8:$dst, (srl GR8:$src1, CL))]>; |
| 1489 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1490 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1491 | [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize; |
| 1492 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1493 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1494 | [(set GR32:$dst, (srl GR32:$src1, CL))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1495 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1496 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1497 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1498 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1499 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1500 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1501 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1502 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1503 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1504 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1505 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1506 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1507 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1508 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1509 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1510 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1511 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1512 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1513 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1514 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1515 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1516 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 1517 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1518 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1519 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1520 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1521 | "shr{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1522 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1523 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1524 | "shr{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1525 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1526 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1527 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1528 | "shr{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1529 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1530 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1531 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1532 | "shr{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1533 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1534 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1535 | "shr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1536 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1537 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1538 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1539 | "shr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1540 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1541 | |
| 1542 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1543 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1544 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1545 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1546 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1547 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1548 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1549 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1550 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1551 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1552 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1553 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1554 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1555 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1556 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1557 | [(set GR8:$dst, (sra GR8:$src1, CL))]>; |
| 1558 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1559 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1560 | [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize; |
| 1561 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1562 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1563 | [(set GR32:$dst, (sra GR32:$src1, CL))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1564 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1565 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1566 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1567 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1568 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1569 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1570 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1571 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1572 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1573 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1574 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1575 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1576 | |
| 1577 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1578 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1579 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1580 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1581 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1582 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1583 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1584 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1585 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1586 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 1587 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1588 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1589 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1590 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1591 | "sar{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1592 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1593 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1594 | "sar{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1595 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1596 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1597 | "sar{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1598 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1599 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1600 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1601 | "sar{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1602 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1603 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1604 | "sar{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1605 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1606 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1607 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1608 | "sar{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1609 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1610 | |
| 1611 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1612 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1613 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1614 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1615 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1616 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1617 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1618 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1619 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1620 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1621 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1622 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1623 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1624 | // Rotate instructions |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1625 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1626 | def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1627 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1628 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1629 | def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1630 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1631 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1632 | def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1633 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1634 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1635 | def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1636 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1637 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1638 | def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1639 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1640 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1641 | def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1642 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1643 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1644 | def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1645 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1646 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1647 | def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1648 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1649 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1650 | def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1651 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1652 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1653 | def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1654 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1655 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1656 | def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1657 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1658 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1659 | def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1660 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1661 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1662 | def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1663 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1664 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1665 | def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1666 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1667 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1668 | def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1669 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1670 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1671 | def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1672 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1673 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1674 | def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1675 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1676 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1677 | def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1678 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Daniel Dunbar | ccfa1db | 2010-02-12 01:22:03 +0000 | [diff] [blame] | 1679 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1680 | let Constraints = "" in { |
Daniel Dunbar | ccfa1db | 2010-02-12 01:22:03 +0000 | [diff] [blame] | 1681 | def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), |
| 1682 | "rcl{b}\t{1, $dst|$dst, 1}", []>; |
| 1683 | def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), |
| 1684 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 1685 | def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), |
| 1686 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 1687 | def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt), |
| 1688 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 1689 | def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), |
| 1690 | "rcl{l}\t{1, $dst|$dst, 1}", []>; |
| 1691 | def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt), |
| 1692 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 1693 | def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), |
| 1694 | "rcr{b}\t{1, $dst|$dst, 1}", []>; |
| 1695 | def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt), |
| 1696 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 1697 | def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), |
| 1698 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize; |
| 1699 | def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt), |
| 1700 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 1701 | def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), |
| 1702 | "rcr{l}\t{1, $dst|$dst, 1}", []>; |
| 1703 | def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt), |
Sean Callanan | a2dc282 | 2009-09-18 19:35:23 +0000 | [diff] [blame] | 1704 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 1705 | |
Daniel Dunbar | ccfa1db | 2010-02-12 01:22:03 +0000 | [diff] [blame] | 1706 | let Uses = [CL] in { |
| 1707 | def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), |
| 1708 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 1709 | def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), |
| 1710 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 1711 | def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), |
| 1712 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 1713 | def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), |
| 1714 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 1715 | def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), |
| 1716 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 1717 | def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), |
| 1718 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 1719 | } |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1720 | } // Constraints = "" |
Daniel Dunbar | ccfa1db | 2010-02-12 01:22:03 +0000 | [diff] [blame] | 1721 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1722 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1723 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1724 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1725 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1726 | [(set GR8:$dst, (rotl GR8:$src1, CL))]>; |
| 1727 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1728 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1729 | [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize; |
| 1730 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1731 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1732 | [(set GR32:$dst, (rotl GR32:$src1, CL))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1733 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1734 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1735 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1736 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1737 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1738 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1739 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1740 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, |
| 1741 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1742 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1743 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1744 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1745 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1746 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1747 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1748 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1749 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1750 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1751 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1752 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1753 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1754 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1755 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 1756 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1757 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1758 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1759 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1760 | "rol{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1761 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1762 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1763 | "rol{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1764 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1765 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1766 | "rol{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1767 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1768 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1769 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1770 | "rol{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1771 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1772 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1773 | "rol{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1774 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1775 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1776 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1777 | "rol{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1778 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1779 | |
| 1780 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1781 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1782 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1783 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1784 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1785 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1786 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1787 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1788 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1789 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1790 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1791 | } // Constraints = "" |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1792 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1793 | let Uses = [CL] in { |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1794 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1795 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1796 | [(set GR8:$dst, (rotr GR8:$src1, CL))]>; |
| 1797 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1798 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1799 | [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize; |
| 1800 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1801 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1802 | [(set GR32:$dst, (rotr GR32:$src1, CL))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1803 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1804 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1805 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1806 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1807 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1808 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1809 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1810 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, |
| 1811 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1812 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1813 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1814 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1815 | |
| 1816 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1817 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1818 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1819 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1820 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1821 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1822 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1823 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1824 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1825 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 1826 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1827 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1828 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1829 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1830 | "ror{b}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1831 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1832 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1833 | "ror{w}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1834 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1835 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1836 | "ror{l}\t{%cl, $dst|$dst, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1837 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1838 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1839 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1840 | "ror{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1841 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1842 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1843 | "ror{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1844 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1845 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1846 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1847 | "ror{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1848 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1849 | |
| 1850 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1851 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1852 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1853 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1854 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1855 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1856 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1857 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1858 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1859 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1860 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1861 | } // Constraints = "" |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1862 | |
| 1863 | |
| 1864 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1865 | let Uses = [CL] in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1866 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), |
| 1867 | (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1868 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1869 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1870 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), |
| 1871 | (ins GR32:$src1, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1872 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1873 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1874 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), |
| 1875 | (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1876 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1877 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1878 | TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1879 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), |
| 1880 | (ins GR16:$src1, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1881 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1882 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1883 | TB, OpSize; |
| 1884 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1885 | |
| 1886 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1887 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1888 | (outs GR32:$dst), |
| 1889 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1890 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1891 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1892 | (i8 imm:$src3)))]>, |
| 1893 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1894 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1895 | (outs GR32:$dst), |
| 1896 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1897 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1898 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1899 | (i8 imm:$src3)))]>, |
| 1900 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1901 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1902 | (outs GR16:$dst), |
| 1903 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1904 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1905 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1906 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1907 | TB, OpSize; |
| 1908 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1909 | (outs GR16:$dst), |
| 1910 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1911 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1912 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1913 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1914 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1915 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1916 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1917 | let Constraints = "" in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1918 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1919 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1920 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1921 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1922 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1923 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1924 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1925 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1926 | addr:$dst)]>, TB; |
| 1927 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1928 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1929 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1930 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1931 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1932 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1933 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1934 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1935 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1936 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1937 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1938 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1939 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1940 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1941 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1942 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1943 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1944 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1945 | addr:$dst)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1946 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Eli Friedman | aace4b1 | 2009-06-19 04:48:38 +0000 | [diff] [blame] | 1947 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1948 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1949 | addr:$dst)]>, TB, OpSize; |
| 1950 | } |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1951 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1952 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1953 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1954 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1955 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1956 | TB, OpSize; |
| 1957 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1958 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1959 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1960 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1961 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1962 | TB, OpSize; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 1963 | } // Constraints = "" |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1964 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1965 | |
| 1966 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1967 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1968 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1969 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1970 | // Register-Register Addition |
| 1971 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 1972 | (ins GR8 :$src1, GR8 :$src2), |
| 1973 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1974 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1975 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1976 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1977 | // Register-Register Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1978 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 1979 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1980 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1981 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1, |
| 1982 | GR16:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1983 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 1984 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1985 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 1986 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1, |
| 1987 | GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1988 | } // end isConvertibleToThreeAddress |
| 1989 | } // end isCommutable |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 1990 | |
Daniel Dunbar | f291be3 | 2010-03-09 22:50:46 +0000 | [diff] [blame] | 1991 | // These are alternate spellings for use by the disassembler, we mark them as |
| 1992 | // code gen only to ensure they aren't matched by the assembler. |
| 1993 | let isCodeGenOnly = 1 in { |
| 1994 | def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 1995 | "add{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 1996 | def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
| 1997 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
Evan Cheng | 18ac410 | 2010-04-05 22:21:09 +0000 | [diff] [blame] | 1998 | def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2), |
Daniel Dunbar | f291be3 | 2010-03-09 22:50:46 +0000 | [diff] [blame] | 1999 | "add{l}\t{$src2, $dst|$dst, $src2}", []>; |
| 2000 | } |
| 2001 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2002 | // Register-Memory Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2003 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 2004 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2005 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2006 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, |
| 2007 | (load addr:$src2)))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2008 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 2009 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2010 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2011 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1, |
| 2012 | (load addr:$src2)))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2013 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 2014 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2015 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2016 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1, |
| 2017 | (load addr:$src2)))]>; |
Sean Callanan | 37be590 | 2009-09-15 20:53:57 +0000 | [diff] [blame] | 2018 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2019 | // Register-Integer Addition |
| 2020 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2021 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2022 | [(set GR8:$dst, EFLAGS, |
| 2023 | (X86add_flag GR8:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2024 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2025 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2026 | // Register-Integer Addition |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2027 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 2028 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2029 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2030 | [(set GR16:$dst, EFLAGS, |
| 2031 | (X86add_flag GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2032 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 2033 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2034 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2035 | [(set GR32:$dst, EFLAGS, |
| 2036 | (X86add_flag GR32:$src1, imm:$src2))]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2037 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 2038 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2039 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2040 | [(set GR16:$dst, EFLAGS, |
| 2041 | (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2042 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 2043 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2044 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2045 | [(set GR32:$dst, EFLAGS, |
| 2046 | (X86add_flag GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 2047 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2048 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2049 | let Constraints = "" in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2050 | // Memory-Register Addition |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2051 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2052 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2053 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 2054 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2055 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2056 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2057 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 2058 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2059 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2060 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2061 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 2062 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2063 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2064 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2065 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2066 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2067 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2068 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2069 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 2070 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2071 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2072 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2073 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 2074 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2075 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2076 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2077 | [(store (add (load addr:$dst), i16immSExt8:$src2), |
| 2078 | addr:$dst), |
| 2079 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2080 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2081 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2082 | [(store (add (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2083 | addr:$dst), |
| 2084 | (implicit EFLAGS)]>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2085 | |
| 2086 | // addition to rAX |
| 2087 | def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2088 | "add{b}\t{$src, %al|%al, $src}", []>; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2089 | def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2090 | "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
Sean Callanan | b08ae6b | 2009-08-11 21:26:06 +0000 | [diff] [blame] | 2091 | def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src), |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2092 | "add{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2093 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2094 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2095 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2096 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2097 | def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2098 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2099 | [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2100 | def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst), |
| 2101 | (ins GR16:$src1, GR16:$src2), |
| 2102 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2103 | [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2104 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), |
| 2105 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2106 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2107 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2108 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2109 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2110 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2111 | def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2112 | "adc{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2113 | def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst), |
| 2114 | (ins GR16:$src1, GR16:$src2), |
| 2115 | "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2116 | def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst), |
| 2117 | (ins GR32:$src1, GR32:$src2), |
| 2118 | "adc{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2119 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2120 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2121 | def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst), |
| 2122 | (ins GR8:$src1, i8mem:$src2), |
| 2123 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2124 | [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2125 | def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst), |
| 2126 | (ins GR16:$src1, i16mem:$src2), |
| 2127 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2128 | [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2129 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2130 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), |
| 2131 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2132 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2133 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
| 2134 | def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2135 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2136 | [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2137 | def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst), |
| 2138 | (ins GR16:$src1, i16imm:$src2), |
| 2139 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2140 | [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2141 | def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst), |
| 2142 | (ins GR16:$src1, i16i8imm:$src2), |
| 2143 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2144 | [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>, |
| 2145 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2146 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), |
| 2147 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2148 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2149 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2150 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), |
| 2151 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2152 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2153 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2154 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2155 | let Constraints = "" in { |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2156 | def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2157 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2158 | [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>; |
| 2159 | def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2160 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2161 | [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>, |
| 2162 | OpSize; |
| 2163 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2164 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2165 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
| 2166 | def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2167 | "adc{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2168 | [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2169 | def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2170 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2171 | [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
| 2172 | OpSize; |
| 2173 | def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2174 | "adc{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2175 | [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
| 2176 | OpSize; |
| 2177 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2178 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2179 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
| 2180 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2181 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2182 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2183 | |
| 2184 | def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src), |
| 2185 | "adc{b}\t{$src, %al|%al, $src}", []>; |
| 2186 | def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src), |
| 2187 | "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2188 | def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src), |
| 2189 | "adc{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2190 | } // Constraints = "" |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2191 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2192 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2193 | // Register-Register Subtraction |
| 2194 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2195 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2196 | [(set GR8:$dst, EFLAGS, |
| 2197 | (X86sub_flag GR8:$src1, GR8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2198 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 2199 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2200 | [(set GR16:$dst, EFLAGS, |
| 2201 | (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2202 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 2203 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2204 | [(set GR32:$dst, EFLAGS, |
| 2205 | (X86sub_flag GR32:$src1, GR32:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2206 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2207 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2208 | def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2209 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2210 | def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst), |
| 2211 | (ins GR16:$src1, GR16:$src2), |
| 2212 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2213 | def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst), |
| 2214 | (ins GR32:$src1, GR32:$src2), |
| 2215 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2216 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2217 | |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2218 | // Register-Memory Subtraction |
| 2219 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), |
| 2220 | (ins GR8 :$src1, i8mem :$src2), |
| 2221 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2222 | [(set GR8:$dst, EFLAGS, |
| 2223 | (X86sub_flag GR8:$src1, (load addr:$src2)))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2224 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), |
| 2225 | (ins GR16:$src1, i16mem:$src2), |
| 2226 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2227 | [(set GR16:$dst, EFLAGS, |
| 2228 | (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2229 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), |
| 2230 | (ins GR32:$src1, i32mem:$src2), |
| 2231 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2232 | [(set GR32:$dst, EFLAGS, |
| 2233 | (X86sub_flag GR32:$src1, (load addr:$src2)))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2234 | |
| 2235 | // Register-Integer Subtraction |
| 2236 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), |
| 2237 | (ins GR8:$src1, i8imm:$src2), |
| 2238 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2239 | [(set GR8:$dst, EFLAGS, |
| 2240 | (X86sub_flag GR8:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2241 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), |
| 2242 | (ins GR16:$src1, i16imm:$src2), |
| 2243 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2244 | [(set GR16:$dst, EFLAGS, |
| 2245 | (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2246 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), |
| 2247 | (ins GR32:$src1, i32imm:$src2), |
| 2248 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2249 | [(set GR32:$dst, EFLAGS, |
| 2250 | (X86sub_flag GR32:$src1, imm:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2251 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), |
| 2252 | (ins GR16:$src1, i16i8imm:$src2), |
| 2253 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2254 | [(set GR16:$dst, EFLAGS, |
| 2255 | (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2256 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), |
| 2257 | (ins GR32:$src1, i32i8imm:$src2), |
| 2258 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2259 | [(set GR32:$dst, EFLAGS, |
| 2260 | (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2261 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2262 | let Constraints = "" in { |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2263 | // Memory-Register Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2264 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2265 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2266 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst), |
| 2267 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2268 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2269 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2270 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst), |
| 2271 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2272 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2273 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2274 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst), |
| 2275 | (implicit EFLAGS)]>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2276 | |
| 2277 | // Memory-Integer Subtraction |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2278 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2279 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2280 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2281 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2282 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2283 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2284 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst), |
| 2285 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2286 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2287 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2288 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst), |
| 2289 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2290 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2291 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2292 | [(store (sub (load addr:$dst), i16immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2293 | addr:$dst), |
| 2294 | (implicit EFLAGS)]>, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2295 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2296 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2297 | [(store (sub (load addr:$dst), i32immSExt8:$src2), |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2298 | addr:$dst), |
| 2299 | (implicit EFLAGS)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2300 | |
| 2301 | def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src), |
| 2302 | "sub{b}\t{$src, %al|%al, $src}", []>; |
| 2303 | def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src), |
| 2304 | "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2305 | def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src), |
| 2306 | "sub{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2307 | } // Constraints = "" |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2308 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2309 | let Uses = [EFLAGS] in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2310 | def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst), |
| 2311 | (ins GR8:$src1, GR8:$src2), |
| 2312 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2313 | [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2314 | def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst), |
| 2315 | (ins GR16:$src1, GR16:$src2), |
| 2316 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2317 | [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2318 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), |
| 2319 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2320 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2321 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2322 | |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2323 | let Constraints = "" in { |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2324 | def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), |
| 2325 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2326 | [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2327 | def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 2328 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2329 | [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2330 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2331 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2332 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2333 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Chris Lattner | 8f60e4d | 2010-02-05 22:56:11 +0000 | [diff] [blame] | 2334 | def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
| 2335 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2336 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2337 | def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2), |
| 2338 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2339 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2340 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2341 | def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
| 2342 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2343 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2344 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2345 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2346 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2347 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2348 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2349 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2350 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Sean Callanan | d00025a | 2009-09-11 19:01:56 +0000 | [diff] [blame] | 2351 | |
| 2352 | def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src), |
| 2353 | "sbb{b}\t{$src, %al|%al, $src}", []>; |
| 2354 | def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src), |
| 2355 | "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2356 | def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src), |
| 2357 | "sbb{l}\t{$src, %eax|%eax, $src}", []>; |
Eric Christopher | a938cfb | 2010-06-19 00:37:40 +0000 | [diff] [blame] | 2358 | } // Constraints = "" |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2359 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2360 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2361 | def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), |
| 2362 | "sbb{b}\t{$src2, $dst|$dst, $src2}", []>; |
| 2363 | def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst), |
| 2364 | (ins GR16:$src1, GR16:$src2), |
| 2365 | "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; |
| 2366 | def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst), |
| 2367 | (ins GR32:$src1, GR32:$src2), |
| 2368 | "sbb{l}\t{$src2, $dst|$dst, $src2}", []>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 2369 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2370 | |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2371 | def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2), |
| 2372 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2373 | [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2374 | def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst), |
| 2375 | (ins GR16:$src1, i16mem:$src2), |
| 2376 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2377 | [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>, |
Dale Johannesen | 94c9cd1 | 2009-05-18 21:41:59 +0000 | [diff] [blame] | 2378 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2379 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), |
| 2380 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2381 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2382 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2383 | def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 2384 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2385 | [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2386 | def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst), |
| 2387 | (ins GR16:$src1, i16imm:$src2), |
| 2388 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2389 | [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2390 | def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst), |
| 2391 | (ins GR16:$src1, i16i8imm:$src2), |
| 2392 | "sbb{w}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2393 | [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>, |
| 2394 | OpSize; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2395 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), |
| 2396 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2397 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2398 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Dale Johannesen | ca11dae | 2009-05-18 17:44:15 +0000 | [diff] [blame] | 2399 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), |
| 2400 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2401 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Dale Johannesen | 874ae25 | 2009-06-02 03:12:52 +0000 | [diff] [blame] | 2402 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2403 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2404 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2405 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2406 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2407 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2408 | // Register-Register Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2409 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2410 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2411 | [(set GR16:$dst, EFLAGS, |
| 2412 | (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2413 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2414 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2415 | [(set GR32:$dst, EFLAGS, |
| 2416 | (X86smul_flag GR32:$src1, GR32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2417 | } |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2418 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2419 | // Register-Memory Signed Integer Multiply |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 2420 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 2421 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2422 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2423 | [(set GR16:$dst, EFLAGS, |
| 2424 | (X86smul_flag GR16:$src1, (load addr:$src2)))]>, |
| 2425 | TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2426 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), |
| 2427 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2428 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2429 | [(set GR32:$dst, EFLAGS, |
| 2430 | (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2431 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2432 | } // end Two Address instructions |
| 2433 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2434 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2435 | let Defs = [EFLAGS] in { |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2436 | // Register-Integer Signed Integer Multiply |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2437 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2438 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2439 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2440 | [(set GR16:$dst, EFLAGS, |
| 2441 | (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2442 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2443 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2444 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2445 | [(set GR32:$dst, EFLAGS, |
| 2446 | (X86smul_flag GR32:$src1, imm:$src2))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2447 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2448 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2449 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2450 | [(set GR16:$dst, EFLAGS, |
| 2451 | (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>, |
| 2452 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2453 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2454 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2455 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2456 | [(set GR32:$dst, EFLAGS, |
| 2457 | (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2458 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2459 | // Memory-Integer Signed Integer Multiply |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2460 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2461 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2462 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2463 | [(set GR16:$dst, EFLAGS, |
| 2464 | (X86smul_flag (load addr:$src1), imm:$src2))]>, |
| 2465 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2466 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2467 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2468 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2469 | [(set GR32:$dst, EFLAGS, |
| 2470 | (X86smul_flag (load addr:$src1), imm:$src2))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2471 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2472 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2473 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2474 | [(set GR16:$dst, EFLAGS, |
| 2475 | (X86smul_flag (load addr:$src1), |
| 2476 | i16immSExt8:$src2))]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2477 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2478 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2479 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Chris Lattner | ec85680 | 2010-03-27 00:45:04 +0000 | [diff] [blame] | 2480 | [(set GR32:$dst, EFLAGS, |
| 2481 | (X86smul_flag (load addr:$src1), |
| 2482 | i32immSExt8:$src2))]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2483 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2484 | |
| 2485 | //===----------------------------------------------------------------------===// |
| 2486 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2487 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2488 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2489 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2490 | def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2491 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2492 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>; |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2493 | def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2494 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2495 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2), |
| 2496 | 0))]>, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2497 | OpSize; |
Daniel Dunbar | b93c72c | 2010-03-08 21:10:36 +0000 | [diff] [blame] | 2498 | def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2499 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2500 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2), |
| 2501 | 0))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2502 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2503 | |
Sean Callanan | 4a93b71 | 2009-09-01 18:14:18 +0000 | [diff] [blame] | 2504 | def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src), |
| 2505 | "test{b}\t{$src, %al|%al, $src}", []>; |
| 2506 | def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src), |
| 2507 | "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2508 | def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src), |
| 2509 | "test{l}\t{$src, %eax|%eax, $src}", []>; |
| 2510 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2511 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2512 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2513 | [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)), |
| 2514 | 0))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2515 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2516 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2517 | [(set EFLAGS, (X86cmp (and GR16:$src1, |
| 2518 | (loadi16 addr:$src2)), 0))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2519 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2520 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2521 | [(set EFLAGS, (X86cmp (and GR32:$src1, |
| 2522 | (loadi32 addr:$src2)), 0))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2523 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2524 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2525 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2526 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2527 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2528 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2529 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2530 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2531 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>, |
| 2532 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2533 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2534 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2535 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2536 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2537 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2538 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2539 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2540 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2541 | [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2), |
| 2542 | 0))]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2543 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2544 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2545 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2546 | [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2), |
| 2547 | 0))]>, OpSize; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2548 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2549 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2550 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2551 | [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2), |
| 2552 | 0))]>; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2553 | } // Defs = [EFLAGS] |
| 2554 | |
| 2555 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2556 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2557 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2558 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2559 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2560 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2561 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2562 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2563 | let Defs = [EFLAGS] in { |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 2564 | def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src), |
| 2565 | "cmp{b}\t{$src, %al|%al, $src}", []>; |
| 2566 | def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src), |
| 2567 | "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2568 | def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src), |
| 2569 | "cmp{l}\t{$src, %eax|%eax, $src}", []>; |
| 2570 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2571 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2572 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2573 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2574 | [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2575 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2576 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2577 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2578 | [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2579 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2580 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2581 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2582 | [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2583 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2584 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2585 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2586 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2587 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2588 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2589 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2590 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>, |
| 2591 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2592 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2593 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2594 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2595 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2596 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2597 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2598 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2599 | [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2600 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2601 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2602 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2603 | [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>, |
| 2604 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2605 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2606 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2607 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2608 | [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>; |
Daniel Dunbar | 1e8ee89 | 2010-03-09 22:50:40 +0000 | [diff] [blame] | 2609 | |
| 2610 | // These are alternate spellings for use by the disassembler, we mark them as |
| 2611 | // code gen only to ensure they aren't matched by the assembler. |
| 2612 | let isCodeGenOnly = 1 in { |
| 2613 | def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2), |
| 2614 | "cmp{b}\t{$src2, $src1|$src1, $src2}", []>; |
| 2615 | def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2616 | "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize; |
| 2617 | def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2618 | "cmp{l}\t{$src2, $src1|$src1, $src2}", []>; |
| 2619 | } |
| 2620 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2621 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2622 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2623 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2624 | [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2625 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2626 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2627 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2628 | [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2629 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2630 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2631 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2632 | [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2633 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2634 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2635 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2636 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2637 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2638 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2639 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2640 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>, |
| 2641 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2642 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2643 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2644 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2645 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2646 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2647 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2648 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2649 | [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>, |
| 2650 | OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2651 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2652 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2653 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2654 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), |
| 2655 | i16immSExt8:$src2))]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2656 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2657 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2658 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2659 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), |
| 2660 | i32immSExt8:$src2))]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2661 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2662 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2663 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2664 | [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2665 | } // Defs = [EFLAGS] |
| 2666 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2667 | // Bit tests. |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2668 | // TODO: BTC, BTR, and BTS |
| 2669 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2670 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2671 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2672 | [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 2673 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2674 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2675 | [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2676 | |
| 2677 | // Unlike with the register+register form, the memory+register form of the |
| 2678 | // bt instruction does not ignore the high bits of the index. From ISel's |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2679 | // perspective, this is pretty bizarre. Make these instructions disassembly |
| 2680 | // only for now. |
| 2681 | |
| 2682 | def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2683 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2684 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2685 | // (implicit EFLAGS)] |
| 2686 | [] |
| 2687 | >, OpSize, TB, Requires<[FastBTMem]>; |
| 2688 | def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2689 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 2690 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2691 | // (implicit EFLAGS)] |
| 2692 | [] |
| 2693 | >, TB, Requires<[FastBTMem]>; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2694 | |
| 2695 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2696 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2697 | [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, |
| 2698 | OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2699 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2700 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2701 | [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2702 | // Note that these instructions don't need FastBTMem because that |
| 2703 | // only applies when the other operand is in a register. When it's |
| 2704 | // an immediate, bt is still fast. |
| 2705 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2706 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2707 | [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) |
| 2708 | ]>, OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 2709 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2710 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 2711 | [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) |
| 2712 | ]>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2713 | |
| 2714 | def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2715 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2716 | def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2717 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2718 | def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2719 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2720 | def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2721 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2722 | def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2723 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2724 | def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2725 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2726 | def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2727 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2728 | def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2729 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2730 | |
| 2731 | def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2732 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2733 | def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2734 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2735 | def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2736 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2737 | def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2738 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2739 | def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2740 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2741 | def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2742 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2743 | def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2744 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2745 | def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2746 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2747 | |
| 2748 | def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
| 2749 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2750 | def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
| 2751 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2752 | def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
| 2753 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2754 | def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
| 2755 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2756 | def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 2757 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2758 | def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 2759 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
| 2760 | def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 2761 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; |
| 2762 | def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 2763 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 2764 | } // Defs = [EFLAGS] |
| 2765 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2766 | // Sign/Zero extenders |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2767 | // Use movsbl intead of movsbw; we don't care about the high 16 bits |
| 2768 | // of the register here. This has a smaller encoding and avoids a |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2769 | // partial-register update. Actual movsbw included for the disassembler. |
| 2770 | def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), |
| 2771 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2772 | def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), |
| 2773 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2774 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 2775 | "", [(set GR16:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2776 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 2777 | "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2778 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2779 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2780 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2781 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2782 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2783 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2784 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2785 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2786 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2787 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2788 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2789 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2790 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2791 | // Use movzbl intead of movzbw; we don't care about the high 16 bits |
| 2792 | // of the register here. This has a smaller encoding and avoids a |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2793 | // partial-register update. Actual movzbw included for the disassembler. |
| 2794 | def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), |
| 2795 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2796 | def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), |
| 2797 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2798 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 2799 | "", [(set GR16:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2800 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Chris Lattner | 172862a | 2009-10-19 19:51:42 +0000 | [diff] [blame] | 2801 | "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2802 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2803 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2804 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2805 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2806 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2807 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2808 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2809 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2810 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2811 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2812 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2813 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2814 | |
Dan Gohman | f451cb8 | 2010-02-10 16:03:48 +0000 | [diff] [blame] | 2815 | // These are the same as the regular MOVZX32rr8 and MOVZX32rm8 |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 2816 | // except that they use GR32_NOREX for the output operand register class |
| 2817 | // instead of GR32. This allows them to operate on h registers on x86-64. |
| 2818 | def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, |
| 2819 | (outs GR32_NOREX:$dst), (ins GR8:$src), |
| 2820 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 2821 | []>, TB; |
Dan Gohman | 78e04d4 | 2009-04-30 03:11:48 +0000 | [diff] [blame] | 2822 | let mayLoad = 1 in |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 2823 | def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, |
| 2824 | (outs GR32_NOREX:$dst), (ins i8mem:$src), |
| 2825 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX", |
| 2826 | []>, TB; |
| 2827 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2828 | let neverHasSideEffects = 1 in { |
| 2829 | let Defs = [AX], Uses = [AL] in |
| 2830 | def CBW : I<0x98, RawFrm, (outs), (ins), |
| 2831 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) |
| 2832 | let Defs = [EAX], Uses = [AX] in |
| 2833 | def CWDE : I<0x98, RawFrm, (outs), (ins), |
| 2834 | "{cwtl|cwde}", []>; // EAX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2835 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2836 | let Defs = [AX,DX], Uses = [AX] in |
| 2837 | def CWD : I<0x99, RawFrm, (outs), (ins), |
| 2838 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) |
| 2839 | let Defs = [EAX,EDX], Uses = [EAX] in |
| 2840 | def CDQ : I<0x99, RawFrm, (outs), (ins), |
| 2841 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) |
| 2842 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2843 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2844 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 2845 | |
| 2846 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 2847 | // Atomic support |
| 2848 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2849 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 2850 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2851 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 2852 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 2853 | let Constraints = "$val = $dst" in { |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2854 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), |
| 2855 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 2856 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2857 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), |
| 2858 | (ins GR16:$val, i16mem:$ptr), |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2859 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 2860 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 2861 | OpSize; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2862 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), |
| 2863 | (ins GR32:$val, i32mem:$ptr), |
| 2864 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 2865 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
| 2866 | def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), |
| 2867 | (ins GR64:$val,i64mem:$ptr), |
| 2868 | "xchg{q}\t{$val, $ptr|$ptr, $val}", |
| 2869 | [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2870 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2871 | def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), |
| 2872 | "xchg{b}\t{$val, $src|$src, $val}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2873 | def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), |
| 2874 | "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize; |
| 2875 | def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), |
| 2876 | "xchg{l}\t{$val, $src|$src, $val}", []>; |
| 2877 | def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), |
| 2878 | "xchg{q}\t{$val, $src|$src, $val}", []>; |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2879 | } |
| 2880 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2881 | def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), |
| 2882 | "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize; |
| 2883 | def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), |
| 2884 | "xchg{l}\t{$src, %eax|%eax, $src}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2885 | def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), |
| 2886 | "xchg{q}\t{$src, %rax|%rax, $src}", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2887 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 2888 | |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2889 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2890 | def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 2891 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2892 | def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 2893 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2894 | def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 2895 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2896 | def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
| 2897 | "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2898 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2899 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2900 | def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 2901 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2902 | def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 2903 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2904 | def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 2905 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2906 | def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
| 2907 | "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2908 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2909 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2910 | |
| 2911 | def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
| 2912 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2913 | def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
| 2914 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2915 | def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
| 2916 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2917 | def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
| 2918 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2919 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2920 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2921 | def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
| 2922 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; |
| 2923 | def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
| 2924 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; |
| 2925 | def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
| 2926 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2927 | def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
| 2928 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 2929 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2930 | |
Evan Cheng | b093bd0 | 2010-01-08 01:29:19 +0000 | [diff] [blame] | 2931 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2932 | def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), |
| 2933 | "cmpxchg8b\t$dst", []>, TB; |
| 2934 | |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2935 | let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in |
| 2936 | def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), |
| 2937 | "cmpxchg16b\t$dst", []>, TB; |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 2938 | |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 2939 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2940 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 2941 | // Lock instruction prefix |
| 2942 | def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; |
| 2943 | |
| 2944 | // Repeat string operation instruction prefixes |
| 2945 | // These uses the DF flag in the EFLAGS register to inc or dec ECX |
| 2946 | let Defs = [ECX], Uses = [ECX,EFLAGS] in { |
| 2947 | // Repeat (used with INS, OUTS, MOVS, LODS and STOS) |
| 2948 | def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; |
| 2949 | // Repeat while not equal (used with CMPS and SCAS) |
| 2950 | def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; |
| 2951 | } |
| 2952 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 2953 | |
Sean Callanan | 9a86f10 | 2009-09-16 22:59:28 +0000 | [diff] [blame] | 2954 | // String manipulation instructions |
| 2955 | |
| 2956 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; |
| 2957 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2958 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 2959 | def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2960 | |
| 2961 | def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>; |
| 2962 | def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize; |
| 2963 | def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>; |
| 2964 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2965 | |
| 2966 | // Flag instructions |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2967 | def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; |
| 2968 | def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; |
| 2969 | def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; |
| 2970 | def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; |
| 2971 | def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; |
| 2972 | def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; |
| 2973 | def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; |
| 2974 | |
| 2975 | def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; |
| 2976 | |
| 2977 | // Table lookup instructions |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 2978 | def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>; |
| 2979 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2980 | |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 2981 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 2982 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2983 | // Subsystems. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2984 | //===----------------------------------------------------------------------===// |
| 2985 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 2986 | // Floating Point Stack Support |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 2987 | include "X86InstrFPStack.td" |
| 2988 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 2989 | // X86-64 Support |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 2990 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 2991 | |
Chris Lattner | 35649fc | 2010-10-05 06:33:16 +0000 | [diff] [blame^] | 2992 | include "X86InstrCMovSetCC.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 2993 | include "X86InstrControl.td" |
| 2994 | |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 2995 | // SIMD support (SSE, MMX and AVX) |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 2996 | include "X86InstrFragmentsSIMD.td" |
| 2997 | |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 2998 | // FMA - Fused Multiply-Add support (requires FMA) |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 2999 | include "X86InstrFMA.td" |
| 3000 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 3001 | // SSE, MMX and 3DNow! vector support. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3002 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 3003 | include "X86InstrMMX.td" |
Chris Lattner | 7330d97 | 2010-10-02 23:06:23 +0000 | [diff] [blame] | 3004 | include "X86Instr3DNow.td" |
| 3005 | |
Chris Lattner | d071b83 | 2010-10-05 06:06:53 +0000 | [diff] [blame] | 3006 | include "X86InstrVMX.td" |
| 3007 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 3008 | // System instructions. |
| 3009 | include "X86InstrSystem.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 3010 | |
| 3011 | // Compiler Pseudo Instructions and Pat Patterns |
| 3012 | include "X86InstrCompiler.td" |
| 3013 | |