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Chris Lattner97f06932009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner95b2c7d2006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000016#include "ARM.h"
Jim Grosbachbaf120f2010-12-01 03:45:07 +000017#include "ARMAsmPrinter.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000018#include "ARMAddressingModes.h"
19#include "ARMBuildAttrs.h"
20#include "ARMBaseRegisterInfo.h"
21#include "ARMConstantPoolValue.h"
Chris Lattner97f06932009-10-19 20:20:46 +000022#include "ARMMachineFunctionInfo.h"
Evan Cheng5de5d4b2011-01-17 08:03:18 +000023#include "ARMMCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000024#include "ARMTargetMachine.h"
Jason W Kim17b443d2010-10-11 23:01:44 +000025#include "ARMTargetObjectFile.h"
Evan Chengb72d2a92011-01-11 21:46:47 +000026#include "InstPrinter/ARMInstPrinter.h"
Dale Johannesen3f282aa2010-04-26 20:07:31 +000027#include "llvm/Analysis/DebugInfo.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000028#include "llvm/Constants.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000029#include "llvm/Module.h"
Benjamin Kramere55b15f2009-12-28 12:27:56 +000030#include "llvm/Type.h"
Dan Gohmancf20ac42009-08-13 01:36:44 +000031#include "llvm/Assembly/Writer.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000032#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000033#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chenga8e29892007-01-19 07:51:42 +000034#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000035#include "llvm/MC/MCAsmInfo.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000036#include "llvm/MC/MCAssembler.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000037#include "llvm/MC/MCContext.h"
Bill Wendlingbecd83e2010-03-09 00:40:17 +000038#include "llvm/MC/MCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000039#include "llvm/MC/MCInst.h"
Chris Lattnerf9bdedd2009-08-10 18:15:01 +000040#include "llvm/MC/MCSectionMachO.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000041#include "llvm/MC/MCObjectStreamer.h"
Chris Lattner6c2f9e12009-08-19 05:49:37 +000042#include "llvm/MC/MCStreamer.h"
Chris Lattner325d3dc2009-09-13 17:14:04 +000043#include "llvm/MC/MCSymbol.h"
Chris Lattnerd62f1b42010-03-12 21:19:23 +000044#include "llvm/Target/Mangler.h"
Rafael Espindolab01c4bb2006-07-27 11:38:51 +000045#include "llvm/Target/TargetData.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000046#include "llvm/Target/TargetMachine.h"
Evan Cheng5be54b02007-01-19 19:25:36 +000047#include "llvm/Target/TargetOptions.h"
Daniel Dunbar51b198a2009-07-15 20:24:03 +000048#include "llvm/Target/TargetRegistry.h"
Evan Chengc324ecb2009-07-24 18:19:46 +000049#include "llvm/ADT/SmallPtrSet.h"
Jim Grosbachc40d9f92009-09-01 18:49:12 +000050#include "llvm/ADT/SmallString.h"
Bob Wilson54c78ef2009-11-06 23:33:28 +000051#include "llvm/ADT/StringExtras.h"
Chris Lattner97f06932009-10-19 20:20:46 +000052#include "llvm/Support/CommandLine.h"
Devang Patel59135f42010-08-04 22:39:39 +000053#include "llvm/Support/Debug.h"
Torok Edwin30464702009-07-08 20:55:50 +000054#include "llvm/Support/ErrorHandling.h"
Chris Lattnerb23569a2010-04-04 08:18:47 +000055#include "llvm/Support/raw_ostream.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000056#include <cctype>
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000057using namespace llvm;
58
Chris Lattner95b2c7d2006-12-19 22:59:26 +000059namespace {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000060
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
66 public:
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void Finish() = 0;
Rafael Espindola4921e232010-10-25 18:38:32 +000070 virtual ~AttributeEmitter() {}
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000071 };
72
73 class AsmAttributeEmitter : public AttributeEmitter {
74 MCStreamer &Streamer;
75
76 public:
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
79
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
83 }
84
85 void Finish() { }
86 };
87
88 class ObjectAttributeEmitter : public AttributeEmitter {
89 MCObjectStreamer &Streamer;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000090 StringRef CurrentVendor;
91 SmallString<64> Contents;
92
93 public:
94 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
95 Streamer(Streamer_), CurrentVendor("") { }
96
97 void MaybeSwitchVendor(StringRef Vendor) {
98 assert(!Vendor.empty() && "Vendor cannot be empty.");
99
100 if (CurrentVendor.empty())
101 CurrentVendor = Vendor;
102 else if (CurrentVendor == Vendor)
103 return;
104 else
105 Finish();
106
107 CurrentVendor = Vendor;
108
Rafael Espindola33363842010-10-25 22:26:55 +0000109 assert(Contents.size() == 0);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000110 }
111
112 void EmitAttribute(unsigned Attribute, unsigned Value) {
113 // FIXME: should be ULEB
114 Contents += Attribute;
115 Contents += Value;
116 }
117
118 void Finish() {
Rafael Espindola33363842010-10-25 22:26:55 +0000119 const size_t ContentsSize = Contents.size();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000120
Rafael Espindola33363842010-10-25 22:26:55 +0000121 // Vendor size + Vendor name + '\0'
122 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000123
Rafael Espindola33363842010-10-25 22:26:55 +0000124 // Tag + Tag Size
125 const size_t TagHeaderSize = 1 + 4;
126
127 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
128 Streamer.EmitBytes(CurrentVendor, 0);
129 Streamer.EmitIntValue(0, 1); // '\0'
130
131 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
132 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000133
134 Streamer.EmitBytes(Contents, 0);
Rafael Espindola33363842010-10-25 22:26:55 +0000135
136 Contents.clear();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000137 }
138 };
139
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000140} // end of anonymous namespace
141
Jim Grosbachbaf120f2010-12-01 03:45:07 +0000142MachineLocation ARMAsmPrinter::
143getDebugValueLocation(const MachineInstr *MI) const {
144 MachineLocation Location;
145 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
146 // Frame address. Currently handles register +- offset only.
147 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
148 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
149 else {
150 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
151 }
152 return Location;
153}
154
Chris Lattner953ebb72010-01-27 23:58:11 +0000155void ARMAsmPrinter::EmitFunctionEntryLabel() {
156 if (AFI->isThumbFunction()) {
Jim Grosbachce792992010-11-05 22:08:08 +0000157 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
158 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
Chris Lattner953ebb72010-01-27 23:58:11 +0000159 }
Jim Grosbachb0739b72010-09-02 01:02:06 +0000160
Chris Lattner953ebb72010-01-27 23:58:11 +0000161 OutStreamer.EmitLabel(CurrentFnSym);
162}
163
Jim Grosbach2317e402010-09-30 01:57:53 +0000164/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000165/// method to print assembly for each instruction.
166///
167bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Chenga8e29892007-01-19 07:51:42 +0000168 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng6d63a722008-09-18 07:27:23 +0000169 MCP = MF.getConstantPool();
Rafael Espindola4b442b52006-05-23 02:48:20 +0000170
Chris Lattnerd49fe1b2010-01-28 01:28:58 +0000171 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000172}
173
Evan Cheng055b0312009-06-29 07:51:04 +0000174void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner35c33bd2010-04-04 04:47:45 +0000175 raw_ostream &O, const char *Modifier) {
Evan Cheng055b0312009-06-29 07:51:04 +0000176 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000177 unsigned TF = MO.getTargetFlags();
178
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000179 switch (MO.getType()) {
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000180 default:
181 assert(0 && "<unknown operand type>");
Bob Wilson5bafff32009-06-22 23:27:02 +0000182 case MachineOperand::MO_Register: {
183 unsigned Reg = MO.getReg();
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000184 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach35636282010-10-06 21:22:32 +0000185 assert(!MO.getSubReg() && "Subregs should be eliminated!");
186 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000187 break;
Bob Wilson5bafff32009-06-22 23:27:02 +0000188 }
Evan Chenga8e29892007-01-19 07:51:42 +0000189 case MachineOperand::MO_Immediate: {
Evan Cheng5adb66a2009-09-28 09:14:39 +0000190 int64_t Imm = MO.getImm();
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000191 O << '#';
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000192 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000193 (TF == ARMII::MO_LO16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000194 O << ":lower16:";
195 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jason W Kim650b7d72011-01-12 23:21:49 +0000196 (TF == ARMII::MO_HI16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000197 O << ":upper16:";
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000198 O << Imm;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000199 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000200 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000201 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner1b2eb0e2010-03-13 21:04:28 +0000202 O << *MO.getMBB()->getSymbol();
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000203 return;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000204 case MachineOperand::MO_GlobalAddress: {
Dan Gohman46510a72010-04-15 01:51:59 +0000205 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000206 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
207 (TF & ARMII::MO_LO16))
208 O << ":lower16:";
209 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
210 (TF & ARMII::MO_HI16))
211 O << ":upper16:";
Chris Lattnerd62f1b42010-03-12 21:19:23 +0000212 O << *Mang->getSymbol(GV);
Anton Korobeynikov7751ad92008-11-22 16:15:34 +0000213
Chris Lattner0c08d092010-04-03 22:28:33 +0000214 printOffset(MO.getOffset(), O);
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000215 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000216 O << "(PLT)";
Evan Chenga8e29892007-01-19 07:51:42 +0000217 break;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000218 }
Evan Chenga8e29892007-01-19 07:51:42 +0000219 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner10b318b2010-01-17 21:43:43 +0000220 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000221 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000222 O << "(PLT)";
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000223 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000224 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000225 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000226 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000227 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000228 case MachineOperand::MO_JumpTableIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000229 O << *GetJTISymbol(MO.getIndex());
Evan Chenga8e29892007-01-19 07:51:42 +0000230 break;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000231 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000232}
233
Evan Cheng055b0312009-06-29 07:51:04 +0000234//===--------------------------------------------------------------------===//
235
Chris Lattner0890cf12010-01-25 19:51:38 +0000236MCSymbol *ARMAsmPrinter::
237GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
238 const MachineBasicBlock *MBB) const {
239 SmallString<60> Name;
240 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000241 << getFunctionNumber() << '_' << uid << '_' << uid2
Chris Lattner0890cf12010-01-25 19:51:38 +0000242 << "_set_" << MBB->getNumber();
Chris Lattner9b97a732010-03-30 18:10:53 +0000243 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner0890cf12010-01-25 19:51:38 +0000244}
245
246MCSymbol *ARMAsmPrinter::
247GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
248 SmallString<60> Name;
249 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner281e7762010-01-25 23:28:03 +0000250 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner9b97a732010-03-30 18:10:53 +0000251 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000252}
253
Jim Grosbach433a5782010-09-24 20:47:58 +0000254
255MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
256 SmallString<60> Name;
257 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
258 << getFunctionNumber();
259 return OutContext.GetOrCreateSymbol(Name.str());
260}
261
Evan Cheng055b0312009-06-29 07:51:04 +0000262bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000263 unsigned AsmVariant, const char *ExtraCode,
264 raw_ostream &O) {
Evan Chenga8e29892007-01-19 07:51:42 +0000265 // Does this asm operand have a single letter operand modifier?
266 if (ExtraCode && ExtraCode[0]) {
267 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikov8e9ece72009-08-08 23:10:41 +0000268
Evan Chenga8e29892007-01-19 07:51:42 +0000269 switch (ExtraCode[0]) {
270 default: return true; // Unknown modifier.
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000271 case 'a': // Print as a memory address.
272 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach2f24c4e2010-09-30 15:25:22 +0000273 O << "["
274 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
275 << "]";
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000276 return false;
277 }
278 // Fallthrough
279 case 'c': // Don't print "#" before an immediate operand.
Bob Wilson4f38b382009-08-21 21:58:55 +0000280 if (!MI->getOperand(OpNum).isImm())
281 return true;
Jim Grosbach2317e402010-09-30 01:57:53 +0000282 O << MI->getOperand(OpNum).getImm();
Bob Wilson8f343462009-04-06 21:46:51 +0000283 return false;
Evan Chenge21e3962007-04-04 00:13:29 +0000284 case 'P': // Print a VFP double precision register.
Evan Chengd831cda2009-12-08 23:06:22 +0000285 case 'q': // Print a NEON quad precision register.
Chris Lattner35c33bd2010-04-04 04:47:45 +0000286 printOperand(MI, OpNum, O);
Evan Cheng23a95702007-03-08 22:42:46 +0000287 return false;
Evan Chenga8e29892007-01-19 07:51:42 +0000288 case 'Q':
Bob Wilsond984eb62010-05-27 20:23:42 +0000289 case 'R':
Bob Wilsond984eb62010-05-27 20:23:42 +0000290 case 'H':
Bob Wilson9bb43e12010-12-17 23:06:42 +0000291 // These modifiers are not yet supported.
Bob Wilsond984eb62010-05-27 20:23:42 +0000292 return true;
Evan Cheng84f60b72010-05-27 22:08:38 +0000293 }
Evan Chenga8e29892007-01-19 07:51:42 +0000294 }
Jim Grosbache9952212009-09-04 01:38:51 +0000295
Chris Lattner35c33bd2010-04-04 04:47:45 +0000296 printOperand(MI, OpNum, O);
Evan Chenga8e29892007-01-19 07:51:42 +0000297 return false;
298}
299
Bob Wilson224c2442009-05-19 05:53:42 +0000300bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Cheng055b0312009-06-29 07:51:04 +0000301 unsigned OpNum, unsigned AsmVariant,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000302 const char *ExtraCode,
303 raw_ostream &O) {
Bob Wilson224c2442009-05-19 05:53:42 +0000304 if (ExtraCode && ExtraCode[0])
305 return true; // Unknown modifier.
Bob Wilson765cc0b2009-10-13 20:50:28 +0000306
307 const MachineOperand &MO = MI->getOperand(OpNum);
308 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach2317e402010-09-30 01:57:53 +0000309 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilson224c2442009-05-19 05:53:42 +0000310 return false;
311}
312
Bob Wilson812209a2009-09-30 22:06:26 +0000313void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson0fb34682009-09-30 00:23:42 +0000314 if (Subtarget->isTargetDarwin()) {
315 Reloc::Model RelocM = TM.getRelocationModel();
316 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
317 // Declare all the text sections up front (before the DWARF sections
318 // emitted by AsmPrinter::doInitialization) so the assembler will keep
319 // them together at the beginning of the object file. This helps
320 // avoid out-of-range branches that are due a fundamental limitation of
321 // the way symbol offsets are encoded with the current Darwin ARM
322 // relocations.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000323 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman0d805c32010-04-17 16:44:48 +0000324 static_cast<const TargetLoweringObjectFileMachO &>(
325 getObjFileLowering());
Bob Wilson29e06692009-09-30 22:25:37 +0000326 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
327 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
328 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
329 if (RelocM == Reloc::DynamicNoPIC) {
330 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000331 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
332 MCSectionMachO::S_SYMBOL_STUBS,
333 12, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000334 OutStreamer.SwitchSection(sect);
335 } else {
336 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000337 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
338 MCSectionMachO::S_SYMBOL_STUBS,
339 16, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000340 OutStreamer.SwitchSection(sect);
341 }
Bob Wilson63db5942010-07-30 19:55:47 +0000342 const MCSection *StaticInitSect =
343 OutContext.getMachOSection("__TEXT", "__StaticInit",
344 MCSectionMachO::S_REGULAR |
345 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
346 SectionKind::getText());
347 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson0fb34682009-09-30 00:23:42 +0000348 }
349 }
350
Jim Grosbache5165492009-11-09 00:11:35 +0000351 // Use unified assembler syntax.
Jason W Kimafd1cc22010-09-30 02:45:56 +0000352 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovd61eca52009-06-17 23:43:18 +0000353
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000354 // Emit ARM Build Attributes
355 if (Subtarget->isTargetELF()) {
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000356
Jason W Kimdef9ac42010-10-06 22:36:46 +0000357 emitAttributes();
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000358 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000359}
360
Anton Korobeynikov0f3cc652008-08-07 09:54:23 +0000361
Chris Lattner4a071d62009-10-19 17:59:19 +0000362void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng5be54b02007-01-19 19:25:36 +0000363 if (Subtarget->isTargetDarwin()) {
Chris Lattnerf61159b2009-08-03 22:18:15 +0000364 // All darwin targets use mach-o.
Dan Gohman0d805c32010-04-17 16:44:48 +0000365 const TargetLoweringObjectFileMachO &TLOFMacho =
366 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000367 MachineModuleInfoMachO &MMIMacho =
368 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbache9952212009-09-04 01:38:51 +0000369
Evan Chenga8e29892007-01-19 07:51:42 +0000370 // Output non-lazy-pointers for external and common global variables.
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000371 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlingcebae362010-03-10 22:34:10 +0000372
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000373 if (!Stubs.empty()) {
Chris Lattnerff4bc462009-08-10 01:39:42 +0000374 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000375 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattnerc076a972009-08-10 18:01:34 +0000376 EmitAlignment(2);
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000377 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000378 // L_foo$stub:
379 OutStreamer.EmitLabel(Stubs[i].first);
380 // .indirect_symbol _foo
Bill Wendling52a50e52010-03-11 01:18:13 +0000381 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
382 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000383
Bill Wendling52a50e52010-03-11 01:18:13 +0000384 if (MCSym.getInt())
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000385 // External to current translation unit.
386 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
387 else
388 // Internal to current translation unit.
Bill Wendling5e1b55d2010-03-31 18:47:10 +0000389 //
Jim Grosbach1b935a32010-09-22 16:45:13 +0000390 // When we place the LSDA into the TEXT section, the type info
391 // pointers need to be indirect and pc-rel. We accomplish this by
392 // using NLPs; however, sometimes the types are local to the file.
393 // We need to fill in the value for the NLP in those cases.
Bill Wendling52a50e52010-03-11 01:18:13 +0000394 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
395 OutContext),
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000396 4/*size*/, 0/*addrspace*/);
Evan Chengae94e592008-12-05 01:06:39 +0000397 }
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000398
399 Stubs.clear();
400 OutStreamer.AddBlankLine();
Evan Chenga8e29892007-01-19 07:51:42 +0000401 }
402
Chris Lattnere4d9ea82009-10-19 18:44:38 +0000403 Stubs = MMIMacho.GetHiddenGVStubList();
404 if (!Stubs.empty()) {
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000405 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerf3231de2009-08-10 18:02:16 +0000406 EmitAlignment(2);
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000407 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
408 // L_foo$stub:
409 OutStreamer.EmitLabel(Stubs[i].first);
410 // .long _foo
Bill Wendlingcebae362010-03-10 22:34:10 +0000411 OutStreamer.EmitValue(MCSymbolRefExpr::
412 Create(Stubs[i].second.getPointer(),
413 OutContext),
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000414 4/*size*/, 0/*addrspace*/);
415 }
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000416
417 Stubs.clear();
418 OutStreamer.AddBlankLine();
Evan Chengae94e592008-12-05 01:06:39 +0000419 }
420
Evan Chenga8e29892007-01-19 07:51:42 +0000421 // Funny Darwin hack: This flag tells the linker that no global symbols
422 // contain code that falls through to other global symbols (e.g. the obvious
423 // implementation of multiple entry points). If this doesn't occur, the
424 // linker can safely perform dead code stripping. Since LLVM never
425 // generates code that does this, it is always safe to set.
Chris Lattnera5ad93a2010-01-23 06:39:22 +0000426 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindolab01c4bb2006-07-27 11:38:51 +0000427 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000428}
Anton Korobeynikov0bd89712008-08-17 13:55:10 +0000429
Chris Lattner97f06932009-10-19 20:20:46 +0000430//===----------------------------------------------------------------------===//
Jason W Kimdef9ac42010-10-06 22:36:46 +0000431// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
432// FIXME:
433// The following seem like one-off assembler flags, but they actually need
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000434// to appear in the .ARM.attributes section in ELF.
Jason W Kimdef9ac42010-10-06 22:36:46 +0000435// Instead of subclassing the MCELFStreamer, we do the work here.
436
437void ARMAsmPrinter::emitAttributes() {
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000438
Jason W Kim17b443d2010-10-11 23:01:44 +0000439 emitARMAttributeSection();
440
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000441 AttributeEmitter *AttrEmitter;
442 if (OutStreamer.hasRawTextSupport())
443 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
444 else {
445 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
446 AttrEmitter = new ObjectAttributeEmitter(O);
447 }
448
449 AttrEmitter->MaybeSwitchVendor("aeabi");
450
Jason W Kimdef9ac42010-10-06 22:36:46 +0000451 std::string CPUString = Subtarget->getCPUString();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000452 if (OutStreamer.hasRawTextSupport()) {
453 if (CPUString != "generic")
454 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
455 } else {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000456 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
457 // FIXME: Why these defaults?
458 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
459 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
460 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000461 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000462
463 // FIXME: Emit FPU type
464 if (Subtarget->hasVFP2())
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000465 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000466
467 // Signal various FP modes.
468 if (!UnsafeFPMath) {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000469 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
470 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000471 }
472
473 if (NoInfsFPMath && NoNaNsFPMath)
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000474 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000475 else
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000476 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000477
478 // 8-bytes alignment stuff.
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000479 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
480 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000481
482 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
483 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000484 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
485 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000486 }
487 // FIXME: Should we signal R9 usage?
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000488
489 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
490
491 AttrEmitter->Finish();
492 delete AttrEmitter;
Jason W Kimdef9ac42010-10-06 22:36:46 +0000493}
494
Jason W Kim17b443d2010-10-11 23:01:44 +0000495void ARMAsmPrinter::emitARMAttributeSection() {
496 // <format-version>
497 // [ <section-length> "vendor-name"
498 // [ <file-tag> <size> <attribute>*
499 // | <section-tag> <size> <section-number>* 0 <attribute>*
500 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
501 // ]+
502 // ]*
503
504 if (OutStreamer.hasRawTextSupport())
505 return;
506
507 const ARMElfTargetObjectFile &TLOFELF =
508 static_cast<const ARMElfTargetObjectFile &>
509 (getObjFileLowering());
510
511 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim17b443d2010-10-11 23:01:44 +0000512
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000513 // Format version
514 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim17b443d2010-10-11 23:01:44 +0000515}
516
Jason W Kimdef9ac42010-10-06 22:36:46 +0000517//===----------------------------------------------------------------------===//
Chris Lattner97f06932009-10-19 20:20:46 +0000518
Jim Grosbach988ce092010-09-18 00:05:05 +0000519static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
520 unsigned LabelId, MCContext &Ctx) {
521
522 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
523 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
524 return Label;
525}
526
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000527static MCSymbolRefExpr::VariantKind
528getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
529 switch (Modifier) {
530 default: llvm_unreachable("Unknown modifier!");
531 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
532 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
533 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
534 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
535 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
536 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
537 }
538 return MCSymbolRefExpr::VK_None;
539}
540
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000541MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
542 bool isIndirect = Subtarget->isTargetDarwin() &&
543 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
544 if (!isIndirect)
545 return Mang->getSymbol(GV);
546
547 // FIXME: Remove this when Darwin transition to @GOT like syntax.
548 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
549 MachineModuleInfoMachO &MMIMachO =
550 MMI->getObjFileInfo<MachineModuleInfoMachO>();
551 MachineModuleInfoImpl::StubValueTy &StubSym =
552 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
553 MMIMachO.getGVStubEntry(MCSym);
554 if (StubSym.getPointer() == 0)
555 StubSym = MachineModuleInfoImpl::
556 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
557 return MCSym;
558}
559
Jim Grosbach5df08d82010-11-09 18:45:04 +0000560void ARMAsmPrinter::
561EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
562 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
563
564 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000565
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000566 MCSymbol *MCSym;
Jim Grosbach5df08d82010-11-09 18:45:04 +0000567 if (ACPV->isLSDA()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000568 SmallString<128> Str;
569 raw_svector_ostream OS(Str);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000570 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000571 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000572 } else if (ACPV->isBlockAddress()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000573 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000574 } else if (ACPV->isGlobalValue()) {
575 const GlobalValue *GV = ACPV->getGV();
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000576 MCSym = GetARMGVSymbol(GV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000577 } else {
578 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000579 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000580 }
581
582 // Create an MCSymbol for the reference.
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000583 const MCExpr *Expr =
584 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
585 OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000586
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000587 if (ACPV->getPCAdjustment()) {
588 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
589 getFunctionNumber(),
590 ACPV->getLabelId(),
591 OutContext);
592 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
593 PCRelExpr =
594 MCBinaryExpr::CreateAdd(PCRelExpr,
595 MCConstantExpr::Create(ACPV->getPCAdjustment(),
596 OutContext),
597 OutContext);
598 if (ACPV->mustAddCurrentAddress()) {
599 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
600 // label, so just emit a local label end reference that instead.
601 MCSymbol *DotSym = OutContext.CreateTempSymbol();
602 OutStreamer.EmitLabel(DotSym);
603 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
604 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000605 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000606 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000607 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000608 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000609}
610
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000611void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
612 unsigned Opcode = MI->getOpcode();
613 int OpNum = 1;
614 if (Opcode == ARM::BR_JTadd)
615 OpNum = 2;
616 else if (Opcode == ARM::BR_JTm)
617 OpNum = 3;
618
619 const MachineOperand &MO1 = MI->getOperand(OpNum);
620 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
621 unsigned JTI = MO1.getIndex();
622
623 // Emit a label for the jump table.
624 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
625 OutStreamer.EmitLabel(JTISymbol);
626
627 // Emit each entry of the table.
628 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
629 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
630 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
631
632 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
633 MachineBasicBlock *MBB = JTBBs[i];
634 // Construct an MCExpr for the entry. We want a value of the form:
635 // (BasicBlockAddr - TableBeginAddr)
636 //
637 // For example, a table with entries jumping to basic blocks BB0 and BB1
638 // would look like:
639 // LJTI_0_0:
640 // .word (LBB0 - LJTI_0_0)
641 // .word (LBB1 - LJTI_0_0)
642 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
643
644 if (TM.getRelocationModel() == Reloc::PIC_)
645 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
646 OutContext),
647 OutContext);
648 OutStreamer.EmitValue(Expr, 4);
649 }
650}
651
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000652void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
653 unsigned Opcode = MI->getOpcode();
654 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
655 const MachineOperand &MO1 = MI->getOperand(OpNum);
656 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
657 unsigned JTI = MO1.getIndex();
658
659 // Emit a label for the jump table.
660 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
661 OutStreamer.EmitLabel(JTISymbol);
662
663 // Emit each entry of the table.
664 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
665 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
666 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000667 unsigned OffsetWidth = 4;
Jim Grosbachd092a872010-11-29 21:28:32 +0000668 if (MI->getOpcode() == ARM::t2TBB_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000669 OffsetWidth = 1;
Jim Grosbachd092a872010-11-29 21:28:32 +0000670 else if (MI->getOpcode() == ARM::t2TBH_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000671 OffsetWidth = 2;
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000672
673 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
674 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000675 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
676 OutContext);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000677 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000678 if (OffsetWidth == 4) {
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000679 MCInst BrInst;
680 BrInst.setOpcode(ARM::t2B);
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000681 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000682 OutStreamer.EmitInstruction(BrInst);
683 continue;
684 }
685 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000686 // MCExpr for the entry. We want a value of the form:
687 // (BasicBlockAddr - TableBeginAddr) / 2
688 //
689 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
690 // would look like:
691 // LJTI_0_0:
692 // .byte (LBB0 - LJTI_0_0) / 2
693 // .byte (LBB1 - LJTI_0_0) / 2
694 const MCExpr *Expr =
695 MCBinaryExpr::CreateSub(MBBSymbolExpr,
696 MCSymbolRefExpr::Create(JTISymbol, OutContext),
697 OutContext);
698 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
699 OutContext);
700 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000701 }
702}
703
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000704void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
705 raw_ostream &OS) {
706 unsigned NOps = MI->getNumOperands();
707 assert(NOps==4);
708 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
709 // cast away const; DIetc do not take const operands for some reason.
710 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
711 OS << V.getName();
712 OS << " <- ";
713 // Frame address. Currently handles register +- offset only.
714 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
715 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
716 OS << ']';
717 OS << "+";
718 printOperand(MI, NOps-2, OS);
719}
720
Jim Grosbach40edf732010-12-14 21:10:47 +0000721static void populateADROperands(MCInst &Inst, unsigned Dest,
722 const MCSymbol *Label,
723 unsigned pred, unsigned ccreg,
724 MCContext &Ctx) {
725 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
726 Inst.addOperand(MCOperand::CreateReg(Dest));
727 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
728 // Add predicate operands.
729 Inst.addOperand(MCOperand::CreateImm(pred));
730 Inst.addOperand(MCOperand::CreateReg(ccreg));
731}
732
Anton Korobeynikov4d728602011-01-01 20:38:38 +0000733void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
734 unsigned Opcode) {
735 MCInst TmpInst;
736
737 // Emit the instruction as usual, just patch the opcode.
738 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
739 TmpInst.setOpcode(Opcode);
740 OutStreamer.EmitInstruction(TmpInst);
741}
742
Jim Grosbachb454cda2010-09-29 15:23:40 +0000743void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000744 unsigned Opc = MI->getOpcode();
745 switch (Opc) {
Chris Lattner4d152222009-10-19 22:23:04 +0000746 default: break;
Jim Grosbach9702e602010-12-09 01:22:19 +0000747 case ARM::t2ADDrSPi:
748 case ARM::t2ADDrSPi12:
749 case ARM::t2SUBrSPi:
750 case ARM::t2SUBrSPi12:
Jim Grosbach766a63d2010-12-09 01:23:51 +0000751 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
752 "Unexpected source register!");
Jim Grosbach9702e602010-12-09 01:22:19 +0000753 break;
754
Chris Lattner112f2392010-11-14 20:31:06 +0000755 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000756 case ARM::DBG_VALUE: {
757 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
758 SmallString<128> TmpStr;
759 raw_svector_ostream OS(TmpStr);
760 PrintDebugValueComment(MI, OS);
761 OutStreamer.EmitRawText(StringRef(OS.str()));
762 }
763 return;
764 }
Jim Grosbach3efad8f2010-12-16 19:11:16 +0000765 case ARM::tBfar: {
766 MCInst TmpInst;
767 TmpInst.setOpcode(ARM::tBL);
768 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
769 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
770 OutStreamer.EmitInstruction(TmpInst);
771 return;
772 }
Jim Grosbach40edf732010-12-14 21:10:47 +0000773 case ARM::LEApcrel:
Jim Grosbachd40963c2010-12-14 22:28:03 +0000774 case ARM::tLEApcrel:
Jim Grosbach40edf732010-12-14 21:10:47 +0000775 case ARM::t2LEApcrel: {
Jim Grosbachdff84b02010-12-02 00:28:45 +0000776 // FIXME: Need to also handle globals and externals
Jim Grosbachdff84b02010-12-02 00:28:45 +0000777 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000778 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
779 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
780 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000781 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
782 GetCPISymbol(MI->getOperand(1).getIndex()),
783 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
784 OutContext);
Jim Grosbachdff84b02010-12-02 00:28:45 +0000785 OutStreamer.EmitInstruction(TmpInst);
786 return;
787 }
Jim Grosbachd40963c2010-12-14 22:28:03 +0000788 case ARM::LEApcrelJT:
789 case ARM::tLEApcrelJT:
790 case ARM::t2LEApcrelJT: {
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000791 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000792 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
793 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
794 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000795 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
796 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
797 MI->getOperand(2).getImm()),
798 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
799 OutContext);
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000800 OutStreamer.EmitInstruction(TmpInst);
801 return;
802 }
Jim Grosbach2e812e12010-11-30 18:56:36 +0000803 case ARM::MOVPCRX: {
804 MCInst TmpInst;
805 TmpInst.setOpcode(ARM::MOVr);
806 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
807 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
808 // Add predicate operands.
809 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
810 TmpInst.addOperand(MCOperand::CreateReg(0));
811 // Add 's' bit operand (always reg0 for this)
812 TmpInst.addOperand(MCOperand::CreateReg(0));
813 OutStreamer.EmitInstruction(TmpInst);
814 return;
815 }
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +0000816 case ARM::BXr9_CALL:
817 case ARM::BX_CALL: {
818 {
819 MCInst TmpInst;
820 TmpInst.setOpcode(ARM::MOVr);
821 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
822 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
823 // Add predicate operands.
824 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
825 TmpInst.addOperand(MCOperand::CreateReg(0));
826 // Add 's' bit operand (always reg0 for this)
827 TmpInst.addOperand(MCOperand::CreateReg(0));
828 OutStreamer.EmitInstruction(TmpInst);
829 }
830 {
831 MCInst TmpInst;
832 TmpInst.setOpcode(ARM::BX);
833 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
834 OutStreamer.EmitInstruction(TmpInst);
835 }
836 return;
837 }
838 case ARM::BMOVPCRXr9_CALL:
839 case ARM::BMOVPCRX_CALL: {
840 {
841 MCInst TmpInst;
842 TmpInst.setOpcode(ARM::MOVr);
843 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
844 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
845 // Add predicate operands.
846 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
847 TmpInst.addOperand(MCOperand::CreateReg(0));
848 // Add 's' bit operand (always reg0 for this)
849 TmpInst.addOperand(MCOperand::CreateReg(0));
850 OutStreamer.EmitInstruction(TmpInst);
851 }
852 {
853 MCInst TmpInst;
854 TmpInst.setOpcode(ARM::MOVr);
855 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
856 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
857 // Add predicate operands.
858 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
859 TmpInst.addOperand(MCOperand::CreateReg(0));
860 // Add 's' bit operand (always reg0 for this)
861 TmpInst.addOperand(MCOperand::CreateReg(0));
862 OutStreamer.EmitInstruction(TmpInst);
863 }
864 return;
865 }
Evan Cheng53519f02011-01-21 18:55:51 +0000866 case ARM::MOVi16_ga_pcrel:
867 case ARM::t2MOVi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000868 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +0000869 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000870 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
871
Evan Cheng53519f02011-01-21 18:55:51 +0000872 unsigned TF = MI->getOperand(1).getTargetFlags();
873 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000874 const GlobalValue *GV = MI->getOperand(1).getGlobal();
875 MCSymbol *GVSym = GetARMGVSymbol(GV);
876 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +0000877 if (isPIC) {
878 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
879 getFunctionNumber(),
880 MI->getOperand(2).getImm(), OutContext);
881 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
882 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
883 const MCExpr *PCRelExpr =
884 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
885 MCBinaryExpr::CreateAdd(LabelSymExpr,
886 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000887 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +0000888 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
889 } else {
890 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
891 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
892 }
893
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000894 // Add predicate operands.
895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
896 TmpInst.addOperand(MCOperand::CreateReg(0));
897 // Add 's' bit operand (always reg0 for this)
898 TmpInst.addOperand(MCOperand::CreateReg(0));
899 OutStreamer.EmitInstruction(TmpInst);
900 return;
901 }
Evan Cheng53519f02011-01-21 18:55:51 +0000902 case ARM::MOVTi16_ga_pcrel:
903 case ARM::t2MOVTi16_ga_pcrel: {
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000904 MCInst TmpInst;
Evan Cheng53519f02011-01-21 18:55:51 +0000905 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
906 ? ARM::MOVTi16 : ARM::t2MOVTi16);
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000907 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
908 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
909
Evan Cheng53519f02011-01-21 18:55:51 +0000910 unsigned TF = MI->getOperand(2).getTargetFlags();
911 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000912 const GlobalValue *GV = MI->getOperand(2).getGlobal();
913 MCSymbol *GVSym = GetARMGVSymbol(GV);
914 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +0000915 if (isPIC) {
916 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
917 getFunctionNumber(),
918 MI->getOperand(3).getImm(), OutContext);
919 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
920 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
921 const MCExpr *PCRelExpr =
922 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
923 MCBinaryExpr::CreateAdd(LabelSymExpr,
924 MCConstantExpr::Create(PCAdj, OutContext),
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000925 OutContext), OutContext), OutContext);
Evan Cheng53519f02011-01-21 18:55:51 +0000926 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
927 } else {
928 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
929 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
930 }
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000931 // Add predicate operands.
932 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
933 TmpInst.addOperand(MCOperand::CreateReg(0));
934 // Add 's' bit operand (always reg0 for this)
935 TmpInst.addOperand(MCOperand::CreateReg(0));
936 OutStreamer.EmitInstruction(TmpInst);
937 return;
938 }
Jim Grosbachfbd18732010-09-17 23:41:53 +0000939 case ARM::tPICADD: {
940 // This is a pseudo op for a label + instruction sequence, which looks like:
941 // LPC0:
942 // add r0, pc
943 // This adds the address of LPC0 to r0.
944
945 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +0000946 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
947 getFunctionNumber(), MI->getOperand(2).getImm(),
948 OutContext));
Jim Grosbachfbd18732010-09-17 23:41:53 +0000949
950 // Form and emit the add.
951 MCInst AddInst;
952 AddInst.setOpcode(ARM::tADDhirr);
953 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
954 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
955 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
956 // Add predicate operands.
957 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
958 AddInst.addOperand(MCOperand::CreateReg(0));
959 OutStreamer.EmitInstruction(AddInst);
960 return;
961 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +0000962 case ARM::PICADD: {
Chris Lattner4d152222009-10-19 22:23:04 +0000963 // This is a pseudo op for a label + instruction sequence, which looks like:
964 // LPC0:
965 // add r0, pc, r0
966 // This adds the address of LPC0 to r0.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000967
Chris Lattner4d152222009-10-19 22:23:04 +0000968 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +0000969 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
970 getFunctionNumber(), MI->getOperand(2).getImm(),
971 OutContext));
Jim Grosbachb0739b72010-09-02 01:02:06 +0000972
Jim Grosbachf3f09522010-09-14 21:05:34 +0000973 // Form and emit the add.
Chris Lattner4d152222009-10-19 22:23:04 +0000974 MCInst AddInst;
975 AddInst.setOpcode(ARM::ADDrr);
976 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
977 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
978 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbach5b46d622010-09-14 21:28:17 +0000979 // Add predicate operands.
980 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
981 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
982 // Add 's' bit operand (always reg0 for this)
983 AddInst.addOperand(MCOperand::CreateReg(0));
Chris Lattner850d2e22010-02-03 01:16:28 +0000984 OutStreamer.EmitInstruction(AddInst);
Chris Lattner4d152222009-10-19 22:23:04 +0000985 return;
986 }
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000987 case ARM::PICSTR:
988 case ARM::PICSTRB:
989 case ARM::PICSTRH:
990 case ARM::PICLDR:
991 case ARM::PICLDRB:
992 case ARM::PICLDRH:
993 case ARM::PICLDRSB:
994 case ARM::PICLDRSH: {
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000995 // This is a pseudo op for a label + instruction sequence, which looks like:
996 // LPC0:
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000997 // OP r0, [pc, r0]
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000998 // The LCP0 label is referenced by a constant pool entry in order to get
999 // a PC-relative address at the ldr instruction.
1000
1001 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +00001002 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1003 getFunctionNumber(), MI->getOperand(2).getImm(),
1004 OutContext));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001005
1006 // Form and emit the load
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001007 unsigned Opcode;
1008 switch (MI->getOpcode()) {
1009 default:
1010 llvm_unreachable("Unexpected opcode!");
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001011 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1012 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001013 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach3e556122010-10-26 22:37:02 +00001014 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbachc1d30212010-10-27 00:19:44 +00001015 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001016 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1017 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1018 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1019 }
1020 MCInst LdStInst;
1021 LdStInst.setOpcode(Opcode);
1022 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1023 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1024 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1025 LdStInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001026 // Add predicate operands.
Jim Grosbacha28abbe2010-09-17 16:25:52 +00001027 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1028 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1029 OutStreamer.EmitInstruction(LdStInst);
Jim Grosbachb74ca9d2010-09-16 17:43:25 +00001030
1031 return;
1032 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001033 case ARM::CONSTPOOL_ENTRY: {
Chris Lattnera70e6442009-10-19 22:33:05 +00001034 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1035 /// in the function. The first operand is the ID# for this instruction, the
1036 /// second is the index into the MachineConstantPool that this is, the third
1037 /// is the size in bytes of this constant pool entry.
1038 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1039 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1040
1041 EmitAlignment(2);
Chris Lattner1b46f432010-01-23 07:00:21 +00001042 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattnera70e6442009-10-19 22:33:05 +00001043
1044 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1045 if (MCPE.isMachineConstantPoolEntry())
1046 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1047 else
1048 EmitGlobalConstant(MCPE.Val.ConstVal);
Jim Grosbachb0739b72010-09-02 01:02:06 +00001049
Chris Lattnera70e6442009-10-19 22:33:05 +00001050 return;
1051 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001052 case ARM::t2BR_JT: {
1053 // Lower and emit the instruction itself, then the jump table following it.
1054 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001055 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1056 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1057 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1058 // Add predicate operands.
1059 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1060 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001061 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbach5ca66692010-11-29 22:37:40 +00001062 // Output the data for the jump table itself
1063 EmitJump2Table(MI);
1064 return;
1065 }
1066 case ARM::t2TBB_JT: {
1067 // Lower and emit the instruction itself, then the jump table following it.
1068 MCInst TmpInst;
1069
1070 TmpInst.setOpcode(ARM::t2TBB);
1071 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1072 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1073 // Add predicate operands.
1074 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1075 TmpInst.addOperand(MCOperand::CreateReg(0));
1076 OutStreamer.EmitInstruction(TmpInst);
1077 // Output the data for the jump table itself
1078 EmitJump2Table(MI);
1079 // Make sure the next instruction is 2-byte aligned.
1080 EmitAlignment(1);
1081 return;
1082 }
1083 case ARM::t2TBH_JT: {
1084 // Lower and emit the instruction itself, then the jump table following it.
1085 MCInst TmpInst;
1086
1087 TmpInst.setOpcode(ARM::t2TBH);
1088 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1089 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1090 // Add predicate operands.
1091 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1092 TmpInst.addOperand(MCOperand::CreateReg(0));
1093 OutStreamer.EmitInstruction(TmpInst);
1094 // Output the data for the jump table itself
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001095 EmitJump2Table(MI);
1096 return;
1097 }
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001098 case ARM::tBR_JTr:
Jim Grosbach2dc77682010-11-29 18:37:44 +00001099 case ARM::BR_JTr: {
1100 // Lower and emit the instruction itself, then the jump table following it.
1101 // mov pc, target
1102 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001103 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1104 ARM::MOVr : ARM::tMOVgpr2gpr;
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001105 TmpInst.setOpcode(Opc);
Jim Grosbach2dc77682010-11-29 18:37:44 +00001106 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1107 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1108 // Add predicate operands.
1109 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1110 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001111 // Add 's' bit operand (always reg0 for this)
1112 if (Opc == ARM::MOVr)
1113 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach2dc77682010-11-29 18:37:44 +00001114 OutStreamer.EmitInstruction(TmpInst);
1115
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001116 // Make sure the Thumb jump table is 4-byte aligned.
Bill Wendlinga68a4fd2010-12-18 02:13:59 +00001117 if (Opc == ARM::tMOVgpr2gpr)
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001118 EmitAlignment(2);
1119
Jim Grosbach2dc77682010-11-29 18:37:44 +00001120 // Output the data for the jump table itself
1121 EmitJumpTable(MI);
1122 return;
1123 }
1124 case ARM::BR_JTm: {
1125 // Lower and emit the instruction itself, then the jump table following it.
1126 // ldr pc, target
1127 MCInst TmpInst;
1128 if (MI->getOperand(1).getReg() == 0) {
1129 // literal offset
1130 TmpInst.setOpcode(ARM::LDRi12);
1131 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1132 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1133 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1134 } else {
1135 TmpInst.setOpcode(ARM::LDRrs);
1136 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1137 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1138 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1139 TmpInst.addOperand(MCOperand::CreateImm(0));
1140 }
1141 // Add predicate operands.
1142 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1143 TmpInst.addOperand(MCOperand::CreateReg(0));
1144 OutStreamer.EmitInstruction(TmpInst);
1145
1146 // Output the data for the jump table itself
Jim Grosbacha2244cb2010-09-22 17:39:48 +00001147 EmitJumpTable(MI);
1148 return;
1149 }
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001150 case ARM::BR_JTadd: {
1151 // Lower and emit the instruction itself, then the jump table following it.
1152 // add pc, target, idx
Jim Grosbach2dc77682010-11-29 18:37:44 +00001153 MCInst TmpInst;
1154 TmpInst.setOpcode(ARM::ADDrr);
1155 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1156 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1157 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001158 // Add predicate operands.
Jim Grosbach2dc77682010-11-29 18:37:44 +00001159 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1160 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001161 // Add 's' bit operand (always reg0 for this)
Jim Grosbach2dc77682010-11-29 18:37:44 +00001162 TmpInst.addOperand(MCOperand::CreateReg(0));
1163 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001164
1165 // Output the data for the jump table itself
1166 EmitJumpTable(MI);
1167 return;
1168 }
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001169 case ARM::TRAP: {
1170 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1171 // FIXME: Remove this special case when they do.
1172 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001173 //.long 0xe7ffdefe @ trap
Jim Grosbachb2dda4b2010-09-23 19:42:17 +00001174 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001175 OutStreamer.AddComment("trap");
1176 OutStreamer.EmitIntValue(Val, 4);
1177 return;
1178 }
1179 break;
1180 }
1181 case ARM::tTRAP: {
1182 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1183 // FIXME: Remove this special case when they do.
1184 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001185 //.short 57086 @ trap
Benjamin Kramerc8ab9eb2010-09-23 18:57:26 +00001186 uint16_t Val = 0xdefe;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001187 OutStreamer.AddComment("trap");
1188 OutStreamer.EmitIntValue(Val, 2);
1189 return;
1190 }
1191 break;
1192 }
Jim Grosbach433a5782010-09-24 20:47:58 +00001193 case ARM::t2Int_eh_sjlj_setjmp:
1194 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001195 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach433a5782010-09-24 20:47:58 +00001196 // Two incoming args: GPR:$src, GPR:$val
1197 // mov $val, pc
1198 // adds $val, #7
1199 // str $val, [$src, #4]
1200 // movs r0, #0
1201 // b 1f
1202 // movs r0, #1
1203 // 1:
1204 unsigned SrcReg = MI->getOperand(0).getReg();
1205 unsigned ValReg = MI->getOperand(1).getReg();
1206 MCSymbol *Label = GetARMSJLJEHLabel();
1207 {
1208 MCInst TmpInst;
1209 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1210 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1211 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1212 // 's' bit operand
1213 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1214 OutStreamer.AddComment("eh_setjmp begin");
1215 OutStreamer.EmitInstruction(TmpInst);
1216 }
1217 {
1218 MCInst TmpInst;
1219 TmpInst.setOpcode(ARM::tADDi3);
1220 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1221 // 's' bit operand
1222 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1223 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1224 TmpInst.addOperand(MCOperand::CreateImm(7));
1225 // Predicate.
1226 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1227 TmpInst.addOperand(MCOperand::CreateReg(0));
1228 OutStreamer.EmitInstruction(TmpInst);
1229 }
1230 {
1231 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001232 TmpInst.setOpcode(ARM::tSTRi);
Jim Grosbach433a5782010-09-24 20:47:58 +00001233 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1234 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1235 // The offset immediate is #4. The operand value is scaled by 4 for the
1236 // tSTR instruction.
1237 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach433a5782010-09-24 20:47:58 +00001238 // Predicate.
1239 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1240 TmpInst.addOperand(MCOperand::CreateReg(0));
1241 OutStreamer.EmitInstruction(TmpInst);
1242 }
1243 {
1244 MCInst TmpInst;
1245 TmpInst.setOpcode(ARM::tMOVi8);
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1247 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1248 TmpInst.addOperand(MCOperand::CreateImm(0));
1249 // Predicate.
1250 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1251 TmpInst.addOperand(MCOperand::CreateReg(0));
1252 OutStreamer.EmitInstruction(TmpInst);
1253 }
1254 {
1255 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1256 MCInst TmpInst;
1257 TmpInst.setOpcode(ARM::tB);
1258 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1259 OutStreamer.EmitInstruction(TmpInst);
1260 }
1261 {
1262 MCInst TmpInst;
1263 TmpInst.setOpcode(ARM::tMOVi8);
1264 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1265 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1266 TmpInst.addOperand(MCOperand::CreateImm(1));
1267 // Predicate.
1268 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1269 TmpInst.addOperand(MCOperand::CreateReg(0));
1270 OutStreamer.AddComment("eh_setjmp end");
1271 OutStreamer.EmitInstruction(TmpInst);
1272 }
1273 OutStreamer.EmitLabel(Label);
1274 return;
1275 }
1276
Jim Grosbach45390082010-09-23 23:33:56 +00001277 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001278 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbach45390082010-09-23 23:33:56 +00001279 // Two incoming args: GPR:$src, GPR:$val
1280 // add $val, pc, #8
1281 // str $val, [$src, #+4]
1282 // mov r0, #0
1283 // add pc, pc, #0
1284 // mov r0, #1
1285 unsigned SrcReg = MI->getOperand(0).getReg();
1286 unsigned ValReg = MI->getOperand(1).getReg();
1287
1288 {
1289 MCInst TmpInst;
1290 TmpInst.setOpcode(ARM::ADDri);
1291 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1292 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1293 TmpInst.addOperand(MCOperand::CreateImm(8));
1294 // Predicate.
1295 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
1297 // 's' bit operand (always reg0 for this).
1298 TmpInst.addOperand(MCOperand::CreateReg(0));
1299 OutStreamer.AddComment("eh_setjmp begin");
1300 OutStreamer.EmitInstruction(TmpInst);
1301 }
1302 {
1303 MCInst TmpInst;
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001304 TmpInst.setOpcode(ARM::STRi12);
Jim Grosbach45390082010-09-23 23:33:56 +00001305 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1306 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach45390082010-09-23 23:33:56 +00001307 TmpInst.addOperand(MCOperand::CreateImm(4));
1308 // Predicate.
1309 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1310 TmpInst.addOperand(MCOperand::CreateReg(0));
1311 OutStreamer.EmitInstruction(TmpInst);
1312 }
1313 {
1314 MCInst TmpInst;
1315 TmpInst.setOpcode(ARM::MOVi);
1316 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1317 TmpInst.addOperand(MCOperand::CreateImm(0));
1318 // Predicate.
1319 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1320 TmpInst.addOperand(MCOperand::CreateReg(0));
1321 // 's' bit operand (always reg0 for this).
1322 TmpInst.addOperand(MCOperand::CreateReg(0));
1323 OutStreamer.EmitInstruction(TmpInst);
1324 }
1325 {
1326 MCInst TmpInst;
1327 TmpInst.setOpcode(ARM::ADDri);
1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1330 TmpInst.addOperand(MCOperand::CreateImm(0));
1331 // Predicate.
1332 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 // 's' bit operand (always reg0 for this).
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(TmpInst);
1337 }
1338 {
1339 MCInst TmpInst;
1340 TmpInst.setOpcode(ARM::MOVi);
1341 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1342 TmpInst.addOperand(MCOperand::CreateImm(1));
1343 // Predicate.
1344 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1345 TmpInst.addOperand(MCOperand::CreateReg(0));
1346 // 's' bit operand (always reg0 for this).
1347 TmpInst.addOperand(MCOperand::CreateReg(0));
1348 OutStreamer.AddComment("eh_setjmp end");
1349 OutStreamer.EmitInstruction(TmpInst);
1350 }
1351 return;
1352 }
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001353 case ARM::Int_eh_sjlj_longjmp: {
1354 // ldr sp, [$src, #8]
1355 // ldr $scratch, [$src, #4]
1356 // ldr r7, [$src]
1357 // bx $scratch
1358 unsigned SrcReg = MI->getOperand(0).getReg();
1359 unsigned ScratchReg = MI->getOperand(1).getReg();
1360 {
1361 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001362 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001363 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1364 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001365 TmpInst.addOperand(MCOperand::CreateImm(8));
1366 // Predicate.
1367 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1368 TmpInst.addOperand(MCOperand::CreateReg(0));
1369 OutStreamer.EmitInstruction(TmpInst);
1370 }
1371 {
1372 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001373 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001374 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1375 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001376 TmpInst.addOperand(MCOperand::CreateImm(4));
1377 // Predicate.
1378 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1379 TmpInst.addOperand(MCOperand::CreateReg(0));
1380 OutStreamer.EmitInstruction(TmpInst);
1381 }
1382 {
1383 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001384 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001385 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1386 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001387 TmpInst.addOperand(MCOperand::CreateImm(0));
1388 // Predicate.
1389 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1390 TmpInst.addOperand(MCOperand::CreateReg(0));
1391 OutStreamer.EmitInstruction(TmpInst);
1392 }
1393 {
1394 MCInst TmpInst;
Bill Wendling6e46d842010-11-30 00:48:15 +00001395 TmpInst.setOpcode(ARM::BX);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001396 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1397 // Predicate.
1398 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1399 TmpInst.addOperand(MCOperand::CreateReg(0));
1400 OutStreamer.EmitInstruction(TmpInst);
1401 }
1402 return;
1403 }
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001404 case ARM::tInt_eh_sjlj_longjmp: {
1405 // ldr $scratch, [$src, #8]
1406 // mov sp, $scratch
1407 // ldr $scratch, [$src, #4]
1408 // ldr r7, [$src]
1409 // bx $scratch
1410 unsigned SrcReg = MI->getOperand(0).getReg();
1411 unsigned ScratchReg = MI->getOperand(1).getReg();
1412 {
1413 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001414 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001415 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1416 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1417 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendlingf4caf692010-12-14 03:36:38 +00001418 // tLDR instruction.
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001419 TmpInst.addOperand(MCOperand::CreateImm(2));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001420 // Predicate.
1421 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1422 TmpInst.addOperand(MCOperand::CreateReg(0));
1423 OutStreamer.EmitInstruction(TmpInst);
1424 }
1425 {
1426 MCInst TmpInst;
1427 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1428 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1429 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1430 // Predicate.
1431 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1432 TmpInst.addOperand(MCOperand::CreateReg(0));
1433 OutStreamer.EmitInstruction(TmpInst);
1434 }
1435 {
1436 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001437 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001438 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1439 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1440 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001441 // Predicate.
1442 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1443 TmpInst.addOperand(MCOperand::CreateReg(0));
1444 OutStreamer.EmitInstruction(TmpInst);
1445 }
1446 {
1447 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001448 TmpInst.setOpcode(ARM::tLDRr);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001449 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1450 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001451 TmpInst.addOperand(MCOperand::CreateReg(0));
1452 // Predicate.
1453 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1454 TmpInst.addOperand(MCOperand::CreateReg(0));
1455 OutStreamer.EmitInstruction(TmpInst);
1456 }
1457 {
1458 MCInst TmpInst;
1459 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1460 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1461 // Predicate.
1462 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1463 TmpInst.addOperand(MCOperand::CreateReg(0));
1464 OutStreamer.EmitInstruction(TmpInst);
1465 }
1466 return;
1467 }
Anton Korobeynikov4d728602011-01-01 20:38:38 +00001468 // These are the pseudos created to comply with stricter operand restrictions
1469 // on ARMv5. Lower them now to "normal" instructions, since all the
1470 // restrictions are already satisfied.
1471 case ARM::MULv5:
1472 EmitPatchedInstruction(MI, ARM::MUL);
1473 return;
1474 case ARM::MLAv5:
1475 EmitPatchedInstruction(MI, ARM::MLA);
1476 return;
1477 case ARM::SMULLv5:
1478 EmitPatchedInstruction(MI, ARM::SMULL);
1479 return;
1480 case ARM::UMULLv5:
1481 EmitPatchedInstruction(MI, ARM::UMULL);
1482 return;
1483 case ARM::SMLALv5:
1484 EmitPatchedInstruction(MI, ARM::SMLAL);
1485 return;
1486 case ARM::UMLALv5:
1487 EmitPatchedInstruction(MI, ARM::UMLAL);
1488 return;
1489 case ARM::UMAALv5:
1490 EmitPatchedInstruction(MI, ARM::UMAAL);
1491 return;
Chris Lattner97f06932009-10-19 20:20:46 +00001492 }
Jim Grosbachb0739b72010-09-02 01:02:06 +00001493
Chris Lattner97f06932009-10-19 20:20:46 +00001494 MCInst TmpInst;
Chris Lattner30e2cc22010-11-14 21:00:02 +00001495 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Chris Lattner850d2e22010-02-03 01:16:28 +00001496 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner97f06932009-10-19 20:20:46 +00001497}
Daniel Dunbar2685a292009-10-20 05:15:36 +00001498
1499//===----------------------------------------------------------------------===//
1500// Target Registry Stuff
1501//===----------------------------------------------------------------------===//
1502
1503static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1504 unsigned SyntaxVariant,
Chris Lattnerd3740872010-04-04 05:04:31 +00001505 const MCAsmInfo &MAI) {
Daniel Dunbar2685a292009-10-20 05:15:36 +00001506 if (SyntaxVariant == 0)
Jim Grosbach74d7e6c2010-09-17 21:33:25 +00001507 return new ARMInstPrinter(MAI);
Daniel Dunbar2685a292009-10-20 05:15:36 +00001508 return 0;
1509}
1510
1511// Force static initialization.
1512extern "C" void LLVMInitializeARMAsmPrinter() {
1513 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1514 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1515
1516 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1517 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
1518}
1519