Arnold Schwaighofer | 92226dd | 2007-10-12 21:53:12 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "X86.h" |
Evan Cheng | 0cc3945 | 2006-01-16 21:21:29 +0000 | [diff] [blame] | 16 | #include "X86InstrBuilder.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 17 | #include "X86ISelLowering.h" |
Evan Cheng | e8bd0a3 | 2006-06-06 23:30:24 +0000 | [diff] [blame] | 18 | #include "X86MachineFunctionInfo.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 19 | #include "X86TargetMachine.h" |
| 20 | #include "llvm/CallingConv.h" |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
Evan Cheng | 347d5f7 | 2006-04-28 21:29:37 +0000 | [diff] [blame] | 22 | #include "llvm/DerivedTypes.h" |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 23 | #include "llvm/GlobalVariable.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 24 | #include "llvm/Function.h" |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 25 | #include "llvm/Intrinsics.h" |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 26 | #include "llvm/ADT/BitVector.h" |
Evan Cheng | 30b37b5 | 2006-03-13 23:18:16 +0000 | [diff] [blame] | 27 | #include "llvm/ADT/VectorExtras.h" |
| 28 | #include "llvm/Analysis/ScalarEvolutionExpressions.h" |
Chris Lattner | 362e98a | 2007-02-27 04:43:02 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/CallingConvLower.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 30 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 31 | #include "llvm/CodeGen/MachineFunction.h" |
| 32 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | a844bde | 2008-02-02 04:07:54 +0000 | [diff] [blame] | 33 | #include "llvm/CodeGen/MachineModuleInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 34 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 35 | #include "llvm/CodeGen/PseudoSourceValue.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 36 | #include "llvm/CodeGen/SelectionDAG.h" |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 37 | #include "llvm/Support/MathExtras.h" |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 38 | #include "llvm/Support/Debug.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 39 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 40 | #include "llvm/ADT/SmallSet.h" |
Chris Lattner | 1a60aa7 | 2006-10-31 19:42:44 +0000 | [diff] [blame] | 41 | #include "llvm/ADT/StringExtras.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 42 | using namespace llvm; |
| 43 | |
Evan Cheng | 10e8642 | 2008-04-25 19:11:04 +0000 | [diff] [blame] | 44 | // Forward declarations. |
| 45 | static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG); |
| 46 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 47 | X86TargetLowering::X86TargetLowering(TargetMachine &TM) |
| 48 | : TargetLowering(TM) { |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 49 | Subtarget = &TM.getSubtarget<X86Subtarget>(); |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 50 | X86ScalarSSEf64 = Subtarget->hasSSE2(); |
| 51 | X86ScalarSSEf32 = Subtarget->hasSSE1(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 52 | X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 53 | |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 54 | bool Fast = false; |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 55 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 56 | RegInfo = TM.getRegisterInfo(); |
| 57 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 58 | // Set up the TargetLowering object. |
| 59 | |
| 60 | // X86 is weird, it always uses i8 for shift amounts and setcc results. |
| 61 | setShiftAmountType(MVT::i8); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 62 | setSetCCResultContents(ZeroOrOneSetCCResult); |
Evan Cheng | 0b2afbd | 2006-01-25 09:15:17 +0000 | [diff] [blame] | 63 | setSchedulingPreference(SchedulingForRegPressure); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 64 | setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 65 | setStackPointerRegisterToSaveRestore(X86StackPtr); |
Evan Cheng | 714554d | 2006-03-16 21:47:42 +0000 | [diff] [blame] | 66 | |
Anton Korobeynikov | d27a258 | 2006-12-10 23:12:42 +0000 | [diff] [blame] | 67 | if (Subtarget->isTargetDarwin()) { |
Evan Cheng | df57fa0 | 2006-03-17 20:31:41 +0000 | [diff] [blame] | 68 | // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. |
Anton Korobeynikov | d27a258 | 2006-12-10 23:12:42 +0000 | [diff] [blame] | 69 | setUseUnderscoreSetJmp(false); |
| 70 | setUseUnderscoreLongJmp(false); |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 71 | } else if (Subtarget->isTargetMingw()) { |
Anton Korobeynikov | d27a258 | 2006-12-10 23:12:42 +0000 | [diff] [blame] | 72 | // MS runtime is weird: it exports _setjmp, but longjmp! |
| 73 | setUseUnderscoreSetJmp(true); |
| 74 | setUseUnderscoreLongJmp(false); |
| 75 | } else { |
| 76 | setUseUnderscoreSetJmp(true); |
| 77 | setUseUnderscoreLongJmp(true); |
| 78 | } |
| 79 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 80 | // Set up the register classes. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 81 | addRegisterClass(MVT::i8, X86::GR8RegisterClass); |
| 82 | addRegisterClass(MVT::i16, X86::GR16RegisterClass); |
| 83 | addRegisterClass(MVT::i32, X86::GR32RegisterClass); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 84 | if (Subtarget->is64Bit()) |
| 85 | addRegisterClass(MVT::i64, X86::GR64RegisterClass); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 86 | |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 87 | setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); |
Evan Cheng | c548428 | 2006-10-04 00:56:09 +0000 | [diff] [blame] | 88 | |
Chris Lattner | ddf8956 | 2008-01-17 19:59:44 +0000 | [diff] [blame] | 89 | // We don't accept any truncstore of integer registers. |
| 90 | setTruncStoreAction(MVT::i64, MVT::i32, Expand); |
| 91 | setTruncStoreAction(MVT::i64, MVT::i16, Expand); |
| 92 | setTruncStoreAction(MVT::i64, MVT::i8 , Expand); |
| 93 | setTruncStoreAction(MVT::i32, MVT::i16, Expand); |
| 94 | setTruncStoreAction(MVT::i32, MVT::i8 , Expand); |
| 95 | setTruncStoreAction(MVT::i16, MVT::i8, Expand); |
| 96 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 97 | // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this |
| 98 | // operation. |
| 99 | setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); |
| 100 | setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); |
| 101 | setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); |
Evan Cheng | 6892f28 | 2006-01-17 02:32:49 +0000 | [diff] [blame] | 102 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 103 | if (Subtarget->is64Bit()) { |
| 104 | setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); |
Evan Cheng | 6892f28 | 2006-01-17 02:32:49 +0000 | [diff] [blame] | 105 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 106 | } else { |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 107 | if (X86ScalarSSEf64) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 108 | // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. |
| 109 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); |
| 110 | else |
| 111 | setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); |
| 112 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 113 | |
| 114 | // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have |
| 115 | // this operation. |
| 116 | setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); |
| 117 | setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 118 | // SSE has no i16 to fp conversion, only i32 |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 119 | if (X86ScalarSSEf32) { |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 120 | setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 121 | // f32 and f64 cases are Legal, f80 case is not |
| 122 | setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); |
| 123 | } else { |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 124 | setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); |
| 125 | setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); |
| 126 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 127 | |
Dale Johannesen | 73328d1 | 2007-09-19 23:55:34 +0000 | [diff] [blame] | 128 | // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 |
| 129 | // are Legal, f80 is custom lowered. |
| 130 | setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); |
| 131 | setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); |
Evan Cheng | 6dab053 | 2006-01-30 08:02:57 +0000 | [diff] [blame] | 132 | |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 133 | // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have |
| 134 | // this operation. |
| 135 | setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); |
| 136 | setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); |
| 137 | |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 138 | if (X86ScalarSSEf32) { |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 139 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 140 | // f32 and f64 cases are Legal, f80 case is not |
| 141 | setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 142 | } else { |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 143 | setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); |
Evan Cheng | 02568ff | 2006-01-30 22:13:22 +0000 | [diff] [blame] | 144 | setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | // Handle FP_TO_UINT by promoting the destination to a larger signed |
| 148 | // conversion. |
| 149 | setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); |
| 150 | setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); |
| 151 | setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); |
| 152 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 153 | if (Subtarget->is64Bit()) { |
| 154 | setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 155 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 156 | } else { |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 157 | if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 158 | // Expand FP_TO_UINT into a select. |
| 159 | // FIXME: We would like to use a Custom expander here eventually to do |
| 160 | // the optimal thing for SSE vs. the default expansion in the legalizer. |
| 161 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); |
| 162 | else |
| 163 | // With SSE3 we can use fisttpll to convert to a signed i64. |
| 164 | setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); |
| 165 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 166 | |
Chris Lattner | 399610a | 2006-12-05 18:22:22 +0000 | [diff] [blame] | 167 | // TODO: when we have SSE, these could be more efficient, by using movd/movq. |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 168 | if (!X86ScalarSSEf64) { |
Chris Lattner | f3597a1 | 2006-12-05 18:45:06 +0000 | [diff] [blame] | 169 | setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); |
| 170 | setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); |
| 171 | } |
Chris Lattner | 21f6685 | 2005-12-23 05:15:23 +0000 | [diff] [blame] | 172 | |
Dan Gohman | b00ee21 | 2008-02-18 19:34:53 +0000 | [diff] [blame] | 173 | // Scalar integer divide and remainder are lowered to use operations that |
| 174 | // produce two results, to match the available instructions. This exposes |
| 175 | // the two-result form to trivial CSE, which is able to combine x/y and x%y |
| 176 | // into a single instruction. |
| 177 | // |
| 178 | // Scalar integer multiply-high is also lowered to use two-result |
| 179 | // operations, to match the available instructions. However, plain multiply |
| 180 | // (low) operations are left as Legal, as there are single-result |
| 181 | // instructions for this in x86. Using the two-result multiply instructions |
| 182 | // when both high and low results are needed must be arranged by dagcombine. |
Dan Gohman | 525178c | 2007-10-08 18:33:35 +0000 | [diff] [blame] | 183 | setOperationAction(ISD::MULHS , MVT::i8 , Expand); |
| 184 | setOperationAction(ISD::MULHU , MVT::i8 , Expand); |
| 185 | setOperationAction(ISD::SDIV , MVT::i8 , Expand); |
| 186 | setOperationAction(ISD::UDIV , MVT::i8 , Expand); |
| 187 | setOperationAction(ISD::SREM , MVT::i8 , Expand); |
| 188 | setOperationAction(ISD::UREM , MVT::i8 , Expand); |
Dan Gohman | 525178c | 2007-10-08 18:33:35 +0000 | [diff] [blame] | 189 | setOperationAction(ISD::MULHS , MVT::i16 , Expand); |
| 190 | setOperationAction(ISD::MULHU , MVT::i16 , Expand); |
| 191 | setOperationAction(ISD::SDIV , MVT::i16 , Expand); |
| 192 | setOperationAction(ISD::UDIV , MVT::i16 , Expand); |
| 193 | setOperationAction(ISD::SREM , MVT::i16 , Expand); |
| 194 | setOperationAction(ISD::UREM , MVT::i16 , Expand); |
Dan Gohman | 525178c | 2007-10-08 18:33:35 +0000 | [diff] [blame] | 195 | setOperationAction(ISD::MULHS , MVT::i32 , Expand); |
| 196 | setOperationAction(ISD::MULHU , MVT::i32 , Expand); |
| 197 | setOperationAction(ISD::SDIV , MVT::i32 , Expand); |
| 198 | setOperationAction(ISD::UDIV , MVT::i32 , Expand); |
| 199 | setOperationAction(ISD::SREM , MVT::i32 , Expand); |
| 200 | setOperationAction(ISD::UREM , MVT::i32 , Expand); |
Dan Gohman | 525178c | 2007-10-08 18:33:35 +0000 | [diff] [blame] | 201 | setOperationAction(ISD::MULHS , MVT::i64 , Expand); |
| 202 | setOperationAction(ISD::MULHU , MVT::i64 , Expand); |
| 203 | setOperationAction(ISD::SDIV , MVT::i64 , Expand); |
| 204 | setOperationAction(ISD::UDIV , MVT::i64 , Expand); |
| 205 | setOperationAction(ISD::SREM , MVT::i64 , Expand); |
| 206 | setOperationAction(ISD::UREM , MVT::i64 , Expand); |
Dan Gohman | a37c9f7 | 2007-09-25 18:23:27 +0000 | [diff] [blame] | 207 | |
Evan Cheng | c35497f | 2006-10-30 08:02:39 +0000 | [diff] [blame] | 208 | setOperationAction(ISD::BR_JT , MVT::Other, Expand); |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 209 | setOperationAction(ISD::BRCOND , MVT::Other, Custom); |
Nate Begeman | 750ac1b | 2006-02-01 07:19:44 +0000 | [diff] [blame] | 210 | setOperationAction(ISD::BR_CC , MVT::Other, Expand); |
| 211 | setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 212 | if (Subtarget->is64Bit()) |
Christopher Lamb | c59e521 | 2007-08-10 21:48:46 +0000 | [diff] [blame] | 213 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); |
| 214 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); |
| 215 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 216 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); |
| 217 | setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); |
Chris Lattner | d110822 | 2008-03-07 06:36:32 +0000 | [diff] [blame] | 218 | setOperationAction(ISD::FREM , MVT::f32 , Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 219 | setOperationAction(ISD::FREM , MVT::f64 , Expand); |
Chris Lattner | d110822 | 2008-03-07 06:36:32 +0000 | [diff] [blame] | 220 | setOperationAction(ISD::FREM , MVT::f80 , Expand); |
Dan Gohman | 1a02486 | 2008-01-31 00:41:03 +0000 | [diff] [blame] | 221 | setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); |
Anton Korobeynikov | 45b22fa | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 222 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 223 | setOperationAction(ISD::CTPOP , MVT::i8 , Expand); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 224 | setOperationAction(ISD::CTTZ , MVT::i8 , Custom); |
| 225 | setOperationAction(ISD::CTLZ , MVT::i8 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 226 | setOperationAction(ISD::CTPOP , MVT::i16 , Expand); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 227 | setOperationAction(ISD::CTTZ , MVT::i16 , Custom); |
| 228 | setOperationAction(ISD::CTLZ , MVT::i16 , Custom); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 229 | setOperationAction(ISD::CTPOP , MVT::i32 , Expand); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 230 | setOperationAction(ISD::CTTZ , MVT::i32 , Custom); |
| 231 | setOperationAction(ISD::CTLZ , MVT::i32 , Custom); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 232 | if (Subtarget->is64Bit()) { |
| 233 | setOperationAction(ISD::CTPOP , MVT::i64 , Expand); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 234 | setOperationAction(ISD::CTTZ , MVT::i64 , Custom); |
| 235 | setOperationAction(ISD::CTLZ , MVT::i64 , Custom); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 236 | } |
| 237 | |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 238 | setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); |
Nate Begeman | d88fc03 | 2006-01-14 03:14:10 +0000 | [diff] [blame] | 239 | setOperationAction(ISD::BSWAP , MVT::i16 , Expand); |
Nate Begeman | 35ef913 | 2006-01-11 21:21:00 +0000 | [diff] [blame] | 240 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 241 | // These should be promoted to a larger select which is supported. |
| 242 | setOperationAction(ISD::SELECT , MVT::i1 , Promote); |
| 243 | setOperationAction(ISD::SELECT , MVT::i8 , Promote); |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 244 | // X86 wants to expand cmov itself. |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 245 | setOperationAction(ISD::SELECT , MVT::i16 , Custom); |
| 246 | setOperationAction(ISD::SELECT , MVT::i32 , Custom); |
| 247 | setOperationAction(ISD::SELECT , MVT::f32 , Custom); |
| 248 | setOperationAction(ISD::SELECT , MVT::f64 , Custom); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 249 | setOperationAction(ISD::SELECT , MVT::f80 , Custom); |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 250 | setOperationAction(ISD::SETCC , MVT::i8 , Custom); |
| 251 | setOperationAction(ISD::SETCC , MVT::i16 , Custom); |
| 252 | setOperationAction(ISD::SETCC , MVT::i32 , Custom); |
| 253 | setOperationAction(ISD::SETCC , MVT::f32 , Custom); |
| 254 | setOperationAction(ISD::SETCC , MVT::f64 , Custom); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 255 | setOperationAction(ISD::SETCC , MVT::f80 , Custom); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 256 | if (Subtarget->is64Bit()) { |
| 257 | setOperationAction(ISD::SELECT , MVT::i64 , Custom); |
| 258 | setOperationAction(ISD::SETCC , MVT::i64 , Custom); |
| 259 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 260 | // X86 ret instruction may pop stack. |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 261 | setOperationAction(ISD::RET , MVT::Other, Custom); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 262 | if (!Subtarget->is64Bit()) |
| 263 | setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); |
| 264 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 265 | // Darwin ABI issue. |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 266 | setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 267 | setOperationAction(ISD::JumpTable , MVT::i32 , Custom); |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 268 | setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 269 | setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 270 | if (Subtarget->is64Bit()) |
| 271 | setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 272 | setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 273 | if (Subtarget->is64Bit()) { |
| 274 | setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); |
| 275 | setOperationAction(ISD::JumpTable , MVT::i64 , Custom); |
| 276 | setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); |
| 277 | setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); |
| 278 | } |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 279 | // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) |
Evan Cheng | 5298bcc | 2006-02-17 07:01:52 +0000 | [diff] [blame] | 280 | setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); |
| 281 | setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); |
| 282 | setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 283 | if (Subtarget->is64Bit()) { |
| 284 | setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); |
| 285 | setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); |
| 286 | setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); |
| 287 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 288 | |
Evan Cheng | d2cde68 | 2008-03-10 19:38:10 +0000 | [diff] [blame] | 289 | if (Subtarget->hasSSE1()) |
| 290 | setOperationAction(ISD::PREFETCH , MVT::Other, Legal); |
Evan Cheng | 27b7db5 | 2008-03-08 00:58:38 +0000 | [diff] [blame] | 291 | |
Andrew Lenharth | d497d9f | 2008-02-16 14:46:26 +0000 | [diff] [blame] | 292 | if (!Subtarget->hasSSE2()) |
| 293 | setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); |
| 294 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 295 | setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom); |
| 296 | setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom); |
| 297 | setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom); |
Andrew Lenharth | a76e2f0 | 2008-03-04 21:13:33 +0000 | [diff] [blame] | 298 | setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom); |
Andrew Lenharth | d497d9f | 2008-02-16 14:46:26 +0000 | [diff] [blame] | 299 | |
Evan Cheng | a844bde | 2008-02-02 04:07:54 +0000 | [diff] [blame] | 300 | // Use the default ISD::LOCATION, ISD::DECLARE expansion. |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 301 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 302 | // FIXME - use subtarget debug flags |
Anton Korobeynikov | ab4022f | 2006-10-31 08:31:24 +0000 | [diff] [blame] | 303 | if (!Subtarget->isTargetDarwin() && |
| 304 | !Subtarget->isTargetELF() && |
Anton Korobeynikov | 317848f | 2007-01-03 11:43:14 +0000 | [diff] [blame] | 305 | !Subtarget->isTargetCygMing()) |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 306 | setOperationAction(ISD::LABEL, MVT::Other, Expand); |
Chris Lattner | f73bae1 | 2005-11-29 06:16:21 +0000 | [diff] [blame] | 307 | |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 308 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); |
| 309 | setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); |
| 310 | setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); |
| 311 | setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); |
| 312 | if (Subtarget->is64Bit()) { |
| 313 | // FIXME: Verify |
| 314 | setExceptionPointerRegister(X86::RAX); |
| 315 | setExceptionSelectorRegister(X86::RDX); |
| 316 | } else { |
| 317 | setExceptionPointerRegister(X86::EAX); |
| 318 | setExceptionSelectorRegister(X86::EDX); |
| 319 | } |
Anton Korobeynikov | 3825262 | 2007-09-03 00:36:06 +0000 | [diff] [blame] | 320 | setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); |
Anton Korobeynikov | ce3b465 | 2007-05-02 19:53:33 +0000 | [diff] [blame] | 321 | |
Duncan Sands | f7331b3 | 2007-09-11 14:10:23 +0000 | [diff] [blame] | 322 | setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 323 | |
Chris Lattner | da68d30 | 2008-01-15 21:58:22 +0000 | [diff] [blame] | 324 | setOperationAction(ISD::TRAP, MVT::Other, Legal); |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 325 | |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 326 | // VASTART needs to be custom lowered to use the VarArgsFrameIndex |
| 327 | setOperationAction(ISD::VASTART , MVT::Other, Custom); |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 328 | setOperationAction(ISD::VAARG , MVT::Other, Expand); |
Nate Begeman | acc398c | 2006-01-25 18:21:52 +0000 | [diff] [blame] | 329 | setOperationAction(ISD::VAEND , MVT::Other, Expand); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 330 | if (Subtarget->is64Bit()) |
| 331 | setOperationAction(ISD::VACOPY , MVT::Other, Custom); |
| 332 | else |
| 333 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); |
| 334 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 335 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
Chris Lattner | e112552 | 2006-01-15 09:00:21 +0000 | [diff] [blame] | 336 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 337 | if (Subtarget->is64Bit()) |
| 338 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 339 | if (Subtarget->isTargetCygMing()) |
| 340 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); |
| 341 | else |
| 342 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); |
Chris Lattner | b99329e | 2006-01-13 02:42:53 +0000 | [diff] [blame] | 343 | |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 344 | if (X86ScalarSSEf64) { |
| 345 | // f32 and f64 use SSE. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 346 | // Set up the FP register classes. |
Evan Cheng | 5ee4ccc | 2006-01-12 08:27:59 +0000 | [diff] [blame] | 347 | addRegisterClass(MVT::f32, X86::FR32RegisterClass); |
| 348 | addRegisterClass(MVT::f64, X86::FR64RegisterClass); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 349 | |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 350 | // Use ANDPD to simulate FABS. |
| 351 | setOperationAction(ISD::FABS , MVT::f64, Custom); |
| 352 | setOperationAction(ISD::FABS , MVT::f32, Custom); |
| 353 | |
| 354 | // Use XORP to simulate FNEG. |
| 355 | setOperationAction(ISD::FNEG , MVT::f64, Custom); |
| 356 | setOperationAction(ISD::FNEG , MVT::f32, Custom); |
| 357 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 358 | // Use ANDPD and ORPD to simulate FCOPYSIGN. |
| 359 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); |
| 360 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); |
| 361 | |
Evan Cheng | d25e9e8 | 2006-02-02 00:28:23 +0000 | [diff] [blame] | 362 | // We don't support sin/cos/fmod |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 363 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 364 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 365 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 366 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 367 | |
Chris Lattner | a54aa94 | 2006-01-29 06:26:08 +0000 | [diff] [blame] | 368 | // Expand FP immediates into loads from the stack, except for the special |
| 369 | // cases we handle. |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 370 | addLegalFPImmediate(APFloat(+0.0)); // xorpd |
| 371 | addLegalFPImmediate(APFloat(+0.0f)); // xorps |
Dale Johannesen | 5411a39 | 2007-08-09 01:04:01 +0000 | [diff] [blame] | 372 | |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 373 | // Floating truncations from f80 and extensions to f80 go through memory. |
| 374 | // If optimizing, we lie about this though and handle it in |
| 375 | // InstructionSelectPreprocess so that dagcombine2 can hack on these. |
| 376 | if (Fast) { |
| 377 | setConvertAction(MVT::f32, MVT::f80, Expand); |
| 378 | setConvertAction(MVT::f64, MVT::f80, Expand); |
| 379 | setConvertAction(MVT::f80, MVT::f32, Expand); |
| 380 | setConvertAction(MVT::f80, MVT::f64, Expand); |
| 381 | } |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 382 | } else if (X86ScalarSSEf32) { |
| 383 | // Use SSE for f32, x87 for f64. |
| 384 | // Set up the FP register classes. |
| 385 | addRegisterClass(MVT::f32, X86::FR32RegisterClass); |
| 386 | addRegisterClass(MVT::f64, X86::RFP64RegisterClass); |
| 387 | |
| 388 | // Use ANDPS to simulate FABS. |
| 389 | setOperationAction(ISD::FABS , MVT::f32, Custom); |
| 390 | |
| 391 | // Use XORP to simulate FNEG. |
| 392 | setOperationAction(ISD::FNEG , MVT::f32, Custom); |
| 393 | |
| 394 | setOperationAction(ISD::UNDEF, MVT::f64, Expand); |
| 395 | |
| 396 | // Use ANDPS and ORPS to simulate FCOPYSIGN. |
| 397 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); |
| 398 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); |
| 399 | |
| 400 | // We don't support sin/cos/fmod |
| 401 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 402 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 403 | |
Nate Begeman | e179584 | 2008-02-14 08:57:00 +0000 | [diff] [blame] | 404 | // Special cases we handle for FP constants. |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 405 | addLegalFPImmediate(APFloat(+0.0f)); // xorps |
| 406 | addLegalFPImmediate(APFloat(+0.0)); // FLD0 |
| 407 | addLegalFPImmediate(APFloat(+1.0)); // FLD1 |
| 408 | addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS |
| 409 | addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS |
| 410 | |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 411 | // SSE <-> X87 conversions go through memory. If optimizing, we lie about |
| 412 | // this though and handle it in InstructionSelectPreprocess so that |
| 413 | // dagcombine2 can hack on these. |
| 414 | if (Fast) { |
| 415 | setConvertAction(MVT::f32, MVT::f64, Expand); |
| 416 | setConvertAction(MVT::f32, MVT::f80, Expand); |
| 417 | setConvertAction(MVT::f80, MVT::f32, Expand); |
| 418 | setConvertAction(MVT::f64, MVT::f32, Expand); |
| 419 | // And x87->x87 truncations also. |
| 420 | setConvertAction(MVT::f80, MVT::f64, Expand); |
| 421 | } |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 422 | |
| 423 | if (!UnsafeFPMath) { |
| 424 | setOperationAction(ISD::FSIN , MVT::f64 , Expand); |
| 425 | setOperationAction(ISD::FCOS , MVT::f64 , Expand); |
| 426 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 427 | } else { |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 428 | // f32 and f64 in x87. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 429 | // Set up the FP register classes. |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 430 | addRegisterClass(MVT::f64, X86::RFP64RegisterClass); |
| 431 | addRegisterClass(MVT::f32, X86::RFP32RegisterClass); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 432 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 433 | setOperationAction(ISD::UNDEF, MVT::f64, Expand); |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 434 | setOperationAction(ISD::UNDEF, MVT::f32, Expand); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 435 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); |
| 436 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); |
Dale Johannesen | 5411a39 | 2007-08-09 01:04:01 +0000 | [diff] [blame] | 437 | |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 438 | // Floating truncations go through memory. If optimizing, we lie about |
| 439 | // this though and handle it in InstructionSelectPreprocess so that |
| 440 | // dagcombine2 can hack on these. |
| 441 | if (Fast) { |
| 442 | setConvertAction(MVT::f80, MVT::f32, Expand); |
| 443 | setConvertAction(MVT::f64, MVT::f32, Expand); |
| 444 | setConvertAction(MVT::f80, MVT::f64, Expand); |
| 445 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 446 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 447 | if (!UnsafeFPMath) { |
| 448 | setOperationAction(ISD::FSIN , MVT::f64 , Expand); |
| 449 | setOperationAction(ISD::FCOS , MVT::f64 , Expand); |
| 450 | } |
Dale Johannesen | f04afdb | 2007-08-30 00:23:21 +0000 | [diff] [blame] | 451 | addLegalFPImmediate(APFloat(+0.0)); // FLD0 |
| 452 | addLegalFPImmediate(APFloat(+1.0)); // FLD1 |
| 453 | addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS |
| 454 | addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 455 | addLegalFPImmediate(APFloat(+0.0f)); // FLD0 |
| 456 | addLegalFPImmediate(APFloat(+1.0f)); // FLD1 |
| 457 | addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS |
| 458 | addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 459 | } |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 460 | |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 461 | // Long double always uses X87. |
| 462 | addRegisterClass(MVT::f80, X86::RFP80RegisterClass); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 463 | setOperationAction(ISD::UNDEF, MVT::f80, Expand); |
| 464 | setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); |
Chris Lattner | 71d07a0 | 2008-01-27 06:19:31 +0000 | [diff] [blame] | 465 | { |
Chris Lattner | 71d07a0 | 2008-01-27 06:19:31 +0000 | [diff] [blame] | 466 | APFloat TmpFlt(+0.0); |
| 467 | TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); |
| 468 | addLegalFPImmediate(TmpFlt); // FLD0 |
| 469 | TmpFlt.changeSign(); |
| 470 | addLegalFPImmediate(TmpFlt); // FLD0/FCHS |
| 471 | APFloat TmpFlt2(+1.0); |
| 472 | TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); |
| 473 | addLegalFPImmediate(TmpFlt2); // FLD1 |
| 474 | TmpFlt2.changeSign(); |
| 475 | addLegalFPImmediate(TmpFlt2); // FLD1/FCHS |
| 476 | } |
| 477 | |
Dale Johannesen | 2f42901 | 2007-09-26 21:10:55 +0000 | [diff] [blame] | 478 | if (!UnsafeFPMath) { |
| 479 | setOperationAction(ISD::FSIN , MVT::f80 , Expand); |
| 480 | setOperationAction(ISD::FCOS , MVT::f80 , Expand); |
| 481 | } |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 482 | |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 483 | // Always use a library call for pow. |
| 484 | setOperationAction(ISD::FPOW , MVT::f32 , Expand); |
| 485 | setOperationAction(ISD::FPOW , MVT::f64 , Expand); |
| 486 | setOperationAction(ISD::FPOW , MVT::f80 , Expand); |
| 487 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 488 | // First set operation action for all vector types to expand. Then we |
| 489 | // will selectively turn on ones that can be effectively codegen'd. |
Dan Gohman | fa0f77d | 2007-05-18 18:44:07 +0000 | [diff] [blame] | 490 | for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; |
| 491 | VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 492 | setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); |
| 493 | setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); |
Evan Cheng | 6bdb3f6 | 2006-10-27 18:49:08 +0000 | [diff] [blame] | 494 | setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); |
Evan Cheng | a72cb0e | 2007-06-29 00:18:15 +0000 | [diff] [blame] | 495 | setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); |
Evan Cheng | 6bdb3f6 | 2006-10-27 18:49:08 +0000 | [diff] [blame] | 496 | setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 497 | setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); |
Evan Cheng | 6bdb3f6 | 2006-10-27 18:49:08 +0000 | [diff] [blame] | 498 | setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); |
| 499 | setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); |
| 500 | setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); |
| 501 | setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); |
| 502 | setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); |
| 503 | setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 504 | setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 505 | setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); |
Chris Lattner | 9b3bd46 | 2006-03-21 20:51:05 +0000 | [diff] [blame] | 506 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 507 | setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 508 | setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand); |
| 509 | setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand); |
| 510 | setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand); |
| 511 | setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand); |
| 512 | setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand); |
| 513 | setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand); |
| 514 | setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand); |
Dan Gohman | 525178c | 2007-10-08 18:33:35 +0000 | [diff] [blame] | 515 | setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 516 | setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); |
| 517 | setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); |
| 518 | setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); |
Dan Gohman | f96e4de | 2007-10-11 23:21:31 +0000 | [diff] [blame] | 519 | setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); |
Dan Gohman | f0d0089 | 2007-10-12 14:09:42 +0000 | [diff] [blame] | 520 | setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); |
| 521 | setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); |
| 522 | setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); |
Dan Gohman | 8908132 | 2007-12-12 22:21:26 +0000 | [diff] [blame] | 523 | setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand); |
| 524 | setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand); |
| 525 | setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand); |
| 526 | setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand); |
| 527 | setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand); |
| 528 | setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand); |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 529 | } |
| 530 | |
Evan Cheng | a88973f | 2006-03-22 19:22:18 +0000 | [diff] [blame] | 531 | if (Subtarget->hasMMX()) { |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 532 | addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); |
| 533 | addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); |
| 534 | addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); |
Bill Wendling | eebc8a1 | 2007-03-26 07:53:08 +0000 | [diff] [blame] | 535 | addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 536 | |
Evan Cheng | d30bf01 | 2006-03-01 01:11:20 +0000 | [diff] [blame] | 537 | // FIXME: add MMX packed arithmetics |
Bill Wendling | bc9bffa | 2007-03-07 05:43:18 +0000 | [diff] [blame] | 538 | |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 539 | setOperationAction(ISD::ADD, MVT::v8i8, Legal); |
| 540 | setOperationAction(ISD::ADD, MVT::v4i16, Legal); |
| 541 | setOperationAction(ISD::ADD, MVT::v2i32, Legal); |
Chris Lattner | 6c284d7 | 2007-04-12 04:14:49 +0000 | [diff] [blame] | 542 | setOperationAction(ISD::ADD, MVT::v1i64, Legal); |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 543 | |
Bill Wendling | c1fb047 | 2007-03-10 09:57:05 +0000 | [diff] [blame] | 544 | setOperationAction(ISD::SUB, MVT::v8i8, Legal); |
| 545 | setOperationAction(ISD::SUB, MVT::v4i16, Legal); |
| 546 | setOperationAction(ISD::SUB, MVT::v2i32, Legal); |
Dale Johannesen | 8d26e59 | 2007-10-30 01:18:38 +0000 | [diff] [blame] | 547 | setOperationAction(ISD::SUB, MVT::v1i64, Legal); |
Bill Wendling | c1fb047 | 2007-03-10 09:57:05 +0000 | [diff] [blame] | 548 | |
Bill Wendling | 74027e9 | 2007-03-15 21:24:36 +0000 | [diff] [blame] | 549 | setOperationAction(ISD::MULHS, MVT::v4i16, Legal); |
| 550 | setOperationAction(ISD::MUL, MVT::v4i16, Legal); |
| 551 | |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 552 | setOperationAction(ISD::AND, MVT::v8i8, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 553 | AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 554 | setOperationAction(ISD::AND, MVT::v4i16, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 555 | AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); |
| 556 | setOperationAction(ISD::AND, MVT::v2i32, Promote); |
| 557 | AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); |
| 558 | setOperationAction(ISD::AND, MVT::v1i64, Legal); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 559 | |
| 560 | setOperationAction(ISD::OR, MVT::v8i8, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 561 | AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 562 | setOperationAction(ISD::OR, MVT::v4i16, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 563 | AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); |
| 564 | setOperationAction(ISD::OR, MVT::v2i32, Promote); |
| 565 | AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); |
| 566 | setOperationAction(ISD::OR, MVT::v1i64, Legal); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 567 | |
| 568 | setOperationAction(ISD::XOR, MVT::v8i8, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 569 | AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 570 | setOperationAction(ISD::XOR, MVT::v4i16, Promote); |
Bill Wendling | ab5b49d | 2007-03-26 08:03:33 +0000 | [diff] [blame] | 571 | AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); |
| 572 | setOperationAction(ISD::XOR, MVT::v2i32, Promote); |
| 573 | AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); |
| 574 | setOperationAction(ISD::XOR, MVT::v1i64, Legal); |
Bill Wendling | 1b7a81d | 2007-03-16 09:44:46 +0000 | [diff] [blame] | 575 | |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 576 | setOperationAction(ISD::LOAD, MVT::v8i8, Promote); |
Bill Wendling | eebc8a1 | 2007-03-26 07:53:08 +0000 | [diff] [blame] | 577 | AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 578 | setOperationAction(ISD::LOAD, MVT::v4i16, Promote); |
Bill Wendling | eebc8a1 | 2007-03-26 07:53:08 +0000 | [diff] [blame] | 579 | AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); |
| 580 | setOperationAction(ISD::LOAD, MVT::v2i32, Promote); |
| 581 | AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); |
| 582 | setOperationAction(ISD::LOAD, MVT::v1i64, Legal); |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 583 | |
Bill Wendling | ccc44ad | 2007-03-27 20:22:40 +0000 | [diff] [blame] | 584 | setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); |
| 585 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); |
| 586 | setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); |
| 587 | setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); |
Bill Wendling | a348c56 | 2007-03-22 18:42:45 +0000 | [diff] [blame] | 588 | |
| 589 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); |
| 590 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); |
| 591 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); |
Bill Wendling | ccc44ad | 2007-03-27 20:22:40 +0000 | [diff] [blame] | 592 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); |
Bill Wendling | 826f36f | 2007-03-28 00:57:11 +0000 | [diff] [blame] | 593 | |
| 594 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); |
| 595 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 596 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 597 | } |
| 598 | |
Evan Cheng | a88973f | 2006-03-22 19:22:18 +0000 | [diff] [blame] | 599 | if (Subtarget->hasSSE1()) { |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 600 | addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); |
| 601 | |
Evan Cheng | 6bdb3f6 | 2006-10-27 18:49:08 +0000 | [diff] [blame] | 602 | setOperationAction(ISD::FADD, MVT::v4f32, Legal); |
| 603 | setOperationAction(ISD::FSUB, MVT::v4f32, Legal); |
| 604 | setOperationAction(ISD::FMUL, MVT::v4f32, Legal); |
| 605 | setOperationAction(ISD::FDIV, MVT::v4f32, Legal); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 606 | setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); |
| 607 | setOperationAction(ISD::FNEG, MVT::v4f32, Custom); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 608 | setOperationAction(ISD::LOAD, MVT::v4f32, Legal); |
| 609 | setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); |
| 610 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 611 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 612 | setOperationAction(ISD::SELECT, MVT::v4f32, Custom); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 613 | } |
| 614 | |
Evan Cheng | a88973f | 2006-03-22 19:22:18 +0000 | [diff] [blame] | 615 | if (Subtarget->hasSSE2()) { |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 616 | addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); |
| 617 | addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); |
| 618 | addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); |
| 619 | addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); |
| 620 | addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); |
| 621 | |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 622 | setOperationAction(ISD::ADD, MVT::v16i8, Legal); |
| 623 | setOperationAction(ISD::ADD, MVT::v8i16, Legal); |
| 624 | setOperationAction(ISD::ADD, MVT::v4i32, Legal); |
Evan Cheng | 37e8856 | 2007-03-12 22:58:52 +0000 | [diff] [blame] | 625 | setOperationAction(ISD::ADD, MVT::v2i64, Legal); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 626 | setOperationAction(ISD::SUB, MVT::v16i8, Legal); |
| 627 | setOperationAction(ISD::SUB, MVT::v8i16, Legal); |
| 628 | setOperationAction(ISD::SUB, MVT::v4i32, Legal); |
Evan Cheng | 37e8856 | 2007-03-12 22:58:52 +0000 | [diff] [blame] | 629 | setOperationAction(ISD::SUB, MVT::v2i64, Legal); |
Evan Cheng | f998984 | 2006-04-13 05:10:25 +0000 | [diff] [blame] | 630 | setOperationAction(ISD::MUL, MVT::v8i16, Legal); |
Evan Cheng | 6bdb3f6 | 2006-10-27 18:49:08 +0000 | [diff] [blame] | 631 | setOperationAction(ISD::FADD, MVT::v2f64, Legal); |
| 632 | setOperationAction(ISD::FSUB, MVT::v2f64, Legal); |
| 633 | setOperationAction(ISD::FMUL, MVT::v2f64, Legal); |
| 634 | setOperationAction(ISD::FDIV, MVT::v2f64, Legal); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 635 | setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); |
| 636 | setOperationAction(ISD::FNEG, MVT::v2f64, Custom); |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 637 | |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 638 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); |
| 639 | setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 640 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); |
Evan Cheng | 5edb8d2 | 2006-04-17 22:04:06 +0000 | [diff] [blame] | 641 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); |
Evan Cheng | 5edb8d2 | 2006-04-17 22:04:06 +0000 | [diff] [blame] | 642 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 643 | |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 644 | // Custom lower build_vector, vector_shuffle, and extract_vector_elt. |
| 645 | for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { |
Nate Begeman | 844e0f9 | 2007-12-11 01:41:33 +0000 | [diff] [blame] | 646 | // Do not attempt to custom lower non-power-of-2 vectors |
| 647 | if (!isPowerOf2_32(MVT::getVectorNumElements(VT))) |
| 648 | continue; |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 649 | setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); |
| 650 | setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); |
| 651 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); |
| 652 | } |
| 653 | setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); |
| 654 | setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); |
| 655 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); |
| 656 | setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); |
Nate Begeman | cdd1eec | 2008-02-12 22:51:28 +0000 | [diff] [blame] | 657 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 658 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); |
Nate Begeman | cdd1eec | 2008-02-12 22:51:28 +0000 | [diff] [blame] | 659 | if (Subtarget->is64Bit()) { |
| 660 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); |
Dale Johannesen | 25f1d08 | 2007-10-31 00:32:36 +0000 | [diff] [blame] | 661 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); |
Nate Begeman | cdd1eec | 2008-02-12 22:51:28 +0000 | [diff] [blame] | 662 | } |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 663 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 664 | // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 665 | for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { |
| 666 | setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); |
| 667 | AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); |
| 668 | setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); |
| 669 | AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); |
| 670 | setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); |
| 671 | AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); |
Evan Cheng | 91b740d | 2006-04-12 17:12:36 +0000 | [diff] [blame] | 672 | setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); |
| 673 | AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 674 | setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); |
| 675 | AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 676 | } |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 677 | |
Chris Lattner | ddf8956 | 2008-01-17 19:59:44 +0000 | [diff] [blame] | 678 | setTruncStoreAction(MVT::f64, MVT::f32, Expand); |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 679 | |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 680 | // Custom lower v2i64 and v2f64 selects. |
| 681 | setOperationAction(ISD::LOAD, MVT::v2f64, Legal); |
Evan Cheng | 91b740d | 2006-04-12 17:12:36 +0000 | [diff] [blame] | 682 | setOperationAction(ISD::LOAD, MVT::v2i64, Legal); |
Evan Cheng | f7c378e | 2006-04-10 07:23:14 +0000 | [diff] [blame] | 683 | setOperationAction(ISD::SELECT, MVT::v2f64, Custom); |
Evan Cheng | 2c3ae37 | 2006-04-12 21:21:57 +0000 | [diff] [blame] | 684 | setOperationAction(ISD::SELECT, MVT::v2i64, Custom); |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 685 | } |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 686 | |
| 687 | if (Subtarget->hasSSE41()) { |
| 688 | // FIXME: Do we need to handle scalar-to-vector here? |
| 689 | setOperationAction(ISD::MUL, MVT::v4i32, Legal); |
| 690 | |
| 691 | // i8 and i16 vectors are custom , because the source register and source |
| 692 | // source memory operand types are not the same width. f32 vectors are |
| 693 | // custom since the immediate controlling the insert encodes additional |
| 694 | // information. |
| 695 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); |
| 696 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); |
| 697 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); |
| 698 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); |
| 699 | |
| 700 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); |
| 701 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); |
| 702 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 703 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 704 | |
| 705 | if (Subtarget->is64Bit()) { |
Nate Begeman | cdd1eec | 2008-02-12 22:51:28 +0000 | [diff] [blame] | 706 | setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); |
| 707 | setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 708 | } |
| 709 | } |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 710 | |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 711 | // We want to custom lower some of our intrinsics. |
| 712 | setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); |
| 713 | |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 714 | // We have target-specific dag combine patterns for the following nodes: |
| 715 | setTargetDAGCombine(ISD::VECTOR_SHUFFLE); |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 716 | setTargetDAGCombine(ISD::SELECT); |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 717 | setTargetDAGCombine(ISD::STORE); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 718 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 719 | computeRegisterProperties(); |
| 720 | |
Evan Cheng | 87ed716 | 2006-02-14 08:25:08 +0000 | [diff] [blame] | 721 | // FIXME: These should be based on subtarget info. Plus, the values should |
| 722 | // be smaller when we are in optimizing for size mode. |
Evan Cheng | a03a5dc | 2006-02-14 08:38:30 +0000 | [diff] [blame] | 723 | maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores |
| 724 | maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores |
| 725 | maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 726 | allowUnalignedMemoryAccesses = true; // x86 supports it! |
Evan Cheng | fb8075d | 2008-02-28 00:43:03 +0000 | [diff] [blame] | 727 | setPrefLoopAlignment(16); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 728 | } |
| 729 | |
Scott Michel | 5b8f82e | 2008-03-10 15:42:14 +0000 | [diff] [blame] | 730 | |
| 731 | MVT::ValueType |
| 732 | X86TargetLowering::getSetCCResultType(const SDOperand &) const { |
| 733 | return MVT::i8; |
| 734 | } |
| 735 | |
| 736 | |
Evan Cheng | 2928650 | 2008-01-23 23:17:41 +0000 | [diff] [blame] | 737 | /// getMaxByValAlign - Helper for getByValTypeAlignment to determine |
| 738 | /// the desired ByVal argument alignment. |
| 739 | static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { |
| 740 | if (MaxAlign == 16) |
| 741 | return; |
| 742 | if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { |
| 743 | if (VTy->getBitWidth() == 128) |
| 744 | MaxAlign = 16; |
Evan Cheng | 2928650 | 2008-01-23 23:17:41 +0000 | [diff] [blame] | 745 | } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { |
| 746 | unsigned EltAlign = 0; |
| 747 | getMaxByValAlign(ATy->getElementType(), EltAlign); |
| 748 | if (EltAlign > MaxAlign) |
| 749 | MaxAlign = EltAlign; |
| 750 | } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { |
| 751 | for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { |
| 752 | unsigned EltAlign = 0; |
| 753 | getMaxByValAlign(STy->getElementType(i), EltAlign); |
| 754 | if (EltAlign > MaxAlign) |
| 755 | MaxAlign = EltAlign; |
| 756 | if (MaxAlign == 16) |
| 757 | break; |
| 758 | } |
| 759 | } |
| 760 | return; |
| 761 | } |
| 762 | |
| 763 | /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate |
| 764 | /// function arguments in the caller parameter area. For X86, aggregates |
Dale Johannesen | 0c19187 | 2008-02-08 19:48:20 +0000 | [diff] [blame] | 765 | /// that contain SSE vectors are placed at 16-byte boundaries while the rest |
| 766 | /// are at 4-byte boundaries. |
Evan Cheng | 2928650 | 2008-01-23 23:17:41 +0000 | [diff] [blame] | 767 | unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { |
| 768 | if (Subtarget->is64Bit()) |
| 769 | return getTargetData()->getABITypeAlignment(Ty); |
| 770 | unsigned Align = 4; |
Dale Johannesen | 0c19187 | 2008-02-08 19:48:20 +0000 | [diff] [blame] | 771 | if (Subtarget->hasSSE1()) |
| 772 | getMaxByValAlign(Ty, Align); |
Evan Cheng | 2928650 | 2008-01-23 23:17:41 +0000 | [diff] [blame] | 773 | return Align; |
| 774 | } |
Chris Lattner | 2b02a44 | 2007-02-25 08:29:00 +0000 | [diff] [blame] | 775 | |
Evan Cheng | cc41586 | 2007-11-09 01:32:10 +0000 | [diff] [blame] | 776 | /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC |
| 777 | /// jumptable. |
| 778 | SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table, |
| 779 | SelectionDAG &DAG) const { |
| 780 | if (usesGlobalOffsetTable()) |
| 781 | return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); |
| 782 | if (!Subtarget->isPICStyleRIPRel()) |
| 783 | return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()); |
| 784 | return Table; |
| 785 | } |
| 786 | |
Chris Lattner | 2b02a44 | 2007-02-25 08:29:00 +0000 | [diff] [blame] | 787 | //===----------------------------------------------------------------------===// |
| 788 | // Return Value Calling Convention Implementation |
| 789 | //===----------------------------------------------------------------------===// |
| 790 | |
Chris Lattner | 59ed56b | 2007-02-28 04:55:35 +0000 | [diff] [blame] | 791 | #include "X86GenCallingConv.inc" |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 792 | |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 793 | /// LowerRET - Lower an ISD::RET node. |
| 794 | SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { |
| 795 | assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); |
| 796 | |
Chris Lattner | 9774c91 | 2007-02-27 05:28:59 +0000 | [diff] [blame] | 797 | SmallVector<CCValAssign, 16> RVLocs; |
| 798 | unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); |
Chris Lattner | 52387be | 2007-06-19 00:13:10 +0000 | [diff] [blame] | 799 | bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); |
| 800 | CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); |
Chris Lattner | e32bbf6 | 2007-02-28 07:09:55 +0000 | [diff] [blame] | 801 | CCInfo.AnalyzeReturn(Op.Val, RetCC_X86); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 802 | |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 803 | // If this is the first return lowered for this function, add the regs to the |
| 804 | // liveout set for the function. |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 805 | if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { |
Chris Lattner | 9774c91 | 2007-02-27 05:28:59 +0000 | [diff] [blame] | 806 | for (unsigned i = 0; i != RVLocs.size(); ++i) |
| 807 | if (RVLocs[i].isRegLoc()) |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 808 | DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 809 | } |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 810 | SDOperand Chain = Op.getOperand(0); |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 811 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 812 | // Handle tail call return. |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 813 | Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 814 | if (Chain.getOpcode() == X86ISD::TAILCALL) { |
| 815 | SDOperand TailCall = Chain; |
| 816 | SDOperand TargetAddress = TailCall.getOperand(1); |
| 817 | SDOperand StackAdjustment = TailCall.getOperand(2); |
Chris Lattner | b4a6eaa | 2008-01-16 05:52:18 +0000 | [diff] [blame] | 818 | assert(((TargetAddress.getOpcode() == ISD::Register && |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 819 | (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX || |
| 820 | cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || |
| 821 | TargetAddress.getOpcode() == ISD::TargetExternalSymbol || |
| 822 | TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && |
| 823 | "Expecting an global address, external symbol, or register"); |
Chris Lattner | b4a6eaa | 2008-01-16 05:52:18 +0000 | [diff] [blame] | 824 | assert(StackAdjustment.getOpcode() == ISD::Constant && |
| 825 | "Expecting a const value"); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 826 | |
| 827 | SmallVector<SDOperand,8> Operands; |
| 828 | Operands.push_back(Chain.getOperand(0)); |
| 829 | Operands.push_back(TargetAddress); |
| 830 | Operands.push_back(StackAdjustment); |
| 831 | // Copy registers used by the call. Last operand is a flag so it is not |
| 832 | // copied. |
Arnold Schwaighofer | 448175f | 2007-10-16 09:05:00 +0000 | [diff] [blame] | 833 | for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 834 | Operands.push_back(Chain.getOperand(i)); |
| 835 | } |
Arnold Schwaighofer | 448175f | 2007-10-16 09:05:00 +0000 | [diff] [blame] | 836 | return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], |
| 837 | Operands.size()); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 838 | } |
| 839 | |
| 840 | // Regular return. |
| 841 | SDOperand Flag; |
| 842 | |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 843 | SmallVector<SDOperand, 6> RetOps; |
| 844 | RetOps.push_back(Chain); // Operand #0 = Chain (updated below) |
| 845 | // Operand #1 = Bytes To Pop |
| 846 | RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); |
| 847 | |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 848 | // Copy the result values into the output registers. |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 849 | for (unsigned i = 0; i != RVLocs.size(); ++i) { |
| 850 | CCValAssign &VA = RVLocs[i]; |
| 851 | assert(VA.isRegLoc() && "Can only return in registers!"); |
| 852 | SDOperand ValToCopy = Op.getOperand(i*2+1); |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 853 | |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 854 | // Returns in ST0/ST1 are handled specially: these are pushed as operands to |
| 855 | // the RET instruction and handled by the FP Stackifier. |
| 856 | if (RVLocs[i].getLocReg() == X86::ST0 || |
| 857 | RVLocs[i].getLocReg() == X86::ST1) { |
| 858 | // If this is a copy from an xmm register to ST(0), use an FPExtend to |
| 859 | // change the value to the FP stack register class. |
| 860 | if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) |
| 861 | ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); |
| 862 | RetOps.push_back(ValToCopy); |
| 863 | // Don't emit a copytoreg. |
| 864 | continue; |
| 865 | } |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 866 | |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 867 | Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 868 | Flag = Chain.getValue(1); |
| 869 | } |
Dan Gohman | 61a9213 | 2008-04-21 23:59:07 +0000 | [diff] [blame] | 870 | |
| 871 | // The x86-64 ABI for returning structs by value requires that we copy |
| 872 | // the sret argument into %rax for the return. We saved the argument into |
| 873 | // a virtual register in the entry block, so now we copy the value out |
| 874 | // and into %rax. |
| 875 | if (Subtarget->is64Bit() && |
| 876 | DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { |
| 877 | MachineFunction &MF = DAG.getMachineFunction(); |
| 878 | X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); |
| 879 | unsigned Reg = FuncInfo->getSRetReturnReg(); |
| 880 | if (!Reg) { |
| 881 | Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); |
| 882 | FuncInfo->setSRetReturnReg(Reg); |
| 883 | } |
| 884 | SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); |
| 885 | |
| 886 | Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); |
| 887 | Flag = Chain.getValue(1); |
| 888 | } |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 889 | |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 890 | RetOps[0] = Chain; // Update chain. |
| 891 | |
| 892 | // Add the flag if we have it. |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 893 | if (Flag.Val) |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 894 | RetOps.push_back(Flag); |
| 895 | |
| 896 | return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); |
Chris Lattner | 2a9bdd7 | 2007-02-25 09:12:39 +0000 | [diff] [blame] | 897 | } |
| 898 | |
| 899 | |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 900 | /// LowerCallResult - Lower the result values of an ISD::CALL into the |
| 901 | /// appropriate copies out of appropriate physical registers. This assumes that |
| 902 | /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call |
| 903 | /// being lowered. The returns a SDNode with the same number of values as the |
| 904 | /// ISD::CALL. |
| 905 | SDNode *X86TargetLowering:: |
| 906 | LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, |
| 907 | unsigned CallingConv, SelectionDAG &DAG) { |
Chris Lattner | e32bbf6 | 2007-02-28 07:09:55 +0000 | [diff] [blame] | 908 | |
| 909 | // Assign locations to each value returned by this call. |
Chris Lattner | 9774c91 | 2007-02-27 05:28:59 +0000 | [diff] [blame] | 910 | SmallVector<CCValAssign, 16> RVLocs; |
Chris Lattner | 52387be | 2007-06-19 00:13:10 +0000 | [diff] [blame] | 911 | bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; |
| 912 | CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); |
Chris Lattner | e32bbf6 | 2007-02-28 07:09:55 +0000 | [diff] [blame] | 913 | CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); |
| 914 | |
Chris Lattner | e32bbf6 | 2007-02-28 07:09:55 +0000 | [diff] [blame] | 915 | SmallVector<SDOperand, 8> ResultVals; |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 916 | |
| 917 | // Copy all of the result registers out of their specified physreg. |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 918 | for (unsigned i = 0; i != RVLocs.size(); ++i) { |
| 919 | MVT::ValueType CopyVT = RVLocs[i].getValVT(); |
| 920 | |
| 921 | // If this is a call to a function that returns an fp value on the floating |
| 922 | // point stack, but where we prefer to use the value in xmm registers, copy |
| 923 | // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. |
| 924 | if (RVLocs[i].getLocReg() == X86::ST0 && |
| 925 | isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { |
| 926 | CopyVT = MVT::f80; |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 927 | } |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 928 | |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 929 | Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), |
| 930 | CopyVT, InFlag).getValue(1); |
| 931 | SDOperand Val = Chain.getValue(0); |
| 932 | InFlag = Chain.getValue(2); |
Chris Lattner | 112dedc | 2007-12-29 06:41:28 +0000 | [diff] [blame] | 933 | |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 934 | if (CopyVT != RVLocs[i].getValVT()) { |
| 935 | // Round the F80 the right size, which also moves to the appropriate xmm |
| 936 | // register. |
| 937 | Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, |
| 938 | // This truncation won't change the value. |
| 939 | DAG.getIntPtrConstant(1)); |
| 940 | } |
Chris Lattner | d43d00c | 2008-01-24 08:07:48 +0000 | [diff] [blame] | 941 | |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 942 | ResultVals.push_back(Val); |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 943 | } |
| 944 | |
| 945 | // Merge everything together with a MERGE_VALUES node. |
| 946 | ResultVals.push_back(Chain); |
| 947 | return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), |
| 948 | &ResultVals[0], ResultVals.size()).Val; |
Chris Lattner | 2b02a44 | 2007-02-25 08:29:00 +0000 | [diff] [blame] | 949 | } |
| 950 | |
| 951 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 952 | //===----------------------------------------------------------------------===// |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 953 | // C & StdCall & Fast Calling Convention implementation |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 954 | //===----------------------------------------------------------------------===// |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 955 | // StdCall calling convention seems to be standard for many Windows' API |
| 956 | // routines and around. It differs from C calling convention just a little: |
| 957 | // callee should clean up the stack, not caller. Symbols should be also |
| 958 | // decorated in some fancy way :) It doesn't support any vector arguments. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 959 | // For info on fast calling convention see Fast Calling Convention (tail call) |
| 960 | // implementation LowerX86_32FastCCCallTo. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 961 | |
Evan Cheng | 85e3800 | 2006-04-27 05:35:28 +0000 | [diff] [blame] | 962 | /// AddLiveIn - This helper function adds the specified physical register to the |
| 963 | /// MachineFunction as a live in value. It also creates a corresponding virtual |
| 964 | /// register for it. |
| 965 | static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 966 | const TargetRegisterClass *RC) { |
Evan Cheng | 85e3800 | 2006-04-27 05:35:28 +0000 | [diff] [blame] | 967 | assert(RC->contains(PReg) && "Not the correct regclass!"); |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 968 | unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); |
| 969 | MF.getRegInfo().addLiveIn(PReg, VReg); |
Evan Cheng | 85e3800 | 2006-04-27 05:35:28 +0000 | [diff] [blame] | 970 | return VReg; |
| 971 | } |
| 972 | |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 973 | /// CallIsStructReturn - Determines whether a CALL node uses struct return |
| 974 | /// semantics. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 975 | static bool CallIsStructReturn(SDOperand Op) { |
| 976 | unsigned NumOps = (Op.getNumOperands() - 5) / 2; |
| 977 | if (!NumOps) |
| 978 | return false; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 979 | |
| 980 | return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 981 | } |
| 982 | |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 983 | /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct |
| 984 | /// return semantics. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 985 | static bool ArgsAreStructReturn(SDOperand Op) { |
| 986 | unsigned NumArgs = Op.Val->getNumValues() - 1; |
| 987 | if (!NumArgs) |
| 988 | return false; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 989 | |
| 990 | return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 991 | } |
| 992 | |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 993 | /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires |
| 994 | /// the callee to pop its own arguments. Callee pop is necessary to support tail |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 995 | /// calls. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 996 | bool X86TargetLowering::IsCalleePop(SDOperand Op) { |
| 997 | bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
| 998 | if (IsVarArg) |
| 999 | return false; |
| 1000 | |
| 1001 | switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { |
| 1002 | default: |
| 1003 | return false; |
| 1004 | case CallingConv::X86_StdCall: |
| 1005 | return !Subtarget->is64Bit(); |
| 1006 | case CallingConv::X86_FastCall: |
| 1007 | return !Subtarget->is64Bit(); |
| 1008 | case CallingConv::Fast: |
| 1009 | return PerformTailCallOpt; |
| 1010 | } |
| 1011 | } |
| 1012 | |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 1013 | /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or |
| 1014 | /// FORMAL_ARGUMENTS node. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1015 | CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const { |
| 1016 | unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 1017 | |
Anton Korobeynikov | 7c1c261 | 2008-02-20 11:22:39 +0000 | [diff] [blame] | 1018 | if (Subtarget->is64Bit()) { |
Anton Korobeynikov | 1a979d9 | 2008-03-22 20:57:27 +0000 | [diff] [blame] | 1019 | if (Subtarget->isTargetWin64()) |
Anton Korobeynikov | 8f88cb0 | 2008-03-22 20:37:30 +0000 | [diff] [blame] | 1020 | return CC_X86_Win64_C; |
| 1021 | else { |
| 1022 | if (CC == CallingConv::Fast && PerformTailCallOpt) |
| 1023 | return CC_X86_64_TailCall; |
| 1024 | else |
| 1025 | return CC_X86_64_C; |
| 1026 | } |
Anton Korobeynikov | 7c1c261 | 2008-02-20 11:22:39 +0000 | [diff] [blame] | 1027 | } |
| 1028 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1029 | if (CC == CallingConv::X86_FastCall) |
| 1030 | return CC_X86_32_FastCall; |
| 1031 | else if (CC == CallingConv::Fast && PerformTailCallOpt) |
| 1032 | return CC_X86_32_TailCall; |
| 1033 | else |
| 1034 | return CC_X86_32_C; |
| 1035 | } |
| 1036 | |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 1037 | /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to |
| 1038 | /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1039 | NameDecorationStyle |
| 1040 | X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) { |
| 1041 | unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 1042 | if (CC == CallingConv::X86_FastCall) |
| 1043 | return FastCall; |
| 1044 | else if (CC == CallingConv::X86_StdCall) |
| 1045 | return StdCall; |
| 1046 | return None; |
| 1047 | } |
| 1048 | |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1049 | |
Arnold Schwaighofer | 258bb1b | 2008-02-26 22:21:54 +0000 | [diff] [blame] | 1050 | /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer |
| 1051 | /// in a register before calling. |
| 1052 | bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { |
| 1053 | return !IsTailCall && !Is64Bit && |
| 1054 | getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 1055 | Subtarget->isPICStyleGOT(); |
| 1056 | } |
| 1057 | |
Arnold Schwaighofer | 258bb1b | 2008-02-26 22:21:54 +0000 | [diff] [blame] | 1058 | /// CallRequiresFnAddressInReg - Check whether the call requires the function |
| 1059 | /// address to be loaded in a register. |
| 1060 | bool |
| 1061 | X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { |
| 1062 | return !Is64Bit && IsTailCall && |
| 1063 | getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 1064 | Subtarget->isPICStyleGOT(); |
| 1065 | } |
| 1066 | |
Arnold Schwaighofer | 16a3e52 | 2008-02-26 17:50:59 +0000 | [diff] [blame] | 1067 | /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified |
| 1068 | /// by "Src" to address "Dst" with size and alignment information specified by |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1069 | /// the specific parameter attribute. The copy will be passed as a byval |
| 1070 | /// function parameter. |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1071 | static SDOperand |
Evan Cheng | 8e5712b | 2008-01-12 01:08:07 +0000 | [diff] [blame] | 1072 | CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1073 | ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1074 | SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 1075 | return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1076 | /*AlwaysInline=*/true, NULL, 0, NULL, 0); |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1077 | } |
| 1078 | |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1079 | SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG, |
| 1080 | const CCValAssign &VA, |
| 1081 | MachineFrameInfo *MFI, |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1082 | unsigned CC, |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1083 | SDOperand Root, unsigned i) { |
| 1084 | // Create the nodes corresponding to a load from this parameter slot. |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1085 | ISD::ArgFlagsTy Flags = |
| 1086 | cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1087 | bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1088 | bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); |
Evan Cheng | e70bb59 | 2008-01-10 02:24:25 +0000 | [diff] [blame] | 1089 | |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1090 | // FIXME: For now, all byval parameter objects are marked mutable. This can be |
| 1091 | // changed with more analysis. |
| 1092 | // In case of tail call optimization mark all arguments mutable. Since they |
| 1093 | // could be overwritten by lowering of arguments in case of a tail call. |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1094 | int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1095 | VA.getLocMemOffset(), isImmutable); |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1096 | SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1097 | if (Flags.isByVal()) |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1098 | return FIN; |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1099 | return DAG.getLoad(VA.getValVT(), Root, FIN, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 1100 | PseudoSourceValue::getFixedStack(), FI); |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 1101 | } |
| 1102 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1103 | SDOperand |
| 1104 | X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1105 | MachineFunction &MF = DAG.getMachineFunction(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1106 | X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); |
| 1107 | |
| 1108 | const Function* Fn = MF.getFunction(); |
| 1109 | if (Fn->hasExternalLinkage() && |
| 1110 | Subtarget->isTargetCygMing() && |
| 1111 | Fn->getName() == "main") |
| 1112 | FuncInfo->setForceFramePointer(true); |
| 1113 | |
| 1114 | // Decorate the function name. |
| 1115 | FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); |
| 1116 | |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1117 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Evan Cheng | 25caf63 | 2006-05-23 21:06:34 +0000 | [diff] [blame] | 1118 | SDOperand Root = Op.getOperand(0); |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1119 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1120 | unsigned CC = MF.getFunction()->getCallingConv(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1121 | bool Is64Bit = Subtarget->is64Bit(); |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1122 | bool IsWin64 = Subtarget->isTargetWin64(); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1123 | |
| 1124 | assert(!(isVarArg && CC == CallingConv::Fast) && |
| 1125 | "Var args not supported with calling convention fastcc"); |
| 1126 | |
Chris Lattner | 638402b | 2007-02-28 07:00:42 +0000 | [diff] [blame] | 1127 | // Assign locations to all of the incoming arguments. |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1128 | SmallVector<CCValAssign, 16> ArgLocs; |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1129 | CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1130 | CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op)); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1131 | |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1132 | SmallVector<SDOperand, 8> ArgValues; |
| 1133 | unsigned LastVal = ~0U; |
| 1134 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
| 1135 | CCValAssign &VA = ArgLocs[i]; |
| 1136 | // TODO: If an arg is passed in two places (e.g. reg and stack), skip later |
| 1137 | // places. |
| 1138 | assert(VA.getValNo() != LastVal && |
| 1139 | "Don't support value assigned to multiple locs yet"); |
| 1140 | LastVal = VA.getValNo(); |
| 1141 | |
| 1142 | if (VA.isRegLoc()) { |
| 1143 | MVT::ValueType RegVT = VA.getLocVT(); |
| 1144 | TargetRegisterClass *RC; |
| 1145 | if (RegVT == MVT::i32) |
| 1146 | RC = X86::GR32RegisterClass; |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1147 | else if (Is64Bit && RegVT == MVT::i64) |
| 1148 | RC = X86::GR64RegisterClass; |
Dale Johannesen | e672af1 | 2008-02-05 20:46:33 +0000 | [diff] [blame] | 1149 | else if (RegVT == MVT::f32) |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1150 | RC = X86::FR32RegisterClass; |
Dale Johannesen | e672af1 | 2008-02-05 20:46:33 +0000 | [diff] [blame] | 1151 | else if (RegVT == MVT::f64) |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1152 | RC = X86::FR64RegisterClass; |
Evan Cheng | ee472b1 | 2008-04-25 07:56:45 +0000 | [diff] [blame] | 1153 | else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128) |
| 1154 | RC = X86::VR128RegisterClass; |
| 1155 | else if (MVT::isVector(RegVT)) { |
| 1156 | assert(MVT::getSizeInBits(RegVT) == 64); |
| 1157 | if (!Is64Bit) |
| 1158 | RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. |
| 1159 | else { |
| 1160 | // Darwin calling convention passes MMX values in either GPRs or |
| 1161 | // XMMs in x86-64. Other targets pass them in memory. |
| 1162 | if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { |
| 1163 | RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. |
| 1164 | RegVT = MVT::v2i64; |
| 1165 | } else { |
| 1166 | RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. |
| 1167 | RegVT = MVT::i64; |
| 1168 | } |
| 1169 | } |
| 1170 | } else { |
| 1171 | assert(0 && "Unknown argument type!"); |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1172 | } |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1173 | |
Chris Lattner | 82932a5 | 2007-03-02 05:12:29 +0000 | [diff] [blame] | 1174 | unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); |
| 1175 | SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1176 | |
| 1177 | // If this is an 8 or 16-bit value, it is really passed promoted to 32 |
| 1178 | // bits. Insert an assert[sz]ext to capture this, then truncate to the |
| 1179 | // right size. |
| 1180 | if (VA.getLocInfo() == CCValAssign::SExt) |
| 1181 | ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, |
| 1182 | DAG.getValueType(VA.getValVT())); |
| 1183 | else if (VA.getLocInfo() == CCValAssign::ZExt) |
| 1184 | ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, |
| 1185 | DAG.getValueType(VA.getValVT())); |
| 1186 | |
| 1187 | if (VA.getLocInfo() != CCValAssign::Full) |
| 1188 | ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); |
| 1189 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1190 | // Handle MMX values passed in GPRs. |
Evan Cheng | 44c0fd1 | 2008-04-25 20:13:28 +0000 | [diff] [blame] | 1191 | if (Is64Bit && RegVT != VA.getLocVT()) { |
| 1192 | if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass) |
| 1193 | ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); |
| 1194 | else if (RC == X86::VR128RegisterClass) { |
| 1195 | ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, |
| 1196 | DAG.getConstant(0, MVT::i64)); |
| 1197 | ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); |
| 1198 | } |
| 1199 | } |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1200 | |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1201 | ArgValues.push_back(ArgValue); |
| 1202 | } else { |
| 1203 | assert(VA.isMemLoc()); |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1204 | ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1205 | } |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1206 | } |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1207 | |
Dan Gohman | 61a9213 | 2008-04-21 23:59:07 +0000 | [diff] [blame] | 1208 | // The x86-64 ABI for returning structs by value requires that we copy |
| 1209 | // the sret argument into %rax for the return. Save the argument into |
| 1210 | // a virtual register so that we can access it from the return points. |
| 1211 | if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { |
| 1212 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1213 | X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); |
| 1214 | unsigned Reg = FuncInfo->getSRetReturnReg(); |
| 1215 | if (!Reg) { |
| 1216 | Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); |
| 1217 | FuncInfo->setSRetReturnReg(Reg); |
| 1218 | } |
| 1219 | SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); |
| 1220 | Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); |
| 1221 | } |
| 1222 | |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1223 | unsigned StackSize = CCInfo.getNextStackOffset(); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1224 | // align stack specially for tail calls |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1225 | if (CC == CallingConv::Fast) |
| 1226 | StackSize = GetAlignedArgumentStackSize(StackSize, DAG); |
Evan Cheng | 25caf63 | 2006-05-23 21:06:34 +0000 | [diff] [blame] | 1227 | |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1228 | // If the function takes variable number of arguments, make a frame index for |
| 1229 | // the start of the first vararg value... for expansion of llvm.va_start. |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1230 | if (isVarArg) { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1231 | if (Is64Bit || CC != CallingConv::X86_FastCall) { |
| 1232 | VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); |
| 1233 | } |
| 1234 | if (Is64Bit) { |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1235 | unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; |
| 1236 | |
| 1237 | // FIXME: We should really autogenerate these arrays |
| 1238 | static const unsigned GPR64ArgRegsWin64[] = { |
| 1239 | X86::RCX, X86::RDX, X86::R8, X86::R9 |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1240 | }; |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1241 | static const unsigned XMMArgRegsWin64[] = { |
| 1242 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 |
| 1243 | }; |
| 1244 | static const unsigned GPR64ArgRegs64Bit[] = { |
| 1245 | X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 |
| 1246 | }; |
| 1247 | static const unsigned XMMArgRegs64Bit[] = { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1248 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, |
| 1249 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
| 1250 | }; |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1251 | const unsigned *GPR64ArgRegs, *XMMArgRegs; |
| 1252 | |
| 1253 | if (IsWin64) { |
| 1254 | TotalNumIntRegs = 4; TotalNumXMMRegs = 4; |
| 1255 | GPR64ArgRegs = GPR64ArgRegsWin64; |
| 1256 | XMMArgRegs = XMMArgRegsWin64; |
| 1257 | } else { |
| 1258 | TotalNumIntRegs = 6; TotalNumXMMRegs = 8; |
| 1259 | GPR64ArgRegs = GPR64ArgRegs64Bit; |
| 1260 | XMMArgRegs = XMMArgRegs64Bit; |
| 1261 | } |
| 1262 | unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, |
| 1263 | TotalNumIntRegs); |
| 1264 | unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, |
| 1265 | TotalNumXMMRegs); |
| 1266 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1267 | // For X86-64, if there are vararg parameters that are passed via |
| 1268 | // registers, then we must store them to their spots on the stack so they |
| 1269 | // may be loaded by deferencing the result of va_next. |
| 1270 | VarArgsGPOffset = NumIntRegs * 8; |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1271 | VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; |
| 1272 | RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + |
| 1273 | TotalNumXMMRegs * 16, 16); |
| 1274 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1275 | // Store the integer parameter registers. |
| 1276 | SmallVector<SDOperand, 8> MemOps; |
| 1277 | SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); |
| 1278 | SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1279 | DAG.getIntPtrConstant(VarArgsGPOffset)); |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1280 | for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1281 | unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], |
| 1282 | X86::GR64RegisterClass); |
| 1283 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1284 | SDOperand Store = |
| 1285 | DAG.getStore(Val.getValue(1), Val, FIN, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 1286 | PseudoSourceValue::getFixedStack(), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1287 | RegSaveFrameIndex); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1288 | MemOps.push_back(Store); |
| 1289 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1290 | DAG.getIntPtrConstant(8)); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1291 | } |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1292 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1293 | // Now store the XMM (fp + vector) parameter registers. |
| 1294 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1295 | DAG.getIntPtrConstant(VarArgsFPOffset)); |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1296 | for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1297 | unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], |
| 1298 | X86::VR128RegisterClass); |
| 1299 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1300 | SDOperand Store = |
| 1301 | DAG.getStore(Val.getValue(1), Val, FIN, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 1302 | PseudoSourceValue::getFixedStack(), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1303 | RegSaveFrameIndex); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1304 | MemOps.push_back(Store); |
| 1305 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1306 | DAG.getIntPtrConstant(16)); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1307 | } |
| 1308 | if (!MemOps.empty()) |
| 1309 | Root = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 1310 | &MemOps[0], MemOps.size()); |
| 1311 | } |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1312 | } |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1313 | |
| 1314 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 1315 | // arguments and the arguments after the retaddr has been pushed are |
| 1316 | // aligned. |
| 1317 | if (!Is64Bit && CC == CallingConv::X86_FastCall && |
| 1318 | !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && |
| 1319 | (StackSize & 7) == 0) |
| 1320 | StackSize += 4; |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1321 | |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1322 | ArgValues.push_back(Root); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1323 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1324 | // Some CCs need callee pop. |
| 1325 | if (IsCalleePop(Op)) { |
| 1326 | BytesToPopOnReturn = StackSize; // Callee pops everything. |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1327 | BytesCallerReserves = 0; |
| 1328 | } else { |
Anton Korobeynikov | 1d9bacc | 2007-03-06 08:12:33 +0000 | [diff] [blame] | 1329 | BytesToPopOnReturn = 0; // Callee pops nothing. |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1330 | // If this is an sret function, the return should pop the hidden pointer. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1331 | if (!Is64Bit && ArgsAreStructReturn(Op)) |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1332 | BytesToPopOnReturn = 4; |
Chris Lattner | f39f771 | 2007-02-28 05:46:49 +0000 | [diff] [blame] | 1333 | BytesCallerReserves = StackSize; |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1334 | } |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1335 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1336 | if (!Is64Bit) { |
| 1337 | RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. |
| 1338 | if (CC == CallingConv::X86_FastCall) |
| 1339 | VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. |
| 1340 | } |
Evan Cheng | 25caf63 | 2006-05-23 21:06:34 +0000 | [diff] [blame] | 1341 | |
Anton Korobeynikov | a2780e1 | 2007-08-15 17:12:32 +0000 | [diff] [blame] | 1342 | FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 1343 | |
Evan Cheng | 25caf63 | 2006-05-23 21:06:34 +0000 | [diff] [blame] | 1344 | // Return the new list of results. |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 1345 | return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), |
Chris Lattner | 14dd4c9 | 2007-02-26 07:50:02 +0000 | [diff] [blame] | 1346 | &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1347 | } |
| 1348 | |
Evan Cheng | dffbd83 | 2008-01-10 00:09:10 +0000 | [diff] [blame] | 1349 | SDOperand |
| 1350 | X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, |
| 1351 | const SDOperand &StackPtr, |
| 1352 | const CCValAssign &VA, |
| 1353 | SDOperand Chain, |
| 1354 | SDOperand Arg) { |
Dan Gohman | 4fdad17 | 2008-02-07 16:28:05 +0000 | [diff] [blame] | 1355 | unsigned LocMemOffset = VA.getLocMemOffset(); |
| 1356 | SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset); |
Evan Cheng | dffbd83 | 2008-01-10 00:09:10 +0000 | [diff] [blame] | 1357 | PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1358 | ISD::ArgFlagsTy Flags = |
| 1359 | cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags(); |
| 1360 | if (Flags.isByVal()) { |
Evan Cheng | 8e5712b | 2008-01-12 01:08:07 +0000 | [diff] [blame] | 1361 | return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); |
Evan Cheng | dffbd83 | 2008-01-10 00:09:10 +0000 | [diff] [blame] | 1362 | } |
Dan Gohman | 4fdad17 | 2008-02-07 16:28:05 +0000 | [diff] [blame] | 1363 | return DAG.getStore(Chain, Arg, PtrOff, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 1364 | PseudoSourceValue::getStack(), LocMemOffset); |
Evan Cheng | dffbd83 | 2008-01-10 00:09:10 +0000 | [diff] [blame] | 1365 | } |
| 1366 | |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1367 | /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call |
| 1368 | /// optimization is performed and it is required. |
| 1369 | SDOperand |
| 1370 | X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, |
| 1371 | SDOperand &OutRetAddr, |
| 1372 | SDOperand Chain, |
| 1373 | bool IsTailCall, |
| 1374 | bool Is64Bit, |
| 1375 | int FPDiff) { |
| 1376 | if (!IsTailCall || FPDiff==0) return Chain; |
| 1377 | |
| 1378 | // Adjust the Return address stack slot. |
| 1379 | MVT::ValueType VT = getPointerTy(); |
| 1380 | OutRetAddr = getReturnAddressFrameIndex(DAG); |
| 1381 | // Load the "old" Return address. |
| 1382 | OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0); |
| 1383 | return SDOperand(OutRetAddr.Val, 1); |
| 1384 | } |
| 1385 | |
| 1386 | /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call |
| 1387 | /// optimization is performed and it is required (FPDiff!=0). |
| 1388 | static SDOperand |
| 1389 | EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, |
| 1390 | SDOperand Chain, SDOperand RetAddrFrIdx, |
| 1391 | bool Is64Bit, int FPDiff) { |
| 1392 | // Store the return address to the appropriate stack slot. |
| 1393 | if (!FPDiff) return Chain; |
| 1394 | // Calculate the new stack slot for the return address. |
| 1395 | int SlotSize = Is64Bit ? 8 : 4; |
| 1396 | int NewReturnAddrFI = |
| 1397 | MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); |
| 1398 | MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32; |
| 1399 | SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); |
| 1400 | Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, |
| 1401 | PseudoSourceValue::getFixedStack(), NewReturnAddrFI); |
| 1402 | return Chain; |
| 1403 | } |
| 1404 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1405 | SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { |
| 1406 | MachineFunction &MF = DAG.getMachineFunction(); |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 1407 | SDOperand Chain = Op.getOperand(0); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1408 | unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1409 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1410 | bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 |
| 1411 | && CC == CallingConv::Fast && PerformTailCallOpt; |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 1412 | SDOperand Callee = Op.getOperand(4); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1413 | bool Is64Bit = Subtarget->is64Bit(); |
Evan Cheng | 0d9e976 | 2008-01-29 19:34:22 +0000 | [diff] [blame] | 1414 | bool IsStructRet = CallIsStructReturn(Op); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1415 | |
| 1416 | assert(!(isVarArg && CC == CallingConv::Fast) && |
| 1417 | "Var args not supported with calling convention fastcc"); |
| 1418 | |
Chris Lattner | 638402b | 2007-02-28 07:00:42 +0000 | [diff] [blame] | 1419 | // Analyze operands of the call, assigning locations to each operand. |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1420 | SmallVector<CCValAssign, 16> ArgLocs; |
Chris Lattner | 52387be | 2007-06-19 00:13:10 +0000 | [diff] [blame] | 1421 | CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); |
Chris Lattner | 920c37a | 2008-03-21 06:50:21 +0000 | [diff] [blame] | 1422 | CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op)); |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1423 | |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1424 | // Get a count of how many bytes are to be pushed on the stack. |
| 1425 | unsigned NumBytes = CCInfo.getNextStackOffset(); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1426 | if (CC == CallingConv::Fast) |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1427 | NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1428 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1429 | // Make sure the instruction takes 8n+4 bytes to make sure the start of the |
| 1430 | // arguments and the arguments after the retaddr has been pushed are aligned. |
| 1431 | if (!Is64Bit && CC == CallingConv::X86_FastCall && |
| 1432 | !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && |
| 1433 | (NumBytes & 7) == 0) |
| 1434 | NumBytes += 4; |
| 1435 | |
| 1436 | int FPDiff = 0; |
| 1437 | if (IsTailCall) { |
| 1438 | // Lower arguments at fp - stackoffset + fpdiff. |
| 1439 | unsigned NumBytesCallerPushed = |
| 1440 | MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); |
| 1441 | FPDiff = NumBytesCallerPushed - NumBytes; |
| 1442 | |
| 1443 | // Set the delta of movement of the returnaddr stackslot. |
| 1444 | // But only set if delta is greater than previous delta. |
| 1445 | if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) |
| 1446 | MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); |
| 1447 | } |
| 1448 | |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1449 | Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes)); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1450 | |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1451 | SDOperand RetAddrFrIdx; |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1452 | // Load return adress for tail calls. |
| 1453 | Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, |
| 1454 | FPDiff); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1455 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 1456 | SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; |
| 1457 | SmallVector<SDOperand, 8> MemOpChains; |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1458 | SDOperand StackPtr; |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1459 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1460 | // Walk the register/memloc assignments, inserting copies/loads. In the case |
| 1461 | // of tail call optimization arguments are handle later. |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1462 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
| 1463 | CCValAssign &VA = ArgLocs[i]; |
| 1464 | SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1465 | bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))-> |
| 1466 | getArgFlags().isByVal(); |
| 1467 | |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1468 | // Promote the value if needed. |
| 1469 | switch (VA.getLocInfo()) { |
| 1470 | default: assert(0 && "Unknown loc info!"); |
| 1471 | case CCValAssign::Full: break; |
| 1472 | case CCValAssign::SExt: |
| 1473 | Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); |
| 1474 | break; |
| 1475 | case CCValAssign::ZExt: |
| 1476 | Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); |
| 1477 | break; |
| 1478 | case CCValAssign::AExt: |
| 1479 | Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); |
| 1480 | break; |
Evan Cheng | 6b5783d | 2006-05-25 18:56:34 +0000 | [diff] [blame] | 1481 | } |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1482 | |
| 1483 | if (VA.isRegLoc()) { |
Evan Cheng | 10e8642 | 2008-04-25 19:11:04 +0000 | [diff] [blame] | 1484 | if (Is64Bit) { |
| 1485 | MVT::ValueType RegVT = VA.getLocVT(); |
| 1486 | if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 64) |
| 1487 | switch (VA.getLocReg()) { |
| 1488 | default: |
| 1489 | break; |
| 1490 | case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: |
| 1491 | case X86::R8: { |
| 1492 | // Special case: passing MMX values in GPR registers. |
| 1493 | Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); |
| 1494 | break; |
| 1495 | } |
| 1496 | case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: |
| 1497 | case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { |
| 1498 | // Special case: passing MMX values in XMM registers. |
| 1499 | Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); |
| 1500 | Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg); |
| 1501 | Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, |
| 1502 | DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg, |
| 1503 | getMOVLMask(2, DAG)); |
| 1504 | break; |
| 1505 | } |
| 1506 | } |
| 1507 | } |
Chris Lattner | 423c5f4 | 2007-02-28 05:31:48 +0000 | [diff] [blame] | 1508 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); |
| 1509 | } else { |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1510 | if (!IsTailCall || (IsTailCall && isByVal)) { |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1511 | assert(VA.isMemLoc()); |
| 1512 | if (StackPtr.Val == 0) |
| 1513 | StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); |
| 1514 | |
| 1515 | MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain, |
| 1516 | Arg)); |
| 1517 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1518 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1519 | } |
Chris Lattner | c0bdf34 | 2007-02-28 05:39:26 +0000 | [diff] [blame] | 1520 | |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 1521 | if (!MemOpChains.empty()) |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 1522 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 1523 | &MemOpChains[0], MemOpChains.size()); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1524 | |
Evan Cheng | 347d5f7 | 2006-04-28 21:29:37 +0000 | [diff] [blame] | 1525 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 1526 | // and flag operands which copy the outgoing args into registers. |
| 1527 | SDOperand InFlag; |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1528 | // Tail call byval lowering might overwrite argument registers so in case of |
| 1529 | // tail call optimization the copies to registers are lowered later. |
| 1530 | if (!IsTailCall) |
| 1531 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
| 1532 | Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, |
| 1533 | InFlag); |
| 1534 | InFlag = Chain.getValue(1); |
| 1535 | } |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1536 | |
Evan Cheng | f468471 | 2007-02-21 21:18:14 +0000 | [diff] [blame] | 1537 | // ELF / PIC requires GOT in the EBX register before function calls via PLT |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1538 | // GOT pointer. |
Arnold Schwaighofer | 258bb1b | 2008-02-26 22:21:54 +0000 | [diff] [blame] | 1539 | if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { |
| 1540 | Chain = DAG.getCopyToReg(Chain, X86::EBX, |
| 1541 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), |
| 1542 | InFlag); |
| 1543 | InFlag = Chain.getValue(1); |
| 1544 | } |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1545 | // If we are tail calling and generating PIC/GOT style code load the address |
| 1546 | // of the callee into ecx. The value in ecx is used as target of the tail |
| 1547 | // jump. This is done to circumvent the ebx/callee-saved problem for tail |
| 1548 | // calls on PIC/GOT architectures. Normally we would just put the address of |
| 1549 | // GOT into ebx and then call target@PLT. But for tail callss ebx would be |
| 1550 | // restored (since ebx is callee saved) before jumping to the target@PLT. |
Arnold Schwaighofer | 258bb1b | 2008-02-26 22:21:54 +0000 | [diff] [blame] | 1551 | if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1552 | // Note: The actual moving to ecx is done further down. |
| 1553 | GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); |
| 1554 | if (G && !G->getGlobal()->hasHiddenVisibility() && |
| 1555 | !G->getGlobal()->hasProtectedVisibility()) |
| 1556 | Callee = LowerGlobalAddress(Callee, DAG); |
| 1557 | else if (isa<ExternalSymbolSDNode>(Callee)) |
| 1558 | Callee = LowerExternalSymbol(Callee,DAG); |
Anton Korobeynikov | 7f70559 | 2007-01-12 19:20:47 +0000 | [diff] [blame] | 1559 | } |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1560 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1561 | if (Is64Bit && isVarArg) { |
| 1562 | // From AMD64 ABI document: |
| 1563 | // For calls that may call functions that use varargs or stdargs |
| 1564 | // (prototype-less calls or calls to functions containing ellipsis (...) in |
| 1565 | // the declaration) %al is used as hidden argument to specify the number |
| 1566 | // of SSE registers used. The contents of %al do not need to match exactly |
| 1567 | // the number of registers, but must be an ubound on the number of SSE |
| 1568 | // registers used and is in the range 0 - 8 inclusive. |
Anton Korobeynikov | 998a5bc | 2008-04-27 23:15:03 +0000 | [diff] [blame] | 1569 | |
| 1570 | // FIXME: Verify this on Win64 |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1571 | // Count the number of XMM registers allocated. |
| 1572 | static const unsigned XMMArgRegs[] = { |
| 1573 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, |
| 1574 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 |
| 1575 | }; |
| 1576 | unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); |
| 1577 | |
| 1578 | Chain = DAG.getCopyToReg(Chain, X86::AL, |
| 1579 | DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); |
| 1580 | InFlag = Chain.getValue(1); |
| 1581 | } |
| 1582 | |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1583 | |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1584 | // For tail calls lower the arguments to the 'real' stack slot. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1585 | if (IsTailCall) { |
| 1586 | SmallVector<SDOperand, 8> MemOpChains2; |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1587 | SDOperand FIN; |
| 1588 | int FI = 0; |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1589 | // Do not flag preceeding copytoreg stuff together with the following stuff. |
| 1590 | InFlag = SDOperand(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1591 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { |
| 1592 | CCValAssign &VA = ArgLocs[i]; |
| 1593 | if (!VA.isRegLoc()) { |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1594 | assert(VA.isMemLoc()); |
| 1595 | SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1596 | SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo()); |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1597 | ISD::ArgFlagsTy Flags = |
| 1598 | cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags(); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1599 | // Create frame index. |
| 1600 | int32_t Offset = VA.getLocMemOffset()+FPDiff; |
| 1601 | uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8; |
| 1602 | FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1603 | FIN = DAG.getFrameIndex(FI, getPointerTy()); |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1604 | |
Duncan Sands | 276dcbd | 2008-03-21 09:14:45 +0000 | [diff] [blame] | 1605 | if (Flags.isByVal()) { |
Evan Cheng | 8e5712b | 2008-01-12 01:08:07 +0000 | [diff] [blame] | 1606 | // Copy relative to framepointer. |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1607 | SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); |
| 1608 | if (StackPtr.Val == 0) |
| 1609 | StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); |
| 1610 | Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); |
| 1611 | |
| 1612 | MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, |
Evan Cheng | 8e5712b | 2008-01-12 01:08:07 +0000 | [diff] [blame] | 1613 | Flags, DAG)); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1614 | } else { |
Evan Cheng | 8e5712b | 2008-01-12 01:08:07 +0000 | [diff] [blame] | 1615 | // Store relative to framepointer. |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 1616 | MemOpChains2.push_back( |
Arnold Schwaighofer | 865c681 | 2008-02-26 09:19:59 +0000 | [diff] [blame] | 1617 | DAG.getStore(Chain, Arg, FIN, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 1618 | PseudoSourceValue::getFixedStack(), FI)); |
Arnold Schwaighofer | c8ab8cd | 2008-01-11 16:49:42 +0000 | [diff] [blame] | 1619 | } |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1620 | } |
| 1621 | } |
| 1622 | |
| 1623 | if (!MemOpChains2.empty()) |
| 1624 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, |
Arnold Schwaighofer | 719eb02 | 2008-01-11 14:34:56 +0000 | [diff] [blame] | 1625 | &MemOpChains2[0], MemOpChains2.size()); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1626 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1627 | // Copy arguments to their registers. |
| 1628 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
| 1629 | Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, |
| 1630 | InFlag); |
| 1631 | InFlag = Chain.getValue(1); |
| 1632 | } |
| 1633 | InFlag =SDOperand(); |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1634 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1635 | // Store the return address to the appropriate stack slot. |
Arnold Schwaighofer | 4b5324a | 2008-04-12 18:11:06 +0000 | [diff] [blame] | 1636 | Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, |
| 1637 | FPDiff); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1638 | } |
| 1639 | |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 1640 | // If the callee is a GlobalAddress node (quite common, every direct call is) |
| 1641 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. |
Anton Korobeynikov | a598685 | 2006-11-20 10:46:14 +0000 | [diff] [blame] | 1642 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { |
Anton Korobeynikov | 2b2bc68 | 2006-12-22 22:29:05 +0000 | [diff] [blame] | 1643 | // We should use extra load for direct calls to dllimported functions in |
| 1644 | // non-JIT mode. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1645 | if ((IsTailCall || !Is64Bit || |
| 1646 | getTargetMachine().getCodeModel() != CodeModel::Large) |
| 1647 | && !Subtarget->GVRequiresExtraLoad(G->getGlobal(), |
| 1648 | getTargetMachine(), true)) |
Anton Korobeynikov | a598685 | 2006-11-20 10:46:14 +0000 | [diff] [blame] | 1649 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1650 | } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1651 | if (IsTailCall || !Is64Bit || |
| 1652 | getTargetMachine().getCodeModel() != CodeModel::Large) |
| 1653 | Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); |
| 1654 | } else if (IsTailCall) { |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1655 | unsigned Opc = Is64Bit ? X86::R9 : X86::ECX; |
| 1656 | |
| 1657 | Chain = DAG.getCopyToReg(Chain, |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1658 | DAG.getRegister(Opc, getPointerTy()), |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1659 | Callee,InFlag); |
| 1660 | Callee = DAG.getRegister(Opc, getPointerTy()); |
| 1661 | // Add register as live out. |
| 1662 | DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1663 | } |
| 1664 | |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 1665 | // Returns a chain & a flag for retval copy to use. |
| 1666 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 1667 | SmallVector<SDOperand, 8> Ops; |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1668 | |
| 1669 | if (IsTailCall) { |
| 1670 | Ops.push_back(Chain); |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1671 | Ops.push_back(DAG.getIntPtrConstant(NumBytes)); |
| 1672 | Ops.push_back(DAG.getIntPtrConstant(0)); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1673 | if (InFlag.Val) |
| 1674 | Ops.push_back(InFlag); |
| 1675 | Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); |
| 1676 | InFlag = Chain.getValue(1); |
| 1677 | |
| 1678 | // Returns a chain & a flag for retval copy to use. |
| 1679 | NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 1680 | Ops.clear(); |
| 1681 | } |
| 1682 | |
Nate Begeman | 4c5dcf5 | 2006-02-17 00:03:04 +0000 | [diff] [blame] | 1683 | Ops.push_back(Chain); |
| 1684 | Ops.push_back(Callee); |
Evan Cheng | b69d113 | 2006-06-14 18:17:40 +0000 | [diff] [blame] | 1685 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1686 | if (IsTailCall) |
| 1687 | Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); |
Evan Cheng | f468471 | 2007-02-21 21:18:14 +0000 | [diff] [blame] | 1688 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1689 | // Add argument registers to the end of the list so that they are known live |
| 1690 | // into the call. |
Evan Cheng | 9b44944 | 2008-01-07 23:08:23 +0000 | [diff] [blame] | 1691 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
| 1692 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, |
| 1693 | RegsToPass[i].second.getValueType())); |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1694 | |
Evan Cheng | 586ccac | 2008-03-18 23:36:35 +0000 | [diff] [blame] | 1695 | // Add an implicit use GOT pointer in EBX. |
| 1696 | if (!IsTailCall && !Is64Bit && |
| 1697 | getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 1698 | Subtarget->isPICStyleGOT()) |
| 1699 | Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); |
| 1700 | |
| 1701 | // Add an implicit use of AL for x86 vararg functions. |
| 1702 | if (Is64Bit && isVarArg) |
| 1703 | Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); |
| 1704 | |
Evan Cheng | 347d5f7 | 2006-04-28 21:29:37 +0000 | [diff] [blame] | 1705 | if (InFlag.Val) |
| 1706 | Ops.push_back(InFlag); |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1707 | |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1708 | if (IsTailCall) { |
| 1709 | assert(InFlag.Val && |
| 1710 | "Flag must be set. Depend on flag being set in LowerRET"); |
| 1711 | Chain = DAG.getNode(X86ISD::TAILCALL, |
| 1712 | Op.Val->getVTList(), &Ops[0], Ops.size()); |
| 1713 | |
| 1714 | return SDOperand(Chain.Val, Op.ResNo); |
| 1715 | } |
| 1716 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1717 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); |
Evan Cheng | 347d5f7 | 2006-04-28 21:29:37 +0000 | [diff] [blame] | 1718 | InFlag = Chain.getValue(1); |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 1719 | |
Chris Lattner | 2d29709 | 2006-05-23 18:50:38 +0000 | [diff] [blame] | 1720 | // Create the CALLSEQ_END node. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1721 | unsigned NumBytesForCalleeToPush; |
| 1722 | if (IsCalleePop(Op)) |
| 1723 | NumBytesForCalleeToPush = NumBytes; // Callee pops everything |
Evan Cheng | 0d9e976 | 2008-01-29 19:34:22 +0000 | [diff] [blame] | 1724 | else if (!Is64Bit && IsStructRet) |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 1725 | // If this is is a call to a struct-return function, the callee |
| 1726 | // pops the hidden struct pointer, so we have to push it back. |
| 1727 | // This is common for Darwin/X86, Linux & Mingw32 targets. |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1728 | NumBytesForCalleeToPush = 4; |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1729 | else |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1730 | NumBytesForCalleeToPush = 0; // Callee pops nothing. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1731 | |
Gordon Henriksen | ae636f8 | 2008-01-03 16:47:34 +0000 | [diff] [blame] | 1732 | // Returns a flag for retval copy to use. |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 1733 | Chain = DAG.getCALLSEQ_END(Chain, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 1734 | DAG.getIntPtrConstant(NumBytes), |
| 1735 | DAG.getIntPtrConstant(NumBytesForCalleeToPush), |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 1736 | InFlag); |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 1737 | InFlag = Chain.getValue(1); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 1738 | |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 1739 | // Handle result values, copying them out of physregs into vregs that we |
| 1740 | // return. |
Chris Lattner | 920c37a | 2008-03-21 06:50:21 +0000 | [diff] [blame] | 1741 | return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1742 | } |
| 1743 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1744 | |
| 1745 | //===----------------------------------------------------------------------===// |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1746 | // Fast Calling Convention (tail call) implementation |
| 1747 | //===----------------------------------------------------------------------===// |
| 1748 | |
| 1749 | // Like std call, callee cleans arguments, convention except that ECX is |
| 1750 | // reserved for storing the tail called function address. Only 2 registers are |
| 1751 | // free for argument passing (inreg). Tail call optimization is performed |
| 1752 | // provided: |
| 1753 | // * tailcallopt is enabled |
| 1754 | // * caller/callee are fastcc |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1755 | // On X86_64 architecture with GOT-style position independent code only local |
| 1756 | // (within module) calls are supported at the moment. |
Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1757 | // To keep the stack aligned according to platform abi the function |
| 1758 | // GetAlignedArgumentStackSize ensures that argument delta is always multiples |
| 1759 | // of stack alignment. (Dynamic linkers need this - darwin's dyld for example) |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1760 | // If a tail called function callee has more arguments than the caller the |
| 1761 | // caller needs to make sure that there is room to move the RETADDR to. This is |
Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1762 | // achieved by reserving an area the size of the argument delta right after the |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1763 | // original REtADDR, but before the saved framepointer or the spilled registers |
| 1764 | // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) |
| 1765 | // stack layout: |
| 1766 | // arg1 |
| 1767 | // arg2 |
| 1768 | // RETADDR |
| 1769 | // [ new RETADDR |
| 1770 | // move area ] |
| 1771 | // (possible EBP) |
| 1772 | // ESI |
| 1773 | // EDI |
| 1774 | // local1 .. |
| 1775 | |
| 1776 | /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned |
| 1777 | /// for a 16 byte align requirement. |
| 1778 | unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, |
| 1779 | SelectionDAG& DAG) { |
| 1780 | if (PerformTailCallOpt) { |
| 1781 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1782 | const TargetMachine &TM = MF.getTarget(); |
| 1783 | const TargetFrameInfo &TFI = *TM.getFrameInfo(); |
| 1784 | unsigned StackAlignment = TFI.getStackAlignment(); |
| 1785 | uint64_t AlignMask = StackAlignment - 1; |
| 1786 | int64_t Offset = StackSize; |
| 1787 | unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4; |
| 1788 | if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { |
| 1789 | // Number smaller than 12 so just add the difference. |
| 1790 | Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); |
| 1791 | } else { |
| 1792 | // Mask out lower bits, add stackalignment once plus the 12 bytes. |
| 1793 | Offset = ((~AlignMask) & Offset) + StackAlignment + |
| 1794 | (StackAlignment-SlotSize); |
| 1795 | } |
| 1796 | StackSize = Offset; |
| 1797 | } |
| 1798 | return StackSize; |
| 1799 | } |
| 1800 | |
| 1801 | /// IsEligibleForTailCallElimination - Check to see whether the next instruction |
Evan Cheng | 9df7dc5 | 2007-11-02 01:26:22 +0000 | [diff] [blame] | 1802 | /// following the call is a return. A function is eligible if caller/callee |
| 1803 | /// calling conventions match, currently only fastcc supports tail calls, and |
| 1804 | /// the function CALL is immediatly followed by a RET. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1805 | bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, |
| 1806 | SDOperand Ret, |
| 1807 | SelectionDAG& DAG) const { |
Evan Cheng | 9df7dc5 | 2007-11-02 01:26:22 +0000 | [diff] [blame] | 1808 | if (!PerformTailCallOpt) |
| 1809 | return false; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1810 | |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 1811 | if (CheckTailCallReturnConstraints(Call, Ret)) { |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1812 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1813 | unsigned CallerCC = MF.getFunction()->getCallingConv(); |
| 1814 | unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue(); |
| 1815 | if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { |
| 1816 | SDOperand Callee = Call.getOperand(4); |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1817 | // On x86/32Bit PIC/GOT tail calls are supported. |
Evan Cheng | 9df7dc5 | 2007-11-02 01:26:22 +0000 | [diff] [blame] | 1818 | if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1819 | !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) |
Evan Cheng | 9df7dc5 | 2007-11-02 01:26:22 +0000 | [diff] [blame] | 1820 | return true; |
| 1821 | |
Arnold Schwaighofer | a2a4b47 | 2008-02-26 10:21:54 +0000 | [diff] [blame] | 1822 | // Can only do local tail calls (in same module, hidden or protected) on |
| 1823 | // x86_64 PIC/GOT at the moment. |
Gordon Henriksen | 8673766 | 2008-01-05 16:56:59 +0000 | [diff] [blame] | 1824 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
| 1825 | return G->getGlobal()->hasHiddenVisibility() |
| 1826 | || G->getGlobal()->hasProtectedVisibility(); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1827 | } |
| 1828 | } |
Evan Cheng | 9df7dc5 | 2007-11-02 01:26:22 +0000 | [diff] [blame] | 1829 | |
| 1830 | return false; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1831 | } |
| 1832 | |
Chris Lattner | fcf1a3d | 2007-02-28 06:10:12 +0000 | [diff] [blame] | 1833 | //===----------------------------------------------------------------------===// |
| 1834 | // Other Lowering Hooks |
| 1835 | //===----------------------------------------------------------------------===// |
| 1836 | |
| 1837 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1838 | SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { |
Anton Korobeynikov | a2780e1 | 2007-08-15 17:12:32 +0000 | [diff] [blame] | 1839 | MachineFunction &MF = DAG.getMachineFunction(); |
| 1840 | X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); |
| 1841 | int ReturnAddrIndex = FuncInfo->getRAIndex(); |
| 1842 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1843 | if (ReturnAddrIndex == 0) { |
| 1844 | // Set up a frame object for the return address. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1845 | if (Subtarget->is64Bit()) |
| 1846 | ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); |
| 1847 | else |
| 1848 | ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); |
Anton Korobeynikov | a2780e1 | 2007-08-15 17:12:32 +0000 | [diff] [blame] | 1849 | |
| 1850 | FuncInfo->setRAIndex(ReturnAddrIndex); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1851 | } |
| 1852 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1853 | return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1854 | } |
| 1855 | |
| 1856 | |
| 1857 | |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1858 | /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 |
| 1859 | /// specific condition code. It returns a false if it cannot do a direct |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 1860 | /// translation. X86CC is the translated CondCode. LHS/RHS are modified as |
| 1861 | /// needed. |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 1862 | static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 1863 | unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, |
| 1864 | SelectionDAG &DAG) { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1865 | X86CC = X86::COND_INVALID; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1866 | if (!isFP) { |
Chris Lattner | bfd68a7 | 2006-09-13 17:04:54 +0000 | [diff] [blame] | 1867 | if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { |
| 1868 | if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { |
| 1869 | // X > -1 -> X == 0, jump !sign. |
| 1870 | RHS = DAG.getConstant(0, RHS.getValueType()); |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1871 | X86CC = X86::COND_NS; |
Chris Lattner | bfd68a7 | 2006-09-13 17:04:54 +0000 | [diff] [blame] | 1872 | return true; |
| 1873 | } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { |
| 1874 | // X < 0 -> X == 0, jump on sign. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1875 | X86CC = X86::COND_S; |
Chris Lattner | bfd68a7 | 2006-09-13 17:04:54 +0000 | [diff] [blame] | 1876 | return true; |
Dan Gohman | 5f6913c | 2007-09-17 14:49:27 +0000 | [diff] [blame] | 1877 | } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) { |
| 1878 | // X < 1 -> X <= 0 |
| 1879 | RHS = DAG.getConstant(0, RHS.getValueType()); |
| 1880 | X86CC = X86::COND_LE; |
| 1881 | return true; |
Chris Lattner | bfd68a7 | 2006-09-13 17:04:54 +0000 | [diff] [blame] | 1882 | } |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 1883 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 1884 | |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1885 | switch (SetCCOpcode) { |
| 1886 | default: break; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1887 | case ISD::SETEQ: X86CC = X86::COND_E; break; |
| 1888 | case ISD::SETGT: X86CC = X86::COND_G; break; |
| 1889 | case ISD::SETGE: X86CC = X86::COND_GE; break; |
| 1890 | case ISD::SETLT: X86CC = X86::COND_L; break; |
| 1891 | case ISD::SETLE: X86CC = X86::COND_LE; break; |
| 1892 | case ISD::SETNE: X86CC = X86::COND_NE; break; |
| 1893 | case ISD::SETULT: X86CC = X86::COND_B; break; |
| 1894 | case ISD::SETUGT: X86CC = X86::COND_A; break; |
| 1895 | case ISD::SETULE: X86CC = X86::COND_BE; break; |
| 1896 | case ISD::SETUGE: X86CC = X86::COND_AE; break; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1897 | } |
| 1898 | } else { |
| 1899 | // On a floating point condition, the flags are set as follows: |
| 1900 | // ZF PF CF op |
| 1901 | // 0 | 0 | 0 | X > Y |
| 1902 | // 0 | 0 | 1 | X < Y |
| 1903 | // 1 | 0 | 0 | X == Y |
| 1904 | // 1 | 1 | 1 | unordered |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 1905 | bool Flip = false; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1906 | switch (SetCCOpcode) { |
| 1907 | default: break; |
| 1908 | case ISD::SETUEQ: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1909 | case ISD::SETEQ: X86CC = X86::COND_E; break; |
Evan Cheng | 5001ea1 | 2006-04-17 07:24:10 +0000 | [diff] [blame] | 1910 | case ISD::SETOLT: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1911 | case ISD::SETOGT: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1912 | case ISD::SETGT: X86CC = X86::COND_A; break; |
Evan Cheng | 5001ea1 | 2006-04-17 07:24:10 +0000 | [diff] [blame] | 1913 | case ISD::SETOLE: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1914 | case ISD::SETOGE: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1915 | case ISD::SETGE: X86CC = X86::COND_AE; break; |
Evan Cheng | 5001ea1 | 2006-04-17 07:24:10 +0000 | [diff] [blame] | 1916 | case ISD::SETUGT: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1917 | case ISD::SETULT: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1918 | case ISD::SETLT: X86CC = X86::COND_B; break; |
Evan Cheng | 5001ea1 | 2006-04-17 07:24:10 +0000 | [diff] [blame] | 1919 | case ISD::SETUGE: Flip = true; // Fallthrough |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1920 | case ISD::SETULE: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1921 | case ISD::SETLE: X86CC = X86::COND_BE; break; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1922 | case ISD::SETONE: |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1923 | case ISD::SETNE: X86CC = X86::COND_NE; break; |
| 1924 | case ISD::SETUO: X86CC = X86::COND_P; break; |
| 1925 | case ISD::SETO: X86CC = X86::COND_NP; break; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1926 | } |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 1927 | if (Flip) |
| 1928 | std::swap(LHS, RHS); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1929 | } |
Evan Cheng | 6dfa999 | 2006-01-30 23:41:35 +0000 | [diff] [blame] | 1930 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1931 | return X86CC != X86::COND_INVALID; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 1932 | } |
| 1933 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1934 | /// hasFPCMov - is there a floating point cmov for the specific X86 condition |
| 1935 | /// code. Current x86 isa includes the following FP cmov instructions: |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1936 | /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 1937 | static bool hasFPCMov(unsigned X86CC) { |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1938 | switch (X86CC) { |
| 1939 | default: |
| 1940 | return false; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 1941 | case X86::COND_B: |
| 1942 | case X86::COND_BE: |
| 1943 | case X86::COND_E: |
| 1944 | case X86::COND_P: |
| 1945 | case X86::COND_A: |
| 1946 | case X86::COND_AE: |
| 1947 | case X86::COND_NE: |
| 1948 | case X86::COND_NP: |
Evan Cheng | aaca22c | 2006-01-10 20:26:56 +0000 | [diff] [blame] | 1949 | return true; |
| 1950 | } |
| 1951 | } |
| 1952 | |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 1953 | /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 1954 | /// true if Op is undef or if its value falls within the specified range (L, H]. |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 1955 | static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { |
| 1956 | if (Op.getOpcode() == ISD::UNDEF) |
| 1957 | return true; |
| 1958 | |
| 1959 | unsigned Val = cast<ConstantSDNode>(Op)->getValue(); |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 1960 | return (Val >= Low && Val < Hi); |
| 1961 | } |
| 1962 | |
| 1963 | /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return |
| 1964 | /// true if Op is undef or if its value equal to the specified value. |
| 1965 | static bool isUndefOrEqual(SDOperand Op, unsigned Val) { |
| 1966 | if (Op.getOpcode() == ISD::UNDEF) |
| 1967 | return true; |
| 1968 | return cast<ConstantSDNode>(Op)->getValue() == Val; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 1969 | } |
| 1970 | |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 1971 | /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand |
| 1972 | /// specifies a shuffle of elements that is suitable for input to PSHUFD. |
| 1973 | bool X86::isPSHUFDMask(SDNode *N) { |
| 1974 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 1975 | |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1976 | if (N->getNumOperands() != 2 && N->getNumOperands() != 4) |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 1977 | return false; |
| 1978 | |
| 1979 | // Check if the value doesn't reference the second vector. |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 1980 | for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 1981 | SDOperand Arg = N->getOperand(i); |
| 1982 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 1983 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
Dan Gohman | 7f55fcb | 2007-08-02 21:17:01 +0000 | [diff] [blame] | 1984 | if (cast<ConstantSDNode>(Arg)->getValue() >= e) |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 1985 | return false; |
| 1986 | } |
| 1987 | |
| 1988 | return true; |
| 1989 | } |
| 1990 | |
| 1991 | /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand |
Evan Cheng | c21a053 | 2006-04-05 01:47:37 +0000 | [diff] [blame] | 1992 | /// specifies a shuffle of elements that is suitable for input to PSHUFHW. |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 1993 | bool X86::isPSHUFHWMask(SDNode *N) { |
| 1994 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 1995 | |
| 1996 | if (N->getNumOperands() != 8) |
| 1997 | return false; |
| 1998 | |
| 1999 | // Lower quadword copied in order. |
| 2000 | for (unsigned i = 0; i != 4; ++i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2001 | SDOperand Arg = N->getOperand(i); |
| 2002 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2003 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2004 | if (cast<ConstantSDNode>(Arg)->getValue() != i) |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2005 | return false; |
| 2006 | } |
| 2007 | |
| 2008 | // Upper quadword shuffled. |
| 2009 | for (unsigned i = 4; i != 8; ++i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2010 | SDOperand Arg = N->getOperand(i); |
| 2011 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2012 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2013 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2014 | if (Val < 4 || Val > 7) |
| 2015 | return false; |
| 2016 | } |
| 2017 | |
| 2018 | return true; |
| 2019 | } |
| 2020 | |
| 2021 | /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand |
Evan Cheng | c21a053 | 2006-04-05 01:47:37 +0000 | [diff] [blame] | 2022 | /// specifies a shuffle of elements that is suitable for input to PSHUFLW. |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2023 | bool X86::isPSHUFLWMask(SDNode *N) { |
| 2024 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2025 | |
| 2026 | if (N->getNumOperands() != 8) |
| 2027 | return false; |
| 2028 | |
| 2029 | // Upper quadword copied in order. |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2030 | for (unsigned i = 4; i != 8; ++i) |
| 2031 | if (!isUndefOrEqual(N->getOperand(i), i)) |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2032 | return false; |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2033 | |
| 2034 | // Lower quadword shuffled. |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2035 | for (unsigned i = 0; i != 4; ++i) |
| 2036 | if (!isUndefOrInRange(N->getOperand(i), 0, 4)) |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2037 | return false; |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 2038 | |
| 2039 | return true; |
| 2040 | } |
| 2041 | |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 2042 | /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2043 | /// specifies a shuffle of elements that is suitable for input to SHUFP*. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2044 | static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) { |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2045 | if (NumElems != 2 && NumElems != 4) return false; |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 2046 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2047 | unsigned Half = NumElems / 2; |
| 2048 | for (unsigned i = 0; i < Half; ++i) |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2049 | if (!isUndefOrInRange(Elems[i], 0, NumElems)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2050 | return false; |
| 2051 | for (unsigned i = Half; i < NumElems; ++i) |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2052 | if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2053 | return false; |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 2054 | |
| 2055 | return true; |
| 2056 | } |
| 2057 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2058 | bool X86::isSHUFPMask(SDNode *N) { |
| 2059 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2060 | return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2061 | } |
| 2062 | |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2063 | /// isCommutedSHUFP - Returns true if the shuffle mask is exactly |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2064 | /// the reverse of what x86 shuffles want. x86 shuffles requires the lower |
| 2065 | /// half elements to come from vector 1 (which would equal the dest.) and |
| 2066 | /// the upper half to come from vector 2. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2067 | static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2068 | if (NumOps != 2 && NumOps != 4) return false; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2069 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2070 | unsigned Half = NumOps / 2; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2071 | for (unsigned i = 0; i < Half; ++i) |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2072 | if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2073 | return false; |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2074 | for (unsigned i = Half; i < NumOps; ++i) |
| 2075 | if (!isUndefOrInRange(Ops[i], 0, NumOps)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2076 | return false; |
| 2077 | return true; |
| 2078 | } |
| 2079 | |
| 2080 | static bool isCommutedSHUFP(SDNode *N) { |
| 2081 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2082 | return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2083 | } |
| 2084 | |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 2085 | /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2086 | /// specifies a shuffle of elements that is suitable for input to MOVHLPS. |
| 2087 | bool X86::isMOVHLPSMask(SDNode *N) { |
| 2088 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2089 | |
Evan Cheng | 2064a2b | 2006-03-28 06:50:32 +0000 | [diff] [blame] | 2090 | if (N->getNumOperands() != 4) |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 2091 | return false; |
| 2092 | |
Evan Cheng | 2064a2b | 2006-03-28 06:50:32 +0000 | [diff] [blame] | 2093 | // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2094 | return isUndefOrEqual(N->getOperand(0), 6) && |
| 2095 | isUndefOrEqual(N->getOperand(1), 7) && |
| 2096 | isUndefOrEqual(N->getOperand(2), 2) && |
| 2097 | isUndefOrEqual(N->getOperand(3), 3); |
Evan Cheng | 2064a2b | 2006-03-28 06:50:32 +0000 | [diff] [blame] | 2098 | } |
| 2099 | |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 2100 | /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form |
| 2101 | /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, |
| 2102 | /// <2, 3, 2, 3> |
| 2103 | bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { |
| 2104 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2105 | |
| 2106 | if (N->getNumOperands() != 4) |
| 2107 | return false; |
| 2108 | |
| 2109 | // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 |
| 2110 | return isUndefOrEqual(N->getOperand(0), 2) && |
| 2111 | isUndefOrEqual(N->getOperand(1), 3) && |
| 2112 | isUndefOrEqual(N->getOperand(2), 2) && |
| 2113 | isUndefOrEqual(N->getOperand(3), 3); |
| 2114 | } |
| 2115 | |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2116 | /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2117 | /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. |
| 2118 | bool X86::isMOVLPMask(SDNode *N) { |
| 2119 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2120 | |
| 2121 | unsigned NumElems = N->getNumOperands(); |
| 2122 | if (NumElems != 2 && NumElems != 4) |
| 2123 | return false; |
| 2124 | |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2125 | for (unsigned i = 0; i < NumElems/2; ++i) |
| 2126 | if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) |
| 2127 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2128 | |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2129 | for (unsigned i = NumElems/2; i < NumElems; ++i) |
| 2130 | if (!isUndefOrEqual(N->getOperand(i), i)) |
| 2131 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2132 | |
| 2133 | return true; |
| 2134 | } |
| 2135 | |
| 2136 | /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2137 | /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} |
| 2138 | /// and MOVLHPS. |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2139 | bool X86::isMOVHPMask(SDNode *N) { |
| 2140 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2141 | |
| 2142 | unsigned NumElems = N->getNumOperands(); |
| 2143 | if (NumElems != 2 && NumElems != 4) |
| 2144 | return false; |
| 2145 | |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2146 | for (unsigned i = 0; i < NumElems/2; ++i) |
| 2147 | if (!isUndefOrEqual(N->getOperand(i), i)) |
| 2148 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2149 | |
| 2150 | for (unsigned i = 0; i < NumElems/2; ++i) { |
| 2151 | SDOperand Arg = N->getOperand(i + NumElems/2); |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2152 | if (!isUndefOrEqual(Arg, i + NumElems)) |
| 2153 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2154 | } |
| 2155 | |
| 2156 | return true; |
| 2157 | } |
| 2158 | |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 2159 | /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2160 | /// specifies a shuffle of elements that is suitable for input to UNPCKL. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2161 | bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts, |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2162 | bool V2IsSplat = false) { |
| 2163 | if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 2164 | return false; |
| 2165 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2166 | for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { |
| 2167 | SDOperand BitI = Elts[i]; |
| 2168 | SDOperand BitI1 = Elts[i+1]; |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2169 | if (!isUndefOrEqual(BitI, j)) |
| 2170 | return false; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2171 | if (V2IsSplat) { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2172 | if (isUndefOrEqual(BitI1, NumElts)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2173 | return false; |
| 2174 | } else { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2175 | if (!isUndefOrEqual(BitI1, j + NumElts)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2176 | return false; |
| 2177 | } |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 2178 | } |
| 2179 | |
| 2180 | return true; |
| 2181 | } |
| 2182 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2183 | bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { |
| 2184 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2185 | return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2186 | } |
| 2187 | |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 2188 | /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2189 | /// specifies a shuffle of elements that is suitable for input to UNPCKH. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2190 | bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts, |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2191 | bool V2IsSplat = false) { |
| 2192 | if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 2193 | return false; |
| 2194 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2195 | for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { |
| 2196 | SDOperand BitI = Elts[i]; |
| 2197 | SDOperand BitI1 = Elts[i+1]; |
| 2198 | if (!isUndefOrEqual(BitI, j + NumElts/2)) |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2199 | return false; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2200 | if (V2IsSplat) { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2201 | if (isUndefOrEqual(BitI1, NumElts)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2202 | return false; |
| 2203 | } else { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2204 | if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2205 | return false; |
| 2206 | } |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 2207 | } |
| 2208 | |
| 2209 | return true; |
| 2210 | } |
| 2211 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2212 | bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { |
| 2213 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2214 | return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2215 | } |
| 2216 | |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2217 | /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form |
| 2218 | /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, |
| 2219 | /// <0, 0, 1, 1> |
| 2220 | bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { |
| 2221 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2222 | |
| 2223 | unsigned NumElems = N->getNumOperands(); |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 2224 | if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2225 | return false; |
| 2226 | |
| 2227 | for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { |
| 2228 | SDOperand BitI = N->getOperand(i); |
| 2229 | SDOperand BitI1 = N->getOperand(i+1); |
| 2230 | |
Evan Cheng | c5cdff2 | 2006-04-07 21:53:05 +0000 | [diff] [blame] | 2231 | if (!isUndefOrEqual(BitI, j)) |
| 2232 | return false; |
| 2233 | if (!isUndefOrEqual(BitI1, j)) |
| 2234 | return false; |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2235 | } |
| 2236 | |
| 2237 | return true; |
| 2238 | } |
| 2239 | |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 2240 | /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form |
| 2241 | /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, |
| 2242 | /// <2, 2, 3, 3> |
| 2243 | bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { |
| 2244 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2245 | |
| 2246 | unsigned NumElems = N->getNumOperands(); |
| 2247 | if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) |
| 2248 | return false; |
| 2249 | |
| 2250 | for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { |
| 2251 | SDOperand BitI = N->getOperand(i); |
| 2252 | SDOperand BitI1 = N->getOperand(i + 1); |
| 2253 | |
| 2254 | if (!isUndefOrEqual(BitI, j)) |
| 2255 | return false; |
| 2256 | if (!isUndefOrEqual(BitI1, j)) |
| 2257 | return false; |
| 2258 | } |
| 2259 | |
| 2260 | return true; |
| 2261 | } |
| 2262 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2263 | /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2264 | /// specifies a shuffle of elements that is suitable for input to MOVSS, |
| 2265 | /// MOVSD, and MOVD, i.e. setting the lowest element. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2266 | static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) { |
Evan Cheng | 1076210 | 2007-12-06 22:14:22 +0000 | [diff] [blame] | 2267 | if (NumElts != 2 && NumElts != 4) |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 2268 | return false; |
| 2269 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2270 | if (!isUndefOrEqual(Elts[0], NumElts)) |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 2271 | return false; |
| 2272 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2273 | for (unsigned i = 1; i < NumElts; ++i) { |
| 2274 | if (!isUndefOrEqual(Elts[i], i)) |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 2275 | return false; |
| 2276 | } |
| 2277 | |
| 2278 | return true; |
| 2279 | } |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 2280 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2281 | bool X86::isMOVLMask(SDNode *N) { |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2282 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2283 | return ::isMOVLMask(N->op_begin(), N->getNumOperands()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2284 | } |
| 2285 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2286 | /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse |
| 2287 | /// of what x86 movss want. X86 movs requires the lowest element to be lowest |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2288 | /// element of vector 2 and the other elements to come from vector 1 in order. |
Roman Levenstein | 9cac525 | 2008-04-16 16:15:27 +0000 | [diff] [blame] | 2289 | static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps, |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2290 | bool V2IsSplat = false, |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 2291 | bool V2IsUndef = false) { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2292 | if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2293 | return false; |
| 2294 | |
| 2295 | if (!isUndefOrEqual(Ops[0], 0)) |
| 2296 | return false; |
| 2297 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2298 | for (unsigned i = 1; i < NumOps; ++i) { |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2299 | SDOperand Arg = Ops[i]; |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2300 | if (!(isUndefOrEqual(Arg, i+NumOps) || |
| 2301 | (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || |
| 2302 | (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 2303 | return false; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2304 | } |
| 2305 | |
| 2306 | return true; |
| 2307 | } |
| 2308 | |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 2309 | static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, |
| 2310 | bool V2IsUndef = false) { |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2311 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2312 | return isCommutedMOVL(N->op_begin(), N->getNumOperands(), |
| 2313 | V2IsSplat, V2IsUndef); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2314 | } |
| 2315 | |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2316 | /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2317 | /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. |
| 2318 | bool X86::isMOVSHDUPMask(SDNode *N) { |
| 2319 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2320 | |
| 2321 | if (N->getNumOperands() != 4) |
| 2322 | return false; |
| 2323 | |
| 2324 | // Expect 1, 1, 3, 3 |
| 2325 | for (unsigned i = 0; i < 2; ++i) { |
| 2326 | SDOperand Arg = N->getOperand(i); |
| 2327 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2328 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2329 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2330 | if (Val != 1) return false; |
| 2331 | } |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2332 | |
| 2333 | bool HasHi = false; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2334 | for (unsigned i = 2; i < 4; ++i) { |
| 2335 | SDOperand Arg = N->getOperand(i); |
| 2336 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2337 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2338 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2339 | if (Val != 3) return false; |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2340 | HasHi = true; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2341 | } |
Evan Cheng | 39fc145 | 2006-04-15 03:13:24 +0000 | [diff] [blame] | 2342 | |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2343 | // Don't use movshdup if it can be done with a shufps. |
| 2344 | return HasHi; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2345 | } |
| 2346 | |
| 2347 | /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2348 | /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. |
| 2349 | bool X86::isMOVSLDUPMask(SDNode *N) { |
| 2350 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2351 | |
| 2352 | if (N->getNumOperands() != 4) |
| 2353 | return false; |
| 2354 | |
| 2355 | // Expect 0, 0, 2, 2 |
| 2356 | for (unsigned i = 0; i < 2; ++i) { |
| 2357 | SDOperand Arg = N->getOperand(i); |
| 2358 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2359 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2360 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2361 | if (Val != 0) return false; |
| 2362 | } |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2363 | |
| 2364 | bool HasHi = false; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2365 | for (unsigned i = 2; i < 4; ++i) { |
| 2366 | SDOperand Arg = N->getOperand(i); |
| 2367 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2368 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2369 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2370 | if (Val != 2) return false; |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2371 | HasHi = true; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2372 | } |
Evan Cheng | 39fc145 | 2006-04-15 03:13:24 +0000 | [diff] [blame] | 2373 | |
Evan Cheng | 57ebe9f | 2006-04-15 05:37:34 +0000 | [diff] [blame] | 2374 | // Don't use movshdup if it can be done with a shufps. |
| 2375 | return HasHi; |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 2376 | } |
| 2377 | |
Evan Cheng | 49892af | 2007-06-19 00:02:56 +0000 | [diff] [blame] | 2378 | /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2379 | /// specifies a identity operation on the LHS or RHS. |
| 2380 | static bool isIdentityMask(SDNode *N, bool RHS = false) { |
| 2381 | unsigned NumElems = N->getNumOperands(); |
| 2382 | for (unsigned i = 0; i < NumElems; ++i) |
| 2383 | if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) |
| 2384 | return false; |
| 2385 | return true; |
| 2386 | } |
| 2387 | |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2388 | /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies |
| 2389 | /// a splat of a single element. |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2390 | static bool isSplatMask(SDNode *N) { |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2391 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2392 | |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2393 | // This is a splat operation if each element of the permute is the same, and |
| 2394 | // if the value doesn't reference the second vector. |
Evan Cheng | 94fe5eb | 2006-04-19 23:28:59 +0000 | [diff] [blame] | 2395 | unsigned NumElems = N->getNumOperands(); |
| 2396 | SDOperand ElementBase; |
| 2397 | unsigned i = 0; |
| 2398 | for (; i != NumElems; ++i) { |
| 2399 | SDOperand Elt = N->getOperand(i); |
Reid Spencer | 3ed469c | 2006-11-02 20:25:50 +0000 | [diff] [blame] | 2400 | if (isa<ConstantSDNode>(Elt)) { |
Evan Cheng | 94fe5eb | 2006-04-19 23:28:59 +0000 | [diff] [blame] | 2401 | ElementBase = Elt; |
| 2402 | break; |
| 2403 | } |
| 2404 | } |
| 2405 | |
| 2406 | if (!ElementBase.Val) |
| 2407 | return false; |
| 2408 | |
| 2409 | for (; i != NumElems; ++i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2410 | SDOperand Arg = N->getOperand(i); |
| 2411 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2412 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
Evan Cheng | 94fe5eb | 2006-04-19 23:28:59 +0000 | [diff] [blame] | 2413 | if (Arg != ElementBase) return false; |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2414 | } |
| 2415 | |
| 2416 | // Make sure it is a splat of the first vector operand. |
Evan Cheng | 94fe5eb | 2006-04-19 23:28:59 +0000 | [diff] [blame] | 2417 | return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2418 | } |
| 2419 | |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2420 | /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies |
| 2421 | /// a splat of a single element and it's a 2 or 4 element mask. |
| 2422 | bool X86::isSplatMask(SDNode *N) { |
| 2423 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2424 | |
Evan Cheng | 94fe5eb | 2006-04-19 23:28:59 +0000 | [diff] [blame] | 2425 | // We can only splat 64-bit, and 32-bit quantities with a single instruction. |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2426 | if (N->getNumOperands() != 4 && N->getNumOperands() != 2) |
| 2427 | return false; |
| 2428 | return ::isSplatMask(N); |
| 2429 | } |
| 2430 | |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 2431 | /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand |
| 2432 | /// specifies a splat of zero element. |
| 2433 | bool X86::isSplatLoMask(SDNode *N) { |
| 2434 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2435 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 2436 | for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 2437 | if (!isUndefOrEqual(N->getOperand(i), 0)) |
| 2438 | return false; |
| 2439 | return true; |
| 2440 | } |
| 2441 | |
Evan Cheng | 63d3300 | 2006-03-22 08:01:21 +0000 | [diff] [blame] | 2442 | /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle |
| 2443 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* |
| 2444 | /// instructions. |
| 2445 | unsigned X86::getShuffleSHUFImmediate(SDNode *N) { |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 2446 | unsigned NumOperands = N->getNumOperands(); |
| 2447 | unsigned Shift = (NumOperands == 4) ? 2 : 1; |
| 2448 | unsigned Mask = 0; |
Evan Cheng | 36b27f3 | 2006-03-28 23:41:33 +0000 | [diff] [blame] | 2449 | for (unsigned i = 0; i < NumOperands; ++i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2450 | unsigned Val = 0; |
| 2451 | SDOperand Arg = N->getOperand(NumOperands-i-1); |
| 2452 | if (Arg.getOpcode() != ISD::UNDEF) |
| 2453 | Val = cast<ConstantSDNode>(Arg)->getValue(); |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 2454 | if (Val >= NumOperands) Val -= NumOperands; |
Evan Cheng | 63d3300 | 2006-03-22 08:01:21 +0000 | [diff] [blame] | 2455 | Mask |= Val; |
Evan Cheng | 36b27f3 | 2006-03-28 23:41:33 +0000 | [diff] [blame] | 2456 | if (i != NumOperands - 1) |
| 2457 | Mask <<= Shift; |
| 2458 | } |
Evan Cheng | 63d3300 | 2006-03-22 08:01:21 +0000 | [diff] [blame] | 2459 | |
| 2460 | return Mask; |
| 2461 | } |
| 2462 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2463 | /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle |
| 2464 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW |
| 2465 | /// instructions. |
| 2466 | unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { |
| 2467 | unsigned Mask = 0; |
| 2468 | // 8 nodes, but we only care about the last 4. |
| 2469 | for (unsigned i = 7; i >= 4; --i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2470 | unsigned Val = 0; |
| 2471 | SDOperand Arg = N->getOperand(i); |
| 2472 | if (Arg.getOpcode() != ISD::UNDEF) |
| 2473 | Val = cast<ConstantSDNode>(Arg)->getValue(); |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2474 | Mask |= (Val - 4); |
| 2475 | if (i != 4) |
| 2476 | Mask <<= 2; |
| 2477 | } |
| 2478 | |
| 2479 | return Mask; |
| 2480 | } |
| 2481 | |
| 2482 | /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle |
| 2483 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW |
| 2484 | /// instructions. |
| 2485 | unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { |
| 2486 | unsigned Mask = 0; |
| 2487 | // 8 nodes, but we only care about the first 4. |
| 2488 | for (int i = 3; i >= 0; --i) { |
Evan Cheng | ef698ca | 2006-03-31 00:30:29 +0000 | [diff] [blame] | 2489 | unsigned Val = 0; |
| 2490 | SDOperand Arg = N->getOperand(i); |
| 2491 | if (Arg.getOpcode() != ISD::UNDEF) |
| 2492 | Val = cast<ConstantSDNode>(Arg)->getValue(); |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 2493 | Mask |= Val; |
| 2494 | if (i != 0) |
| 2495 | Mask <<= 2; |
| 2496 | } |
| 2497 | |
| 2498 | return Mask; |
| 2499 | } |
| 2500 | |
Evan Cheng | c21a053 | 2006-04-05 01:47:37 +0000 | [diff] [blame] | 2501 | /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand |
| 2502 | /// specifies a 8 element shuffle that can be broken into a pair of |
| 2503 | /// PSHUFHW and PSHUFLW. |
| 2504 | static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { |
| 2505 | assert(N->getOpcode() == ISD::BUILD_VECTOR); |
| 2506 | |
| 2507 | if (N->getNumOperands() != 8) |
| 2508 | return false; |
| 2509 | |
| 2510 | // Lower quadword shuffled. |
| 2511 | for (unsigned i = 0; i != 4; ++i) { |
| 2512 | SDOperand Arg = N->getOperand(i); |
| 2513 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2514 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2515 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 2516 | if (Val >= 4) |
Evan Cheng | c21a053 | 2006-04-05 01:47:37 +0000 | [diff] [blame] | 2517 | return false; |
| 2518 | } |
| 2519 | |
| 2520 | // Upper quadword shuffled. |
| 2521 | for (unsigned i = 4; i != 8; ++i) { |
| 2522 | SDOperand Arg = N->getOperand(i); |
| 2523 | if (Arg.getOpcode() == ISD::UNDEF) continue; |
| 2524 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2525 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2526 | if (Val < 4 || Val > 7) |
| 2527 | return false; |
| 2528 | } |
| 2529 | |
| 2530 | return true; |
| 2531 | } |
| 2532 | |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2533 | /// CommuteVectorShuffle - Swap vector_shuffle operands as well as |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2534 | /// values in ther permute mask. |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 2535 | static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, |
| 2536 | SDOperand &V2, SDOperand &Mask, |
| 2537 | SelectionDAG &DAG) { |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2538 | MVT::ValueType VT = Op.getValueType(); |
| 2539 | MVT::ValueType MaskVT = Mask.getValueType(); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2540 | MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2541 | unsigned NumElems = Mask.getNumOperands(); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2542 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2543 | |
| 2544 | for (unsigned i = 0; i != NumElems; ++i) { |
| 2545 | SDOperand Arg = Mask.getOperand(i); |
Evan Cheng | 80d428c | 2006-04-19 22:48:17 +0000 | [diff] [blame] | 2546 | if (Arg.getOpcode() == ISD::UNDEF) { |
| 2547 | MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); |
| 2548 | continue; |
| 2549 | } |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2550 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2551 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2552 | if (Val < NumElems) |
| 2553 | MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); |
| 2554 | else |
| 2555 | MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); |
| 2556 | } |
| 2557 | |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 2558 | std::swap(V1, V2); |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 2559 | Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 2560 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2561 | } |
| 2562 | |
Evan Cheng | 779ccea | 2007-12-07 21:30:01 +0000 | [diff] [blame] | 2563 | /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming |
| 2564 | /// the two vector operands have swapped position. |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 2565 | static |
| 2566 | SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) { |
| 2567 | MVT::ValueType MaskVT = Mask.getValueType(); |
| 2568 | MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); |
| 2569 | unsigned NumElems = Mask.getNumOperands(); |
| 2570 | SmallVector<SDOperand, 8> MaskVec; |
| 2571 | for (unsigned i = 0; i != NumElems; ++i) { |
| 2572 | SDOperand Arg = Mask.getOperand(i); |
| 2573 | if (Arg.getOpcode() == ISD::UNDEF) { |
| 2574 | MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); |
| 2575 | continue; |
| 2576 | } |
| 2577 | assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); |
| 2578 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2579 | if (Val < NumElems) |
| 2580 | MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); |
| 2581 | else |
| 2582 | MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); |
| 2583 | } |
| 2584 | return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); |
| 2585 | } |
| 2586 | |
| 2587 | |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2588 | /// ShouldXformToMOVHLPS - Return true if the node should be transformed to |
| 2589 | /// match movhlps. The lower half elements should come from upper half of |
| 2590 | /// V1 (and in order), and the upper half elements should come from the upper |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 2591 | /// half of V2 (and in order). |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2592 | static bool ShouldXformToMOVHLPS(SDNode *Mask) { |
| 2593 | unsigned NumElems = Mask->getNumOperands(); |
| 2594 | if (NumElems != 4) |
| 2595 | return false; |
| 2596 | for (unsigned i = 0, e = 2; i != e; ++i) |
| 2597 | if (!isUndefOrEqual(Mask->getOperand(i), i+2)) |
| 2598 | return false; |
| 2599 | for (unsigned i = 2; i != 4; ++i) |
| 2600 | if (!isUndefOrEqual(Mask->getOperand(i), i+4)) |
| 2601 | return false; |
| 2602 | return true; |
| 2603 | } |
| 2604 | |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2605 | /// isScalarLoadToVector - Returns true if the node is a scalar load that |
| 2606 | /// is promoted to a vector. |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2607 | static inline bool isScalarLoadToVector(SDNode *N) { |
| 2608 | if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { |
| 2609 | N = N->getOperand(0).Val; |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 2610 | return ISD::isNON_EXTLoad(N); |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2611 | } |
| 2612 | return false; |
| 2613 | } |
| 2614 | |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2615 | /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to |
| 2616 | /// match movlp{s|d}. The lower half elements should come from lower half of |
| 2617 | /// V1 (and in order), and the upper half elements should come from the upper |
| 2618 | /// half of V2 (and in order). And since V1 will become the source of the |
| 2619 | /// MOVLP, it must be either a vector load or a scalar load to vector. |
Evan Cheng | 23425f5 | 2006-10-09 21:39:25 +0000 | [diff] [blame] | 2620 | static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 2621 | if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2622 | return false; |
Evan Cheng | 23425f5 | 2006-10-09 21:39:25 +0000 | [diff] [blame] | 2623 | // Is V2 is a vector load, don't do this transformation. We will try to use |
| 2624 | // load folding shufps op. |
| 2625 | if (ISD::isNON_EXTLoad(V2)) |
| 2626 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2627 | |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 2628 | unsigned NumElems = Mask->getNumOperands(); |
| 2629 | if (NumElems != 2 && NumElems != 4) |
| 2630 | return false; |
| 2631 | for (unsigned i = 0, e = NumElems/2; i != e; ++i) |
| 2632 | if (!isUndefOrEqual(Mask->getOperand(i), i)) |
| 2633 | return false; |
| 2634 | for (unsigned i = NumElems/2; i != NumElems; ++i) |
| 2635 | if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) |
| 2636 | return false; |
| 2637 | return true; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2638 | } |
| 2639 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2640 | /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are |
| 2641 | /// all the same. |
| 2642 | static bool isSplatVector(SDNode *N) { |
| 2643 | if (N->getOpcode() != ISD::BUILD_VECTOR) |
| 2644 | return false; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2645 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2646 | SDOperand SplatValue = N->getOperand(0); |
| 2647 | for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) |
| 2648 | if (N->getOperand(i) != SplatValue) |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 2649 | return false; |
| 2650 | return true; |
| 2651 | } |
| 2652 | |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 2653 | /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved |
| 2654 | /// to an undef. |
| 2655 | static bool isUndefShuffle(SDNode *N) { |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2656 | if (N->getOpcode() != ISD::VECTOR_SHUFFLE) |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 2657 | return false; |
| 2658 | |
| 2659 | SDOperand V1 = N->getOperand(0); |
| 2660 | SDOperand V2 = N->getOperand(1); |
| 2661 | SDOperand Mask = N->getOperand(2); |
| 2662 | unsigned NumElems = Mask.getNumOperands(); |
| 2663 | for (unsigned i = 0; i != NumElems; ++i) { |
| 2664 | SDOperand Arg = Mask.getOperand(i); |
| 2665 | if (Arg.getOpcode() != ISD::UNDEF) { |
| 2666 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2667 | if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) |
| 2668 | return false; |
| 2669 | else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) |
| 2670 | return false; |
| 2671 | } |
| 2672 | } |
| 2673 | return true; |
| 2674 | } |
| 2675 | |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2676 | /// isZeroNode - Returns true if Elt is a constant zero or a floating point |
| 2677 | /// constant +0.0. |
| 2678 | static inline bool isZeroNode(SDOperand Elt) { |
| 2679 | return ((isa<ConstantSDNode>(Elt) && |
| 2680 | cast<ConstantSDNode>(Elt)->getValue() == 0) || |
| 2681 | (isa<ConstantFPSDNode>(Elt) && |
Dale Johannesen | eaf0894 | 2007-08-31 04:03:46 +0000 | [diff] [blame] | 2682 | cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2683 | } |
| 2684 | |
| 2685 | /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved |
| 2686 | /// to an zero vector. |
| 2687 | static bool isZeroShuffle(SDNode *N) { |
| 2688 | if (N->getOpcode() != ISD::VECTOR_SHUFFLE) |
| 2689 | return false; |
| 2690 | |
| 2691 | SDOperand V1 = N->getOperand(0); |
| 2692 | SDOperand V2 = N->getOperand(1); |
| 2693 | SDOperand Mask = N->getOperand(2); |
| 2694 | unsigned NumElems = Mask.getNumOperands(); |
| 2695 | for (unsigned i = 0; i != NumElems; ++i) { |
| 2696 | SDOperand Arg = Mask.getOperand(i); |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2697 | if (Arg.getOpcode() == ISD::UNDEF) |
| 2698 | continue; |
| 2699 | |
| 2700 | unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); |
| 2701 | if (Idx < NumElems) { |
| 2702 | unsigned Opc = V1.Val->getOpcode(); |
| 2703 | if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val)) |
| 2704 | continue; |
| 2705 | if (Opc != ISD::BUILD_VECTOR || |
| 2706 | !isZeroNode(V1.Val->getOperand(Idx))) |
| 2707 | return false; |
| 2708 | } else if (Idx >= NumElems) { |
| 2709 | unsigned Opc = V2.Val->getOpcode(); |
| 2710 | if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val)) |
| 2711 | continue; |
| 2712 | if (Opc != ISD::BUILD_VECTOR || |
| 2713 | !isZeroNode(V2.Val->getOperand(Idx - NumElems))) |
| 2714 | return false; |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2715 | } |
| 2716 | } |
| 2717 | return true; |
| 2718 | } |
| 2719 | |
| 2720 | /// getZeroVector - Returns a vector of specified type with all zero elements. |
| 2721 | /// |
| 2722 | static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) { |
| 2723 | assert(MVT::isVector(VT) && "Expected a vector type"); |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2724 | |
| 2725 | // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest |
| 2726 | // type. This ensures they get CSE'd. |
| 2727 | SDOperand Cst = DAG.getTargetConstant(0, MVT::i32); |
| 2728 | SDOperand Vec; |
| 2729 | if (MVT::getSizeInBits(VT) == 64) // MMX |
| 2730 | Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); |
| 2731 | else // SSE |
| 2732 | Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); |
| 2733 | return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 2734 | } |
| 2735 | |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2736 | /// getOnesVector - Returns a vector of specified type with all bits set. |
| 2737 | /// |
| 2738 | static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) { |
| 2739 | assert(MVT::isVector(VT) && "Expected a vector type"); |
| 2740 | |
| 2741 | // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest |
| 2742 | // type. This ensures they get CSE'd. |
| 2743 | SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32); |
| 2744 | SDOperand Vec; |
| 2745 | if (MVT::getSizeInBits(VT) == 64) // MMX |
| 2746 | Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); |
| 2747 | else // SSE |
| 2748 | Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); |
| 2749 | return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); |
| 2750 | } |
| 2751 | |
| 2752 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2753 | /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements |
| 2754 | /// that point to V2 points to its first element. |
| 2755 | static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { |
| 2756 | assert(Mask.getOpcode() == ISD::BUILD_VECTOR); |
| 2757 | |
| 2758 | bool Changed = false; |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2759 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2760 | unsigned NumElems = Mask.getNumOperands(); |
| 2761 | for (unsigned i = 0; i != NumElems; ++i) { |
| 2762 | SDOperand Arg = Mask.getOperand(i); |
| 2763 | if (Arg.getOpcode() != ISD::UNDEF) { |
| 2764 | unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); |
| 2765 | if (Val > NumElems) { |
| 2766 | Arg = DAG.getConstant(NumElems, Arg.getValueType()); |
| 2767 | Changed = true; |
| 2768 | } |
| 2769 | } |
| 2770 | MaskVec.push_back(Arg); |
| 2771 | } |
| 2772 | |
| 2773 | if (Changed) |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 2774 | Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), |
| 2775 | &MaskVec[0], MaskVec.size()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2776 | return Mask; |
| 2777 | } |
| 2778 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2779 | /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd |
| 2780 | /// operation of specified width. |
| 2781 | static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2782 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2783 | MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2784 | |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2785 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2786 | MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); |
| 2787 | for (unsigned i = 1; i != NumElems; ++i) |
| 2788 | MaskVec.push_back(DAG.getConstant(i, BaseVT)); |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 2789 | return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2790 | } |
| 2791 | |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2792 | /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation |
| 2793 | /// of specified width. |
| 2794 | static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { |
| 2795 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2796 | MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2797 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2798 | for (unsigned i = 0, e = NumElems/2; i != e; ++i) { |
| 2799 | MaskVec.push_back(DAG.getConstant(i, BaseVT)); |
| 2800 | MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); |
| 2801 | } |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 2802 | return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2803 | } |
| 2804 | |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2805 | /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation |
| 2806 | /// of specified width. |
| 2807 | static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { |
| 2808 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2809 | MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2810 | unsigned Half = NumElems/2; |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 2811 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2812 | for (unsigned i = 0; i != Half; ++i) { |
| 2813 | MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); |
| 2814 | MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); |
| 2815 | } |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 2816 | return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 2817 | } |
| 2818 | |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 2819 | /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps |
| 2820 | /// element #0 of a vector with the specified index, leaving the rest of the |
| 2821 | /// elements in place. |
| 2822 | static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, |
| 2823 | SelectionDAG &DAG) { |
| 2824 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
| 2825 | MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); |
| 2826 | SmallVector<SDOperand, 8> MaskVec; |
| 2827 | // Element #0 of the result gets the elt we are replacing. |
| 2828 | MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); |
| 2829 | for (unsigned i = 1; i != NumElems; ++i) |
| 2830 | MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); |
| 2831 | return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); |
| 2832 | } |
| 2833 | |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 2834 | /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. |
| 2835 | static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) { |
| 2836 | MVT::ValueType PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; |
| 2837 | MVT::ValueType VT = Op.getValueType(); |
| 2838 | if (PVT == VT) |
| 2839 | return Op; |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2840 | SDOperand V1 = Op.getOperand(0); |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2841 | SDOperand Mask = Op.getOperand(2); |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2842 | unsigned NumElems = Mask.getNumOperands(); |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 2843 | // Special handling of v4f32 -> v4i32. |
| 2844 | if (VT != MVT::v4f32) { |
| 2845 | Mask = getUnpacklMask(NumElems, DAG); |
| 2846 | while (NumElems > 4) { |
| 2847 | V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); |
| 2848 | NumElems >>= 1; |
| 2849 | } |
| 2850 | Mask = getZeroVector(MVT::v4i32, DAG); |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2851 | } |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2852 | |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 2853 | V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); |
| 2854 | SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, |
| 2855 | DAG.getNode(ISD::UNDEF, PVT), Mask); |
Evan Cheng | c575ca2 | 2006-04-17 20:43:08 +0000 | [diff] [blame] | 2856 | return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); |
| 2857 | } |
| 2858 | |
Evan Cheng | ba05f72 | 2006-04-21 23:03:30 +0000 | [diff] [blame] | 2859 | /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2860 | /// vector of zero or undef vector. This produces a shuffle where the low |
| 2861 | /// element of V2 is swizzled into the zero/undef vector, landing at element |
| 2862 | /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 2863 | static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx, |
Evan Cheng | ba05f72 | 2006-04-21 23:03:30 +0000 | [diff] [blame] | 2864 | bool isZero, SelectionDAG &DAG) { |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 2865 | MVT::ValueType VT = V2.getValueType(); |
Evan Cheng | ba05f72 | 2006-04-21 23:03:30 +0000 | [diff] [blame] | 2866 | SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT); |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 2867 | unsigned NumElems = MVT::getVectorNumElements(V2.getValueType()); |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2868 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2869 | MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2870 | SmallVector<SDOperand, 16> MaskVec; |
| 2871 | for (unsigned i = 0; i != NumElems; ++i) |
| 2872 | if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. |
| 2873 | MaskVec.push_back(DAG.getConstant(NumElems, EVT)); |
| 2874 | else |
| 2875 | MaskVec.push_back(DAG.getConstant(i, EVT)); |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 2876 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 2877 | &MaskVec[0], MaskVec.size()); |
Evan Cheng | ba05f72 | 2006-04-21 23:03:30 +0000 | [diff] [blame] | 2878 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 2879 | } |
| 2880 | |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2881 | /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. |
| 2882 | /// |
| 2883 | static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, |
| 2884 | unsigned NumNonZero, unsigned NumZero, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2885 | SelectionDAG &DAG, TargetLowering &TLI) { |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2886 | if (NumNonZero > 8) |
| 2887 | return SDOperand(); |
| 2888 | |
| 2889 | SDOperand V(0, 0); |
| 2890 | bool First = true; |
| 2891 | for (unsigned i = 0; i < 16; ++i) { |
| 2892 | bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; |
| 2893 | if (ThisIsNonZero && First) { |
| 2894 | if (NumZero) |
| 2895 | V = getZeroVector(MVT::v8i16, DAG); |
| 2896 | else |
| 2897 | V = DAG.getNode(ISD::UNDEF, MVT::v8i16); |
| 2898 | First = false; |
| 2899 | } |
| 2900 | |
| 2901 | if ((i & 1) != 0) { |
| 2902 | SDOperand ThisElt(0, 0), LastElt(0, 0); |
| 2903 | bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; |
| 2904 | if (LastIsNonZero) { |
| 2905 | LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); |
| 2906 | } |
| 2907 | if (ThisIsNonZero) { |
| 2908 | ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); |
| 2909 | ThisElt = DAG.getNode(ISD::SHL, MVT::i16, |
| 2910 | ThisElt, DAG.getConstant(8, MVT::i8)); |
| 2911 | if (LastIsNonZero) |
| 2912 | ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); |
| 2913 | } else |
| 2914 | ThisElt = LastElt; |
| 2915 | |
| 2916 | if (ThisElt.Val) |
| 2917 | V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 2918 | DAG.getIntPtrConstant(i/2)); |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2919 | } |
| 2920 | } |
| 2921 | |
| 2922 | return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); |
| 2923 | } |
| 2924 | |
Bill Wendling | a348c56 | 2007-03-22 18:42:45 +0000 | [diff] [blame] | 2925 | /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2926 | /// |
| 2927 | static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, |
| 2928 | unsigned NumNonZero, unsigned NumZero, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2929 | SelectionDAG &DAG, TargetLowering &TLI) { |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2930 | if (NumNonZero > 4) |
| 2931 | return SDOperand(); |
| 2932 | |
| 2933 | SDOperand V(0, 0); |
| 2934 | bool First = true; |
| 2935 | for (unsigned i = 0; i < 8; ++i) { |
| 2936 | bool isNonZero = (NonZeros & (1 << i)) != 0; |
| 2937 | if (isNonZero) { |
| 2938 | if (First) { |
| 2939 | if (NumZero) |
| 2940 | V = getZeroVector(MVT::v8i16, DAG); |
| 2941 | else |
| 2942 | V = DAG.getNode(ISD::UNDEF, MVT::v8i16); |
| 2943 | First = false; |
| 2944 | } |
| 2945 | V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 2946 | DAG.getIntPtrConstant(i)); |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 2947 | } |
| 2948 | } |
| 2949 | |
| 2950 | return V; |
| 2951 | } |
| 2952 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2953 | SDOperand |
| 2954 | X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2955 | // All zero's are handled with pxor, all one's are handled with pcmpeqd. |
| 2956 | if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) { |
| 2957 | // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to |
| 2958 | // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are |
| 2959 | // eliminated on x86-32 hosts. |
| 2960 | if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) |
| 2961 | return Op; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2962 | |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2963 | if (ISD::isBuildVectorAllOnes(Op.Val)) |
| 2964 | return getOnesVector(Op.getValueType(), DAG); |
| 2965 | return getZeroVector(Op.getValueType(), DAG); |
| 2966 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2967 | |
| 2968 | MVT::ValueType VT = Op.getValueType(); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 2969 | MVT::ValueType EVT = MVT::getVectorElementType(VT); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2970 | unsigned EVTBits = MVT::getSizeInBits(EVT); |
| 2971 | |
| 2972 | unsigned NumElems = Op.getNumOperands(); |
| 2973 | unsigned NumZero = 0; |
| 2974 | unsigned NumNonZero = 0; |
| 2975 | unsigned NonZeros = 0; |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 2976 | bool IsAllConstants = true; |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 2977 | SmallSet<SDOperand, 8> Values; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2978 | for (unsigned i = 0; i < NumElems; ++i) { |
| 2979 | SDOperand Elt = Op.getOperand(i); |
Evan Cheng | db2d524 | 2007-12-12 06:45:40 +0000 | [diff] [blame] | 2980 | if (Elt.getOpcode() == ISD::UNDEF) |
| 2981 | continue; |
| 2982 | Values.insert(Elt); |
| 2983 | if (Elt.getOpcode() != ISD::Constant && |
| 2984 | Elt.getOpcode() != ISD::ConstantFP) |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 2985 | IsAllConstants = false; |
Evan Cheng | db2d524 | 2007-12-12 06:45:40 +0000 | [diff] [blame] | 2986 | if (isZeroNode(Elt)) |
| 2987 | NumZero++; |
| 2988 | else { |
| 2989 | NonZeros |= (1 << i); |
| 2990 | NumNonZero++; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2991 | } |
| 2992 | } |
| 2993 | |
Dan Gohman | 7f32156 | 2007-06-25 16:23:39 +0000 | [diff] [blame] | 2994 | if (NumNonZero == 0) { |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 2995 | // All undef vector. Return an UNDEF. All zero vectors were handled above. |
| 2996 | return DAG.getNode(ISD::UNDEF, VT); |
Dan Gohman | 7f32156 | 2007-06-25 16:23:39 +0000 | [diff] [blame] | 2997 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 2998 | |
Chris Lattner | 67f453a | 2008-03-09 05:42:06 +0000 | [diff] [blame] | 2999 | // Special case for single non-zero, non-undef, element. |
Evan Cheng | db2d524 | 2007-12-12 06:45:40 +0000 | [diff] [blame] | 3000 | if (NumNonZero == 1 && NumElems <= 4) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3001 | unsigned Idx = CountTrailingZeros_32(NonZeros); |
| 3002 | SDOperand Item = Op.getOperand(Idx); |
Chris Lattner | 19f7969 | 2008-03-08 22:59:52 +0000 | [diff] [blame] | 3003 | |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 3004 | // If this is an insertion of an i64 value on x86-32, and if the top bits of |
| 3005 | // the value are obviously zero, truncate the value to i32 and do the |
| 3006 | // insertion that way. Only do this if the value is non-constant or if the |
| 3007 | // value is a constant being inserted into element 0. It is cheaper to do |
| 3008 | // a constant pool load than it is to do a movd + shuffle. |
| 3009 | if (EVT == MVT::i64 && !Subtarget->is64Bit() && |
| 3010 | (!IsAllConstants || Idx == 0)) { |
| 3011 | if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { |
| 3012 | // Handle MMX and SSE both. |
| 3013 | MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; |
| 3014 | MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2; |
| 3015 | |
| 3016 | // Truncate the value (which may itself be a constant) to i32, and |
| 3017 | // convert it to a vector with movd (S2V+shuffle to zero extend). |
| 3018 | Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); |
| 3019 | Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); |
| 3020 | Item = getShuffleVectorZeroOrUndef(Item, 0, true, DAG); |
| 3021 | |
| 3022 | // Now we have our 32-bit value zero extended in the low element of |
| 3023 | // a vector. If Idx != 0, swizzle it into place. |
| 3024 | if (Idx != 0) { |
| 3025 | SDOperand Ops[] = { |
| 3026 | Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), |
| 3027 | getSwapEltZeroMask(VecElts, Idx, DAG) |
| 3028 | }; |
| 3029 | Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); |
| 3030 | } |
| 3031 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); |
| 3032 | } |
| 3033 | } |
| 3034 | |
Chris Lattner | 19f7969 | 2008-03-08 22:59:52 +0000 | [diff] [blame] | 3035 | // If we have a constant or non-constant insertion into the low element of |
| 3036 | // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into |
| 3037 | // the rest of the elements. This will be matched as movd/movq/movss/movsd |
| 3038 | // depending on what the source datatype is. Because we can only get here |
| 3039 | // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. |
| 3040 | if (Idx == 0 && |
| 3041 | // Don't do this for i64 values on x86-32. |
| 3042 | (EVT != MVT::i64 || Subtarget->is64Bit())) { |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 3043 | Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3044 | // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 3045 | return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG); |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 3046 | } |
| 3047 | |
| 3048 | if (IsAllConstants) // Otherwise, it's better to do a constpool load. |
Evan Cheng | db2d524 | 2007-12-12 06:45:40 +0000 | [diff] [blame] | 3049 | return SDOperand(); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3050 | |
Chris Lattner | 19f7969 | 2008-03-08 22:59:52 +0000 | [diff] [blame] | 3051 | // Otherwise, if this is a vector with i32 or f32 elements, and the element |
| 3052 | // is a non-constant being inserted into an element other than the low one, |
| 3053 | // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka |
| 3054 | // movd/movss) to move this into the low element, then shuffle it into |
| 3055 | // place. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3056 | if (EVTBits == 32) { |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 3057 | Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); |
| 3058 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3059 | // Turn it into a shuffle of zero and zero-extended scalar to vector. |
Chris Lattner | 6209804 | 2008-03-09 01:05:04 +0000 | [diff] [blame] | 3060 | Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3061 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 3062 | MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3063 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3064 | for (unsigned i = 0; i < NumElems; i++) |
| 3065 | MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 3066 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3067 | &MaskVec[0], MaskVec.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3068 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, |
| 3069 | DAG.getNode(ISD::UNDEF, VT), Mask); |
| 3070 | } |
| 3071 | } |
| 3072 | |
Chris Lattner | 67f453a | 2008-03-09 05:42:06 +0000 | [diff] [blame] | 3073 | // Splat is obviously ok. Let legalizer expand it to a shuffle. |
| 3074 | if (Values.size() == 1) |
| 3075 | return SDOperand(); |
| 3076 | |
Dan Gohman | a394117 | 2007-07-24 22:55:08 +0000 | [diff] [blame] | 3077 | // A vector full of immediates; various special cases are already |
| 3078 | // handled, so this is best done with a single constant-pool load. |
Chris Lattner | c9517fb | 2008-03-08 22:48:29 +0000 | [diff] [blame] | 3079 | if (IsAllConstants) |
Dan Gohman | a394117 | 2007-07-24 22:55:08 +0000 | [diff] [blame] | 3080 | return SDOperand(); |
| 3081 | |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 3082 | // Let legalizer expand 2-wide build_vectors. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3083 | if (EVTBits == 64) |
| 3084 | return SDOperand(); |
| 3085 | |
| 3086 | // If element VT is < 32 bits, convert it to inserts into a zero vector. |
Bill Wendling | 826f36f | 2007-03-28 00:57:11 +0000 | [diff] [blame] | 3087 | if (EVTBits == 8 && NumElems == 16) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3088 | SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, |
| 3089 | *this); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3090 | if (V.Val) return V; |
| 3091 | } |
| 3092 | |
Bill Wendling | 826f36f | 2007-03-28 00:57:11 +0000 | [diff] [blame] | 3093 | if (EVTBits == 16 && NumElems == 8) { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 3094 | SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, |
| 3095 | *this); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3096 | if (V.Val) return V; |
| 3097 | } |
| 3098 | |
| 3099 | // If element VT is == 32 bits, turn it into a number of shuffles. |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3100 | SmallVector<SDOperand, 8> V; |
| 3101 | V.resize(NumElems); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3102 | if (NumElems == 4 && NumZero > 0) { |
| 3103 | for (unsigned i = 0; i < 4; ++i) { |
| 3104 | bool isZero = !(NonZeros & (1 << i)); |
| 3105 | if (isZero) |
| 3106 | V[i] = getZeroVector(VT, DAG); |
| 3107 | else |
| 3108 | V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); |
| 3109 | } |
| 3110 | |
| 3111 | for (unsigned i = 0; i < 2; ++i) { |
| 3112 | switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { |
| 3113 | default: break; |
| 3114 | case 0: |
| 3115 | V[i] = V[i*2]; // Must be a zero vector. |
| 3116 | break; |
| 3117 | case 1: |
| 3118 | V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], |
| 3119 | getMOVLMask(NumElems, DAG)); |
| 3120 | break; |
| 3121 | case 2: |
| 3122 | V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], |
| 3123 | getMOVLMask(NumElems, DAG)); |
| 3124 | break; |
| 3125 | case 3: |
| 3126 | V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], |
| 3127 | getUnpacklMask(NumElems, DAG)); |
| 3128 | break; |
| 3129 | } |
| 3130 | } |
| 3131 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3132 | // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 3133 | // clears the upper bits. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3134 | // FIXME: we can do the same for v4f32 case when we know both parts of |
| 3135 | // the lower half come from scalar_to_vector (loadf32). We should do |
| 3136 | // that in post legalizer dag combiner with target specific hooks. |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3137 | if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3138 | return V[0]; |
| 3139 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 3140 | MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3141 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3142 | bool Reverse = (NonZeros & 0x3) == 2; |
| 3143 | for (unsigned i = 0; i < 2; ++i) |
| 3144 | if (Reverse) |
| 3145 | MaskVec.push_back(DAG.getConstant(1-i, EVT)); |
| 3146 | else |
| 3147 | MaskVec.push_back(DAG.getConstant(i, EVT)); |
| 3148 | Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; |
| 3149 | for (unsigned i = 0; i < 2; ++i) |
| 3150 | if (Reverse) |
| 3151 | MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); |
| 3152 | else |
| 3153 | MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3154 | SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3155 | &MaskVec[0], MaskVec.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3156 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); |
| 3157 | } |
| 3158 | |
| 3159 | if (Values.size() > 2) { |
| 3160 | // Expand into a number of unpckl*. |
| 3161 | // e.g. for v4f32 |
| 3162 | // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> |
| 3163 | // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> |
| 3164 | // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> |
| 3165 | SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); |
| 3166 | for (unsigned i = 0; i < NumElems; ++i) |
| 3167 | V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); |
| 3168 | NumElems >>= 1; |
| 3169 | while (NumElems != 0) { |
| 3170 | for (unsigned i = 0; i < NumElems; ++i) |
| 3171 | V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], |
| 3172 | UnpckMask); |
| 3173 | NumElems >>= 1; |
| 3174 | } |
| 3175 | return V[0]; |
| 3176 | } |
| 3177 | |
| 3178 | return SDOperand(); |
| 3179 | } |
| 3180 | |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3181 | static |
| 3182 | SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, |
| 3183 | SDOperand PermMask, SelectionDAG &DAG, |
| 3184 | TargetLowering &TLI) { |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3185 | SDOperand NewV; |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3186 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8); |
| 3187 | MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3188 | MVT::ValueType PtrVT = TLI.getPointerTy(); |
| 3189 | SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(), |
| 3190 | PermMask.Val->op_end()); |
| 3191 | |
| 3192 | // First record which half of which vector the low elements come from. |
| 3193 | SmallVector<unsigned, 4> LowQuad(4); |
| 3194 | for (unsigned i = 0; i < 4; ++i) { |
| 3195 | SDOperand Elt = MaskElts[i]; |
| 3196 | if (Elt.getOpcode() == ISD::UNDEF) |
| 3197 | continue; |
| 3198 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3199 | int QuadIdx = EltIdx / 4; |
| 3200 | ++LowQuad[QuadIdx]; |
| 3201 | } |
| 3202 | int BestLowQuad = -1; |
| 3203 | unsigned MaxQuad = 1; |
| 3204 | for (unsigned i = 0; i < 4; ++i) { |
| 3205 | if (LowQuad[i] > MaxQuad) { |
| 3206 | BestLowQuad = i; |
| 3207 | MaxQuad = LowQuad[i]; |
| 3208 | } |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3209 | } |
| 3210 | |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3211 | // Record which half of which vector the high elements come from. |
| 3212 | SmallVector<unsigned, 4> HighQuad(4); |
| 3213 | for (unsigned i = 4; i < 8; ++i) { |
| 3214 | SDOperand Elt = MaskElts[i]; |
| 3215 | if (Elt.getOpcode() == ISD::UNDEF) |
| 3216 | continue; |
| 3217 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3218 | int QuadIdx = EltIdx / 4; |
| 3219 | ++HighQuad[QuadIdx]; |
| 3220 | } |
| 3221 | int BestHighQuad = -1; |
| 3222 | MaxQuad = 1; |
| 3223 | for (unsigned i = 0; i < 4; ++i) { |
| 3224 | if (HighQuad[i] > MaxQuad) { |
| 3225 | BestHighQuad = i; |
| 3226 | MaxQuad = HighQuad[i]; |
| 3227 | } |
| 3228 | } |
| 3229 | |
| 3230 | // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. |
| 3231 | if (BestLowQuad != -1 || BestHighQuad != -1) { |
| 3232 | // First sort the 4 chunks in order using shufpd. |
| 3233 | SmallVector<SDOperand, 8> MaskVec; |
| 3234 | if (BestLowQuad != -1) |
| 3235 | MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); |
| 3236 | else |
| 3237 | MaskVec.push_back(DAG.getConstant(0, MVT::i32)); |
| 3238 | if (BestHighQuad != -1) |
| 3239 | MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); |
| 3240 | else |
| 3241 | MaskVec.push_back(DAG.getConstant(1, MVT::i32)); |
| 3242 | SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); |
| 3243 | NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, |
| 3244 | DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), |
| 3245 | DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); |
| 3246 | NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); |
| 3247 | |
| 3248 | // Now sort high and low parts separately. |
| 3249 | BitVector InOrder(8); |
| 3250 | if (BestLowQuad != -1) { |
| 3251 | // Sort lower half in order using PSHUFLW. |
| 3252 | MaskVec.clear(); |
| 3253 | bool AnyOutOrder = false; |
| 3254 | for (unsigned i = 0; i != 4; ++i) { |
| 3255 | SDOperand Elt = MaskElts[i]; |
| 3256 | if (Elt.getOpcode() == ISD::UNDEF) { |
| 3257 | MaskVec.push_back(Elt); |
| 3258 | InOrder.set(i); |
| 3259 | } else { |
| 3260 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3261 | if (EltIdx != i) |
| 3262 | AnyOutOrder = true; |
| 3263 | MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT)); |
| 3264 | // If this element is in the right place after this shuffle, then |
| 3265 | // remember it. |
| 3266 | if ((int)(EltIdx / 4) == BestLowQuad) |
| 3267 | InOrder.set(i); |
| 3268 | } |
| 3269 | } |
| 3270 | if (AnyOutOrder) { |
| 3271 | for (unsigned i = 4; i != 8; ++i) |
| 3272 | MaskVec.push_back(DAG.getConstant(i, MaskEVT)); |
| 3273 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); |
| 3274 | NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); |
| 3275 | } |
| 3276 | } |
| 3277 | |
| 3278 | if (BestHighQuad != -1) { |
| 3279 | // Sort high half in order using PSHUFHW if possible. |
| 3280 | MaskVec.clear(); |
| 3281 | for (unsigned i = 0; i != 4; ++i) |
| 3282 | MaskVec.push_back(DAG.getConstant(i, MaskEVT)); |
| 3283 | bool AnyOutOrder = false; |
| 3284 | for (unsigned i = 4; i != 8; ++i) { |
| 3285 | SDOperand Elt = MaskElts[i]; |
| 3286 | if (Elt.getOpcode() == ISD::UNDEF) { |
| 3287 | MaskVec.push_back(Elt); |
| 3288 | InOrder.set(i); |
| 3289 | } else { |
| 3290 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3291 | if (EltIdx != i) |
| 3292 | AnyOutOrder = true; |
| 3293 | MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT)); |
| 3294 | // If this element is in the right place after this shuffle, then |
| 3295 | // remember it. |
| 3296 | if ((int)(EltIdx / 4) == BestHighQuad) |
| 3297 | InOrder.set(i); |
| 3298 | } |
| 3299 | } |
| 3300 | if (AnyOutOrder) { |
| 3301 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); |
| 3302 | NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); |
| 3303 | } |
| 3304 | } |
| 3305 | |
| 3306 | // The other elements are put in the right place using pextrw and pinsrw. |
| 3307 | for (unsigned i = 0; i != 8; ++i) { |
| 3308 | if (InOrder[i]) |
| 3309 | continue; |
| 3310 | SDOperand Elt = MaskElts[i]; |
| 3311 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3312 | if (EltIdx == i) |
| 3313 | continue; |
| 3314 | SDOperand ExtOp = (EltIdx < 8) |
| 3315 | ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, |
| 3316 | DAG.getConstant(EltIdx, PtrVT)) |
| 3317 | : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, |
| 3318 | DAG.getConstant(EltIdx - 8, PtrVT)); |
| 3319 | NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, |
| 3320 | DAG.getConstant(i, PtrVT)); |
| 3321 | } |
| 3322 | return NewV; |
| 3323 | } |
| 3324 | |
| 3325 | // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use |
| 3326 | ///as few as possible. |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3327 | // First, let's find out how many elements are already in the right order. |
| 3328 | unsigned V1InOrder = 0; |
| 3329 | unsigned V1FromV1 = 0; |
| 3330 | unsigned V2InOrder = 0; |
| 3331 | unsigned V2FromV2 = 0; |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3332 | SmallVector<SDOperand, 8> V1Elts; |
| 3333 | SmallVector<SDOperand, 8> V2Elts; |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3334 | for (unsigned i = 0; i < 8; ++i) { |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3335 | SDOperand Elt = MaskElts[i]; |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3336 | if (Elt.getOpcode() == ISD::UNDEF) { |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3337 | V1Elts.push_back(Elt); |
| 3338 | V2Elts.push_back(Elt); |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3339 | ++V1InOrder; |
| 3340 | ++V2InOrder; |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3341 | continue; |
| 3342 | } |
| 3343 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3344 | if (EltIdx == i) { |
| 3345 | V1Elts.push_back(Elt); |
| 3346 | V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); |
| 3347 | ++V1InOrder; |
| 3348 | } else if (EltIdx == i+8) { |
| 3349 | V1Elts.push_back(Elt); |
| 3350 | V2Elts.push_back(DAG.getConstant(i, MaskEVT)); |
| 3351 | ++V2InOrder; |
| 3352 | } else if (EltIdx < 8) { |
| 3353 | V1Elts.push_back(Elt); |
| 3354 | ++V1FromV1; |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3355 | } else { |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3356 | V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT)); |
| 3357 | ++V2FromV2; |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3358 | } |
| 3359 | } |
| 3360 | |
| 3361 | if (V2InOrder > V1InOrder) { |
| 3362 | PermMask = CommuteVectorShuffleMask(PermMask, DAG); |
| 3363 | std::swap(V1, V2); |
| 3364 | std::swap(V1Elts, V2Elts); |
| 3365 | std::swap(V1FromV1, V2FromV2); |
| 3366 | } |
| 3367 | |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3368 | if ((V1FromV1 + V1InOrder) != 8) { |
| 3369 | // Some elements are from V2. |
| 3370 | if (V1FromV1) { |
| 3371 | // If there are elements that are from V1 but out of place, |
| 3372 | // then first sort them in place |
| 3373 | SmallVector<SDOperand, 8> MaskVec; |
| 3374 | for (unsigned i = 0; i < 8; ++i) { |
| 3375 | SDOperand Elt = V1Elts[i]; |
| 3376 | if (Elt.getOpcode() == ISD::UNDEF) { |
| 3377 | MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3378 | continue; |
| 3379 | } |
| 3380 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3381 | if (EltIdx >= 8) |
| 3382 | MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3383 | else |
| 3384 | MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); |
| 3385 | } |
| 3386 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); |
| 3387 | V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3388 | } |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3389 | |
| 3390 | NewV = V1; |
| 3391 | for (unsigned i = 0; i < 8; ++i) { |
| 3392 | SDOperand Elt = V1Elts[i]; |
| 3393 | if (Elt.getOpcode() == ISD::UNDEF) |
| 3394 | continue; |
| 3395 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3396 | if (EltIdx < 8) |
| 3397 | continue; |
| 3398 | SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, |
| 3399 | DAG.getConstant(EltIdx - 8, PtrVT)); |
| 3400 | NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, |
| 3401 | DAG.getConstant(i, PtrVT)); |
| 3402 | } |
| 3403 | return NewV; |
| 3404 | } else { |
| 3405 | // All elements are from V1. |
| 3406 | NewV = V1; |
| 3407 | for (unsigned i = 0; i < 8; ++i) { |
| 3408 | SDOperand Elt = V1Elts[i]; |
| 3409 | if (Elt.getOpcode() == ISD::UNDEF) |
| 3410 | continue; |
| 3411 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3412 | SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, |
| 3413 | DAG.getConstant(EltIdx, PtrVT)); |
| 3414 | NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, |
| 3415 | DAG.getConstant(i, PtrVT)); |
| 3416 | } |
| 3417 | return NewV; |
| 3418 | } |
| 3419 | } |
| 3420 | |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3421 | /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide |
| 3422 | /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be |
| 3423 | /// done when every pair / quad of shuffle mask elements point to elements in |
| 3424 | /// the right sequence. e.g. |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3425 | /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> |
| 3426 | static |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3427 | SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, |
| 3428 | MVT::ValueType VT, |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3429 | SDOperand PermMask, SelectionDAG &DAG, |
| 3430 | TargetLowering &TLI) { |
| 3431 | unsigned NumElems = PermMask.getNumOperands(); |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3432 | unsigned NewWidth = (NumElems == 4) ? 2 : 4; |
| 3433 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth); |
| 3434 | MVT::ValueType NewVT = MaskVT; |
| 3435 | switch (VT) { |
| 3436 | case MVT::v4f32: NewVT = MVT::v2f64; break; |
| 3437 | case MVT::v4i32: NewVT = MVT::v2i64; break; |
| 3438 | case MVT::v8i16: NewVT = MVT::v4i32; break; |
| 3439 | case MVT::v16i8: NewVT = MVT::v4i32; break; |
| 3440 | default: assert(false && "Unexpected!"); |
| 3441 | } |
| 3442 | |
Anton Korobeynikov | 7c1c261 | 2008-02-20 11:22:39 +0000 | [diff] [blame] | 3443 | if (NewWidth == 2) { |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3444 | if (MVT::isInteger(VT)) |
| 3445 | NewVT = MVT::v2i64; |
| 3446 | else |
| 3447 | NewVT = MVT::v2f64; |
Anton Korobeynikov | 7c1c261 | 2008-02-20 11:22:39 +0000 | [diff] [blame] | 3448 | } |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3449 | unsigned Scale = NumElems / NewWidth; |
| 3450 | SmallVector<SDOperand, 8> MaskVec; |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3451 | for (unsigned i = 0; i < NumElems; i += Scale) { |
| 3452 | unsigned StartIdx = ~0U; |
| 3453 | for (unsigned j = 0; j < Scale; ++j) { |
| 3454 | SDOperand Elt = PermMask.getOperand(i+j); |
| 3455 | if (Elt.getOpcode() == ISD::UNDEF) |
| 3456 | continue; |
| 3457 | unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); |
| 3458 | if (StartIdx == ~0U) |
| 3459 | StartIdx = EltIdx - (EltIdx % Scale); |
| 3460 | if (EltIdx != StartIdx + j) |
| 3461 | return SDOperand(); |
| 3462 | } |
| 3463 | if (StartIdx == ~0U) |
| 3464 | MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); |
| 3465 | else |
| 3466 | MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32)); |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3467 | } |
| 3468 | |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3469 | V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); |
| 3470 | V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); |
| 3471 | return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, |
| 3472 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3473 | &MaskVec[0], MaskVec.size())); |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3474 | } |
| 3475 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3476 | SDOperand |
| 3477 | X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { |
| 3478 | SDOperand V1 = Op.getOperand(0); |
| 3479 | SDOperand V2 = Op.getOperand(1); |
| 3480 | SDOperand PermMask = Op.getOperand(2); |
| 3481 | MVT::ValueType VT = Op.getValueType(); |
| 3482 | unsigned NumElems = PermMask.getNumOperands(); |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 3483 | bool isMMX = MVT::getSizeInBits(VT) == 64; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3484 | bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; |
| 3485 | bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; |
Evan Cheng | d9b8e40 | 2006-10-16 06:36:00 +0000 | [diff] [blame] | 3486 | bool V1IsSplat = false; |
| 3487 | bool V2IsSplat = false; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3488 | |
Evan Cheng | 8cf723d | 2006-09-08 01:50:06 +0000 | [diff] [blame] | 3489 | if (isUndefShuffle(Op.Val)) |
| 3490 | return DAG.getNode(ISD::UNDEF, VT); |
| 3491 | |
Evan Cheng | 213d2cf | 2007-05-17 18:45:50 +0000 | [diff] [blame] | 3492 | if (isZeroShuffle(Op.Val)) |
| 3493 | return getZeroVector(VT, DAG); |
| 3494 | |
Evan Cheng | 49892af | 2007-06-19 00:02:56 +0000 | [diff] [blame] | 3495 | if (isIdentityMask(PermMask.Val)) |
| 3496 | return V1; |
| 3497 | else if (isIdentityMask(PermMask.Val, true)) |
| 3498 | return V2; |
| 3499 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3500 | if (isSplatMask(PermMask.Val)) { |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 3501 | if (isMMX || NumElems < 4) return Op; |
| 3502 | // Promote it to a v4{if}32 splat. |
| 3503 | return PromoteSplat(Op, DAG, Subtarget->hasSSE2()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3504 | } |
| 3505 | |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3506 | // If the shuffle can be profitably rewritten as a narrower shuffle, then |
| 3507 | // do it! |
| 3508 | if (VT == MVT::v8i16 || VT == MVT::v16i8) { |
| 3509 | SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); |
| 3510 | if (NewOp.Val) |
| 3511 | return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); |
| 3512 | } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { |
| 3513 | // FIXME: Figure out a cleaner way to do this. |
| 3514 | // Try to make use of movq to zero out the top part. |
| 3515 | if (ISD::isBuildVectorAllZeros(V2.Val)) { |
| 3516 | SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); |
| 3517 | if (NewOp.Val) { |
| 3518 | SDOperand NewV1 = NewOp.getOperand(0); |
| 3519 | SDOperand NewV2 = NewOp.getOperand(1); |
| 3520 | SDOperand NewMask = NewOp.getOperand(2); |
| 3521 | if (isCommutedMOVL(NewMask.Val, true, false)) { |
| 3522 | NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); |
| 3523 | NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(), |
| 3524 | NewV1, NewV2, getMOVLMask(2, DAG)); |
| 3525 | return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); |
| 3526 | } |
| 3527 | } |
| 3528 | } else if (ISD::isBuildVectorAllZeros(V1.Val)) { |
| 3529 | SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); |
| 3530 | if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val)) |
| 3531 | return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); |
| 3532 | } |
| 3533 | } |
| 3534 | |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3535 | if (X86::isMOVLMask(PermMask.Val)) |
| 3536 | return (V1IsUndef) ? V2 : Op; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 3537 | |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3538 | if (X86::isMOVSHDUPMask(PermMask.Val) || |
| 3539 | X86::isMOVSLDUPMask(PermMask.Val) || |
| 3540 | X86::isMOVHLPSMask(PermMask.Val) || |
| 3541 | X86::isMOVHPMask(PermMask.Val) || |
| 3542 | X86::isMOVLPMask(PermMask.Val)) |
| 3543 | return Op; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3544 | |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3545 | if (ShouldXformToMOVHLPS(PermMask.Val) || |
| 3546 | ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3547 | return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3548 | |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3549 | bool Commuted = false; |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 3550 | // FIXME: This should also accept a bitcast of a splat? Be careful, not |
| 3551 | // 1,1,1,1 -> v8i16 though. |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3552 | V1IsSplat = isSplatVector(V1.Val); |
| 3553 | V2IsSplat = isSplatVector(V2.Val); |
Chris Lattner | 8a59448 | 2007-11-25 00:24:49 +0000 | [diff] [blame] | 3554 | |
| 3555 | // Canonicalize the splat or undef, if present, to be on the RHS. |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3556 | if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3557 | Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3558 | std::swap(V1IsSplat, V2IsSplat); |
| 3559 | std::swap(V1IsUndef, V2IsUndef); |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3560 | Commuted = true; |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3561 | } |
| 3562 | |
Evan Cheng | 7a831ce | 2007-12-15 03:00:47 +0000 | [diff] [blame] | 3563 | // FIXME: Figure out a cleaner way to do this. |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3564 | if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { |
| 3565 | if (V2IsUndef) return V1; |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3566 | Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3567 | if (V2IsSplat) { |
| 3568 | // V2 is a splat, so the mask may be malformed. That is, it may point |
| 3569 | // to any V2 element. The instruction selectior won't like this. Get |
| 3570 | // a corrected mask and commute to form a proper MOVS{S|D}. |
| 3571 | SDOperand NewMask = getMOVLMask(NumElems, DAG); |
| 3572 | if (NewMask.Val != PermMask.Val) |
| 3573 | Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3574 | } |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3575 | return Op; |
Evan Cheng | d9b8e40 | 2006-10-16 06:36:00 +0000 | [diff] [blame] | 3576 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3577 | |
Evan Cheng | d9b8e40 | 2006-10-16 06:36:00 +0000 | [diff] [blame] | 3578 | if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 3579 | X86::isUNPCKH_v_undef_Mask(PermMask.Val) || |
Evan Cheng | d9b8e40 | 2006-10-16 06:36:00 +0000 | [diff] [blame] | 3580 | X86::isUNPCKLMask(PermMask.Val) || |
| 3581 | X86::isUNPCKHMask(PermMask.Val)) |
| 3582 | return Op; |
Evan Cheng | e111303 | 2006-10-04 18:33:38 +0000 | [diff] [blame] | 3583 | |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3584 | if (V2IsSplat) { |
| 3585 | // Normalize mask so all entries that point to V2 points to its first |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 3586 | // element then try to match unpck{h|l} again. If match, return a |
Evan Cheng | 9bbbb98 | 2006-10-25 20:48:19 +0000 | [diff] [blame] | 3587 | // new vector_shuffle with the corrected mask. |
| 3588 | SDOperand NewMask = NormalizeMask(PermMask, DAG); |
| 3589 | if (NewMask.Val != PermMask.Val) { |
| 3590 | if (X86::isUNPCKLMask(PermMask.Val, true)) { |
| 3591 | SDOperand NewMask = getUnpacklMask(NumElems, DAG); |
| 3592 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); |
| 3593 | } else if (X86::isUNPCKHMask(PermMask.Val, true)) { |
| 3594 | SDOperand NewMask = getUnpackhMask(NumElems, DAG); |
| 3595 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3596 | } |
| 3597 | } |
| 3598 | } |
| 3599 | |
| 3600 | // Normalize the node to match x86 shuffle ops if needed |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3601 | if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val)) |
| 3602 | Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); |
| 3603 | |
| 3604 | if (Commuted) { |
| 3605 | // Commute is back and try unpck* again. |
| 3606 | Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); |
| 3607 | if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 3608 | X86::isUNPCKH_v_undef_Mask(PermMask.Val) || |
Evan Cheng | 9eca5e8 | 2006-10-25 21:49:50 +0000 | [diff] [blame] | 3609 | X86::isUNPCKLMask(PermMask.Val) || |
| 3610 | X86::isUNPCKHMask(PermMask.Val)) |
| 3611 | return Op; |
| 3612 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3613 | |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 3614 | // Try PSHUF* first, then SHUFP*. |
| 3615 | // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically |
| 3616 | // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. |
| 3617 | if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) { |
| 3618 | if (V2.getOpcode() != ISD::UNDEF) |
| 3619 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, |
| 3620 | DAG.getNode(ISD::UNDEF, VT), PermMask); |
| 3621 | return Op; |
| 3622 | } |
| 3623 | |
| 3624 | if (!isMMX) { |
| 3625 | if (Subtarget->hasSSE2() && |
| 3626 | (X86::isPSHUFDMask(PermMask.Val) || |
| 3627 | X86::isPSHUFHWMask(PermMask.Val) || |
| 3628 | X86::isPSHUFLWMask(PermMask.Val))) { |
| 3629 | MVT::ValueType RVT = VT; |
| 3630 | if (VT == MVT::v4f32) { |
| 3631 | RVT = MVT::v4i32; |
| 3632 | Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, |
| 3633 | DAG.getNode(ISD::BIT_CONVERT, RVT, V1), |
| 3634 | DAG.getNode(ISD::UNDEF, RVT), PermMask); |
| 3635 | } else if (V2.getOpcode() != ISD::UNDEF) |
| 3636 | Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1, |
| 3637 | DAG.getNode(ISD::UNDEF, RVT), PermMask); |
| 3638 | if (RVT != VT) |
| 3639 | Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3640 | return Op; |
| 3641 | } |
| 3642 | |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 3643 | // Binary or unary shufps. |
| 3644 | if (X86::isSHUFPMask(PermMask.Val) || |
| 3645 | (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val))) |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3646 | return Op; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3647 | } |
| 3648 | |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3649 | // Handle v8i16 specifically since SSE can do byte extraction and insertion. |
| 3650 | if (VT == MVT::v8i16) { |
| 3651 | SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); |
| 3652 | if (NewOp.Val) |
| 3653 | return NewOp; |
| 3654 | } |
| 3655 | |
| 3656 | // Handle all 4 wide cases with a number of shuffles. |
Evan Cheng | 0c0f83f | 2008-04-05 00:30:36 +0000 | [diff] [blame] | 3657 | if (NumElems == 4 && !isMMX) { |
Evan Cheng | 8a86c3f | 2007-12-07 08:07:39 +0000 | [diff] [blame] | 3658 | // Don't do this for MMX. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3659 | MVT::ValueType MaskVT = PermMask.getValueType(); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 3660 | MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3661 | SmallVector<std::pair<int, int>, 8> Locs; |
Evan Cheng | 43f3bd3 | 2006-04-28 07:03:38 +0000 | [diff] [blame] | 3662 | Locs.reserve(NumElems); |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3663 | SmallVector<SDOperand, 8> Mask1(NumElems, |
| 3664 | DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3665 | SmallVector<SDOperand, 8> Mask2(NumElems, |
| 3666 | DAG.getNode(ISD::UNDEF, MaskEVT)); |
Evan Cheng | 43f3bd3 | 2006-04-28 07:03:38 +0000 | [diff] [blame] | 3667 | unsigned NumHi = 0; |
| 3668 | unsigned NumLo = 0; |
| 3669 | // If no more than two elements come from either vector. This can be |
| 3670 | // implemented with two shuffles. First shuffle gather the elements. |
| 3671 | // The second shuffle, which takes the first shuffle as both of its |
| 3672 | // vector operands, put the elements into the right order. |
| 3673 | for (unsigned i = 0; i != NumElems; ++i) { |
| 3674 | SDOperand Elt = PermMask.getOperand(i); |
| 3675 | if (Elt.getOpcode() == ISD::UNDEF) { |
| 3676 | Locs[i] = std::make_pair(-1, -1); |
| 3677 | } else { |
| 3678 | unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); |
| 3679 | if (Val < NumElems) { |
| 3680 | Locs[i] = std::make_pair(0, NumLo); |
| 3681 | Mask1[NumLo] = Elt; |
| 3682 | NumLo++; |
| 3683 | } else { |
| 3684 | Locs[i] = std::make_pair(1, NumHi); |
| 3685 | if (2+NumHi < NumElems) |
| 3686 | Mask1[2+NumHi] = Elt; |
| 3687 | NumHi++; |
| 3688 | } |
| 3689 | } |
| 3690 | } |
| 3691 | if (NumLo <= 2 && NumHi <= 2) { |
| 3692 | V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3693 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3694 | &Mask1[0], Mask1.size())); |
Evan Cheng | 43f3bd3 | 2006-04-28 07:03:38 +0000 | [diff] [blame] | 3695 | for (unsigned i = 0; i != NumElems; ++i) { |
| 3696 | if (Locs[i].first == -1) |
| 3697 | continue; |
| 3698 | else { |
| 3699 | unsigned Idx = (i < NumElems/2) ? 0 : NumElems; |
| 3700 | Idx += Locs[i].first * (NumElems/2) + Locs[i].second; |
| 3701 | Mask2[i] = DAG.getConstant(Idx, MaskEVT); |
| 3702 | } |
| 3703 | } |
| 3704 | |
| 3705 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3706 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3707 | &Mask2[0], Mask2.size())); |
Evan Cheng | 43f3bd3 | 2006-04-28 07:03:38 +0000 | [diff] [blame] | 3708 | } |
| 3709 | |
| 3710 | // Break it into (shuffle shuffle_hi, shuffle_lo). |
| 3711 | Locs.clear(); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3712 | SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3713 | SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3714 | SmallVector<SDOperand,8> *MaskPtr = &LoMask; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3715 | unsigned MaskIdx = 0; |
| 3716 | unsigned LoIdx = 0; |
| 3717 | unsigned HiIdx = NumElems/2; |
| 3718 | for (unsigned i = 0; i != NumElems; ++i) { |
| 3719 | if (i == NumElems/2) { |
| 3720 | MaskPtr = &HiMask; |
| 3721 | MaskIdx = 1; |
| 3722 | LoIdx = 0; |
| 3723 | HiIdx = NumElems/2; |
| 3724 | } |
| 3725 | SDOperand Elt = PermMask.getOperand(i); |
| 3726 | if (Elt.getOpcode() == ISD::UNDEF) { |
| 3727 | Locs[i] = std::make_pair(-1, -1); |
| 3728 | } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) { |
| 3729 | Locs[i] = std::make_pair(MaskIdx, LoIdx); |
| 3730 | (*MaskPtr)[LoIdx] = Elt; |
| 3731 | LoIdx++; |
| 3732 | } else { |
| 3733 | Locs[i] = std::make_pair(MaskIdx, HiIdx); |
| 3734 | (*MaskPtr)[HiIdx] = Elt; |
| 3735 | HiIdx++; |
| 3736 | } |
| 3737 | } |
| 3738 | |
Chris Lattner | 8c0c10c | 2006-05-16 06:45:34 +0000 | [diff] [blame] | 3739 | SDOperand LoShuffle = |
| 3740 | DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3741 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3742 | &LoMask[0], LoMask.size())); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 3743 | SDOperand HiShuffle = |
Chris Lattner | 8c0c10c | 2006-05-16 06:45:34 +0000 | [diff] [blame] | 3744 | DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3745 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3746 | &HiMask[0], HiMask.size())); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3747 | SmallVector<SDOperand, 8> MaskOps; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3748 | for (unsigned i = 0; i != NumElems; ++i) { |
| 3749 | if (Locs[i].first == -1) { |
| 3750 | MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); |
| 3751 | } else { |
| 3752 | unsigned Idx = Locs[i].first * NumElems + Locs[i].second; |
| 3753 | MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); |
| 3754 | } |
| 3755 | } |
| 3756 | return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3757 | DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3758 | &MaskOps[0], MaskOps.size())); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3759 | } |
| 3760 | |
| 3761 | return SDOperand(); |
| 3762 | } |
| 3763 | |
| 3764 | SDOperand |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3765 | X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, |
| 3766 | SelectionDAG &DAG) { |
| 3767 | MVT::ValueType VT = Op.getValueType(); |
| 3768 | if (MVT::getSizeInBits(VT) == 8) { |
| 3769 | SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, |
| 3770 | Op.getOperand(0), Op.getOperand(1)); |
| 3771 | SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, |
| 3772 | DAG.getValueType(VT)); |
| 3773 | return DAG.getNode(ISD::TRUNCATE, VT, Assert); |
| 3774 | } else if (MVT::getSizeInBits(VT) == 16) { |
| 3775 | SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, |
| 3776 | Op.getOperand(0), Op.getOperand(1)); |
| 3777 | SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, |
| 3778 | DAG.getValueType(VT)); |
| 3779 | return DAG.getNode(ISD::TRUNCATE, VT, Assert); |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3780 | } else if (VT == MVT::f32) { |
| 3781 | // EXTRACTPS outputs to a GPR32 register which will require a movd to copy |
| 3782 | // the result back to FR32 register. It's only worth matching if the |
Dan Gohman | 171c11e | 2008-04-16 02:32:24 +0000 | [diff] [blame] | 3783 | // result has a single use which is a store or a bitcast to i32. |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3784 | if (!Op.hasOneUse()) |
| 3785 | return SDOperand(); |
Roman Levenstein | dc1adac | 2008-04-07 10:06:32 +0000 | [diff] [blame] | 3786 | SDNode *User = Op.Val->use_begin()->getUser(); |
Dan Gohman | 171c11e | 2008-04-16 02:32:24 +0000 | [diff] [blame] | 3787 | if (User->getOpcode() != ISD::STORE && |
| 3788 | (User->getOpcode() != ISD::BIT_CONVERT || |
| 3789 | User->getValueType(0) != MVT::i32)) |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3790 | return SDOperand(); |
| 3791 | SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, |
| 3792 | DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), |
| 3793 | Op.getOperand(1)); |
| 3794 | return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3795 | } |
| 3796 | return SDOperand(); |
| 3797 | } |
| 3798 | |
| 3799 | |
| 3800 | SDOperand |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3801 | X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { |
| 3802 | if (!isa<ConstantSDNode>(Op.getOperand(1))) |
| 3803 | return SDOperand(); |
| 3804 | |
Evan Cheng | 62a3f15 | 2008-03-24 21:52:23 +0000 | [diff] [blame] | 3805 | if (Subtarget->hasSSE41()) { |
| 3806 | SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); |
| 3807 | if (Res.Val) |
| 3808 | return Res; |
| 3809 | } |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3810 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3811 | MVT::ValueType VT = Op.getValueType(); |
| 3812 | // TODO: handle v16i8. |
| 3813 | if (MVT::getSizeInBits(VT) == 16) { |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3814 | SDOperand Vec = Op.getOperand(0); |
| 3815 | unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 3816 | if (Idx == 0) |
| 3817 | return DAG.getNode(ISD::TRUNCATE, MVT::i16, |
| 3818 | DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, |
| 3819 | DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), |
| 3820 | Op.getOperand(1))); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3821 | // Transform it so it match pextrw which produces a 32-bit result. |
| 3822 | MVT::ValueType EVT = (MVT::ValueType)(VT+1); |
| 3823 | SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, |
| 3824 | Op.getOperand(0), Op.getOperand(1)); |
| 3825 | SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, |
| 3826 | DAG.getValueType(VT)); |
| 3827 | return DAG.getNode(ISD::TRUNCATE, VT, Assert); |
| 3828 | } else if (MVT::getSizeInBits(VT) == 32) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3829 | unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 3830 | if (Idx == 0) |
| 3831 | return Op; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3832 | // SHUFPS the element to the lowest double word, then movss. |
| 3833 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3834 | SmallVector<SDOperand, 8> IdxVec; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3835 | IdxVec. |
| 3836 | push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT))); |
| 3837 | IdxVec. |
| 3838 | push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); |
| 3839 | IdxVec. |
| 3840 | push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); |
| 3841 | IdxVec. |
| 3842 | push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3843 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3844 | &IdxVec[0], IdxVec.size()); |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3845 | SDOperand Vec = Op.getOperand(0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3846 | Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 3847 | Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3848 | return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 3849 | DAG.getIntPtrConstant(0)); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3850 | } else if (MVT::getSizeInBits(VT) == 64) { |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3851 | // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b |
| 3852 | // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught |
| 3853 | // to match extract_elt for f64. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3854 | unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 3855 | if (Idx == 0) |
| 3856 | return Op; |
| 3857 | |
| 3858 | // UNPCKHPD the element to the lowest double word, then movsd. |
| 3859 | // Note if the lower 64 bits of the result of the UNPCKHPD is then stored |
| 3860 | // to a f64mem, the whole operation is folded into a single MOVHPDmr. |
| 3861 | MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 3862 | SmallVector<SDOperand, 8> IdxVec; |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 3863 | IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT))); |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 3864 | IdxVec. |
| 3865 | push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); |
Chris Lattner | e219945 | 2006-08-11 17:38:39 +0000 | [diff] [blame] | 3866 | SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, |
| 3867 | &IdxVec[0], IdxVec.size()); |
Evan Cheng | 14b32e1 | 2007-12-11 01:46:18 +0000 | [diff] [blame] | 3868 | SDOperand Vec = Op.getOperand(0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3869 | Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), |
| 3870 | Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); |
| 3871 | return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 3872 | DAG.getIntPtrConstant(0)); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3873 | } |
| 3874 | |
| 3875 | return SDOperand(); |
| 3876 | } |
| 3877 | |
| 3878 | SDOperand |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3879 | X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ |
| 3880 | MVT::ValueType VT = Op.getValueType(); |
| 3881 | MVT::ValueType EVT = MVT::getVectorElementType(VT); |
| 3882 | |
| 3883 | SDOperand N0 = Op.getOperand(0); |
| 3884 | SDOperand N1 = Op.getOperand(1); |
| 3885 | SDOperand N2 = Op.getOperand(2); |
| 3886 | |
| 3887 | if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) { |
| 3888 | unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB |
| 3889 | : X86ISD::PINSRW; |
| 3890 | // Transform it so it match pinsr{b,w} which expects a GR32 as its second |
| 3891 | // argument. |
| 3892 | if (N1.getValueType() != MVT::i32) |
| 3893 | N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); |
| 3894 | if (N2.getValueType() != MVT::i32) |
| 3895 | N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); |
| 3896 | return DAG.getNode(Opc, VT, N0, N1, N2); |
| 3897 | } else if (EVT == MVT::f32) { |
| 3898 | // Bits [7:6] of the constant are the source select. This will always be |
| 3899 | // zero here. The DAG Combiner may combine an extract_elt index into these |
| 3900 | // bits. For example (insert (extract, 3), 2) could be matched by putting |
| 3901 | // the '3' into bits [7:6] of X86ISD::INSERTPS. |
| 3902 | // Bits [5:4] of the constant are the destination select. This is the |
| 3903 | // value of the incoming immediate. |
| 3904 | // Bits [3:0] of the constant are the zero mask. The DAG Combiner may |
| 3905 | // combine either bitwise AND or insert of float 0.0 to set these bits. |
| 3906 | N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4); |
| 3907 | return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); |
| 3908 | } |
| 3909 | return SDOperand(); |
| 3910 | } |
| 3911 | |
| 3912 | SDOperand |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3913 | X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3914 | MVT::ValueType VT = Op.getValueType(); |
Evan Cheng | 794405e | 2007-12-12 07:55:34 +0000 | [diff] [blame] | 3915 | MVT::ValueType EVT = MVT::getVectorElementType(VT); |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 3916 | |
| 3917 | if (Subtarget->hasSSE41()) |
| 3918 | return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); |
| 3919 | |
Evan Cheng | 794405e | 2007-12-12 07:55:34 +0000 | [diff] [blame] | 3920 | if (EVT == MVT::i8) |
| 3921 | return SDOperand(); |
| 3922 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3923 | SDOperand N0 = Op.getOperand(0); |
| 3924 | SDOperand N1 = Op.getOperand(1); |
| 3925 | SDOperand N2 = Op.getOperand(2); |
Evan Cheng | 794405e | 2007-12-12 07:55:34 +0000 | [diff] [blame] | 3926 | |
| 3927 | if (MVT::getSizeInBits(EVT) == 16) { |
| 3928 | // Transform it so it match pinsrw which expects a 16-bit value in a GR32 |
| 3929 | // as its second argument. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3930 | if (N1.getValueType() != MVT::i32) |
| 3931 | N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); |
| 3932 | if (N2.getValueType() != MVT::i32) |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 3933 | N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3934 | return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3935 | } |
Nate Begeman | 219f67f | 2008-01-05 20:51:30 +0000 | [diff] [blame] | 3936 | return SDOperand(); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3937 | } |
| 3938 | |
| 3939 | SDOperand |
| 3940 | X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { |
| 3941 | SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); |
Evan Cheng | efec751 | 2008-02-18 23:04:32 +0000 | [diff] [blame] | 3942 | MVT::ValueType VT = MVT::v2i32; |
| 3943 | switch (Op.getValueType()) { |
| 3944 | default: break; |
| 3945 | case MVT::v16i8: |
| 3946 | case MVT::v8i16: |
| 3947 | VT = MVT::v4i32; |
| 3948 | break; |
| 3949 | } |
| 3950 | return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), |
| 3951 | DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3952 | } |
| 3953 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 3954 | // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3955 | // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is |
| 3956 | // one of the above mentioned nodes. It has to be wrapped because otherwise |
| 3957 | // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only |
| 3958 | // be used to form addressing mode. These wrapped nodes will be selected |
| 3959 | // into MOV32ri. |
| 3960 | SDOperand |
| 3961 | X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { |
| 3962 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); |
Evan Cheng | d0ff02c | 2006-11-29 23:19:46 +0000 | [diff] [blame] | 3963 | SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(), |
| 3964 | getPointerTy(), |
| 3965 | CP->getAlignment()); |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 3966 | Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); |
Anton Korobeynikov | 7f70559 | 2007-01-12 19:20:47 +0000 | [diff] [blame] | 3967 | // With PIC, the address is actually $g + Offset. |
| 3968 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 3969 | !Subtarget->isPICStyleRIPRel()) { |
| 3970 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 3971 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), |
| 3972 | Result); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3973 | } |
| 3974 | |
| 3975 | return Result; |
| 3976 | } |
| 3977 | |
| 3978 | SDOperand |
| 3979 | X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { |
| 3980 | GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); |
Evan Cheng | d0ff02c | 2006-11-29 23:19:46 +0000 | [diff] [blame] | 3981 | SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); |
Evan Cheng | a844bde | 2008-02-02 04:07:54 +0000 | [diff] [blame] | 3982 | // If it's a debug information descriptor, don't mess with it. |
| 3983 | if (DAG.isVerifiedDebugInfoDesc(Op)) |
| 3984 | return Result; |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 3985 | Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); |
Anton Korobeynikov | 7f70559 | 2007-01-12 19:20:47 +0000 | [diff] [blame] | 3986 | // With PIC, the address is actually $g + Offset. |
| 3987 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 3988 | !Subtarget->isPICStyleRIPRel()) { |
| 3989 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 3990 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), |
| 3991 | Result); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 3992 | } |
Anton Korobeynikov | 2b2bc68 | 2006-12-22 22:29:05 +0000 | [diff] [blame] | 3993 | |
| 3994 | // For Darwin & Mingw32, external and weak symbols are indirect, so we want to |
| 3995 | // load the value at address GV, not the value of GV itself. This means that |
| 3996 | // the GlobalAddress must be in the base or index register of the address, not |
| 3997 | // the GV offset field. Platform check is inside GVRequiresExtraLoad() call |
Anton Korobeynikov | 7f70559 | 2007-01-12 19:20:47 +0000 | [diff] [blame] | 3998 | // The same applies for external symbols during PIC codegen |
Anton Korobeynikov | 2b2bc68 | 2006-12-22 22:29:05 +0000 | [diff] [blame] | 3999 | if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4000 | Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4001 | PseudoSourceValue::getGOT(), 0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4002 | |
| 4003 | return Result; |
| 4004 | } |
| 4005 | |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 4006 | // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4007 | static SDOperand |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 4008 | LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, |
| 4009 | const MVT::ValueType PtrVT) { |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4010 | SDOperand InFlag; |
| 4011 | SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, |
| 4012 | DAG.getNode(X86ISD::GlobalBaseReg, |
| 4013 | PtrVT), InFlag); |
| 4014 | InFlag = Chain.getValue(1); |
| 4015 | |
| 4016 | // emit leal symbol@TLSGD(,%ebx,1), %eax |
| 4017 | SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); |
| 4018 | SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), |
| 4019 | GA->getValueType(0), |
| 4020 | GA->getOffset()); |
| 4021 | SDOperand Ops[] = { Chain, TGA, InFlag }; |
| 4022 | SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); |
| 4023 | InFlag = Result.getValue(2); |
| 4024 | Chain = Result.getValue(1); |
| 4025 | |
| 4026 | // call ___tls_get_addr. This function receives its argument in |
| 4027 | // the register EAX. |
| 4028 | Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); |
| 4029 | InFlag = Chain.getValue(1); |
| 4030 | |
| 4031 | NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 4032 | SDOperand Ops1[] = { Chain, |
| 4033 | DAG.getTargetExternalSymbol("___tls_get_addr", |
| 4034 | PtrVT), |
| 4035 | DAG.getRegister(X86::EAX, PtrVT), |
| 4036 | DAG.getRegister(X86::EBX, PtrVT), |
| 4037 | InFlag }; |
| 4038 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); |
| 4039 | InFlag = Chain.getValue(1); |
| 4040 | |
| 4041 | return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); |
| 4042 | } |
| 4043 | |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 4044 | // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit |
| 4045 | static SDOperand |
| 4046 | LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, |
| 4047 | const MVT::ValueType PtrVT) { |
| 4048 | SDOperand InFlag, Chain; |
| 4049 | |
| 4050 | // emit leaq symbol@TLSGD(%rip), %rdi |
| 4051 | SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); |
| 4052 | SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), |
| 4053 | GA->getValueType(0), |
| 4054 | GA->getOffset()); |
| 4055 | SDOperand Ops[] = { DAG.getEntryNode(), TGA}; |
| 4056 | SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); |
| 4057 | Chain = Result.getValue(1); |
| 4058 | InFlag = Result.getValue(2); |
| 4059 | |
| 4060 | // call ___tls_get_addr. This function receives its argument in |
| 4061 | // the register RDI. |
| 4062 | Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag); |
| 4063 | InFlag = Chain.getValue(1); |
| 4064 | |
| 4065 | NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 4066 | SDOperand Ops1[] = { Chain, |
| 4067 | DAG.getTargetExternalSymbol("___tls_get_addr", |
| 4068 | PtrVT), |
| 4069 | DAG.getRegister(X86::RDI, PtrVT), |
| 4070 | InFlag }; |
| 4071 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4); |
| 4072 | InFlag = Chain.getValue(1); |
| 4073 | |
| 4074 | return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag); |
| 4075 | } |
| 4076 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4077 | // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or |
| 4078 | // "local exec" model. |
| 4079 | static SDOperand |
| 4080 | LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, |
| 4081 | const MVT::ValueType PtrVT) { |
| 4082 | // Get the Thread Pointer |
| 4083 | SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); |
| 4084 | // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial |
| 4085 | // exec) |
| 4086 | SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), |
| 4087 | GA->getValueType(0), |
| 4088 | GA->getOffset()); |
| 4089 | SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); |
Lauro Ramos Venancio | 7d2cc2b | 2007-04-22 22:50:52 +0000 | [diff] [blame] | 4090 | |
| 4091 | if (GA->getGlobal()->isDeclaration()) // initial exec TLS model |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4092 | Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4093 | PseudoSourceValue::getGOT(), 0); |
Lauro Ramos Venancio | 7d2cc2b | 2007-04-22 22:50:52 +0000 | [diff] [blame] | 4094 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4095 | // The address of the thread local variable is the add of the thread |
| 4096 | // pointer with the offset of the variable. |
| 4097 | return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); |
| 4098 | } |
| 4099 | |
| 4100 | SDOperand |
| 4101 | X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { |
| 4102 | // TODO: implement the "local dynamic" model |
Lauro Ramos Venancio | 2c5c111 | 2007-04-21 20:56:26 +0000 | [diff] [blame] | 4103 | // TODO: implement the "initial exec"model for pic executables |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 4104 | assert(Subtarget->isTargetELF() && |
| 4105 | "TLS not implemented for non-ELF targets"); |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4106 | GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); |
| 4107 | // If the relocation model is PIC, use the "General Dynamic" TLS Model, |
| 4108 | // otherwise use the "Local Exec"TLS Model |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame^] | 4109 | if (Subtarget->is64Bit()) { |
| 4110 | return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); |
| 4111 | } else { |
| 4112 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_) |
| 4113 | return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); |
| 4114 | else |
| 4115 | return LowerToTLSExecModel(GA, DAG, getPointerTy()); |
| 4116 | } |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 4117 | } |
| 4118 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4119 | SDOperand |
| 4120 | X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { |
| 4121 | const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); |
Evan Cheng | d0ff02c | 2006-11-29 23:19:46 +0000 | [diff] [blame] | 4122 | SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 4123 | Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); |
Anton Korobeynikov | 7f70559 | 2007-01-12 19:20:47 +0000 | [diff] [blame] | 4124 | // With PIC, the address is actually $g + Offset. |
| 4125 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 4126 | !Subtarget->isPICStyleRIPRel()) { |
| 4127 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 4128 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), |
| 4129 | Result); |
| 4130 | } |
| 4131 | |
| 4132 | return Result; |
| 4133 | } |
| 4134 | |
| 4135 | SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { |
| 4136 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); |
| 4137 | SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); |
| 4138 | Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); |
| 4139 | // With PIC, the address is actually $g + Offset. |
| 4140 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && |
| 4141 | !Subtarget->isPICStyleRIPRel()) { |
| 4142 | Result = DAG.getNode(ISD::ADD, getPointerTy(), |
| 4143 | DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), |
| 4144 | Result); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4145 | } |
| 4146 | |
| 4147 | return Result; |
| 4148 | } |
| 4149 | |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4150 | /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and |
| 4151 | /// take a 2 x i32 value to shift plus a shift amount. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4152 | SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4153 | assert(Op.getNumOperands() == 3 && "Not a double-shift!"); |
| 4154 | MVT::ValueType VT = Op.getValueType(); |
| 4155 | unsigned VTBits = MVT::getSizeInBits(VT); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4156 | bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; |
| 4157 | SDOperand ShOpLo = Op.getOperand(0); |
| 4158 | SDOperand ShOpHi = Op.getOperand(1); |
| 4159 | SDOperand ShAmt = Op.getOperand(2); |
| 4160 | SDOperand Tmp1 = isSRA ? |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4161 | DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : |
| 4162 | DAG.getConstant(0, VT); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 4163 | |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4164 | SDOperand Tmp2, Tmp3; |
| 4165 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4166 | Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); |
| 4167 | Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4168 | } else { |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4169 | Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); |
| 4170 | Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4171 | } |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 4172 | |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4173 | const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); |
| 4174 | SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4175 | DAG.getConstant(VTBits, MVT::i8)); |
| 4176 | SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4177 | AndNode, DAG.getConstant(0, MVT::i8)); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 4178 | |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4179 | SDOperand Hi, Lo; |
| 4180 | SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4181 | VTs = DAG.getNodeValueTypes(VT, MVT::Flag); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4182 | SmallVector<SDOperand, 4> Ops; |
| 4183 | if (Op.getOpcode() == ISD::SHL_PARTS) { |
| 4184 | Ops.push_back(Tmp2); |
| 4185 | Ops.push_back(Tmp3); |
| 4186 | Ops.push_back(CC); |
| 4187 | Ops.push_back(Cond); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4188 | Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 4189 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 4190 | Ops.clear(); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4191 | Ops.push_back(Tmp3); |
| 4192 | Ops.push_back(Tmp1); |
| 4193 | Ops.push_back(CC); |
| 4194 | Ops.push_back(Cond); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4195 | Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4196 | } else { |
| 4197 | Ops.push_back(Tmp2); |
| 4198 | Ops.push_back(Tmp3); |
| 4199 | Ops.push_back(CC); |
| 4200 | Ops.push_back(Cond); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4201 | Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4202 | |
| 4203 | Ops.clear(); |
| 4204 | Ops.push_back(Tmp3); |
| 4205 | Ops.push_back(Tmp1); |
| 4206 | Ops.push_back(CC); |
| 4207 | Ops.push_back(Cond); |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4208 | Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4209 | } |
| 4210 | |
Dan Gohman | 4c1fa61 | 2008-03-03 22:22:09 +0000 | [diff] [blame] | 4211 | VTs = DAG.getNodeValueTypes(VT, VT); |
Chris Lattner | 2ff75ee | 2007-10-17 06:02:13 +0000 | [diff] [blame] | 4212 | Ops.clear(); |
| 4213 | Ops.push_back(Lo); |
| 4214 | Ops.push_back(Hi); |
| 4215 | return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4216 | } |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 4217 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4218 | SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4219 | MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); |
Chris Lattner | b09916b | 2008-02-27 05:57:41 +0000 | [diff] [blame] | 4220 | assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && |
| 4221 | "Unknown SINT_TO_FP to lower!"); |
| 4222 | |
| 4223 | // These are really Legal; caller falls through into that case. |
| 4224 | if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) |
| 4225 | return SDOperand(); |
| 4226 | if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && |
| 4227 | Subtarget->is64Bit()) |
| 4228 | return SDOperand(); |
| 4229 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4230 | unsigned Size = MVT::getSizeInBits(SrcVT)/8; |
| 4231 | MachineFunction &MF = DAG.getMachineFunction(); |
| 4232 | int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); |
| 4233 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
Evan Cheng | 786225a | 2006-10-05 23:01:46 +0000 | [diff] [blame] | 4234 | SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4235 | StackSlot, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4236 | PseudoSourceValue::getFixedStack(), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4237 | SSFI); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4238 | |
| 4239 | // Build the FILD |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4240 | SDVTList Tys; |
Chris Lattner | 7863116 | 2008-01-16 06:24:21 +0000 | [diff] [blame] | 4241 | bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 4242 | if (useSSE) |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4243 | Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); |
| 4244 | else |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 4245 | Tys = DAG.getVTList(Op.getValueType(), MVT::Other); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4246 | SmallVector<SDOperand, 8> Ops; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4247 | Ops.push_back(Chain); |
| 4248 | Ops.push_back(StackSlot); |
| 4249 | Ops.push_back(DAG.getValueType(SrcVT)); |
Chris Lattner | b09916b | 2008-02-27 05:57:41 +0000 | [diff] [blame] | 4250 | SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, |
| 4251 | Tys, &Ops[0], Ops.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4252 | |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 4253 | if (useSSE) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4254 | Chain = Result.getValue(1); |
| 4255 | SDOperand InFlag = Result.getValue(2); |
| 4256 | |
| 4257 | // FIXME: Currently the FST is flagged to the FILD_FLAG. This |
| 4258 | // shouldn't be necessary except that RFP cannot be live across |
| 4259 | // multiple blocks. When stackifier is fixed, they can be uncoupled. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4260 | MachineFunction &MF = DAG.getMachineFunction(); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4261 | int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4262 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4263 | Tys = DAG.getVTList(MVT::Other); |
| 4264 | SmallVector<SDOperand, 8> Ops; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 4265 | Ops.push_back(Chain); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4266 | Ops.push_back(Result); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4267 | Ops.push_back(StackSlot); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4268 | Ops.push_back(DAG.getValueType(Op.getValueType())); |
| 4269 | Ops.push_back(InFlag); |
Chris Lattner | bd564bf | 2006-08-08 02:23:42 +0000 | [diff] [blame] | 4270 | Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4271 | Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4272 | PseudoSourceValue::getFixedStack(), SSFI); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4273 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4274 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4275 | return Result; |
| 4276 | } |
| 4277 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4278 | std::pair<SDOperand,SDOperand> X86TargetLowering:: |
| 4279 | FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4280 | assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && |
| 4281 | "Unknown FP_TO_SINT to lower!"); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4282 | |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 4283 | // These are really Legal. |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 4284 | if (Op.getValueType() == MVT::i32 && |
Chris Lattner | 7863116 | 2008-01-16 06:24:21 +0000 | [diff] [blame] | 4285 | isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4286 | return std::make_pair(SDOperand(), SDOperand()); |
Dale Johannesen | 73328d1 | 2007-09-19 23:55:34 +0000 | [diff] [blame] | 4287 | if (Subtarget->is64Bit() && |
| 4288 | Op.getValueType() == MVT::i64 && |
| 4289 | Op.getOperand(0).getValueType() != MVT::f80) |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4290 | return std::make_pair(SDOperand(), SDOperand()); |
Dale Johannesen | 9e3d3ab | 2007-09-14 22:26:36 +0000 | [diff] [blame] | 4291 | |
Evan Cheng | 87c8935 | 2007-10-15 20:11:21 +0000 | [diff] [blame] | 4292 | // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary |
| 4293 | // stack slot. |
| 4294 | MachineFunction &MF = DAG.getMachineFunction(); |
| 4295 | unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; |
| 4296 | int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 4297 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4298 | unsigned Opc; |
| 4299 | switch (Op.getValueType()) { |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4300 | default: assert(0 && "Invalid FP_TO_SINT to lower!"); |
| 4301 | case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; |
| 4302 | case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; |
| 4303 | case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4304 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4305 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4306 | SDOperand Chain = DAG.getEntryNode(); |
| 4307 | SDOperand Value = Op.getOperand(0); |
Chris Lattner | 7863116 | 2008-01-16 06:24:21 +0000 | [diff] [blame] | 4308 | if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4309 | assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4310 | Chain = DAG.getStore(Chain, Value, StackSlot, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4311 | PseudoSourceValue::getFixedStack(), SSFI); |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 4312 | SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4313 | SDOperand Ops[] = { |
| 4314 | Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) |
| 4315 | }; |
| 4316 | Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4317 | Chain = Value.getValue(1); |
| 4318 | SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); |
| 4319 | StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 4320 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 4321 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4322 | // Build the FP_TO_INT*_IN_MEM |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4323 | SDOperand Ops[] = { Chain, Value, StackSlot }; |
| 4324 | SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 4325 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4326 | return std::make_pair(FIST, StackSlot); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4327 | } |
| 4328 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4329 | SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4330 | std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG); |
| 4331 | SDOperand FIST = Vals.first, StackSlot = Vals.second; |
| 4332 | if (FIST.Val == 0) return SDOperand(); |
| 4333 | |
| 4334 | // Load the result. |
| 4335 | return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); |
| 4336 | } |
| 4337 | |
| 4338 | SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { |
| 4339 | std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG); |
| 4340 | SDOperand FIST = Vals.first, StackSlot = Vals.second; |
| 4341 | if (FIST.Val == 0) return 0; |
| 4342 | |
| 4343 | // Return an i64 load from the stack slot. |
| 4344 | SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0); |
| 4345 | |
| 4346 | // Use a MERGE_VALUES node to drop the chain result value. |
| 4347 | return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val; |
| 4348 | } |
| 4349 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4350 | SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { |
| 4351 | MVT::ValueType VT = Op.getValueType(); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4352 | MVT::ValueType EltVT = VT; |
| 4353 | if (MVT::isVector(VT)) |
| 4354 | EltVT = MVT::getVectorElementType(VT); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4355 | std::vector<Constant*> CV; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4356 | if (EltVT == MVT::f64) { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4357 | Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4358 | CV.push_back(C); |
| 4359 | CV.push_back(C); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4360 | } else { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4361 | Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4362 | CV.push_back(C); |
| 4363 | CV.push_back(C); |
| 4364 | CV.push_back(C); |
| 4365 | CV.push_back(C); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4366 | } |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4367 | Constant *C = ConstantVector::get(CV); |
| 4368 | SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4369 | SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4370 | PseudoSourceValue::getConstantPool(), 0, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4371 | false, 16); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4372 | return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); |
| 4373 | } |
| 4374 | |
| 4375 | SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { |
| 4376 | MVT::ValueType VT = Op.getValueType(); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4377 | MVT::ValueType EltVT = VT; |
Evan Cheng | d4d01b7 | 2007-07-19 23:36:01 +0000 | [diff] [blame] | 4378 | unsigned EltNum = 1; |
| 4379 | if (MVT::isVector(VT)) { |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4380 | EltVT = MVT::getVectorElementType(VT); |
Evan Cheng | d4d01b7 | 2007-07-19 23:36:01 +0000 | [diff] [blame] | 4381 | EltNum = MVT::getVectorNumElements(VT); |
| 4382 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4383 | std::vector<Constant*> CV; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4384 | if (EltVT == MVT::f64) { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4385 | Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4386 | CV.push_back(C); |
| 4387 | CV.push_back(C); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4388 | } else { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4389 | Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 4390 | CV.push_back(C); |
| 4391 | CV.push_back(C); |
| 4392 | CV.push_back(C); |
| 4393 | CV.push_back(C); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4394 | } |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4395 | Constant *C = ConstantVector::get(CV); |
| 4396 | SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4397 | SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4398 | PseudoSourceValue::getConstantPool(), 0, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4399 | false, 16); |
Evan Cheng | d4d01b7 | 2007-07-19 23:36:01 +0000 | [diff] [blame] | 4400 | if (MVT::isVector(VT)) { |
Evan Cheng | d4d01b7 | 2007-07-19 23:36:01 +0000 | [diff] [blame] | 4401 | return DAG.getNode(ISD::BIT_CONVERT, VT, |
| 4402 | DAG.getNode(ISD::XOR, MVT::v2i64, |
| 4403 | DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), |
| 4404 | DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); |
| 4405 | } else { |
Evan Cheng | d4d01b7 | 2007-07-19 23:36:01 +0000 | [diff] [blame] | 4406 | return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); |
| 4407 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4408 | } |
| 4409 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4410 | SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4411 | SDOperand Op0 = Op.getOperand(0); |
| 4412 | SDOperand Op1 = Op.getOperand(1); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4413 | MVT::ValueType VT = Op.getValueType(); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4414 | MVT::ValueType SrcVT = Op1.getValueType(); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4415 | |
| 4416 | // If second operand is smaller, extend it first. |
| 4417 | if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) { |
| 4418 | Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); |
| 4419 | SrcVT = VT; |
| 4420 | } |
Dale Johannesen | 61c7ef3 | 2007-10-21 01:07:44 +0000 | [diff] [blame] | 4421 | // And if it is bigger, shrink it first. |
| 4422 | if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4423 | Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); |
Dale Johannesen | 61c7ef3 | 2007-10-21 01:07:44 +0000 | [diff] [blame] | 4424 | SrcVT = VT; |
Dale Johannesen | 61c7ef3 | 2007-10-21 01:07:44 +0000 | [diff] [blame] | 4425 | } |
| 4426 | |
| 4427 | // At this point the operands and the result should have the same |
| 4428 | // type, and that won't be f80 since that is not custom lowered. |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4429 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4430 | // First get the sign bit of second operand. |
| 4431 | std::vector<Constant*> CV; |
| 4432 | if (SrcVT == MVT::f64) { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4433 | CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); |
| 4434 | CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4435 | } else { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4436 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); |
| 4437 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
| 4438 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
| 4439 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4440 | } |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4441 | Constant *C = ConstantVector::get(CV); |
| 4442 | SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4443 | SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4444 | PseudoSourceValue::getConstantPool(), 0, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4445 | false, 16); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4446 | SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4447 | |
| 4448 | // Shift sign bit right or left if the two operands have different types. |
| 4449 | if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { |
| 4450 | // Op0 is MVT::f32, Op1 is MVT::f64. |
| 4451 | SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); |
| 4452 | SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, |
| 4453 | DAG.getConstant(32, MVT::i32)); |
| 4454 | SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); |
| 4455 | SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4456 | DAG.getIntPtrConstant(0)); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4457 | } |
| 4458 | |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4459 | // Clear first operand sign bit. |
| 4460 | CV.clear(); |
| 4461 | if (VT == MVT::f64) { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4462 | CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); |
| 4463 | CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4464 | } else { |
Chris Lattner | 02a260a | 2008-04-20 00:41:09 +0000 | [diff] [blame] | 4465 | CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); |
| 4466 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
| 4467 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
| 4468 | CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4469 | } |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4470 | C = ConstantVector::get(CV); |
| 4471 | CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4472 | SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, |
Dan Gohman | 3069b87 | 2008-02-07 18:41:25 +0000 | [diff] [blame] | 4473 | PseudoSourceValue::getConstantPool(), 0, |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 4474 | false, 16); |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 4475 | SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); |
| 4476 | |
| 4477 | // Or the value with the sign bit. |
| 4478 | return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 4479 | } |
| 4480 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4481 | SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4482 | assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); |
Evan Cheng | 1a35edb | 2007-09-26 00:45:55 +0000 | [diff] [blame] | 4483 | SDOperand Cond; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4484 | SDOperand Op0 = Op.getOperand(0); |
| 4485 | SDOperand Op1 = Op.getOperand(1); |
| 4486 | SDOperand CC = Op.getOperand(2); |
| 4487 | ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); |
| 4488 | bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); |
| 4489 | unsigned X86CC; |
| 4490 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4491 | if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, |
Evan Cheng | 1a35edb | 2007-09-26 00:45:55 +0000 | [diff] [blame] | 4492 | Op0, Op1, DAG)) { |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4493 | Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); |
| 4494 | return DAG.getNode(X86ISD::SETCC, MVT::i8, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4495 | DAG.getConstant(X86CC, MVT::i8), Cond); |
Evan Cheng | 1a35edb | 2007-09-26 00:45:55 +0000 | [diff] [blame] | 4496 | } |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4497 | |
| 4498 | assert(isFP && "Illegal integer SetCC!"); |
| 4499 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4500 | Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4501 | switch (SetCCOpcode) { |
| 4502 | default: assert(false && "Illegal floating point SetCC!"); |
| 4503 | case ISD::SETOEQ: { // !PF & ZF |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4504 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4505 | DAG.getConstant(X86::COND_NP, MVT::i8), Cond); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4506 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4507 | DAG.getConstant(X86::COND_E, MVT::i8), Cond); |
| 4508 | return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); |
| 4509 | } |
| 4510 | case ISD::SETUNE: { // PF | !ZF |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4511 | SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4512 | DAG.getConstant(X86::COND_P, MVT::i8), Cond); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4513 | SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4514 | DAG.getConstant(X86::COND_NE, MVT::i8), Cond); |
| 4515 | return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); |
| 4516 | } |
| 4517 | } |
| 4518 | } |
| 4519 | |
| 4520 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4521 | SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4522 | bool addTest = true; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4523 | SDOperand Cond = Op.getOperand(0); |
| 4524 | SDOperand CC; |
Evan Cheng | 9bba894 | 2006-01-26 02:13:10 +0000 | [diff] [blame] | 4525 | |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4526 | if (Cond.getOpcode() == ISD::SETCC) |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4527 | Cond = LowerSETCC(Cond, DAG); |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4528 | |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4529 | // If condition flag is set by a X86ISD::CMP, then use it as the condition |
| 4530 | // setting operand in place of the X86ISD::SETCC. |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4531 | if (Cond.getOpcode() == X86ISD::SETCC) { |
| 4532 | CC = Cond.getOperand(0); |
| 4533 | |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4534 | SDOperand Cmp = Cond.getOperand(1); |
| 4535 | unsigned Opc = Cmp.getOpcode(); |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4536 | MVT::ValueType VT = Op.getValueType(); |
Chris Lattner | 1956d15 | 2008-01-16 06:19:45 +0000 | [diff] [blame] | 4537 | |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4538 | bool IllegalFPCMov = false; |
Chris Lattner | 1956d15 | 2008-01-16 06:19:45 +0000 | [diff] [blame] | 4539 | if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) && |
Chris Lattner | 7863116 | 2008-01-16 06:24:21 +0000 | [diff] [blame] | 4540 | !isScalarFPTypeInSSEReg(VT)) // FPStack? |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4541 | IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); |
Chris Lattner | 1956d15 | 2008-01-16 06:19:45 +0000 | [diff] [blame] | 4542 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4543 | if ((Opc == X86ISD::CMP || |
| 4544 | Opc == X86ISD::COMI || |
| 4545 | Opc == X86ISD::UCOMI) && !IllegalFPCMov) { |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4546 | Cond = Cmp; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4547 | addTest = false; |
| 4548 | } |
| 4549 | } |
| 4550 | |
| 4551 | if (addTest) { |
| 4552 | CC = DAG.getConstant(X86::COND_NE, MVT::i8); |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4553 | Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4554 | } |
| 4555 | |
| 4556 | const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(), |
| 4557 | MVT::Flag); |
| 4558 | SmallVector<SDOperand, 4> Ops; |
| 4559 | // X86ISD::CMOV means set the result (which is operand 1) to the RHS if |
| 4560 | // condition is true. |
| 4561 | Ops.push_back(Op.getOperand(2)); |
| 4562 | Ops.push_back(Op.getOperand(1)); |
| 4563 | Ops.push_back(CC); |
| 4564 | Ops.push_back(Cond); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4565 | return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4566 | } |
| 4567 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4568 | SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4569 | bool addTest = true; |
| 4570 | SDOperand Chain = Op.getOperand(0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4571 | SDOperand Cond = Op.getOperand(1); |
| 4572 | SDOperand Dest = Op.getOperand(2); |
| 4573 | SDOperand CC; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4574 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4575 | if (Cond.getOpcode() == ISD::SETCC) |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4576 | Cond = LowerSETCC(Cond, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4577 | |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4578 | // If condition flag is set by a X86ISD::CMP, then use it as the condition |
| 4579 | // setting operand in place of the X86ISD::SETCC. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4580 | if (Cond.getOpcode() == X86ISD::SETCC) { |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4581 | CC = Cond.getOperand(0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4582 | |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 4583 | SDOperand Cmp = Cond.getOperand(1); |
| 4584 | unsigned Opc = Cmp.getOpcode(); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4585 | if (Opc == X86ISD::CMP || |
| 4586 | Opc == X86ISD::COMI || |
| 4587 | Opc == X86ISD::UCOMI) { |
Evan Cheng | 3f41d66 | 2007-10-08 22:16:29 +0000 | [diff] [blame] | 4588 | Cond = Cmp; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4589 | addTest = false; |
| 4590 | } |
| 4591 | } |
| 4592 | |
| 4593 | if (addTest) { |
| 4594 | CC = DAG.getConstant(X86::COND_NE, MVT::i8); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4595 | Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4596 | } |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 4597 | return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 4598 | Chain, Op.getOperand(2), CC, Cond); |
| 4599 | } |
| 4600 | |
Anton Korobeynikov | e060b53 | 2007-04-17 19:34:00 +0000 | [diff] [blame] | 4601 | |
| 4602 | // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. |
| 4603 | // Calls to _alloca is needed to probe the stack when allocating more than 4k |
| 4604 | // bytes in one go. Touching the stack at 4K increments is necessary to ensure |
| 4605 | // that the guard pages used by the OS virtual memory manager are allocated in |
| 4606 | // correct sequence. |
Anton Korobeynikov | 4304bcc | 2007-07-05 20:36:08 +0000 | [diff] [blame] | 4607 | SDOperand |
| 4608 | X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, |
| 4609 | SelectionDAG &DAG) { |
Anton Korobeynikov | e060b53 | 2007-04-17 19:34:00 +0000 | [diff] [blame] | 4610 | assert(Subtarget->isTargetCygMing() && |
| 4611 | "This should be used only on Cygwin/Mingw targets"); |
| 4612 | |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 4613 | // Get the inputs. |
| 4614 | SDOperand Chain = Op.getOperand(0); |
| 4615 | SDOperand Size = Op.getOperand(1); |
| 4616 | // FIXME: Ensure alignment here |
| 4617 | |
Anton Korobeynikov | 4304bcc | 2007-07-05 20:36:08 +0000 | [diff] [blame] | 4618 | SDOperand Flag; |
| 4619 | |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 4620 | MVT::ValueType IntPtr = getPointerTy(); |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4621 | MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 4622 | |
Anton Korobeynikov | 4304bcc | 2007-07-05 20:36:08 +0000 | [diff] [blame] | 4623 | Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); |
| 4624 | Flag = Chain.getValue(1); |
| 4625 | |
| 4626 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 4627 | SDOperand Ops[] = { Chain, |
| 4628 | DAG.getTargetExternalSymbol("_alloca", IntPtr), |
| 4629 | DAG.getRegister(X86::EAX, IntPtr), |
| 4630 | Flag }; |
| 4631 | Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4); |
| 4632 | Flag = Chain.getValue(1); |
| 4633 | |
| 4634 | Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 4635 | |
| 4636 | std::vector<MVT::ValueType> Tys; |
| 4637 | Tys.push_back(SPTy); |
| 4638 | Tys.push_back(MVT::Other); |
Anton Korobeynikov | 4304bcc | 2007-07-05 20:36:08 +0000 | [diff] [blame] | 4639 | SDOperand Ops1[2] = { Chain.getValue(0), Chain }; |
| 4640 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 4641 | } |
| 4642 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4643 | SDOperand |
| 4644 | X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, |
| 4645 | SDOperand Chain, |
| 4646 | SDOperand Dst, SDOperand Src, |
| 4647 | SDOperand Size, unsigned Align, |
Dan Gohman | 1f13c68 | 2008-04-28 17:15:20 +0000 | [diff] [blame] | 4648 | const Value *DstSV, uint64_t DstSVOff) { |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4649 | ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4650 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4651 | /// If not DWORD aligned or size is more than the threshold, call the library. |
| 4652 | /// The libc version is likely to be faster for these cases. It can use the |
| 4653 | /// address value and run time information about the CPU. |
| 4654 | if ((Align & 3) == 0 || |
| 4655 | !ConstantSize || |
| 4656 | ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) { |
| 4657 | SDOperand InFlag(0, 0); |
Dan Gohman | 68d599d | 2008-04-01 20:38:36 +0000 | [diff] [blame] | 4658 | |
| 4659 | // Check to see if there is a specialized entry-point for memory zeroing. |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4660 | ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); |
| 4661 | if (const char *bzeroEntry = |
| 4662 | V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { |
| 4663 | MVT::ValueType IntPtr = getPointerTy(); |
| 4664 | const Type *IntPtrTy = getTargetData()->getIntPtrType(); |
| 4665 | TargetLowering::ArgListTy Args; |
| 4666 | TargetLowering::ArgListEntry Entry; |
| 4667 | Entry.Node = Dst; |
Dan Gohman | 68d599d | 2008-04-01 20:38:36 +0000 | [diff] [blame] | 4668 | Entry.Ty = IntPtrTy; |
| 4669 | Args.push_back(Entry); |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4670 | Entry.Node = Size; |
| 4671 | Args.push_back(Entry); |
| 4672 | std::pair<SDOperand,SDOperand> CallResult = |
| 4673 | LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, |
| 4674 | false, DAG.getExternalSymbol(bzeroEntry, IntPtr), |
| 4675 | Args, DAG); |
| 4676 | return CallResult.second; |
Dan Gohman | 68d599d | 2008-04-01 20:38:36 +0000 | [diff] [blame] | 4677 | } |
| 4678 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4679 | // Otherwise have the target-independent code call memset. |
| 4680 | return SDOperand(); |
Evan Cheng | 48090aa | 2006-03-21 23:01:21 +0000 | [diff] [blame] | 4681 | } |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 4682 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4683 | uint64_t SizeVal = ConstantSize->getValue(); |
| 4684 | SDOperand InFlag(0, 0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4685 | MVT::ValueType AVT; |
| 4686 | SDOperand Count; |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4687 | ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4688 | unsigned BytesLeft = 0; |
| 4689 | bool TwoRepStos = false; |
| 4690 | if (ValC) { |
| 4691 | unsigned ValReg; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4692 | uint64_t Val = ValC->getValue() & 255; |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 4693 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4694 | // If the value is a constant, then we can potentially use larger sets. |
| 4695 | switch (Align & 3) { |
| 4696 | case 2: // WORD aligned |
| 4697 | AVT = MVT::i16; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4698 | ValReg = X86::AX; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4699 | Val = (Val << 8) | Val; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4700 | break; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4701 | case 0: // DWORD aligned |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4702 | AVT = MVT::i32; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4703 | ValReg = X86::EAX; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4704 | Val = (Val << 8) | Val; |
| 4705 | Val = (Val << 16) | Val; |
Dan Gohman | 6f836ad | 2008-04-12 02:35:39 +0000 | [diff] [blame] | 4706 | if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4707 | AVT = MVT::i64; |
| 4708 | ValReg = X86::RAX; |
| 4709 | Val = (Val << 32) | Val; |
| 4710 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4711 | break; |
| 4712 | default: // Byte aligned |
| 4713 | AVT = MVT::i8; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4714 | ValReg = X86::AL; |
Dan Gohman | bcda285 | 2008-04-16 01:32:32 +0000 | [diff] [blame] | 4715 | Count = DAG.getIntPtrConstant(SizeVal); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4716 | break; |
Evan Cheng | 80d428c | 2006-04-19 22:48:17 +0000 | [diff] [blame] | 4717 | } |
| 4718 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4719 | if (AVT > MVT::i8) { |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4720 | unsigned UBytes = MVT::getSizeInBits(AVT) / 8; |
| 4721 | Count = DAG.getIntPtrConstant(SizeVal / UBytes); |
| 4722 | BytesLeft = SizeVal % UBytes; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4723 | } |
| 4724 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4725 | Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), |
| 4726 | InFlag); |
| 4727 | InFlag = Chain.getValue(1); |
| 4728 | } else { |
| 4729 | AVT = MVT::i8; |
Dan Gohman | bcda285 | 2008-04-16 01:32:32 +0000 | [diff] [blame] | 4730 | Count = DAG.getIntPtrConstant(SizeVal); |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4731 | Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4732 | InFlag = Chain.getValue(1); |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 4733 | } |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 4734 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4735 | Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, |
| 4736 | Count, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4737 | InFlag = Chain.getValue(1); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4738 | Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4739 | Dst, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4740 | InFlag = Chain.getValue(1); |
Evan Cheng | a0b3afb | 2006-03-27 07:00:16 +0000 | [diff] [blame] | 4741 | |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 4742 | SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4743 | SmallVector<SDOperand, 8> Ops; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4744 | Ops.push_back(Chain); |
| 4745 | Ops.push_back(DAG.getValueType(AVT)); |
| 4746 | Ops.push_back(InFlag); |
Evan Cheng | 311ace0 | 2006-08-11 07:35:45 +0000 | [diff] [blame] | 4747 | Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); |
Evan Cheng | c78d3b4 | 2006-04-24 18:01:45 +0000 | [diff] [blame] | 4748 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4749 | if (TwoRepStos) { |
| 4750 | InFlag = Chain.getValue(1); |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4751 | Count = Size; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4752 | MVT::ValueType CVT = Count.getValueType(); |
| 4753 | SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4754 | DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); |
| 4755 | Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, |
| 4756 | Left, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4757 | InFlag = Chain.getValue(1); |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 4758 | Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4759 | Ops.clear(); |
| 4760 | Ops.push_back(Chain); |
| 4761 | Ops.push_back(DAG.getValueType(MVT::i8)); |
| 4762 | Ops.push_back(InFlag); |
Evan Cheng | 311ace0 | 2006-08-11 07:35:45 +0000 | [diff] [blame] | 4763 | Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4764 | } else if (BytesLeft) { |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4765 | // Handle the last 1 - 7 bytes. |
| 4766 | unsigned Offset = SizeVal - BytesLeft; |
| 4767 | MVT::ValueType AddrVT = Dst.getValueType(); |
| 4768 | MVT::ValueType SizeVT = Size.getValueType(); |
| 4769 | |
| 4770 | Chain = DAG.getMemset(Chain, |
| 4771 | DAG.getNode(ISD::ADD, AddrVT, Dst, |
| 4772 | DAG.getConstant(Offset, AddrVT)), |
| 4773 | Src, |
| 4774 | DAG.getConstant(BytesLeft, SizeVT), |
Dan Gohman | 1f13c68 | 2008-04-28 17:15:20 +0000 | [diff] [blame] | 4775 | Align, DstSV, DstSVOff + Offset); |
Evan Cheng | 386031a | 2006-03-24 07:29:27 +0000 | [diff] [blame] | 4776 | } |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 4777 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4778 | // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4779 | return Chain; |
| 4780 | } |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 4781 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4782 | SDOperand |
| 4783 | X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, |
| 4784 | SDOperand Chain, |
| 4785 | SDOperand Dst, SDOperand Src, |
| 4786 | SDOperand Size, unsigned Align, |
| 4787 | bool AlwaysInline, |
Dan Gohman | 1f13c68 | 2008-04-28 17:15:20 +0000 | [diff] [blame] | 4788 | const Value *DstSV, uint64_t DstSVOff, |
| 4789 | const Value *SrcSV, uint64_t SrcSVOff){ |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4790 | |
| 4791 | // This requires the copy size to be a constant, preferrably |
| 4792 | // within a subtarget-specific limit. |
| 4793 | ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); |
| 4794 | if (!ConstantSize) |
| 4795 | return SDOperand(); |
| 4796 | uint64_t SizeVal = ConstantSize->getValue(); |
| 4797 | if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) |
| 4798 | return SDOperand(); |
| 4799 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4800 | MVT::ValueType AVT; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4801 | unsigned BytesLeft = 0; |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4802 | if (Align >= 8 && Subtarget->is64Bit()) |
| 4803 | AVT = MVT::i64; |
| 4804 | else if (Align >= 4) |
| 4805 | AVT = MVT::i32; |
| 4806 | else if (Align >= 2) |
| 4807 | AVT = MVT::i16; |
| 4808 | else |
| 4809 | AVT = MVT::i8; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4810 | |
Rafael Espindola | 068317b | 2007-09-28 12:53:01 +0000 | [diff] [blame] | 4811 | unsigned UBytes = MVT::getSizeInBits(AVT) / 8; |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4812 | unsigned CountVal = SizeVal / UBytes; |
| 4813 | SDOperand Count = DAG.getIntPtrConstant(CountVal); |
| 4814 | BytesLeft = SizeVal % UBytes; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4815 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4816 | SDOperand InFlag(0, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4817 | Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, |
| 4818 | Count, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4819 | InFlag = Chain.getValue(1); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4820 | Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4821 | Dst, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4822 | InFlag = Chain.getValue(1); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4823 | Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4824 | Src, InFlag); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4825 | InFlag = Chain.getValue(1); |
| 4826 | |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 4827 | SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4828 | SmallVector<SDOperand, 8> Ops; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4829 | Ops.push_back(Chain); |
| 4830 | Ops.push_back(DAG.getValueType(AVT)); |
| 4831 | Ops.push_back(InFlag); |
Evan Cheng | 2749c72 | 2008-04-25 00:26:43 +0000 | [diff] [blame] | 4832 | SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4833 | |
Evan Cheng | 2749c72 | 2008-04-25 00:26:43 +0000 | [diff] [blame] | 4834 | SmallVector<SDOperand, 4> Results; |
| 4835 | Results.push_back(RepMovs); |
Rafael Espindola | 068317b | 2007-09-28 12:53:01 +0000 | [diff] [blame] | 4836 | if (BytesLeft) { |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4837 | // Handle the last 1 - 7 bytes. |
| 4838 | unsigned Offset = SizeVal - BytesLeft; |
| 4839 | MVT::ValueType DstVT = Dst.getValueType(); |
| 4840 | MVT::ValueType SrcVT = Src.getValueType(); |
| 4841 | MVT::ValueType SizeVT = Size.getValueType(); |
Evan Cheng | 2749c72 | 2008-04-25 00:26:43 +0000 | [diff] [blame] | 4842 | Results.push_back(DAG.getMemcpy(Chain, |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4843 | DAG.getNode(ISD::ADD, DstVT, Dst, |
Evan Cheng | 2749c72 | 2008-04-25 00:26:43 +0000 | [diff] [blame] | 4844 | DAG.getConstant(Offset, DstVT)), |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4845 | DAG.getNode(ISD::ADD, SrcVT, Src, |
Evan Cheng | 2749c72 | 2008-04-25 00:26:43 +0000 | [diff] [blame] | 4846 | DAG.getConstant(Offset, SrcVT)), |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4847 | DAG.getConstant(BytesLeft, SizeVT), |
| 4848 | Align, AlwaysInline, |
Dan Gohman | 1f13c68 | 2008-04-28 17:15:20 +0000 | [diff] [blame] | 4849 | DstSV, DstSVOff + Offset, |
| 4850 | SrcSV, SrcSVOff + Offset)); |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 4851 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4852 | |
Dan Gohman | 707e018 | 2008-04-12 04:36:06 +0000 | [diff] [blame] | 4853 | return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4854 | } |
| 4855 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4856 | /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain |
| 4857 | SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 4858 | SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4859 | SDOperand TheChain = N->getOperand(0); |
| 4860 | SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); |
Evan Cheng | 3fa9dff | 2006-11-29 08:28:13 +0000 | [diff] [blame] | 4861 | if (Subtarget->is64Bit()) { |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4862 | SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); |
| 4863 | SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, |
| 4864 | MVT::i64, rax.getValue(2)); |
| 4865 | SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, |
Evan Cheng | 3fa9dff | 2006-11-29 08:28:13 +0000 | [diff] [blame] | 4866 | DAG.getConstant(32, MVT::i8)); |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4867 | SDOperand Ops[] = { |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4868 | DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1) |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4869 | }; |
Chris Lattner | d96d072 | 2007-02-25 06:40:16 +0000 | [diff] [blame] | 4870 | |
| 4871 | Tys = DAG.getVTList(MVT::i64, MVT::Other); |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4872 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; |
Evan Cheng | 3fa9dff | 2006-11-29 08:28:13 +0000 | [diff] [blame] | 4873 | } |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4874 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 4875 | SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); |
| 4876 | SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, |
| 4877 | MVT::i32, eax.getValue(2)); |
| 4878 | // Use a buildpair to merge the two 32-bit values into a 64-bit one. |
| 4879 | SDOperand Ops[] = { eax, edx }; |
| 4880 | Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2); |
| 4881 | |
| 4882 | // Use a MERGE_VALUES to return the value and chain. |
| 4883 | Ops[1] = edx.getValue(1); |
| 4884 | Tys = DAG.getVTList(MVT::i64, MVT::Other); |
| 4885 | return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4886 | } |
| 4887 | |
| 4888 | SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4889 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
Evan Cheng | 8b2794a | 2006-10-13 21:14:26 +0000 | [diff] [blame] | 4890 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4891 | if (!Subtarget->is64Bit()) { |
| 4892 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
| 4893 | // memory location argument. |
| 4894 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4895 | return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4896 | } |
| 4897 | |
| 4898 | // __va_list_tag: |
| 4899 | // gp_offset (0 - 6 * 8) |
| 4900 | // fp_offset (48 - 48 + 8 * 16) |
| 4901 | // overflow_arg_area (point to parameters coming in memory). |
| 4902 | // reg_save_area |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 4903 | SmallVector<SDOperand, 8> MemOps; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4904 | SDOperand FIN = Op.getOperand(1); |
| 4905 | // Store gp_offset |
Evan Cheng | 786225a | 2006-10-05 23:01:46 +0000 | [diff] [blame] | 4906 | SDOperand Store = DAG.getStore(Op.getOperand(0), |
| 4907 | DAG.getConstant(VarArgsGPOffset, MVT::i32), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4908 | FIN, SV, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4909 | MemOps.push_back(Store); |
| 4910 | |
| 4911 | // Store fp_offset |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4912 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); |
Evan Cheng | 786225a | 2006-10-05 23:01:46 +0000 | [diff] [blame] | 4913 | Store = DAG.getStore(Op.getOperand(0), |
| 4914 | DAG.getConstant(VarArgsFPOffset, MVT::i32), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4915 | FIN, SV, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4916 | MemOps.push_back(Store); |
| 4917 | |
| 4918 | // Store ptr to overflow_arg_area |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4919 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4920 | SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4921 | Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4922 | MemOps.push_back(Store); |
| 4923 | |
| 4924 | // Store ptr to reg_save_area. |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 4925 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4926 | SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4927 | Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 4928 | MemOps.push_back(Store); |
| 4929 | return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4930 | } |
| 4931 | |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 4932 | SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) { |
| 4933 | // X86-64 va_list is a struct { i32, i32, i8*, i8* }. |
Dan Gohman | 2826913 | 2008-04-18 20:55:41 +0000 | [diff] [blame] | 4934 | assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 4935 | SDOperand Chain = Op.getOperand(0); |
| 4936 | SDOperand DstPtr = Op.getOperand(1); |
| 4937 | SDOperand SrcPtr = Op.getOperand(2); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 4938 | const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); |
| 4939 | const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 4940 | |
Dan Gohman | 2826913 | 2008-04-18 20:55:41 +0000 | [diff] [blame] | 4941 | return DAG.getMemcpy(Chain, DstPtr, SrcPtr, |
| 4942 | DAG.getIntPtrConstant(24), 8, false, |
| 4943 | DstSV, 0, SrcSV, 0); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 4944 | } |
| 4945 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4946 | SDOperand |
| 4947 | X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { |
| 4948 | unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); |
| 4949 | switch (IntNo) { |
| 4950 | default: return SDOperand(); // Don't custom lower most intrinsics. |
Evan Cheng | 5759f97 | 2008-05-04 09:15:50 +0000 | [diff] [blame] | 4951 | // Comparison intrinsics. |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4952 | case Intrinsic::x86_sse_comieq_ss: |
| 4953 | case Intrinsic::x86_sse_comilt_ss: |
| 4954 | case Intrinsic::x86_sse_comile_ss: |
| 4955 | case Intrinsic::x86_sse_comigt_ss: |
| 4956 | case Intrinsic::x86_sse_comige_ss: |
| 4957 | case Intrinsic::x86_sse_comineq_ss: |
| 4958 | case Intrinsic::x86_sse_ucomieq_ss: |
| 4959 | case Intrinsic::x86_sse_ucomilt_ss: |
| 4960 | case Intrinsic::x86_sse_ucomile_ss: |
| 4961 | case Intrinsic::x86_sse_ucomigt_ss: |
| 4962 | case Intrinsic::x86_sse_ucomige_ss: |
| 4963 | case Intrinsic::x86_sse_ucomineq_ss: |
| 4964 | case Intrinsic::x86_sse2_comieq_sd: |
| 4965 | case Intrinsic::x86_sse2_comilt_sd: |
| 4966 | case Intrinsic::x86_sse2_comile_sd: |
| 4967 | case Intrinsic::x86_sse2_comigt_sd: |
| 4968 | case Intrinsic::x86_sse2_comige_sd: |
| 4969 | case Intrinsic::x86_sse2_comineq_sd: |
| 4970 | case Intrinsic::x86_sse2_ucomieq_sd: |
| 4971 | case Intrinsic::x86_sse2_ucomilt_sd: |
| 4972 | case Intrinsic::x86_sse2_ucomile_sd: |
| 4973 | case Intrinsic::x86_sse2_ucomigt_sd: |
| 4974 | case Intrinsic::x86_sse2_ucomige_sd: |
| 4975 | case Intrinsic::x86_sse2_ucomineq_sd: { |
| 4976 | unsigned Opc = 0; |
| 4977 | ISD::CondCode CC = ISD::SETCC_INVALID; |
| 4978 | switch (IntNo) { |
| 4979 | default: break; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 4980 | case Intrinsic::x86_sse_comieq_ss: |
| 4981 | case Intrinsic::x86_sse2_comieq_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4982 | Opc = X86ISD::COMI; |
| 4983 | CC = ISD::SETEQ; |
| 4984 | break; |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 4985 | case Intrinsic::x86_sse_comilt_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 4986 | case Intrinsic::x86_sse2_comilt_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4987 | Opc = X86ISD::COMI; |
| 4988 | CC = ISD::SETLT; |
| 4989 | break; |
| 4990 | case Intrinsic::x86_sse_comile_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 4991 | case Intrinsic::x86_sse2_comile_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4992 | Opc = X86ISD::COMI; |
| 4993 | CC = ISD::SETLE; |
| 4994 | break; |
| 4995 | case Intrinsic::x86_sse_comigt_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 4996 | case Intrinsic::x86_sse2_comigt_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 4997 | Opc = X86ISD::COMI; |
| 4998 | CC = ISD::SETGT; |
| 4999 | break; |
| 5000 | case Intrinsic::x86_sse_comige_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5001 | case Intrinsic::x86_sse2_comige_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5002 | Opc = X86ISD::COMI; |
| 5003 | CC = ISD::SETGE; |
| 5004 | break; |
| 5005 | case Intrinsic::x86_sse_comineq_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5006 | case Intrinsic::x86_sse2_comineq_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5007 | Opc = X86ISD::COMI; |
| 5008 | CC = ISD::SETNE; |
| 5009 | break; |
| 5010 | case Intrinsic::x86_sse_ucomieq_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5011 | case Intrinsic::x86_sse2_ucomieq_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5012 | Opc = X86ISD::UCOMI; |
| 5013 | CC = ISD::SETEQ; |
| 5014 | break; |
| 5015 | case Intrinsic::x86_sse_ucomilt_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5016 | case Intrinsic::x86_sse2_ucomilt_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5017 | Opc = X86ISD::UCOMI; |
| 5018 | CC = ISD::SETLT; |
| 5019 | break; |
| 5020 | case Intrinsic::x86_sse_ucomile_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5021 | case Intrinsic::x86_sse2_ucomile_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5022 | Opc = X86ISD::UCOMI; |
| 5023 | CC = ISD::SETLE; |
| 5024 | break; |
| 5025 | case Intrinsic::x86_sse_ucomigt_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5026 | case Intrinsic::x86_sse2_ucomigt_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5027 | Opc = X86ISD::UCOMI; |
| 5028 | CC = ISD::SETGT; |
| 5029 | break; |
| 5030 | case Intrinsic::x86_sse_ucomige_ss: |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5031 | case Intrinsic::x86_sse2_ucomige_sd: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5032 | Opc = X86ISD::UCOMI; |
| 5033 | CC = ISD::SETGE; |
| 5034 | break; |
| 5035 | case Intrinsic::x86_sse_ucomineq_ss: |
| 5036 | case Intrinsic::x86_sse2_ucomineq_sd: |
| 5037 | Opc = X86ISD::UCOMI; |
| 5038 | CC = ISD::SETNE; |
| 5039 | break; |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5040 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 5041 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5042 | unsigned X86CC; |
Chris Lattner | f957051 | 2006-09-13 03:22:10 +0000 | [diff] [blame] | 5043 | SDOperand LHS = Op.getOperand(1); |
| 5044 | SDOperand RHS = Op.getOperand(2); |
| 5045 | translateX86CC(CC, true, X86CC, LHS, RHS, DAG); |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 5046 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 5047 | SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); |
| 5048 | SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, |
| 5049 | DAG.getConstant(X86CC, MVT::i8), Cond); |
| 5050 | return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5051 | } |
Evan Cheng | 5759f97 | 2008-05-04 09:15:50 +0000 | [diff] [blame] | 5052 | |
| 5053 | // Fix vector shift instructions where the last operand is a non-immediate |
| 5054 | // i32 value. |
| 5055 | case Intrinsic::x86_sse2_pslli_w: |
| 5056 | case Intrinsic::x86_sse2_pslli_d: |
| 5057 | case Intrinsic::x86_sse2_pslli_q: |
| 5058 | case Intrinsic::x86_sse2_psrli_w: |
| 5059 | case Intrinsic::x86_sse2_psrli_d: |
| 5060 | case Intrinsic::x86_sse2_psrli_q: |
| 5061 | case Intrinsic::x86_sse2_psrai_w: |
| 5062 | case Intrinsic::x86_sse2_psrai_d: |
| 5063 | case Intrinsic::x86_mmx_pslli_w: |
| 5064 | case Intrinsic::x86_mmx_pslli_d: |
| 5065 | case Intrinsic::x86_mmx_pslli_q: |
| 5066 | case Intrinsic::x86_mmx_psrli_w: |
| 5067 | case Intrinsic::x86_mmx_psrli_d: |
| 5068 | case Intrinsic::x86_mmx_psrli_q: |
| 5069 | case Intrinsic::x86_mmx_psrai_w: |
| 5070 | case Intrinsic::x86_mmx_psrai_d: { |
| 5071 | SDOperand ShAmt = Op.getOperand(2); |
| 5072 | if (isa<ConstantSDNode>(ShAmt)) |
| 5073 | return SDOperand(); |
| 5074 | |
| 5075 | unsigned NewIntNo = 0; |
| 5076 | MVT::ValueType ShAmtVT = MVT::v4i32; |
| 5077 | switch (IntNo) { |
| 5078 | case Intrinsic::x86_sse2_pslli_w: |
| 5079 | NewIntNo = Intrinsic::x86_sse2_psll_w; |
| 5080 | break; |
| 5081 | case Intrinsic::x86_sse2_pslli_d: |
| 5082 | NewIntNo = Intrinsic::x86_sse2_psll_d; |
| 5083 | break; |
| 5084 | case Intrinsic::x86_sse2_pslli_q: |
| 5085 | NewIntNo = Intrinsic::x86_sse2_psll_q; |
| 5086 | break; |
| 5087 | case Intrinsic::x86_sse2_psrli_w: |
| 5088 | NewIntNo = Intrinsic::x86_sse2_psrl_w; |
| 5089 | break; |
| 5090 | case Intrinsic::x86_sse2_psrli_d: |
| 5091 | NewIntNo = Intrinsic::x86_sse2_psrl_d; |
| 5092 | break; |
| 5093 | case Intrinsic::x86_sse2_psrli_q: |
| 5094 | NewIntNo = Intrinsic::x86_sse2_psrl_q; |
| 5095 | break; |
| 5096 | case Intrinsic::x86_sse2_psrai_w: |
| 5097 | NewIntNo = Intrinsic::x86_sse2_psra_w; |
| 5098 | break; |
| 5099 | case Intrinsic::x86_sse2_psrai_d: |
| 5100 | NewIntNo = Intrinsic::x86_sse2_psra_d; |
| 5101 | break; |
| 5102 | default: { |
| 5103 | ShAmtVT = MVT::v2i32; |
| 5104 | switch (IntNo) { |
| 5105 | case Intrinsic::x86_mmx_pslli_w: |
| 5106 | NewIntNo = Intrinsic::x86_mmx_psll_w; |
| 5107 | break; |
| 5108 | case Intrinsic::x86_mmx_pslli_d: |
| 5109 | NewIntNo = Intrinsic::x86_mmx_psll_d; |
| 5110 | break; |
| 5111 | case Intrinsic::x86_mmx_pslli_q: |
| 5112 | NewIntNo = Intrinsic::x86_mmx_psll_q; |
| 5113 | break; |
| 5114 | case Intrinsic::x86_mmx_psrli_w: |
| 5115 | NewIntNo = Intrinsic::x86_mmx_psrl_w; |
| 5116 | break; |
| 5117 | case Intrinsic::x86_mmx_psrli_d: |
| 5118 | NewIntNo = Intrinsic::x86_mmx_psrl_d; |
| 5119 | break; |
| 5120 | case Intrinsic::x86_mmx_psrli_q: |
| 5121 | NewIntNo = Intrinsic::x86_mmx_psrl_q; |
| 5122 | break; |
| 5123 | case Intrinsic::x86_mmx_psrai_w: |
| 5124 | NewIntNo = Intrinsic::x86_mmx_psra_w; |
| 5125 | break; |
| 5126 | case Intrinsic::x86_mmx_psrai_d: |
| 5127 | NewIntNo = Intrinsic::x86_mmx_psra_d; |
| 5128 | break; |
| 5129 | default: abort(); // Can't reach here. |
| 5130 | } |
| 5131 | break; |
| 5132 | } |
| 5133 | } |
| 5134 | MVT::ValueType VT = Op.getValueType(); |
| 5135 | ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, |
| 5136 | DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); |
| 5137 | return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, |
| 5138 | DAG.getConstant(NewIntNo, MVT::i32), |
| 5139 | Op.getOperand(1), ShAmt); |
| 5140 | } |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 5141 | } |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 5142 | } |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5143 | |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 5144 | SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { |
| 5145 | // Depths > 0 not supported yet! |
| 5146 | if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) |
| 5147 | return SDOperand(); |
| 5148 | |
| 5149 | // Just load the return address |
| 5150 | SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); |
| 5151 | return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); |
| 5152 | } |
| 5153 | |
| 5154 | SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { |
| 5155 | // Depths > 0 not supported yet! |
| 5156 | if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) |
| 5157 | return SDOperand(); |
| 5158 | |
| 5159 | SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); |
| 5160 | return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 5161 | DAG.getIntPtrConstant(4)); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 5162 | } |
| 5163 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5164 | SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, |
| 5165 | SelectionDAG &DAG) { |
| 5166 | // Is not yet supported on x86-64 |
| 5167 | if (Subtarget->is64Bit()) |
| 5168 | return SDOperand(); |
| 5169 | |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 5170 | return DAG.getIntPtrConstant(8); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5171 | } |
| 5172 | |
| 5173 | SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG) |
| 5174 | { |
| 5175 | assert(!Subtarget->is64Bit() && |
| 5176 | "Lowering of eh_return builtin is not supported yet on x86-64"); |
| 5177 | |
| 5178 | MachineFunction &MF = DAG.getMachineFunction(); |
| 5179 | SDOperand Chain = Op.getOperand(0); |
| 5180 | SDOperand Offset = Op.getOperand(1); |
| 5181 | SDOperand Handler = Op.getOperand(2); |
| 5182 | |
| 5183 | SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF), |
| 5184 | getPointerTy()); |
| 5185 | |
| 5186 | SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, |
Chris Lattner | 0bd4893 | 2008-01-17 07:00:52 +0000 | [diff] [blame] | 5187 | DAG.getIntPtrConstant(-4UL)); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5188 | StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); |
| 5189 | Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); |
| 5190 | Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr); |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 5191 | MF.getRegInfo().addLiveOut(X86::ECX); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5192 | |
| 5193 | return DAG.getNode(X86ISD::EH_RETURN, MVT::Other, |
| 5194 | Chain, DAG.getRegister(X86::ECX, getPointerTy())); |
| 5195 | } |
| 5196 | |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5197 | SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, |
| 5198 | SelectionDAG &DAG) { |
| 5199 | SDOperand Root = Op.getOperand(0); |
| 5200 | SDOperand Trmp = Op.getOperand(1); // trampoline |
| 5201 | SDOperand FPtr = Op.getOperand(2); // nested function |
| 5202 | SDOperand Nest = Op.getOperand(3); // 'nest' parameter value |
| 5203 | |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5204 | const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5205 | |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5206 | const X86InstrInfo *TII = |
| 5207 | ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); |
| 5208 | |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5209 | if (Subtarget->is64Bit()) { |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5210 | SDOperand OutChains[6]; |
| 5211 | |
| 5212 | // Large code-model. |
| 5213 | |
| 5214 | const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); |
| 5215 | const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); |
| 5216 | |
| 5217 | const unsigned char N86R10 = |
Dan Gohman | 6078330 | 2008-02-08 03:29:40 +0000 | [diff] [blame] | 5218 | ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5219 | const unsigned char N86R11 = |
Dan Gohman | 6078330 | 2008-02-08 03:29:40 +0000 | [diff] [blame] | 5220 | ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5221 | |
| 5222 | const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix |
| 5223 | |
| 5224 | // Load the pointer to the nested function into R11. |
| 5225 | unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 |
| 5226 | SDOperand Addr = Trmp; |
| 5227 | OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5228 | TrmpAddr, 0); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5229 | |
| 5230 | Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5231 | OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5232 | |
| 5233 | // Load the 'nest' parameter value into R10. |
| 5234 | // R10 is specified in X86CallingConv.td |
| 5235 | OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 |
| 5236 | Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); |
| 5237 | OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5238 | TrmpAddr, 10); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5239 | |
| 5240 | Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5241 | OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5242 | |
| 5243 | // Jump to the nested function. |
| 5244 | OpCode = (JMP64r << 8) | REX_WB; // jmpq *... |
| 5245 | Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); |
| 5246 | OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5247 | TrmpAddr, 20); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5248 | |
| 5249 | unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 |
| 5250 | Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); |
| 5251 | OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5252 | TrmpAddr, 22); |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5253 | |
| 5254 | SDOperand Ops[] = |
| 5255 | { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; |
| 5256 | return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5257 | } else { |
Dan Gohman | bbfb9c5 | 2008-01-31 01:01:48 +0000 | [diff] [blame] | 5258 | const Function *Func = |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5259 | cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); |
| 5260 | unsigned CC = Func->getCallingConv(); |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 5261 | unsigned NestReg; |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5262 | |
| 5263 | switch (CC) { |
| 5264 | default: |
| 5265 | assert(0 && "Unsupported calling convention"); |
| 5266 | case CallingConv::C: |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5267 | case CallingConv::X86_StdCall: { |
| 5268 | // Pass 'nest' parameter in ECX. |
| 5269 | // Must be kept in sync with X86CallingConv.td |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 5270 | NestReg = X86::ECX; |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5271 | |
| 5272 | // Check that ECX wasn't needed by an 'inreg' parameter. |
| 5273 | const FunctionType *FTy = Func->getFunctionType(); |
Chris Lattner | 58d7491 | 2008-03-12 17:45:29 +0000 | [diff] [blame] | 5274 | const PAListPtr &Attrs = Func->getParamAttrs(); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5275 | |
Chris Lattner | 58d7491 | 2008-03-12 17:45:29 +0000 | [diff] [blame] | 5276 | if (!Attrs.isEmpty() && !Func->isVarArg()) { |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5277 | unsigned InRegCount = 0; |
| 5278 | unsigned Idx = 1; |
| 5279 | |
| 5280 | for (FunctionType::param_iterator I = FTy->param_begin(), |
| 5281 | E = FTy->param_end(); I != E; ++I, ++Idx) |
Chris Lattner | 58d7491 | 2008-03-12 17:45:29 +0000 | [diff] [blame] | 5282 | if (Attrs.paramHasAttr(Idx, ParamAttr::InReg)) |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5283 | // FIXME: should only count parameters that are lowered to integers. |
| 5284 | InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32; |
| 5285 | |
| 5286 | if (InRegCount > 2) { |
| 5287 | cerr << "Nest register in use - reduce number of inreg parameters!\n"; |
| 5288 | abort(); |
| 5289 | } |
| 5290 | } |
| 5291 | break; |
| 5292 | } |
| 5293 | case CallingConv::X86_FastCall: |
| 5294 | // Pass 'nest' parameter in EAX. |
| 5295 | // Must be kept in sync with X86CallingConv.td |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 5296 | NestReg = X86::EAX; |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5297 | break; |
| 5298 | } |
| 5299 | |
| 5300 | SDOperand OutChains[4]; |
| 5301 | SDOperand Addr, Disp; |
| 5302 | |
| 5303 | Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); |
| 5304 | Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); |
| 5305 | |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5306 | const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); |
| 5307 | const unsigned char N86Reg = |
Dan Gohman | 6078330 | 2008-02-08 03:29:40 +0000 | [diff] [blame] | 5308 | ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 5309 | OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5310 | Trmp, TrmpAddr, 0); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5311 | |
| 5312 | Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5313 | OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5314 | |
Duncan Sands | 339e14f | 2008-01-16 22:55:25 +0000 | [diff] [blame] | 5315 | const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5316 | Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); |
| 5317 | OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5318 | TrmpAddr, 5, false, 1); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5319 | |
| 5320 | Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); |
Dan Gohman | 69de193 | 2008-02-06 22:27:42 +0000 | [diff] [blame] | 5321 | OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5322 | |
Duncan Sands | f7331b3 | 2007-09-11 14:10:23 +0000 | [diff] [blame] | 5323 | SDOperand Ops[] = |
| 5324 | { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; |
| 5325 | return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5326 | } |
| 5327 | } |
| 5328 | |
Dan Gohman | 1a02486 | 2008-01-31 00:41:03 +0000 | [diff] [blame] | 5329 | SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { |
Anton Korobeynikov | 45b22fa | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 5330 | /* |
| 5331 | The rounding mode is in bits 11:10 of FPSR, and has the following |
| 5332 | settings: |
| 5333 | 00 Round to nearest |
| 5334 | 01 Round to -inf |
| 5335 | 10 Round to +inf |
| 5336 | 11 Round to 0 |
| 5337 | |
| 5338 | FLT_ROUNDS, on the other hand, expects the following: |
| 5339 | -1 Undefined |
| 5340 | 0 Round to 0 |
| 5341 | 1 Round to nearest |
| 5342 | 2 Round to +inf |
| 5343 | 3 Round to -inf |
| 5344 | |
| 5345 | To perform the conversion, we do: |
| 5346 | (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) |
| 5347 | */ |
| 5348 | |
| 5349 | MachineFunction &MF = DAG.getMachineFunction(); |
| 5350 | const TargetMachine &TM = MF.getTarget(); |
| 5351 | const TargetFrameInfo &TFI = *TM.getFrameInfo(); |
| 5352 | unsigned StackAlignment = TFI.getStackAlignment(); |
| 5353 | MVT::ValueType VT = Op.getValueType(); |
| 5354 | |
| 5355 | // Save FP Control Word to stack slot |
| 5356 | int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); |
| 5357 | SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); |
| 5358 | |
| 5359 | SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, |
| 5360 | DAG.getEntryNode(), StackSlot); |
| 5361 | |
| 5362 | // Load FP Control Word from stack slot |
| 5363 | SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); |
| 5364 | |
| 5365 | // Transform as necessary |
| 5366 | SDOperand CWD1 = |
| 5367 | DAG.getNode(ISD::SRL, MVT::i16, |
| 5368 | DAG.getNode(ISD::AND, MVT::i16, |
| 5369 | CWD, DAG.getConstant(0x800, MVT::i16)), |
| 5370 | DAG.getConstant(11, MVT::i8)); |
| 5371 | SDOperand CWD2 = |
| 5372 | DAG.getNode(ISD::SRL, MVT::i16, |
| 5373 | DAG.getNode(ISD::AND, MVT::i16, |
| 5374 | CWD, DAG.getConstant(0x400, MVT::i16)), |
| 5375 | DAG.getConstant(9, MVT::i8)); |
| 5376 | |
| 5377 | SDOperand RetVal = |
| 5378 | DAG.getNode(ISD::AND, MVT::i16, |
| 5379 | DAG.getNode(ISD::ADD, MVT::i16, |
| 5380 | DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), |
| 5381 | DAG.getConstant(1, MVT::i16)), |
| 5382 | DAG.getConstant(3, MVT::i16)); |
| 5383 | |
| 5384 | |
| 5385 | return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? |
| 5386 | ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); |
| 5387 | } |
| 5388 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5389 | SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { |
| 5390 | MVT::ValueType VT = Op.getValueType(); |
| 5391 | MVT::ValueType OpVT = VT; |
| 5392 | unsigned NumBits = MVT::getSizeInBits(VT); |
| 5393 | |
| 5394 | Op = Op.getOperand(0); |
| 5395 | if (VT == MVT::i8) { |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 5396 | // Zero extend to i32 since there is not an i8 bsr. |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5397 | OpVT = MVT::i32; |
| 5398 | Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); |
| 5399 | } |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5400 | |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 5401 | // Issue a bsr (scan bits in reverse) which also sets EFLAGS. |
| 5402 | SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); |
| 5403 | Op = DAG.getNode(X86ISD::BSR, VTs, Op); |
| 5404 | |
| 5405 | // If src is zero (i.e. bsr sets ZF), returns NumBits. |
| 5406 | SmallVector<SDOperand, 4> Ops; |
| 5407 | Ops.push_back(Op); |
| 5408 | Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); |
| 5409 | Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); |
| 5410 | Ops.push_back(Op.getValue(1)); |
| 5411 | Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); |
| 5412 | |
| 5413 | // Finally xor with NumBits-1. |
| 5414 | Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); |
| 5415 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5416 | if (VT == MVT::i8) |
| 5417 | Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); |
| 5418 | return Op; |
| 5419 | } |
| 5420 | |
| 5421 | SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { |
| 5422 | MVT::ValueType VT = Op.getValueType(); |
| 5423 | MVT::ValueType OpVT = VT; |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 5424 | unsigned NumBits = MVT::getSizeInBits(VT); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5425 | |
| 5426 | Op = Op.getOperand(0); |
| 5427 | if (VT == MVT::i8) { |
| 5428 | OpVT = MVT::i32; |
| 5429 | Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); |
| 5430 | } |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 5431 | |
| 5432 | // Issue a bsf (scan bits forward) which also sets EFLAGS. |
| 5433 | SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); |
| 5434 | Op = DAG.getNode(X86ISD::BSF, VTs, Op); |
| 5435 | |
| 5436 | // If src is zero (i.e. bsf sets ZF), returns NumBits. |
| 5437 | SmallVector<SDOperand, 4> Ops; |
| 5438 | Ops.push_back(Op); |
| 5439 | Ops.push_back(DAG.getConstant(NumBits, OpVT)); |
| 5440 | Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); |
| 5441 | Ops.push_back(Op.getValue(1)); |
| 5442 | Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); |
| 5443 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5444 | if (VT == MVT::i8) |
| 5445 | Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); |
| 5446 | return Op; |
| 5447 | } |
| 5448 | |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5449 | SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) { |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5450 | MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT(); |
Andrew Lenharth | a76e2f0 | 2008-03-04 21:13:33 +0000 | [diff] [blame] | 5451 | unsigned Reg = 0; |
| 5452 | unsigned size = 0; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5453 | switch(T) { |
| 5454 | case MVT::i8: Reg = X86::AL; size = 1; break; |
| 5455 | case MVT::i16: Reg = X86::AX; size = 2; break; |
| 5456 | case MVT::i32: Reg = X86::EAX; size = 4; break; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5457 | case MVT::i64: |
| 5458 | if (Subtarget->is64Bit()) { |
| 5459 | Reg = X86::RAX; size = 8; |
| 5460 | } else //Should go away when LowerType stuff lands |
| 5461 | return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0); |
| 5462 | break; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5463 | }; |
| 5464 | SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, |
Andrew Lenharth | ce1105d | 2008-03-01 22:27:48 +0000 | [diff] [blame] | 5465 | Op.getOperand(3), SDOperand()); |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5466 | SDOperand Ops[] = { cpIn.getValue(0), |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5467 | Op.getOperand(1), |
| 5468 | Op.getOperand(2), |
| 5469 | DAG.getTargetConstant(size, MVT::i8), |
| 5470 | cpIn.getValue(1) }; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5471 | SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 5472 | SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); |
| 5473 | SDOperand cpOut = |
| 5474 | DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); |
| 5475 | return cpOut; |
| 5476 | } |
| 5477 | |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5478 | SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) { |
| 5479 | MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT(); |
| 5480 | assert (T == MVT::i64 && "Only know how to expand i64 CAS"); |
| 5481 | SDOperand cpInL, cpInH; |
| 5482 | cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), |
| 5483 | DAG.getConstant(0, MVT::i32)); |
| 5484 | cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), |
| 5485 | DAG.getConstant(1, MVT::i32)); |
| 5486 | cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX, |
| 5487 | cpInL, SDOperand()); |
| 5488 | cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, |
| 5489 | cpInH, cpInL.getValue(1)); |
| 5490 | SDOperand swapInL, swapInH; |
| 5491 | swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), |
| 5492 | DAG.getConstant(0, MVT::i32)); |
| 5493 | swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), |
| 5494 | DAG.getConstant(1, MVT::i32)); |
| 5495 | swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, |
| 5496 | swapInL, cpInH.getValue(1)); |
| 5497 | swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, |
| 5498 | swapInH, swapInL.getValue(1)); |
| 5499 | SDOperand Ops[] = { swapInH.getValue(0), |
| 5500 | Op->getOperand(1), |
| 5501 | swapInH.getValue(1)}; |
| 5502 | SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); |
| 5503 | SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); |
| 5504 | SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, |
| 5505 | Result.getValue(1)); |
| 5506 | SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, |
| 5507 | cpOutL.getValue(2)); |
| 5508 | SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; |
| 5509 | SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); |
| 5510 | Tys = DAG.getVTList(MVT::i64, MVT::Other); |
| 5511 | return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val; |
| 5512 | } |
| 5513 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5514 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 5515 | /// |
| 5516 | SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
| 5517 | switch (Op.getOpcode()) { |
| 5518 | default: assert(0 && "Should not custom lower this!"); |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5519 | case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5520 | case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); |
| 5521 | case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); |
| 5522 | case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); |
| 5523 | case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); |
| 5524 | case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); |
| 5525 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
| 5526 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 5527 | case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5528 | case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); |
| 5529 | case ISD::SHL_PARTS: |
| 5530 | case ISD::SRA_PARTS: |
| 5531 | case ISD::SRL_PARTS: return LowerShift(Op, DAG); |
| 5532 | case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); |
| 5533 | case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); |
| 5534 | case ISD::FABS: return LowerFABS(Op, DAG); |
| 5535 | case ISD::FNEG: return LowerFNEG(Op, DAG); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 5536 | case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 5537 | case ISD::SETCC: return LowerSETCC(Op, DAG); |
| 5538 | case ISD::SELECT: return LowerSELECT(Op, DAG); |
| 5539 | case ISD::BRCOND: return LowerBRCOND(Op, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5540 | case ISD::JumpTable: return LowerJumpTable(Op, DAG); |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 5541 | case ISD::CALL: return LowerCALL(Op, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5542 | case ISD::RET: return LowerRET(Op, DAG); |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 5543 | case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5544 | case ISD::VASTART: return LowerVASTART(Op, DAG); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 5545 | case ISD::VACOPY: return LowerVACOPY(Op, DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5546 | case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 5547 | case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); |
| 5548 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5549 | case ISD::FRAME_TO_ARGS_OFFSET: |
| 5550 | return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 5551 | case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5552 | case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 5553 | case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); |
Dan Gohman | 1a02486 | 2008-01-31 00:41:03 +0000 | [diff] [blame] | 5554 | case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5555 | case ISD::CTLZ: return LowerCTLZ(Op, DAG); |
| 5556 | case ISD::CTTZ: return LowerCTTZ(Op, DAG); |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 5557 | |
| 5558 | // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands. |
| 5559 | case ISD::READCYCLECOUNTER: |
| 5560 | return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5561 | } |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 5562 | } |
| 5563 | |
| 5564 | /// ExpandOperation - Provide custom lowering hooks for expanding operations. |
| 5565 | SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { |
| 5566 | switch (N->getOpcode()) { |
| 5567 | default: assert(0 && "Should not custom lower this!"); |
| 5568 | case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG); |
| 5569 | case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG); |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5570 | case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG); |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 5571 | } |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 5572 | } |
| 5573 | |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5574 | const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 5575 | switch (Opcode) { |
| 5576 | default: return NULL; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 5577 | case X86ISD::BSF: return "X86ISD::BSF"; |
| 5578 | case X86ISD::BSR: return "X86ISD::BSR"; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 5579 | case X86ISD::SHLD: return "X86ISD::SHLD"; |
| 5580 | case X86ISD::SHRD: return "X86ISD::SHRD"; |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 5581 | case X86ISD::FAND: return "X86ISD::FAND"; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 5582 | case X86ISD::FOR: return "X86ISD::FOR"; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 5583 | case X86ISD::FXOR: return "X86ISD::FXOR"; |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 5584 | case X86ISD::FSRL: return "X86ISD::FSRL"; |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 5585 | case X86ISD::FILD: return "X86ISD::FILD"; |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 5586 | case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5587 | case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; |
| 5588 | case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; |
| 5589 | case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 5590 | case X86ISD::FLD: return "X86ISD::FLD"; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 5591 | case X86ISD::FST: return "X86ISD::FST"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5592 | case X86ISD::CALL: return "X86ISD::CALL"; |
| 5593 | case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; |
| 5594 | case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; |
| 5595 | case X86ISD::CMP: return "X86ISD::CMP"; |
Evan Cheng | 6be2c58 | 2006-04-05 23:38:46 +0000 | [diff] [blame] | 5596 | case X86ISD::COMI: return "X86ISD::COMI"; |
| 5597 | case X86ISD::UCOMI: return "X86ISD::UCOMI"; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 5598 | case X86ISD::SETCC: return "X86ISD::SETCC"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5599 | case X86ISD::CMOV: return "X86ISD::CMOV"; |
| 5600 | case X86ISD::BRCOND: return "X86ISD::BRCOND"; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 5601 | case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; |
Evan Cheng | 8df346b | 2006-03-04 01:12:00 +0000 | [diff] [blame] | 5602 | case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; |
| 5603 | case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 5604 | case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 5605 | case X86ISD::Wrapper: return "X86ISD::Wrapper"; |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 5606 | case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 5607 | case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; |
Nate Begeman | 14d12ca | 2008-02-11 04:19:36 +0000 | [diff] [blame] | 5608 | case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; |
| 5609 | case X86ISD::PINSRB: return "X86ISD::PINSRB"; |
Evan Cheng | 653159f | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 5610 | case X86ISD::PINSRW: return "X86ISD::PINSRW"; |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 5611 | case X86ISD::FMAX: return "X86ISD::FMAX"; |
| 5612 | case X86ISD::FMIN: return "X86ISD::FMIN"; |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 5613 | case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; |
| 5614 | case X86ISD::FRCP: return "X86ISD::FRCP"; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 5615 | case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; |
| 5616 | case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 5617 | case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 5618 | case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; |
Anton Korobeynikov | 45b22fa | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 5619 | case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 5620 | case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG"; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 5621 | case X86ISD::LCMPXCHG8_DAG: return "x86ISD::LCMPXCHG8_DAG"; |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 5622 | } |
| 5623 | } |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5624 | |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 5625 | // isLegalAddressingMode - Return true if the addressing mode represented |
| 5626 | // by AM is legal for this target, for a load/store of the specified type. |
| 5627 | bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, |
| 5628 | const Type *Ty) const { |
| 5629 | // X86 supports extremely general addressing modes. |
| 5630 | |
| 5631 | // X86 allows a sign-extended 32-bit immediate field as a displacement. |
| 5632 | if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) |
| 5633 | return false; |
| 5634 | |
| 5635 | if (AM.BaseGV) { |
Evan Cheng | 5278784 | 2007-08-01 23:46:47 +0000 | [diff] [blame] | 5636 | // We can only fold this if we don't need an extra load. |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 5637 | if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) |
| 5638 | return false; |
Evan Cheng | 5278784 | 2007-08-01 23:46:47 +0000 | [diff] [blame] | 5639 | |
| 5640 | // X86-64 only supports addr of globals in small code model. |
| 5641 | if (Subtarget->is64Bit()) { |
| 5642 | if (getTargetMachine().getCodeModel() != CodeModel::Small) |
| 5643 | return false; |
| 5644 | // If lower 4G is not available, then we must use rip-relative addressing. |
| 5645 | if (AM.BaseOffs || AM.Scale > 1) |
| 5646 | return false; |
| 5647 | } |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 5648 | } |
| 5649 | |
| 5650 | switch (AM.Scale) { |
| 5651 | case 0: |
| 5652 | case 1: |
| 5653 | case 2: |
| 5654 | case 4: |
| 5655 | case 8: |
| 5656 | // These scales always work. |
| 5657 | break; |
| 5658 | case 3: |
| 5659 | case 5: |
| 5660 | case 9: |
| 5661 | // These scales are formed with basereg+scalereg. Only accept if there is |
| 5662 | // no basereg yet. |
| 5663 | if (AM.HasBaseReg) |
| 5664 | return false; |
| 5665 | break; |
| 5666 | default: // Other stuff never works. |
| 5667 | return false; |
| 5668 | } |
| 5669 | |
| 5670 | return true; |
| 5671 | } |
| 5672 | |
| 5673 | |
Evan Cheng | 2bd122c | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 5674 | bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { |
| 5675 | if (!Ty1->isInteger() || !Ty2->isInteger()) |
| 5676 | return false; |
Evan Cheng | e127a73 | 2007-10-29 07:57:50 +0000 | [diff] [blame] | 5677 | unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); |
| 5678 | unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); |
Evan Cheng | 260e07e | 2008-03-20 02:18:41 +0000 | [diff] [blame] | 5679 | if (NumBits1 <= NumBits2) |
Evan Cheng | e127a73 | 2007-10-29 07:57:50 +0000 | [diff] [blame] | 5680 | return false; |
| 5681 | return Subtarget->is64Bit() || NumBits1 < 64; |
Evan Cheng | 2bd122c | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 5682 | } |
| 5683 | |
Evan Cheng | 3c3ddb3 | 2007-10-29 19:58:20 +0000 | [diff] [blame] | 5684 | bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1, |
| 5685 | MVT::ValueType VT2) const { |
| 5686 | if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2)) |
| 5687 | return false; |
| 5688 | unsigned NumBits1 = MVT::getSizeInBits(VT1); |
| 5689 | unsigned NumBits2 = MVT::getSizeInBits(VT2); |
Evan Cheng | 260e07e | 2008-03-20 02:18:41 +0000 | [diff] [blame] | 5690 | if (NumBits1 <= NumBits2) |
Evan Cheng | 3c3ddb3 | 2007-10-29 19:58:20 +0000 | [diff] [blame] | 5691 | return false; |
| 5692 | return Subtarget->is64Bit() || NumBits1 < 64; |
| 5693 | } |
Evan Cheng | 2bd122c | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 5694 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5695 | /// isShuffleMaskLegal - Targets can use this to indicate that they only |
| 5696 | /// support *some* VECTOR_SHUFFLE operations, those with specific masks. |
| 5697 | /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values |
| 5698 | /// are assumed to be legal. |
| 5699 | bool |
| 5700 | X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { |
| 5701 | // Only do shuffles on 128-bit vector types for now. |
| 5702 | if (MVT::getSizeInBits(VT) == 64) return false; |
| 5703 | return (Mask.Val->getNumOperands() <= 4 || |
Evan Cheng | 49892af | 2007-06-19 00:02:56 +0000 | [diff] [blame] | 5704 | isIdentityMask(Mask.Val) || |
| 5705 | isIdentityMask(Mask.Val, true) || |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5706 | isSplatMask(Mask.Val) || |
| 5707 | isPSHUFHW_PSHUFLWMask(Mask.Val) || |
| 5708 | X86::isUNPCKLMask(Mask.Val) || |
Evan Cheng | 49892af | 2007-06-19 00:02:56 +0000 | [diff] [blame] | 5709 | X86::isUNPCKHMask(Mask.Val) || |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5710 | X86::isUNPCKL_v_undef_Mask(Mask.Val) || |
Evan Cheng | 49892af | 2007-06-19 00:02:56 +0000 | [diff] [blame] | 5711 | X86::isUNPCKH_v_undef_Mask(Mask.Val)); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5712 | } |
| 5713 | |
Dan Gohman | 7d8143f | 2008-04-09 20:09:42 +0000 | [diff] [blame] | 5714 | bool |
| 5715 | X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps, |
| 5716 | MVT::ValueType EVT, |
| 5717 | SelectionDAG &DAG) const { |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5718 | unsigned NumElts = BVOps.size(); |
| 5719 | // Only do shuffles on 128-bit vector types for now. |
| 5720 | if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; |
| 5721 | if (NumElts == 2) return true; |
| 5722 | if (NumElts == 4) { |
Chris Lattner | 5a88b83 | 2007-02-25 07:10:00 +0000 | [diff] [blame] | 5723 | return (isMOVLMask(&BVOps[0], 4) || |
| 5724 | isCommutedMOVL(&BVOps[0], 4, true) || |
| 5725 | isSHUFPMask(&BVOps[0], 4) || |
| 5726 | isCommutedSHUFP(&BVOps[0], 4)); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5727 | } |
| 5728 | return false; |
| 5729 | } |
| 5730 | |
| 5731 | //===----------------------------------------------------------------------===// |
| 5732 | // X86 Scheduler Hooks |
| 5733 | //===----------------------------------------------------------------------===// |
| 5734 | |
| 5735 | MachineBasicBlock * |
Evan Cheng | ff9b373 | 2008-01-30 18:18:23 +0000 | [diff] [blame] | 5736 | X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, |
| 5737 | MachineBasicBlock *BB) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5738 | const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5739 | switch (MI->getOpcode()) { |
| 5740 | default: assert(false && "Unexpected instr type to insert"); |
| 5741 | case X86::CMOV_FR32: |
| 5742 | case X86::CMOV_FR64: |
| 5743 | case X86::CMOV_V4F32: |
| 5744 | case X86::CMOV_V2F64: |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 5745 | case X86::CMOV_V2I64: { |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5746 | // To "insert" a SELECT_CC instruction, we actually have to insert the |
| 5747 | // diamond control-flow pattern. The incoming instruction knows the |
| 5748 | // destination vreg to set, the condition code register to branch on, the |
| 5749 | // true/false values to select between, and a branch opcode to use. |
| 5750 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 5751 | ilist<MachineBasicBlock>::iterator It = BB; |
| 5752 | ++It; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5753 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5754 | // thisMBB: |
| 5755 | // ... |
| 5756 | // TrueVal = ... |
| 5757 | // cmpTY ccX, r1, r2 |
| 5758 | // bCC copy1MBB |
| 5759 | // fallthrough --> copy0MBB |
| 5760 | MachineBasicBlock *thisMBB = BB; |
| 5761 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 5762 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5763 | unsigned Opc = |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 5764 | X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5765 | BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5766 | MachineFunction *F = BB->getParent(); |
| 5767 | F->getBasicBlockList().insert(It, copy0MBB); |
| 5768 | F->getBasicBlockList().insert(It, sinkMBB); |
| 5769 | // Update machine-CFG edges by first adding all successors of the current |
| 5770 | // block to the new block which will contain the Phi node for the select. |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5771 | for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5772 | e = BB->succ_end(); i != e; ++i) |
| 5773 | sinkMBB->addSuccessor(*i); |
| 5774 | // Next, remove all successors of the current block, and add the true |
| 5775 | // and fallthrough blocks as its successors. |
| 5776 | while(!BB->succ_empty()) |
| 5777 | BB->removeSuccessor(BB->succ_begin()); |
| 5778 | BB->addSuccessor(copy0MBB); |
| 5779 | BB->addSuccessor(sinkMBB); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5780 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5781 | // copy0MBB: |
| 5782 | // %FalseValue = ... |
| 5783 | // # fallthrough to sinkMBB |
| 5784 | BB = copy0MBB; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5785 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5786 | // Update machine-CFG edges |
| 5787 | BB->addSuccessor(sinkMBB); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5788 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5789 | // sinkMBB: |
| 5790 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 5791 | // ... |
| 5792 | BB = sinkMBB; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5793 | BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5794 | .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) |
| 5795 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
| 5796 | |
| 5797 | delete MI; // The pseudo instruction is gone now. |
| 5798 | return BB; |
| 5799 | } |
| 5800 | |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 5801 | case X86::FP32_TO_INT16_IN_MEM: |
| 5802 | case X86::FP32_TO_INT32_IN_MEM: |
| 5803 | case X86::FP32_TO_INT64_IN_MEM: |
| 5804 | case X86::FP64_TO_INT16_IN_MEM: |
| 5805 | case X86::FP64_TO_INT32_IN_MEM: |
Dale Johannesen | a996d52 | 2007-08-07 01:17:37 +0000 | [diff] [blame] | 5806 | case X86::FP64_TO_INT64_IN_MEM: |
| 5807 | case X86::FP80_TO_INT16_IN_MEM: |
| 5808 | case X86::FP80_TO_INT32_IN_MEM: |
| 5809 | case X86::FP80_TO_INT64_IN_MEM: { |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5810 | // Change the floating point control register to use "round towards zero" |
| 5811 | // mode when truncating to an integer value. |
| 5812 | MachineFunction *F = BB->getParent(); |
| 5813 | int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5814 | addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5815 | |
| 5816 | // Load the old value of the high byte of the control word... |
| 5817 | unsigned OldCW = |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 5818 | F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5819 | addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5820 | |
| 5821 | // Set the high part to be round to zero... |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5822 | addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) |
| 5823 | .addImm(0xC7F); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5824 | |
| 5825 | // Reload the modified control word now... |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5826 | addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5827 | |
| 5828 | // Restore the memory image of control word to original value |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5829 | addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) |
| 5830 | .addReg(OldCW); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5831 | |
| 5832 | // Get the X86 opcode to use. |
| 5833 | unsigned Opc; |
| 5834 | switch (MI->getOpcode()) { |
| 5835 | default: assert(0 && "illegal opcode!"); |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 5836 | case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; |
| 5837 | case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; |
| 5838 | case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; |
| 5839 | case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; |
| 5840 | case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; |
| 5841 | case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; |
Dale Johannesen | a996d52 | 2007-08-07 01:17:37 +0000 | [diff] [blame] | 5842 | case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; |
| 5843 | case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; |
| 5844 | case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5845 | } |
| 5846 | |
| 5847 | X86AddressMode AM; |
| 5848 | MachineOperand &Op = MI->getOperand(0); |
| 5849 | if (Op.isRegister()) { |
| 5850 | AM.BaseType = X86AddressMode::RegBase; |
| 5851 | AM.Base.Reg = Op.getReg(); |
| 5852 | } else { |
| 5853 | AM.BaseType = X86AddressMode::FrameIndexBase; |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 5854 | AM.Base.FrameIndex = Op.getIndex(); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5855 | } |
| 5856 | Op = MI->getOperand(1); |
| 5857 | if (Op.isImmediate()) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 5858 | AM.Scale = Op.getImm(); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5859 | Op = MI->getOperand(2); |
| 5860 | if (Op.isImmediate()) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 5861 | AM.IndexReg = Op.getImm(); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5862 | Op = MI->getOperand(3); |
| 5863 | if (Op.isGlobalAddress()) { |
| 5864 | AM.GV = Op.getGlobal(); |
| 5865 | } else { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 5866 | AM.Disp = Op.getImm(); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5867 | } |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5868 | addFullAddress(BuildMI(BB, TII->get(Opc)), AM) |
| 5869 | .addReg(MI->getOperand(4).getReg()); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5870 | |
| 5871 | // Reload the original control word now. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 5872 | addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 5873 | |
| 5874 | delete MI; // The pseudo instruction is gone now. |
| 5875 | return BB; |
| 5876 | } |
| 5877 | } |
| 5878 | } |
| 5879 | |
| 5880 | //===----------------------------------------------------------------------===// |
| 5881 | // X86 Optimization Hooks |
| 5882 | //===----------------------------------------------------------------------===// |
| 5883 | |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 5884 | void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, |
Dan Gohman | 977a76f | 2008-02-13 22:28:48 +0000 | [diff] [blame] | 5885 | const APInt &Mask, |
Dan Gohman | fd29e0e | 2008-02-13 00:35:47 +0000 | [diff] [blame] | 5886 | APInt &KnownZero, |
| 5887 | APInt &KnownOne, |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 5888 | const SelectionDAG &DAG, |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 5889 | unsigned Depth) const { |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5890 | unsigned Opc = Op.getOpcode(); |
Evan Cheng | 865f060 | 2006-04-05 06:11:20 +0000 | [diff] [blame] | 5891 | assert((Opc >= ISD::BUILTIN_OP_END || |
| 5892 | Opc == ISD::INTRINSIC_WO_CHAIN || |
| 5893 | Opc == ISD::INTRINSIC_W_CHAIN || |
| 5894 | Opc == ISD::INTRINSIC_VOID) && |
| 5895 | "Should use MaskedValueIsZero if you don't know whether Op" |
| 5896 | " is a target node!"); |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5897 | |
Dan Gohman | f4f92f5 | 2008-02-13 23:07:24 +0000 | [diff] [blame] | 5898 | KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5899 | switch (Opc) { |
Evan Cheng | 865f060 | 2006-04-05 06:11:20 +0000 | [diff] [blame] | 5900 | default: break; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 5901 | case X86ISD::SETCC: |
Dan Gohman | fd29e0e | 2008-02-13 00:35:47 +0000 | [diff] [blame] | 5902 | KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), |
| 5903 | Mask.getBitWidth() - 1); |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 5904 | break; |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5905 | } |
Evan Cheng | 3a03ebb | 2005-12-21 23:05:39 +0000 | [diff] [blame] | 5906 | } |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 5907 | |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5908 | /// getShuffleScalarElt - Returns the scalar element that will make up the ith |
| 5909 | /// element of the result of the vector shuffle. |
| 5910 | static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) { |
| 5911 | MVT::ValueType VT = N->getValueType(0); |
| 5912 | SDOperand PermMask = N->getOperand(2); |
| 5913 | unsigned NumElems = PermMask.getNumOperands(); |
| 5914 | SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1); |
| 5915 | i %= NumElems; |
| 5916 | if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) { |
| 5917 | return (i == 0) |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 5918 | ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5919 | } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { |
| 5920 | SDOperand Idx = PermMask.getOperand(i); |
| 5921 | if (Idx.getOpcode() == ISD::UNDEF) |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 5922 | return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5923 | return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG); |
| 5924 | } |
| 5925 | return SDOperand(); |
| 5926 | } |
| 5927 | |
| 5928 | /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the |
| 5929 | /// node is a GlobalAddress + an offset. |
| 5930 | static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) { |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 5931 | unsigned Opc = N->getOpcode(); |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 5932 | if (Opc == X86ISD::Wrapper) { |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5933 | if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) { |
| 5934 | GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); |
| 5935 | return true; |
| 5936 | } |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 5937 | } else if (Opc == ISD::ADD) { |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5938 | SDOperand N1 = N->getOperand(0); |
| 5939 | SDOperand N2 = N->getOperand(1); |
| 5940 | if (isGAPlusOffset(N1.Val, GA, Offset)) { |
| 5941 | ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); |
| 5942 | if (V) { |
| 5943 | Offset += V->getSignExtended(); |
| 5944 | return true; |
| 5945 | } |
| 5946 | } else if (isGAPlusOffset(N2.Val, GA, Offset)) { |
| 5947 | ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); |
| 5948 | if (V) { |
| 5949 | Offset += V->getSignExtended(); |
| 5950 | return true; |
| 5951 | } |
| 5952 | } |
| 5953 | } |
| 5954 | return false; |
| 5955 | } |
| 5956 | |
| 5957 | /// isConsecutiveLoad - Returns true if N is loading from an address of Base |
| 5958 | /// + Dist * Size. |
| 5959 | static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size, |
| 5960 | MachineFrameInfo *MFI) { |
| 5961 | if (N->getOperand(0).Val != Base->getOperand(0).Val) |
| 5962 | return false; |
| 5963 | |
| 5964 | SDOperand Loc = N->getOperand(1); |
| 5965 | SDOperand BaseLoc = Base->getOperand(1); |
| 5966 | if (Loc.getOpcode() == ISD::FrameIndex) { |
| 5967 | if (BaseLoc.getOpcode() != ISD::FrameIndex) |
| 5968 | return false; |
Dan Gohman | 275769a | 2007-07-23 20:24:29 +0000 | [diff] [blame] | 5969 | int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); |
| 5970 | int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5971 | int FS = MFI->getObjectSize(FI); |
| 5972 | int BFS = MFI->getObjectSize(BFI); |
| 5973 | if (FS != BFS || FS != Size) return false; |
| 5974 | return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size); |
| 5975 | } else { |
| 5976 | GlobalValue *GV1 = NULL; |
| 5977 | GlobalValue *GV2 = NULL; |
| 5978 | int64_t Offset1 = 0; |
| 5979 | int64_t Offset2 = 0; |
| 5980 | bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); |
| 5981 | bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); |
| 5982 | if (isGA1 && isGA2 && GV1 == GV2) |
| 5983 | return Offset1 == (Offset2 + Dist*Size); |
| 5984 | } |
| 5985 | |
| 5986 | return false; |
| 5987 | } |
| 5988 | |
Evan Cheng | 1e60c09 | 2006-07-10 21:37:44 +0000 | [diff] [blame] | 5989 | static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, |
| 5990 | const X86Subtarget *Subtarget) { |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5991 | GlobalValue *GV; |
Nick Lewycky | 916a9f0 | 2008-02-02 08:29:58 +0000 | [diff] [blame] | 5992 | int64_t Offset = 0; |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5993 | if (isGAPlusOffset(Base, GV, Offset)) |
| 5994 | return (GV->getAlignment() >= 16 && (Offset % 16) == 0); |
Chris Lattner | ba96fbc | 2008-01-26 20:07:42 +0000 | [diff] [blame] | 5995 | // DAG combine handles the stack object case. |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 5996 | return false; |
| 5997 | } |
| 5998 | |
| 5999 | |
| 6000 | /// PerformShuffleCombine - Combine a vector_shuffle that is equal to |
| 6001 | /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load |
| 6002 | /// if the load addresses are consecutive, non-overlapping, and in the right |
| 6003 | /// order. |
Evan Cheng | 1e60c09 | 2006-07-10 21:37:44 +0000 | [diff] [blame] | 6004 | static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, |
| 6005 | const X86Subtarget *Subtarget) { |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6006 | MachineFunction &MF = DAG.getMachineFunction(); |
| 6007 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 6008 | MVT::ValueType VT = N->getValueType(0); |
Dan Gohman | 51eaa86 | 2007-06-14 22:58:02 +0000 | [diff] [blame] | 6009 | MVT::ValueType EVT = MVT::getVectorElementType(VT); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6010 | SDOperand PermMask = N->getOperand(2); |
| 6011 | int NumElems = (int)PermMask.getNumOperands(); |
| 6012 | SDNode *Base = NULL; |
| 6013 | for (int i = 0; i < NumElems; ++i) { |
| 6014 | SDOperand Idx = PermMask.getOperand(i); |
| 6015 | if (Idx.getOpcode() == ISD::UNDEF) { |
| 6016 | if (!Base) return SDOperand(); |
| 6017 | } else { |
| 6018 | SDOperand Arg = |
| 6019 | getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 6020 | if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val)) |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6021 | return SDOperand(); |
| 6022 | if (!Base) |
| 6023 | Base = Arg.Val; |
| 6024 | else if (!isConsecutiveLoad(Arg.Val, Base, |
| 6025 | i, MVT::getSizeInBits(EVT)/8,MFI)) |
| 6026 | return SDOperand(); |
| 6027 | } |
| 6028 | } |
| 6029 | |
Evan Cheng | 1e60c09 | 2006-07-10 21:37:44 +0000 | [diff] [blame] | 6030 | bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 6031 | LoadSDNode *LD = cast<LoadSDNode>(Base); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 6032 | if (isAlign16) { |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 6033 | return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 6034 | LD->getSrcValueOffset(), LD->isVolatile()); |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 6035 | } else { |
Dan Gohman | d300622 | 2007-07-27 17:16:43 +0000 | [diff] [blame] | 6036 | return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), |
| 6037 | LD->getSrcValueOffset(), LD->isVolatile(), |
| 6038 | LD->getAlignment()); |
Evan Cheng | 311ace0 | 2006-08-11 07:35:45 +0000 | [diff] [blame] | 6039 | } |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6040 | } |
| 6041 | |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6042 | /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. |
| 6043 | static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, |
| 6044 | const X86Subtarget *Subtarget) { |
| 6045 | SDOperand Cond = N->getOperand(0); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6046 | |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6047 | // If we have SSE[12] support, try to form min/max nodes. |
| 6048 | if (Subtarget->hasSSE2() && |
| 6049 | (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { |
| 6050 | if (Cond.getOpcode() == ISD::SETCC) { |
| 6051 | // Get the LHS/RHS of the select. |
| 6052 | SDOperand LHS = N->getOperand(1); |
| 6053 | SDOperand RHS = N->getOperand(2); |
| 6054 | ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6055 | |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6056 | unsigned Opcode = 0; |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6057 | if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6058 | switch (CC) { |
| 6059 | default: break; |
| 6060 | case ISD::SETOLE: // (X <= Y) ? X : Y -> min |
| 6061 | case ISD::SETULE: |
| 6062 | case ISD::SETLE: |
| 6063 | if (!UnsafeFPMath) break; |
| 6064 | // FALL THROUGH. |
| 6065 | case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min |
| 6066 | case ISD::SETLT: |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6067 | Opcode = X86ISD::FMIN; |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6068 | break; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6069 | |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6070 | case ISD::SETOGT: // (X > Y) ? X : Y -> max |
| 6071 | case ISD::SETUGT: |
| 6072 | case ISD::SETGT: |
| 6073 | if (!UnsafeFPMath) break; |
| 6074 | // FALL THROUGH. |
| 6075 | case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max |
| 6076 | case ISD::SETGE: |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6077 | Opcode = X86ISD::FMAX; |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6078 | break; |
| 6079 | } |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6080 | } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6081 | switch (CC) { |
| 6082 | default: break; |
| 6083 | case ISD::SETOGT: // (X > Y) ? Y : X -> min |
| 6084 | case ISD::SETUGT: |
| 6085 | case ISD::SETGT: |
| 6086 | if (!UnsafeFPMath) break; |
| 6087 | // FALL THROUGH. |
| 6088 | case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min |
| 6089 | case ISD::SETGE: |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6090 | Opcode = X86ISD::FMIN; |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6091 | break; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6092 | |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6093 | case ISD::SETOLE: // (X <= Y) ? Y : X -> max |
| 6094 | case ISD::SETULE: |
| 6095 | case ISD::SETLE: |
| 6096 | if (!UnsafeFPMath) break; |
| 6097 | // FALL THROUGH. |
| 6098 | case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max |
| 6099 | case ISD::SETLT: |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6100 | Opcode = X86ISD::FMAX; |
Chris Lattner | 1907a7b | 2006-10-05 04:11:26 +0000 | [diff] [blame] | 6101 | break; |
| 6102 | } |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6103 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6104 | |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 6105 | if (Opcode) |
| 6106 | return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6107 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6108 | |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6109 | } |
| 6110 | |
| 6111 | return SDOperand(); |
| 6112 | } |
| 6113 | |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6114 | /// PerformSTORECombine - Do target-specific dag combines on STORE nodes. |
| 6115 | static SDOperand PerformSTORECombine(StoreSDNode *St, SelectionDAG &DAG, |
| 6116 | const X86Subtarget *Subtarget) { |
| 6117 | // Turn load->store of MMX types into GPR load/stores. This avoids clobbering |
| 6118 | // the FP state in cases where an emms may be missing. |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6119 | // A preferable solution to the general problem is to figure out the right |
| 6120 | // places to insert EMMS. This qualifies as a quick hack. |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6121 | if (MVT::isVector(St->getValue().getValueType()) && |
| 6122 | MVT::getSizeInBits(St->getValue().getValueType()) == 64 && |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6123 | isa<LoadSDNode>(St->getValue()) && |
| 6124 | !cast<LoadSDNode>(St->getValue())->isVolatile() && |
| 6125 | St->getChain().hasOneUse() && !St->isVolatile()) { |
Dale Johannesen | 14e2ea9 | 2008-02-25 22:29:22 +0000 | [diff] [blame] | 6126 | SDNode* LdVal = St->getValue().Val; |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6127 | LoadSDNode *Ld = 0; |
| 6128 | int TokenFactorIndex = -1; |
| 6129 | SmallVector<SDOperand, 8> Ops; |
| 6130 | SDNode* ChainVal = St->getChain().Val; |
| 6131 | // Must be a store of a load. We currently handle two cases: the load |
| 6132 | // is a direct child, and it's under an intervening TokenFactor. It is |
| 6133 | // possible to dig deeper under nested TokenFactors. |
Dale Johannesen | 14e2ea9 | 2008-02-25 22:29:22 +0000 | [diff] [blame] | 6134 | if (ChainVal == LdVal) |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6135 | Ld = cast<LoadSDNode>(St->getChain()); |
| 6136 | else if (St->getValue().hasOneUse() && |
| 6137 | ChainVal->getOpcode() == ISD::TokenFactor) { |
| 6138 | for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { |
Dale Johannesen | 14e2ea9 | 2008-02-25 22:29:22 +0000 | [diff] [blame] | 6139 | if (ChainVal->getOperand(i).Val == LdVal) { |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6140 | TokenFactorIndex = i; |
| 6141 | Ld = cast<LoadSDNode>(St->getValue()); |
| 6142 | } else |
| 6143 | Ops.push_back(ChainVal->getOperand(i)); |
| 6144 | } |
| 6145 | } |
| 6146 | if (Ld) { |
| 6147 | // If we are a 64-bit capable x86, lower to a single movq load/store pair. |
| 6148 | if (Subtarget->is64Bit()) { |
| 6149 | SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), |
| 6150 | Ld->getBasePtr(), Ld->getSrcValue(), |
| 6151 | Ld->getSrcValueOffset(), Ld->isVolatile(), |
| 6152 | Ld->getAlignment()); |
| 6153 | SDOperand NewChain = NewLd.getValue(1); |
| 6154 | if (TokenFactorIndex != -1) { |
Dan Gohman | d4a2ad3 | 2008-03-28 23:45:16 +0000 | [diff] [blame] | 6155 | Ops.push_back(NewChain); |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6156 | NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], |
| 6157 | Ops.size()); |
| 6158 | } |
| 6159 | return DAG.getStore(NewChain, NewLd, St->getBasePtr(), |
| 6160 | St->getSrcValue(), St->getSrcValueOffset(), |
| 6161 | St->isVolatile(), St->getAlignment()); |
| 6162 | } |
| 6163 | |
| 6164 | // Otherwise, lower to two 32-bit copies. |
| 6165 | SDOperand LoAddr = Ld->getBasePtr(); |
| 6166 | SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, |
| 6167 | DAG.getConstant(MVT::i32, 4)); |
| 6168 | |
| 6169 | SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, |
| 6170 | Ld->getSrcValue(), Ld->getSrcValueOffset(), |
| 6171 | Ld->isVolatile(), Ld->getAlignment()); |
| 6172 | SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, |
| 6173 | Ld->getSrcValue(), Ld->getSrcValueOffset()+4, |
| 6174 | Ld->isVolatile(), |
| 6175 | MinAlign(Ld->getAlignment(), 4)); |
| 6176 | |
| 6177 | SDOperand NewChain = LoLd.getValue(1); |
| 6178 | if (TokenFactorIndex != -1) { |
| 6179 | Ops.push_back(LoLd); |
| 6180 | Ops.push_back(HiLd); |
| 6181 | NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], |
| 6182 | Ops.size()); |
| 6183 | } |
| 6184 | |
| 6185 | LoAddr = St->getBasePtr(); |
| 6186 | HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, |
| 6187 | DAG.getConstant(MVT::i32, 4)); |
| 6188 | |
| 6189 | SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr, |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6190 | St->getSrcValue(), St->getSrcValueOffset(), |
| 6191 | St->isVolatile(), St->getAlignment()); |
Dale Johannesen | 079f2a6 | 2008-02-25 19:20:14 +0000 | [diff] [blame] | 6192 | SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr, |
| 6193 | St->getSrcValue(), St->getSrcValueOffset()+4, |
| 6194 | St->isVolatile(), |
| 6195 | MinAlign(St->getAlignment(), 4)); |
| 6196 | return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6197 | } |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6198 | } |
| 6199 | return SDOperand(); |
| 6200 | } |
| 6201 | |
Chris Lattner | 6cf7326 | 2008-01-25 06:14:17 +0000 | [diff] [blame] | 6202 | /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and |
| 6203 | /// X86ISD::FXOR nodes. |
Chris Lattner | af723b9 | 2008-01-25 05:46:26 +0000 | [diff] [blame] | 6204 | static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) { |
Chris Lattner | 6cf7326 | 2008-01-25 06:14:17 +0000 | [diff] [blame] | 6205 | assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); |
| 6206 | // F[X]OR(0.0, x) -> x |
| 6207 | // F[X]OR(x, 0.0) -> x |
Chris Lattner | af723b9 | 2008-01-25 05:46:26 +0000 | [diff] [blame] | 6208 | if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) |
| 6209 | if (C->getValueAPF().isPosZero()) |
| 6210 | return N->getOperand(1); |
| 6211 | if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) |
| 6212 | if (C->getValueAPF().isPosZero()) |
| 6213 | return N->getOperand(0); |
| 6214 | return SDOperand(); |
| 6215 | } |
| 6216 | |
| 6217 | /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. |
| 6218 | static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { |
| 6219 | // FAND(0.0, x) -> 0.0 |
| 6220 | // FAND(x, 0.0) -> 0.0 |
| 6221 | if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) |
| 6222 | if (C->getValueAPF().isPosZero()) |
| 6223 | return N->getOperand(0); |
| 6224 | if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) |
| 6225 | if (C->getValueAPF().isPosZero()) |
| 6226 | return N->getOperand(1); |
| 6227 | return SDOperand(); |
| 6228 | } |
| 6229 | |
Chris Lattner | 83e6c99 | 2006-10-04 06:57:07 +0000 | [diff] [blame] | 6230 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6231 | SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6232 | DAGCombinerInfo &DCI) const { |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6233 | SelectionDAG &DAG = DCI.DAG; |
| 6234 | switch (N->getOpcode()) { |
| 6235 | default: break; |
Chris Lattner | af723b9 | 2008-01-25 05:46:26 +0000 | [diff] [blame] | 6236 | case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget); |
| 6237 | case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); |
Chris Lattner | 149a4e5 | 2008-02-22 02:09:43 +0000 | [diff] [blame] | 6238 | case ISD::STORE: |
| 6239 | return PerformSTORECombine(cast<StoreSDNode>(N), DAG, Subtarget); |
Chris Lattner | 6cf7326 | 2008-01-25 06:14:17 +0000 | [diff] [blame] | 6240 | case X86ISD::FXOR: |
Chris Lattner | af723b9 | 2008-01-25 05:46:26 +0000 | [diff] [blame] | 6241 | case X86ISD::FOR: return PerformFORCombine(N, DAG); |
| 6242 | case X86ISD::FAND: return PerformFANDCombine(N, DAG); |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 6243 | } |
| 6244 | |
| 6245 | return SDOperand(); |
| 6246 | } |
| 6247 | |
Evan Cheng | 60c07e1 | 2006-07-05 22:17:51 +0000 | [diff] [blame] | 6248 | //===----------------------------------------------------------------------===// |
| 6249 | // X86 Inline Assembly Support |
| 6250 | //===----------------------------------------------------------------------===// |
| 6251 | |
Chris Lattner | f4dff84 | 2006-07-11 02:54:03 +0000 | [diff] [blame] | 6252 | /// getConstraintType - Given a constraint letter, return the type of |
| 6253 | /// constraint it is for this target. |
| 6254 | X86TargetLowering::ConstraintType |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 6255 | X86TargetLowering::getConstraintType(const std::string &Constraint) const { |
| 6256 | if (Constraint.size() == 1) { |
| 6257 | switch (Constraint[0]) { |
| 6258 | case 'A': |
Chris Lattner | fce84ac | 2008-03-11 19:06:29 +0000 | [diff] [blame] | 6259 | case 'f': |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 6260 | case 'r': |
| 6261 | case 'R': |
| 6262 | case 'l': |
| 6263 | case 'q': |
| 6264 | case 'Q': |
| 6265 | case 'x': |
Dale Johannesen | 2ffbcac | 2008-04-01 00:57:48 +0000 | [diff] [blame] | 6266 | case 'y': |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 6267 | case 'Y': |
| 6268 | return C_RegisterClass; |
| 6269 | default: |
| 6270 | break; |
| 6271 | } |
Chris Lattner | f4dff84 | 2006-07-11 02:54:03 +0000 | [diff] [blame] | 6272 | } |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 6273 | return TargetLowering::getConstraintType(Constraint); |
Chris Lattner | f4dff84 | 2006-07-11 02:54:03 +0000 | [diff] [blame] | 6274 | } |
| 6275 | |
Dale Johannesen | ba2a0b9 | 2008-01-29 02:21:21 +0000 | [diff] [blame] | 6276 | /// LowerXConstraint - try to replace an X constraint, which matches anything, |
| 6277 | /// with another that has more specific requirements based on the type of the |
| 6278 | /// corresponding operand. |
Chris Lattner | 5e76423 | 2008-04-26 23:02:14 +0000 | [diff] [blame] | 6279 | const char *X86TargetLowering:: |
| 6280 | LowerXConstraint(MVT::ValueType ConstraintVT) const { |
| 6281 | // FP X constraints get lowered to SSE1/2 registers if available, otherwise |
| 6282 | // 'f' like normal targets. |
Dale Johannesen | ba2a0b9 | 2008-01-29 02:21:21 +0000 | [diff] [blame] | 6283 | if (MVT::isFloatingPoint(ConstraintVT)) { |
| 6284 | if (Subtarget->hasSSE2()) |
Chris Lattner | 5e76423 | 2008-04-26 23:02:14 +0000 | [diff] [blame] | 6285 | return "Y"; |
| 6286 | if (Subtarget->hasSSE1()) |
| 6287 | return "x"; |
| 6288 | } |
| 6289 | |
| 6290 | return TargetLowering::LowerXConstraint(ConstraintVT); |
Dale Johannesen | ba2a0b9 | 2008-01-29 02:21:21 +0000 | [diff] [blame] | 6291 | } |
| 6292 | |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6293 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops |
| 6294 | /// vector. If it is invalid, don't add anything to Ops. |
| 6295 | void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, |
| 6296 | char Constraint, |
| 6297 | std::vector<SDOperand>&Ops, |
Chris Lattner | 5e76423 | 2008-04-26 23:02:14 +0000 | [diff] [blame] | 6298 | SelectionDAG &DAG) const { |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6299 | SDOperand Result(0, 0); |
| 6300 | |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6301 | switch (Constraint) { |
| 6302 | default: break; |
Devang Patel | 84f7fd2 | 2007-03-17 00:13:28 +0000 | [diff] [blame] | 6303 | case 'I': |
Chris Lattner | 188b9fe | 2007-03-25 01:57:35 +0000 | [diff] [blame] | 6304 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6305 | if (C->getValue() <= 31) { |
| 6306 | Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); |
| 6307 | break; |
| 6308 | } |
Devang Patel | 84f7fd2 | 2007-03-17 00:13:28 +0000 | [diff] [blame] | 6309 | } |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6310 | return; |
Chris Lattner | 188b9fe | 2007-03-25 01:57:35 +0000 | [diff] [blame] | 6311 | case 'N': |
| 6312 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6313 | if (C->getValue() <= 255) { |
| 6314 | Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); |
| 6315 | break; |
| 6316 | } |
Chris Lattner | 188b9fe | 2007-03-25 01:57:35 +0000 | [diff] [blame] | 6317 | } |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6318 | return; |
Chris Lattner | dc43a88 | 2007-05-03 16:52:29 +0000 | [diff] [blame] | 6319 | case 'i': { |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6320 | // Literal immediates are always ok. |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6321 | if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { |
| 6322 | Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType()); |
| 6323 | break; |
| 6324 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6325 | |
Chris Lattner | dc43a88 | 2007-05-03 16:52:29 +0000 | [diff] [blame] | 6326 | // If we are in non-pic codegen mode, we allow the address of a global (with |
| 6327 | // an optional displacement) to be used with 'i'. |
| 6328 | GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); |
| 6329 | int64_t Offset = 0; |
| 6330 | |
| 6331 | // Match either (GA) or (GA+C) |
| 6332 | if (GA) { |
| 6333 | Offset = GA->getOffset(); |
| 6334 | } else if (Op.getOpcode() == ISD::ADD) { |
| 6335 | ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); |
| 6336 | GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); |
| 6337 | if (C && GA) { |
| 6338 | Offset = GA->getOffset()+C->getValue(); |
| 6339 | } else { |
| 6340 | C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); |
| 6341 | GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); |
| 6342 | if (C && GA) |
| 6343 | Offset = GA->getOffset()+C->getValue(); |
| 6344 | else |
| 6345 | C = 0, GA = 0; |
| 6346 | } |
| 6347 | } |
| 6348 | |
| 6349 | if (GA) { |
| 6350 | // If addressing this global requires a load (e.g. in PIC mode), we can't |
| 6351 | // match. |
| 6352 | if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(), |
| 6353 | false)) |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6354 | return; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6355 | |
Chris Lattner | dc43a88 | 2007-05-03 16:52:29 +0000 | [diff] [blame] | 6356 | Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), |
| 6357 | Offset); |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6358 | Result = Op; |
| 6359 | break; |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6360 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6361 | |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6362 | // Otherwise, not valid for this mode. |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6363 | return; |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6364 | } |
Chris Lattner | dc43a88 | 2007-05-03 16:52:29 +0000 | [diff] [blame] | 6365 | } |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 6366 | |
| 6367 | if (Result.Val) { |
| 6368 | Ops.push_back(Result); |
| 6369 | return; |
| 6370 | } |
| 6371 | return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 6372 | } |
| 6373 | |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6374 | std::vector<unsigned> X86TargetLowering:: |
Chris Lattner | 1efa40f | 2006-02-22 00:56:39 +0000 | [diff] [blame] | 6375 | getRegClassForInlineAsmConstraint(const std::string &Constraint, |
| 6376 | MVT::ValueType VT) const { |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6377 | if (Constraint.size() == 1) { |
| 6378 | // FIXME: not handling fp-stack yet! |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6379 | switch (Constraint[0]) { // GCC X86 Constraint Letters |
Chris Lattner | f4dff84 | 2006-07-11 02:54:03 +0000 | [diff] [blame] | 6380 | default: break; // Unknown constraint letter |
| 6381 | case 'A': // EAX/EDX |
| 6382 | if (VT == MVT::i32 || VT == MVT::i64) |
| 6383 | return make_vector<unsigned>(X86::EAX, X86::EDX, 0); |
| 6384 | break; |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6385 | case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) |
| 6386 | case 'Q': // Q_REGS |
Chris Lattner | 80a7ecc | 2006-05-06 00:29:37 +0000 | [diff] [blame] | 6387 | if (VT == MVT::i32) |
| 6388 | return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); |
| 6389 | else if (VT == MVT::i16) |
| 6390 | return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); |
| 6391 | else if (VT == MVT::i8) |
Evan Cheng | 1291438 | 2007-08-13 23:27:11 +0000 | [diff] [blame] | 6392 | return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); |
Chris Lattner | 03e6c70 | 2007-11-04 06:51:12 +0000 | [diff] [blame] | 6393 | else if (VT == MVT::i64) |
| 6394 | return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); |
| 6395 | break; |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6396 | } |
| 6397 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6398 | |
Chris Lattner | 1efa40f | 2006-02-22 00:56:39 +0000 | [diff] [blame] | 6399 | return std::vector<unsigned>(); |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 6400 | } |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6401 | |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6402 | std::pair<unsigned, const TargetRegisterClass*> |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6403 | X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, |
| 6404 | MVT::ValueType VT) const { |
Chris Lattner | ad043e8 | 2007-04-09 05:11:28 +0000 | [diff] [blame] | 6405 | // First, see if this is a constraint that directly corresponds to an LLVM |
| 6406 | // register class. |
| 6407 | if (Constraint.size() == 1) { |
| 6408 | // GCC Constraint Letters |
| 6409 | switch (Constraint[0]) { |
| 6410 | default: break; |
Chris Lattner | 0f65cad | 2007-04-09 05:49:22 +0000 | [diff] [blame] | 6411 | case 'r': // GENERAL_REGS |
| 6412 | case 'R': // LEGACY_REGS |
| 6413 | case 'l': // INDEX_REGS |
| 6414 | if (VT == MVT::i64 && Subtarget->is64Bit()) |
| 6415 | return std::make_pair(0U, X86::GR64RegisterClass); |
| 6416 | if (VT == MVT::i32) |
| 6417 | return std::make_pair(0U, X86::GR32RegisterClass); |
| 6418 | else if (VT == MVT::i16) |
| 6419 | return std::make_pair(0U, X86::GR16RegisterClass); |
| 6420 | else if (VT == MVT::i8) |
| 6421 | return std::make_pair(0U, X86::GR8RegisterClass); |
| 6422 | break; |
Chris Lattner | fce84ac | 2008-03-11 19:06:29 +0000 | [diff] [blame] | 6423 | case 'f': // FP Stack registers. |
| 6424 | // If SSE is enabled for this VT, use f80 to ensure the isel moves the |
| 6425 | // value to the correct fpstack register class. |
| 6426 | if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) |
| 6427 | return std::make_pair(0U, X86::RFP32RegisterClass); |
| 6428 | if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) |
| 6429 | return std::make_pair(0U, X86::RFP64RegisterClass); |
| 6430 | return std::make_pair(0U, X86::RFP80RegisterClass); |
Chris Lattner | 6c284d7 | 2007-04-12 04:14:49 +0000 | [diff] [blame] | 6431 | case 'y': // MMX_REGS if MMX allowed. |
| 6432 | if (!Subtarget->hasMMX()) break; |
| 6433 | return std::make_pair(0U, X86::VR64RegisterClass); |
| 6434 | break; |
Chris Lattner | 0f65cad | 2007-04-09 05:49:22 +0000 | [diff] [blame] | 6435 | case 'Y': // SSE_REGS if SSE2 allowed |
| 6436 | if (!Subtarget->hasSSE2()) break; |
| 6437 | // FALL THROUGH. |
| 6438 | case 'x': // SSE_REGS if SSE1 allowed |
| 6439 | if (!Subtarget->hasSSE1()) break; |
| 6440 | |
| 6441 | switch (VT) { |
| 6442 | default: break; |
| 6443 | // Scalar SSE types. |
| 6444 | case MVT::f32: |
| 6445 | case MVT::i32: |
Chris Lattner | ad043e8 | 2007-04-09 05:11:28 +0000 | [diff] [blame] | 6446 | return std::make_pair(0U, X86::FR32RegisterClass); |
Chris Lattner | 0f65cad | 2007-04-09 05:49:22 +0000 | [diff] [blame] | 6447 | case MVT::f64: |
| 6448 | case MVT::i64: |
Chris Lattner | ad043e8 | 2007-04-09 05:11:28 +0000 | [diff] [blame] | 6449 | return std::make_pair(0U, X86::FR64RegisterClass); |
Chris Lattner | 0f65cad | 2007-04-09 05:49:22 +0000 | [diff] [blame] | 6450 | // Vector types. |
Chris Lattner | 0f65cad | 2007-04-09 05:49:22 +0000 | [diff] [blame] | 6451 | case MVT::v16i8: |
| 6452 | case MVT::v8i16: |
| 6453 | case MVT::v4i32: |
| 6454 | case MVT::v2i64: |
| 6455 | case MVT::v4f32: |
| 6456 | case MVT::v2f64: |
| 6457 | return std::make_pair(0U, X86::VR128RegisterClass); |
| 6458 | } |
Chris Lattner | ad043e8 | 2007-04-09 05:11:28 +0000 | [diff] [blame] | 6459 | break; |
| 6460 | } |
| 6461 | } |
| 6462 | |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6463 | // Use the default implementation in TargetLowering to convert the register |
| 6464 | // constraint into a member of a register class. |
| 6465 | std::pair<unsigned, const TargetRegisterClass*> Res; |
| 6466 | Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); |
Chris Lattner | 1a60aa7 | 2006-10-31 19:42:44 +0000 | [diff] [blame] | 6467 | |
| 6468 | // Not found as a standard register? |
| 6469 | if (Res.second == 0) { |
| 6470 | // GCC calls "st(0)" just plain "st". |
| 6471 | if (StringsEqualNoCase("{st}", Constraint)) { |
| 6472 | Res.first = X86::ST0; |
Chris Lattner | 9b4baf1 | 2007-09-24 05:27:37 +0000 | [diff] [blame] | 6473 | Res.second = X86::RFP80RegisterClass; |
Chris Lattner | 1a60aa7 | 2006-10-31 19:42:44 +0000 | [diff] [blame] | 6474 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6475 | |
Chris Lattner | 1a60aa7 | 2006-10-31 19:42:44 +0000 | [diff] [blame] | 6476 | return Res; |
| 6477 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6478 | |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6479 | // Otherwise, check to see if this is a register class of the wrong value |
| 6480 | // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to |
| 6481 | // turn into {ax},{dx}. |
| 6482 | if (Res.second->hasType(VT)) |
| 6483 | return Res; // Correct type already, nothing to do. |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6484 | |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6485 | // All of the single-register GCC register classes map their values onto |
| 6486 | // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we |
| 6487 | // really want an 8-bit or 32-bit register, map to the appropriate register |
| 6488 | // class and return the appropriate register. |
| 6489 | if (Res.second != X86::GR16RegisterClass) |
| 6490 | return Res; |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6491 | |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6492 | if (VT == MVT::i8) { |
| 6493 | unsigned DestReg = 0; |
| 6494 | switch (Res.first) { |
| 6495 | default: break; |
| 6496 | case X86::AX: DestReg = X86::AL; break; |
| 6497 | case X86::DX: DestReg = X86::DL; break; |
| 6498 | case X86::CX: DestReg = X86::CL; break; |
| 6499 | case X86::BX: DestReg = X86::BL; break; |
| 6500 | } |
| 6501 | if (DestReg) { |
| 6502 | Res.first = DestReg; |
| 6503 | Res.second = Res.second = X86::GR8RegisterClass; |
| 6504 | } |
| 6505 | } else if (VT == MVT::i32) { |
| 6506 | unsigned DestReg = 0; |
| 6507 | switch (Res.first) { |
| 6508 | default: break; |
| 6509 | case X86::AX: DestReg = X86::EAX; break; |
| 6510 | case X86::DX: DestReg = X86::EDX; break; |
| 6511 | case X86::CX: DestReg = X86::ECX; break; |
| 6512 | case X86::BX: DestReg = X86::EBX; break; |
| 6513 | case X86::SI: DestReg = X86::ESI; break; |
| 6514 | case X86::DI: DestReg = X86::EDI; break; |
| 6515 | case X86::BP: DestReg = X86::EBP; break; |
| 6516 | case X86::SP: DestReg = X86::ESP; break; |
| 6517 | } |
| 6518 | if (DestReg) { |
| 6519 | Res.first = DestReg; |
| 6520 | Res.second = Res.second = X86::GR32RegisterClass; |
| 6521 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 6522 | } else if (VT == MVT::i64) { |
| 6523 | unsigned DestReg = 0; |
| 6524 | switch (Res.first) { |
| 6525 | default: break; |
| 6526 | case X86::AX: DestReg = X86::RAX; break; |
| 6527 | case X86::DX: DestReg = X86::RDX; break; |
| 6528 | case X86::CX: DestReg = X86::RCX; break; |
| 6529 | case X86::BX: DestReg = X86::RBX; break; |
| 6530 | case X86::SI: DestReg = X86::RSI; break; |
| 6531 | case X86::DI: DestReg = X86::RDI; break; |
| 6532 | case X86::BP: DestReg = X86::RBP; break; |
| 6533 | case X86::SP: DestReg = X86::RSP; break; |
| 6534 | } |
| 6535 | if (DestReg) { |
| 6536 | Res.first = DestReg; |
| 6537 | Res.second = Res.second = X86::GR64RegisterClass; |
| 6538 | } |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6539 | } |
Anton Korobeynikov | 12c49af | 2006-11-21 00:01:06 +0000 | [diff] [blame] | 6540 | |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 6541 | return Res; |
| 6542 | } |