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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 78caa12a415bbd16db04088be6378398d4909b6f / . / lib / Target / ARM / ARMScheduleV7.td
blob: 33af58a1e21d138c22f4c8f46617d12f7348329d [file] [log] [blame]
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]1//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v7 processors.
11//
12//===----------------------------------------------------------------------===//
13
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]14//
15// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
16//
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]17// Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]18//
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]19def CortexA8Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]20
21 // Two fully-pipelined integer ALU pipelines
22 //
23 // No operand cycles
24 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
25 //
26 // Binary Instructions that produce a result
27 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
31 //
32 // Unary Instructions that produce a result
33 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
35 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
36 //
37 // Compare instructions
38 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
39 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
40 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
41 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
42 //
43 // Move instructions, unconditional
44 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
45 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
48 //
49 // Move instructions, conditional
50 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
52 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
54
55 // Integer multiply pipeline
56 // Result written in E5, but that is relative to the last cycle of multicycle,
57 // so we use 6 for those cases
58 //
59 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
60 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
61 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
62 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
63 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
64 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
65 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
66 InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
67 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
68 InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
69 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
70
71 // Integer load pipeline
72 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]73 // loads have an extra cycle of latency, but are fully pipelined
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]74 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]75 //
76 // Immediate offset
77 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
78 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
79 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
80 //
81 // Register offset
82 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
83 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
84 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
85 //
86 // Scaled register offset, issues over 2 cycles
87 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
88 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]89 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]90 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
91 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
92 //
93 // Immediate offset with update
94 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
95 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
96 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
97 //
98 // Register offset with update
99 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
100 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
101 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
105 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]106 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]107 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
108 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
109 //
110 // Load multiple
111 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
112 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]113 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]114 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
115 InstrStage<1, [FU_LdSt0]>]>,
116
117 // Integer store pipeline
118 //
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]119 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]120 //
121 // Immediate offset
122 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]123 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
124 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]125 //
126 // Register offset
127 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]128 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
129 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]130 //
131 // Scaled register offset, issues over 2 cycles
132 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
133 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]134 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]135 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
136 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
137 //
138 // Immediate offset with update
139 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
140 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
141 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
142 //
143 // Register offset with update
144 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
145 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
146 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
147 //
148 // Scaled register offset with update, issues over 2 cycles
149 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
150 InstrStage<1, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]151 InstrStage<1, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]152 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
153 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
154 //
155 // Store multiple
156 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
157 InstrStage<2, [FU_Pipe0], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]158 InstrStage<2, [FU_Pipe1]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame]159 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
160 InstrStage<1, [FU_LdSt0]>]>,
161
162 // Branch
163 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]164 // no delay slots, so the latency of a branch is unimportant
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]165 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
166
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]167 // VFP
168 // Issue through integer pipeline, and execute in NEON unit. We assume
169 // RunFast mode so that NFP pipeline is used for single-precision when
170 // possible.
171 //
172 // FP Special Register to Integer Register File Move
173 InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
174 InstrStage<1, [FU_NLSPipe], 1>]>,
175 //
176 // Integer to Single-Precision FP Register File Move
177 InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
178 InstrStage<1, [FU_NLSPipe], 1>]>,
179 //
180 // Integer to Double-Precision FP Register File Move
181 InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
182 InstrStage<1, [FU_NLSPipe], 1>]>,
183 //
184 // Single-Precision FP to Integer Register File Move
185 InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
186 InstrStage<1, [FU_NLSPipe], 1>], [20, 1]>,
187 //
188 // Double-Precision FP to Integer Register File Move
189 InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
190 InstrStage<1, [FU_NLSPipe], 1>], [20, 20, 1]>,
191 //
192 // Single-precision FP Unary
193 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
194 InstrStage<1, [FU_NPipe]>], [7, 1]>,
195 //
196 // Double-precision FP Unary
197 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
198 InstrStage<4, [FU_NPipe], 0>,
199 InstrStage<4, [FU_NLSPipe]>]>,
200 //
201 // Single-precision FP Compare
202 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
203 InstrStage<1, [FU_NPipe]>], [7, 1]>,
204 //
205 // Double-precision FP Compare
206 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
207 InstrStage<4, [FU_NPipe], 0>,
208 InstrStage<4, [FU_NLSPipe]>]>,
209 //
210 // Single to Double FP Convert
211 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
212 InstrStage<7, [FU_NPipe], 0>,
213 InstrStage<7, [FU_NLSPipe]>]>,
214 //
215 // Double to Single FP Convert
216 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
217 InstrStage<5, [FU_NPipe], 0>,
218 InstrStage<5, [FU_NLSPipe]>]>,
219 //
220 // Single-Precision FP to Integer Convert
221 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
222 InstrStage<1, [FU_NPipe]>], [7, 1]>,
223 //
224 // Double-Precision FP to Integer Convert
225 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
226 InstrStage<8, [FU_NPipe], 0>,
227 InstrStage<8, [FU_NLSPipe]>]>,
228 //
229 // Integer to Single-Precision FP Convert
230 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
231 InstrStage<1, [FU_NPipe]>], [7, 1]>,
232 //
233 // Integer to Double-Precision FP Convert
234 InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
235 InstrStage<8, [FU_NPipe], 0>,
236 InstrStage<8, [FU_NLSPipe]>]>,
237 //
238 // Single-precision FP ALU
239 InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
240 InstrStage<1, [FU_NPipe]>], [7, 1]>,
241 //
242 // Double-precision FP ALU
243 InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
244 InstrStage<9, [FU_NPipe], 0>,
245 InstrStage<9, [FU_NLSPipe]>]>,
246 //
247 // Single-precision FP Multiply
248 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
249 InstrStage<1, [FU_NPipe]>], [7, 1]>,
250 //
251 // Double-precision FP Multiply
252 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
253 InstrStage<11, [FU_NPipe], 0>,
254 InstrStage<11, [FU_NLSPipe]>]>,
255 //
256 // Single-precision FP MAC
257 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
258 InstrStage<1, [FU_NPipe]>], [7, 1]>,
259 //
260 // Double-precision FP MAC
261 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
262 InstrStage<19, [FU_NPipe], 0>,
263 InstrStage<19, [FU_NLSPipe]>]>,
264 //
265 // Single-precision FP DIV
266 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
267 InstrStage<20, [FU_NPipe], 0>,
268 InstrStage<20, [FU_NLSPipe]>]>,
269 //
270 // Double-precision FP DIV
271 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
272 InstrStage<29, [FU_NPipe], 0>,
273 InstrStage<29, [FU_NLSPipe]>]>,
274 //
275 // Single-precision FP SQRT
276 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
277 InstrStage<19, [FU_NPipe], 0>,
278 InstrStage<19, [FU_NLSPipe]>]>,
279 //
280 // Double-precision FP SQRT
281 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
282 InstrStage<29, [FU_NPipe], 0>,
283 InstrStage<29, [FU_NLSPipe]>]>,
284 //
285 // Single-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]286 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]287 InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]288 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]289 InstrStage<1, [FU_LdSt0], 0>,
290 InstrStage<1, [FU_NLSPipe]>]>,
291 //
292 // Double-precision FP Load
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]293 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]294 InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
295 InstrStage<1, [FU_Pipe0], 0>,
296 InstrStage<1, [FU_Pipe1]>,
297 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
298 InstrStage<1, [FU_LdSt0], 0>,
299 InstrStage<1, [FU_NLSPipe]>]>,
300 //
301 // FP Load Multiple
302 // use FU_Issue to enforce the 1 load/store per cycle limit
303 InstrItinData<IIC_fpLoadm, [InstrStage<3, [FU_Issue], 0>,
304 InstrStage<2, [FU_Pipe0], 0>,
305 InstrStage<2, [FU_Pipe1]>,
306 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
307 InstrStage<1, [FU_LdSt0], 0>,
308 InstrStage<1, [FU_NLSPipe]>]>,
309 //
310 // Single-precision FP Store
311 // use FU_Issue to enforce the 1 load/store per cycle limit
312 InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
313 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
314 InstrStage<1, [FU_LdSt0], 0>,
315 InstrStage<1, [FU_NLSPipe]>]>,
316 //
317 // Double-precision FP Store
318 // use FU_Issue to enforce the 1 load/store per cycle limit
319 InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
320 InstrStage<1, [FU_Pipe0], 0>,
321 InstrStage<1, [FU_Pipe1]>,
322 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
323 InstrStage<1, [FU_LdSt0], 0>,
324 InstrStage<1, [FU_NLSPipe]>]>,
325 //
326 // FP Store Multiple
327 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame^]328 InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
David Goodwin35d49122009-09-21 20:52:17 +0000[diff] [blame]329 InstrStage<2, [FU_Pipe0], 0>,
330 InstrStage<2, [FU_Pipe1]>,
331 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
332 InstrStage<1, [FU_LdSt0], 0>,
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame^]333 InstrStage<1, [FU_NLSPipe]>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]334
David Goodwin78caa122009-09-23 21:38:08 +0000[diff] [blame^]335 // NEON
336 // Issue through integer pipeline, and execute in NEON unit.
337 //
338 // VLD1
339 InstrItinData<IIC_VLD1, [InstrStage<1, [FU_Issue], 0>,
340 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
341 InstrStage<1, [FU_LdSt0], 0>,
342 InstrStage<1, [FU_NLSPipe]>]>,
343 //
344 // VLD2
345 InstrItinData<IIC_VLD2, [InstrStage<1, [FU_Issue], 0>,
346 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
347 InstrStage<1, [FU_LdSt0], 0>,
348 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
349 //
350 // VLD3
351 InstrItinData<IIC_VLD3, [InstrStage<1, [FU_Issue], 0>,
352 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
353 InstrStage<1, [FU_LdSt0], 0>,
354 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
355 //
356 // VLD4
357 InstrItinData<IIC_VLD4, [InstrStage<1, [FU_Issue], 0>,
358 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
359 InstrStage<1, [FU_LdSt0], 0>,
360 InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
361 //
362 // VST
363 InstrItinData<IIC_VST, [InstrStage<1, [FU_Issue], 0>,
364 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
365 InstrStage<1, [FU_LdSt0], 0>,
366 InstrStage<1, [FU_NLSPipe]>]>,
367 //
368 // Double-register FP Unary
369 InstrItinData<IIC_VUNAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
370 InstrStage<1, [FU_NPipe]>], [5, 2]>,
371 //
372 // Quad-register FP Unary
373 // Result written in N5, but that is relative to the last cycle of multicycle,
374 // so we use 6 for those cases
375 InstrItinData<IIC_VUNAQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
376 InstrStage<2, [FU_NPipe]>], [6, 2]>,
377 //
378 // Double-register FP Binary
379 InstrItinData<IIC_VBIND, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
380 InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
381 //
382 // Quad-register FP Binary
383 // Result written in N5, but that is relative to the last cycle of multicycle,
384 // so we use 6 for those cases
385 InstrItinData<IIC_VBINQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
386 InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
387 //
388 // Double-register Permute Move
389 InstrItinData<IIC_VMOVD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
390 InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
391 //
392 // Quad-register Permute Move
393 // Result written in N2, but that is relative to the last cycle of multicycle,
394 // so we use 3 for those cases
395 InstrItinData<IIC_VMOVQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
396 InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
397 //
398 // Double-register Permute
399 InstrItinData<IIC_VPERMD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
400 InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
401 //
402 // Quad-register Permute
403 // Result written in N2, but that is relative to the last cycle of multicycle,
404 // so we use 3 for those cases
405 InstrItinData<IIC_VPERMQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
406 InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
407 //
408 // Quad-register Permute (3 cycle issue)
409 // Result written in N2, but that is relative to the last cycle of multicycle,
410 // so we use 4 for those cases
411 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
412 InstrStage<1, [FU_NLSPipe]>,
413 InstrStage<1, [FU_NPipe], 0>,
414 InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
415 //
416 // Double-register Integer Count
417 InstrItinData<IIC_VCNTiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
418 InstrStage<1, [FU_NPipe]>], [3, 2]>,
419 //
420 // Quad-register Integer Count
421 // Result written in N3, but that is relative to the last cycle of multicycle,
422 // so we use 4 for those cases
423 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
424 InstrStage<2, [FU_NPipe]>], [4, 2]>,
425 //
426 // Double-register Integer Unary
427 InstrItinData<IIC_VUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
428 InstrStage<1, [FU_NPipe]>], [4, 2]>,
429 //
430 // Quad-register Integer Unary
431 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
432 InstrStage<1, [FU_NPipe]>], [4, 2]>,
433 //
434 // Double-register Integer Q-Unary
435 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
436 InstrStage<1, [FU_NPipe]>], [4, 1]>,
437 //
438 // Quad-register Integer CountQ-Unary
439 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
440 InstrStage<1, [FU_NPipe]>], [4, 1]>,
441 //
442 // Double-register Integer Binary
443 InstrItinData<IIC_VBINiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
444 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
445 //
446 // Quad-register Integer Binary
447 InstrItinData<IIC_VBINiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
448 InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
449 //
450 // Double-register Integer Binary (4 cycle)
451 InstrItinData<IIC_VBINi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
452 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
453 //
454 // Quad-register Integer Binary (4 cycle)
455 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
456 InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
457 //
458 // Double-register Integer Subtract
459 InstrItinData<IIC_VSUBiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
460 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
461 //
462 // Quad-register Integer Subtract
463 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
464 InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
465 //
466 // Double-register Integer Multiply (.8, .16)
467 InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
468 InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
469 //
470 // Double-register Integer Multiply (.32)
471 InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
472 InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
473 //
474 // Quad-register Integer Multiply (.8, .16)
475 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
476 InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
477 //
478 // Quad-register Integer Multiply (.32)
479 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
480 InstrStage<1, [FU_NPipe]>,
481 InstrStage<2, [FU_NLSPipe], 0>,
482 InstrStage<3, [FU_NPipe]>], [9, 2, 1]>
483
484
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]485]>;