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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 7f4cb8522d024a11885ad2056fbefb287cc36654 / . / lib / Target / X86 / X86.td
blob: 47861d5a67dc973279b9bb3d399ad8031410d074 [file] [log] [blame]
Arnold Schwaighofer373e8652007-10-12 21:30:57 +0000[diff] [blame]1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
Evan Cheng301aaf52008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget features.
21//===----------------------------------------------------------------------===//
22
23def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
24 "Enable MMX instructions">;
25def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
26 "Enable SSE instructions",
27 [FeatureMMX]>;
28def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
29 "Enable SSE2 instructions",
30 [FeatureSSE1]>;
31def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
32 "Enable SSE3 instructions",
33 [FeatureSSE2]>;
34def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
35 "Enable SSSE3 instructions",
36 [FeatureSSE3]>;
Nate Begemanb2975562008-02-03 07:18:54 +0000[diff] [blame]37def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
38 "Enable SSE 4.1 instructions",
39 [FeatureSSSE3]>;
40def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
41 "Enable SSE 4.2 instructions",
42 [FeatureSSE41]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]43def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
44 "Enable 3DNow! instructions">;
45def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
46 "Enable 3DNow! Athlon instructions",
47 [Feature3DNow]>;
Dan Gohman4092bbc2009-02-03 00:04:43 +0000[diff] [blame]48// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
49// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
50// without disabling 64-bit mode.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]51def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
Dan Gohman4092bbc2009-02-03 00:04:43 +0000[diff] [blame]52 "Support 64-bit instructions">;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]53def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
54 "Bit testing of memory is slow">;
Stefanus Du Toitfe086e62009-05-26 21:04:35 +0000[diff] [blame]55def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
56 "Support SSE 4a instructions">;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]57
David Greene8bf22bc2009-06-26 22:46:54 +0000[diff] [blame]58def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
59 "Enable AVX instructions">;
60def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
61 "Enable three-operand fused multiple-add">;
62def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
63 "Enable four-operand fused multiple-add">;
64
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]65//===----------------------------------------------------------------------===//
66// X86 processors supported.
67//===----------------------------------------------------------------------===//
68
69class Proc<string Name, list<SubtargetFeature> Features>
70 : Processor<Name, NoItineraries, Features>;
71
72def : Proc<"generic", []>;
73def : Proc<"i386", []>;
74def : Proc<"i486", []>;
Dale Johannesen68a99ca2008-10-14 22:06:33 +0000[diff] [blame]75def : Proc<"i586", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]76def : Proc<"pentium", []>;
77def : Proc<"pentium-mmx", [FeatureMMX]>;
78def : Proc<"i686", []>;
79def : Proc<"pentiumpro", []>;
80def : Proc<"pentium2", [FeatureMMX]>;
81def : Proc<"pentium3", [FeatureSSE1]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]82def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]83def : Proc<"pentium4", [FeatureSSE2]>;
Dan Gohman4092bbc2009-02-03 00:04:43 +0000[diff] [blame]84def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]85def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
86def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
87def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
88def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
89def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
Evan Cheng2b5a6212009-01-03 04:24:44 +0000[diff] [blame]90def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
91def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
David Greene8bf22bc2009-06-26 22:46:54 +0000[diff] [blame]92def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
93// Sandy Bridge does not have FMA
94def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]95
96def : Proc<"k6", [FeatureMMX]>;
97def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
98def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
Evan Cheng95a77fd2009-01-02 05:35:45 +0000[diff] [blame]99def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
100def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
101def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
102def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
103def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
Dan Gohman4092bbc2009-02-03 00:04:43 +0000[diff] [blame]104def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
105 FeatureSlowBTMem]>;
106def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
107 FeatureSlowBTMem]>;
108def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
109 FeatureSlowBTMem]>;
110def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
111 FeatureSlowBTMem]>;
Stefanus Du Toitfe086e62009-05-26 21:04:35 +0000[diff] [blame]112def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
113 FeatureSlowBTMem]>;
114def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
115 FeatureSlowBTMem]>;
116def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
117 FeatureSlowBTMem]>;
118def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
119 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
120def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
121 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
David Greene7f4cb852009-06-29 16:54:06 +0000[diff] [blame^]122def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
123 Feature3DNowA]>;
124def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
125 Feature3DNowA]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]126
127def : Proc<"winchip-c6", [FeatureMMX]>;
128def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
129def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
130def : Proc<"c3-2", [FeatureSSE1]>;
131
132//===----------------------------------------------------------------------===//
133// Register File Description
134//===----------------------------------------------------------------------===//
135
136include "X86RegisterInfo.td"
137
138//===----------------------------------------------------------------------===//
139// Instruction Descriptions
140//===----------------------------------------------------------------------===//
141
142include "X86InstrInfo.td"
143
144def X86InstrInfo : InstrInfo {
145
146 // Define how we want to layout our TargetSpecific information field... This
147 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
148 let TSFlagsFields = ["FormBits",
149 "hasOpSizePrefix",
150 "hasAdSizePrefix",
151 "Prefix",
152 "hasREX_WPrefix",
153 "ImmTypeBits",
154 "FPFormBits",
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]155 "hasLockPrefix",
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]156 "SegOvrBits",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]157 "Opcode"];
158 let TSFlagsShifts = [0,
159 6,
160 7,
161 8,
162 12,
163 13,
164 16,
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]165 19,
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]166 20,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]167 24];
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]168}
169
170//===----------------------------------------------------------------------===//
171// Calling Conventions
172//===----------------------------------------------------------------------===//
173
174include "X86CallingConv.td"
175
176
177//===----------------------------------------------------------------------===//
178// Assembly Printers
179//===----------------------------------------------------------------------===//
180
181// The X86 target supports two different syntaxes for emitting machine code.
182// This is controlled by the -x86-asm-syntax={att|intel}
183def ATTAsmWriter : AsmWriter {
184 string AsmWriterClassName = "ATTAsmPrinter";
185 int Variant = 0;
186}
187def IntelAsmWriter : AsmWriter {
188 string AsmWriterClassName = "IntelAsmPrinter";
189 int Variant = 1;
190}
191
192
193def X86 : Target {
194 // Information about the instructions...
195 let InstructionSet = X86InstrInfo;
196
197 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
198}