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Evan Chenga8e29892007-01-19 07:51:42 +00001//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMINSTRUCTIONINFO_H
15#define ARMINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "ARMRegisterInfo.h"
Jim Grosbachcbc47b82008-10-07 21:01:51 +000019#include "ARM.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000020
21namespace llvm {
Evan Chenga8e29892007-01-19 07:51:42 +000022 class ARMSubtarget;
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28 enum {
29 //===------------------------------------------------------------------===//
30 // Instruction Flags.
31
32 //===------------------------------------------------------------------===//
Jim Grosbach0a4b9dc2008-11-03 18:38:31 +000033 // This four-bit field describes the addressing mode used.
Evan Chenga8e29892007-01-19 07:51:42 +000034
35 AddrModeMask = 0xf,
Evan Cheng0ff94f72007-08-07 01:37:15 +000036 AddrModeNone = 0,
Evan Chenga8e29892007-01-19 07:51:42 +000037 AddrMode1 = 1,
38 AddrMode2 = 2,
39 AddrMode3 = 3,
40 AddrMode4 = 4,
41 AddrMode5 = 5,
Evan Chengedda31c2008-11-05 18:35:52 +000042 AddrModeT1 = 6,
43 AddrModeT2 = 7,
44 AddrModeT4 = 8,
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
Evan Chenga8e29892007-01-19 07:51:42 +000046
47 // Size* - Flags to keep track of the size of an instruction.
48 SizeShift = 4,
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
51 Size8Bytes = 2,
52 Size4Bytes = 3,
53 Size2Bytes = 4,
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000054
Evan Chenga8e29892007-01-19 07:51:42 +000055 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000056 // and store ops
Evan Chenga8e29892007-01-19 07:51:42 +000057 IndexModeShift = 7,
58 IndexModeMask = 3 << IndexModeShift,
59 IndexModePre = 1,
60 IndexModePost = 2,
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000061
Evan Chengedda31c2008-11-05 18:35:52 +000062 //===------------------------------------------------------------------===//
63 // Misc flags.
64
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
Evan Chengd87293c2008-11-06 08:47:38 +000067 UnaryDP = 1 << 9,
Evan Chengedda31c2008-11-05 18:35:52 +000068
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
71 //
Evan Chengcd8e66a2008-11-11 21:48:44 +000072 FormShift = 10,
73 FormMask = 0x1f << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000074
Raul Herbster8c132632007-08-30 23:34:14 +000075 // Pseudo instructions
Evan Chengffa6d962008-11-13 23:36:57 +000076 Pseudo = 0 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000077
Raul Herbster8c132632007-08-30 23:34:14 +000078 // Multiply instructions
Evan Chengffa6d962008-11-13 23:36:57 +000079 MulFrm = 1 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000080
Raul Herbster8c132632007-08-30 23:34:14 +000081 // Branch instructions
Evan Chengffa6d962008-11-13 23:36:57 +000082 BrFrm = 2 << FormShift,
83 BrMiscFrm = 3 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000084
Raul Herbster8c132632007-08-30 23:34:14 +000085 // Data Processing instructions
Evan Chengffa6d962008-11-13 23:36:57 +000086 DPFrm = 4 << FormShift,
87 DPSoRegFrm = 5 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000088
Raul Herbster8c132632007-08-30 23:34:14 +000089 // Load and Store
Evan Chengffa6d962008-11-13 23:36:57 +000090 LdFrm = 6 << FormShift,
91 StFrm = 7 << FormShift,
92 LdMiscFrm = 8 << FormShift,
93 StMiscFrm = 9 << FormShift,
94 LdStMulFrm = 10 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +000095
Raul Herbster8c132632007-08-30 23:34:14 +000096 // Miscellaneous arithmetic instructions
Evan Chengffa6d962008-11-13 23:36:57 +000097 ArithMiscFrm = 11 << FormShift,
Evan Cheng97f48c32008-11-06 22:15:19 +000098
99 // Extend instructions
Evan Chengffa6d962008-11-13 23:36:57 +0000100 ExtFrm = 12 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000101
Evan Cheng96581d32008-11-11 02:11:05 +0000102 // VFP formats
Evan Chengffa6d962008-11-13 23:36:57 +0000103 VFPUnaryFrm = 13 << FormShift,
104 VFPBinaryFrm = 14 << FormShift,
105 VFPConv1Frm = 15 << FormShift,
106 VFPConv2Frm = 16 << FormShift,
107 VFPConv3Frm = 17 << FormShift,
108 VFPConv4Frm = 18 << FormShift,
109 VFPConv5Frm = 19 << FormShift,
110 VFPLdStFrm = 20 << FormShift,
111 VFPLdStMulFrm = 21 << FormShift,
112 VFPMiscFrm = 22 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000113
Evan Cheng96581d32008-11-11 02:11:05 +0000114 // Thumb format
Evan Chengffa6d962008-11-13 23:36:57 +0000115 ThumbFrm = 23 << FormShift,
Evan Cheng0ff94f72007-08-07 01:37:15 +0000116
Bob Wilson5bafff32009-06-22 23:27:02 +0000117 // NEON format
118 NEONFrm = 24 << FormShift,
119 NEONGetLnFrm = 25 << FormShift,
120 NEONSetLnFrm = 26 << FormShift,
121 NEONDupFrm = 27 << FormShift,
122
Evan Chengedda31c2008-11-05 18:35:52 +0000123 //===------------------------------------------------------------------===//
Raul Herbster8c132632007-08-30 23:34:14 +0000124 // Field shifts - such shifts are used to set field while generating
125 // machine instructions.
Evan Cheng96581d32008-11-11 02:11:05 +0000126 M_BitShift = 5,
Evan Cheng70632912008-11-12 07:34:37 +0000127 ShiftImmShift = 5,
Evan Cheng8b59db32008-11-07 01:41:35 +0000128 ShiftShift = 7,
Evan Cheng96581d32008-11-11 02:11:05 +0000129 N_BitShift = 7,
Evan Cheng70632912008-11-12 07:34:37 +0000130 ImmHiShift = 8,
Evan Cheng97f48c32008-11-06 22:15:19 +0000131 SoRotImmShift = 8,
132 RegRsShift = 8,
133 ExtRotImmShift = 10,
134 RegRdLoShift = 12,
135 RegRdShift = 12,
136 RegRdHiShift = 16,
137 RegRnShift = 16,
138 S_BitShift = 20,
139 W_BitShift = 21,
140 AM3_I_BitShift = 22,
Evan Cheng96581d32008-11-11 02:11:05 +0000141 D_BitShift = 22,
Evan Cheng97f48c32008-11-06 22:15:19 +0000142 U_BitShift = 23,
143 P_BitShift = 24,
144 I_BitShift = 25,
145 CondShift = 28
Evan Chenga8e29892007-01-19 07:51:42 +0000146 };
147}
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000148
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000149class ARMBaseInstrInfo : public TargetInstrInfoImpl {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000150protected:
151 // Can be only subclassed.
152 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000153public:
Evan Chenga8e29892007-01-19 07:51:42 +0000154 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
155 MachineBasicBlock::iterator &MBBI,
Owen Andersonf660c172008-07-02 23:41:07 +0000156 LiveVariables *LV) const;
Chris Lattner578e64a2006-10-24 16:47:57 +0000157
Evan Chenga8e29892007-01-19 07:51:42 +0000158 // Branch analysis.
159 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
160 MachineBasicBlock *&FBB,
Evan Chengdc54d312009-02-09 07:14:22 +0000161 SmallVectorImpl<MachineOperand> &Cond,
162 bool AllowModify) const;
Evan Cheng6ae36262007-05-18 00:18:17 +0000163 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
164 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
165 MachineBasicBlock *FBB,
Owen Anderson44eb65c2008-08-14 22:49:33 +0000166 const SmallVectorImpl<MachineOperand> &Cond) const;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000167
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000168 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
169 virtual
170 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
171
172 // Predication support.
173 virtual bool isPredicated(const MachineInstr *MI) const;
174
175 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
176 int PIdx = MI->findFirstPredOperandIdx();
177 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
178 : ARMCC::AL;
179 }
180
181 virtual
182 bool PredicateInstruction(MachineInstr *MI,
183 const SmallVectorImpl<MachineOperand> &Pred) const;
184
185 virtual
186 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
187 const SmallVectorImpl<MachineOperand> &Pred2) const;
188
189 virtual bool DefinesPredicate(MachineInstr *MI,
190 std::vector<MachineOperand> &Pred) const;
191
192 /// GetInstSize - Returns the size of the specified MachineInstr.
193 ///
194 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
195};
196
197class ARMInstrInfo : public ARMBaseInstrInfo {
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000198 ARMRegisterInfo RI;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000199public:
200 explicit ARMInstrInfo(const ARMSubtarget &STI);
201
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000202 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
203 /// such, whenever a client has an instance of instruction info, it should
204 /// always be able to get register info as well (through this method).
205 ///
206 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
207
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000208 /// Return true if the instruction is a register to register move and return
209 /// the source and dest operands and their sub-register indices by reference.
210 virtual bool isMoveInstr(const MachineInstr &MI,
211 unsigned &SrcReg, unsigned &DstReg,
212 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
213
214 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
215 int &FrameIndex) const;
216 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
217 int &FrameIndex) const;
218
Owen Anderson940f83e2008-08-26 18:03:31 +0000219 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Andersond10fd972007-12-31 06:32:00 +0000220 MachineBasicBlock::iterator I,
221 unsigned DestReg, unsigned SrcReg,
222 const TargetRegisterClass *DestRC,
223 const TargetRegisterClass *SrcRC) const;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000224 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
225 MachineBasicBlock::iterator MBBI,
226 unsigned SrcReg, bool isKill, int FrameIndex,
227 const TargetRegisterClass *RC) const;
228
229 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
230 SmallVectorImpl<MachineOperand> &Addr,
231 const TargetRegisterClass *RC,
232 SmallVectorImpl<MachineInstr*> &NewMIs) const;
233
234 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
235 MachineBasicBlock::iterator MBBI,
236 unsigned DestReg, int FrameIndex,
237 const TargetRegisterClass *RC) const;
238
239 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
240 SmallVectorImpl<MachineOperand> &Addr,
241 const TargetRegisterClass *RC,
242 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000243
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000244 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
245 unsigned DestReg, const MachineInstr *Orig) const;
246
247 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
248 const SmallVectorImpl<unsigned> &Ops) const;
249
Dan Gohmanc54baa22008-12-03 18:43:12 +0000250 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
251 MachineInstr* MI,
252 const SmallVectorImpl<unsigned> &Ops,
253 int FrameIndex) const;
Owen Anderson43dbe052008-01-07 01:35:02 +0000254
Dan Gohmanc54baa22008-12-03 18:43:12 +0000255 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
256 MachineInstr* MI,
257 const SmallVectorImpl<unsigned> &Ops,
258 MachineInstr* LoadMI) const {
Owen Anderson43dbe052008-01-07 01:35:02 +0000259 return 0;
260 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000261};
262
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000263}
264
265#endif