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Chris Lattner1c08c712005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
Chris Lattner1c08c712005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
Chris Lattner1c08c712005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
Dan Gohman84fbac52009-02-06 17:22:58 +000015#include "ScheduleDAGSDNodes.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000016#include "SelectionDAGBuild.h"
Dan Gohman84fbac52009-02-06 17:22:58 +000017#include "llvm/CodeGen/SelectionDAGISel.h"
Jim Laskeyc7c3f112006-10-16 20:52:31 +000018#include "llvm/Analysis/AliasAnalysis.h"
Anton Korobeynikov5502bf62007-04-04 21:14:49 +000019#include "llvm/Constants.h"
Chris Lattneradf6a962005-05-13 18:50:42 +000020#include "llvm/CallingConv.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000021#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
Chris Lattner36ce6912005-11-29 06:21:05 +000023#include "llvm/GlobalVariable.h"
Chris Lattnerce7518c2006-01-26 22:24:51 +000024#include "llvm/InlineAsm.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000025#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
Jim Laskey43970fe2006-03-23 18:06:46 +000027#include "llvm/IntrinsicInst.h"
Dan Gohman78eca172008-08-19 22:33:34 +000028#include "llvm/CodeGen/FastISel.h"
Gordon Henriksen5a29c9e2008-08-17 12:56:54 +000029#include "llvm/CodeGen/GCStrategy.h"
Gordon Henriksen5eca0752008-08-17 18:44:35 +000030#include "llvm/CodeGen/GCMetadata.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000031#include "llvm/CodeGen/MachineFunction.h"
Dan Gohmanad2afc22009-07-31 18:16:33 +000032#include "llvm/CodeGen/MachineFunctionAnalysis.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000033#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000035#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohmanfc54c552009-01-15 22:18:12 +000038#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000039#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000040#include "llvm/CodeGen/SelectionDAG.h"
Devang Patel6e7a1612009-01-09 19:11:50 +000041#include "llvm/CodeGen/DwarfWriter.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000042#include "llvm/Target/TargetRegisterInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000043#include "llvm/Target/TargetData.h"
44#include "llvm/Target/TargetFrameInfo.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
Vladimir Prus12472912006-05-23 13:43:15 +000048#include "llvm/Target/TargetOptions.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000049#include "llvm/Support/Compiler.h"
Evan Chengdb8d56b2008-06-30 20:45:06 +000050#include "llvm/Support/Debug.h"
Torok Edwin7d696d82009-07-11 13:10:19 +000051#include "llvm/Support/ErrorHandling.h"
Evan Chengdb8d56b2008-06-30 20:45:06 +000052#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/Timer.h"
Daniel Dunbarce63ffb2009-07-25 00:23:56 +000054#include "llvm/Support/raw_ostream.h"
Jeff Cohen7e881032006-02-24 02:52:40 +000055#include <algorithm>
Chris Lattner1c08c712005-01-07 07:47:53 +000056using namespace llvm;
57
Chris Lattneread0d882008-06-17 06:09:18 +000058static cl::opt<bool>
Duncan Sands7cb07872008-10-27 08:42:46 +000059DisableLegalizeTypes("disable-legalize-types", cl::Hidden);
Dan Gohman78eca172008-08-19 22:33:34 +000060static cl::opt<bool>
Dan Gohman293d5f82008-09-09 22:06:46 +000061EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
Dan Gohmand659d502008-10-20 21:30:12 +000062 cl::desc("Enable verbose messages in the \"fast\" "
Dan Gohman293d5f82008-09-09 22:06:46 +000063 "instruction selector"));
64static cl::opt<bool>
Dan Gohman4344a5d2008-09-09 23:05:00 +000065EnableFastISelAbort("fast-isel-abort", cl::Hidden,
66 cl::desc("Enable abort calls when \"fast\" instruction fails"));
Dan Gohman8a110532008-09-05 22:59:21 +000067static cl::opt<bool>
68SchedLiveInCopies("schedule-livein-copies",
69 cl::desc("Schedule copies of livein registers"),
70 cl::init(false));
Chris Lattneread0d882008-06-17 06:09:18 +000071
Chris Lattnerda8abb02005-09-01 18:44:10 +000072#ifndef NDEBUG
Chris Lattner7944d9d2005-01-12 03:41:21 +000073static cl::opt<bool>
Dan Gohman462dc7f2008-07-21 20:00:07 +000074ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
75 cl::desc("Pop up a window to show dags before the first "
76 "dag combine pass"));
77static cl::opt<bool>
78ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before legalize types"));
80static cl::opt<bool>
81ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
82 cl::desc("Pop up a window to show dags before legalize"));
83static cl::opt<bool>
84ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before the second "
86 "dag combine pass"));
87static cl::opt<bool>
Duncan Sands25cf2272008-11-24 14:53:14 +000088ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
89 cl::desc("Pop up a window to show dags before the post legalize types"
90 " dag combine pass"));
91static cl::opt<bool>
Evan Chenga9c20912006-01-21 02:32:06 +000092ViewISelDAGs("view-isel-dags", cl::Hidden,
93 cl::desc("Pop up a window to show isel dags as they are selected"));
94static cl::opt<bool>
95ViewSchedDAGs("view-sched-dags", cl::Hidden,
96 cl::desc("Pop up a window to show sched dags as they are processed"));
Dan Gohman3e1a7ae2007-08-28 20:32:58 +000097static cl::opt<bool>
98ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
Chris Lattner5bab7852008-01-25 17:24:52 +000099 cl::desc("Pop up a window to show SUnit dags after they are processed"));
Chris Lattner7944d9d2005-01-12 03:41:21 +0000100#else
Dan Gohman462dc7f2008-07-21 20:00:07 +0000101static const bool ViewDAGCombine1 = false,
102 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
103 ViewDAGCombine2 = false,
Duncan Sands25cf2272008-11-24 14:53:14 +0000104 ViewDAGCombineLT = false,
Dan Gohman462dc7f2008-07-21 20:00:07 +0000105 ViewISelDAGs = false, ViewSchedDAGs = false,
106 ViewSUnitDAGs = false;
Chris Lattner7944d9d2005-01-12 03:41:21 +0000107#endif
108
Jim Laskeyeb577ba2006-08-02 12:30:23 +0000109//===---------------------------------------------------------------------===//
110///
111/// RegisterScheduler class - Track the registration of instruction schedulers.
112///
113//===---------------------------------------------------------------------===//
114MachinePassRegistry RegisterScheduler::Registry;
115
116//===---------------------------------------------------------------------===//
117///
118/// ISHeuristic command line option for instruction schedulers.
119///
120//===---------------------------------------------------------------------===//
Dan Gohman844731a2008-05-13 00:00:25 +0000121static cl::opt<RegisterScheduler::FunctionPassCtor, false,
122 RegisterPassParser<RegisterScheduler> >
123ISHeuristic("pre-RA-sched",
124 cl::init(&createDefaultScheduler),
125 cl::desc("Instruction schedulers available (before register"
126 " allocation):"));
Jim Laskey13ec7022006-08-01 14:21:23 +0000127
Dan Gohman844731a2008-05-13 00:00:25 +0000128static RegisterScheduler
Dan Gohmanb8cab922008-10-14 20:25:08 +0000129defaultListDAGScheduler("default", "Best scheduler for the target",
Dan Gohman844731a2008-05-13 00:00:25 +0000130 createDefaultScheduler);
Evan Cheng4ef10862006-01-23 07:01:07 +0000131
Chris Lattner1c08c712005-01-07 07:47:53 +0000132namespace llvm {
133 //===--------------------------------------------------------------------===//
Jim Laskey9373beb2006-08-01 19:14:14 +0000134 /// createDefaultScheduler - This creates an instruction scheduler appropriate
135 /// for the target.
Dan Gohman47ac0f02009-02-11 04:27:20 +0000136 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
Bill Wendling98a366d2009-04-29 23:29:43 +0000137 CodeGenOpt::Level OptLevel) {
Dan Gohmane9530ec2009-01-15 16:58:17 +0000138 const TargetLowering &TLI = IS->getTargetLowering();
139
Bill Wendling98a366d2009-04-29 23:29:43 +0000140 if (OptLevel == CodeGenOpt::None)
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000141 return createFastDAGScheduler(IS, OptLevel);
Dan Gohman9e76fea2008-11-20 03:11:19 +0000142 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000143 return createTDListDAGScheduler(IS, OptLevel);
Dan Gohman9e76fea2008-11-20 03:11:19 +0000144 assert(TLI.getSchedulingPreference() ==
145 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000146 return createBURRListDAGScheduler(IS, OptLevel);
Jim Laskey9373beb2006-08-01 19:14:14 +0000147 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000148}
149
Evan Chengff9b3732008-01-30 18:18:23 +0000150// EmitInstrWithCustomInserter - This method should be implemented by targets
151// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
Chris Lattner025c39b2005-08-26 20:54:47 +0000152// instructions are special in various ways, which require special support to
153// insert. The specified MachineInstr is created but not inserted into any
154// basic blocks, and the scheduler passes ownership of it to this method.
Evan Chengff9b3732008-01-30 18:18:23 +0000155MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohman1fdbc1d2009-02-07 16:15:20 +0000156 MachineBasicBlock *MBB) const {
Torok Edwinf3689232009-07-12 20:07:01 +0000157#ifndef NDEBUG
158 cerr << "If a target marks an instruction with "
159 "'usesCustomDAGSchedInserter', it must implement "
160 "TargetLowering::EmitInstrWithCustomInserter!";
161#endif
Torok Edwinc23197a2009-07-14 16:55:14 +0000162 llvm_unreachable(0);
Chris Lattner025c39b2005-08-26 20:54:47 +0000163 return 0;
164}
165
Dan Gohman8a110532008-09-05 22:59:21 +0000166/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
167/// physical register has only a single copy use, then coalesced the copy
168/// if possible.
169static void EmitLiveInCopy(MachineBasicBlock *MBB,
170 MachineBasicBlock::iterator &InsertPos,
171 unsigned VirtReg, unsigned PhysReg,
172 const TargetRegisterClass *RC,
173 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
174 const MachineRegisterInfo &MRI,
175 const TargetRegisterInfo &TRI,
176 const TargetInstrInfo &TII) {
177 unsigned NumUses = 0;
178 MachineInstr *UseMI = NULL;
179 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
180 UE = MRI.use_end(); UI != UE; ++UI) {
181 UseMI = &*UI;
182 if (++NumUses > 1)
183 break;
184 }
185
186 // If the number of uses is not one, or the use is not a move instruction,
187 // don't coalesce. Also, only coalesce away a virtual register to virtual
188 // register copy.
189 bool Coalesced = false;
Evan Cheng04ee5a12009-01-20 19:12:24 +0000190 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
Dan Gohman8a110532008-09-05 22:59:21 +0000191 if (NumUses == 1 &&
Evan Cheng04ee5a12009-01-20 19:12:24 +0000192 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
Dan Gohman8a110532008-09-05 22:59:21 +0000193 TargetRegisterInfo::isVirtualRegister(DstReg)) {
194 VirtReg = DstReg;
195 Coalesced = true;
196 }
197
198 // Now find an ideal location to insert the copy.
199 MachineBasicBlock::iterator Pos = InsertPos;
200 while (Pos != MBB->begin()) {
201 MachineInstr *PrevMI = prior(Pos);
202 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
203 // copyRegToReg might emit multiple instructions to do a copy.
204 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
205 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
206 // This is what the BB looks like right now:
207 // r1024 = mov r0
208 // ...
209 // r1 = mov r1024
210 //
211 // We want to insert "r1025 = mov r1". Inserting this copy below the
212 // move to r1024 makes it impossible for that move to be coalesced.
213 //
214 // r1025 = mov r1
215 // r1024 = mov r0
216 // ...
217 // r1 = mov 1024
218 // r2 = mov 1025
219 break; // Woot! Found a good location.
220 --Pos;
221 }
222
David Goodwinf1daf7d2009-07-08 23:10:31 +0000223 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
224 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
225 (void) Emitted;
226
227CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
Dan Gohman8a110532008-09-05 22:59:21 +0000228 if (Coalesced) {
229 if (&*InsertPos == UseMI) ++InsertPos;
230 MBB->erase(UseMI);
231 }
232}
233
234/// EmitLiveInCopies - If this is the first basic block in the function,
235/// and if it has live ins that need to be copied into vregs, emit the
236/// copies into the block.
237static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
238 const MachineRegisterInfo &MRI,
239 const TargetRegisterInfo &TRI,
240 const TargetInstrInfo &TII) {
241 if (SchedLiveInCopies) {
242 // Emit the copies at a heuristically-determined location in the block.
243 DenseMap<MachineInstr*, unsigned> CopyRegMap;
244 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
245 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
246 E = MRI.livein_end(); LI != E; ++LI)
247 if (LI->second) {
248 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
249 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
250 RC, CopyRegMap, MRI, TRI, TII);
251 }
252 } else {
253 // Emit the copies into the top of the block.
254 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
255 E = MRI.livein_end(); LI != E; ++LI)
256 if (LI->second) {
257 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
David Goodwinf1daf7d2009-07-08 23:10:31 +0000258 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
259 LI->second, LI->first, RC, RC);
260 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
261 (void) Emitted;
Dan Gohman8a110532008-09-05 22:59:21 +0000262 }
263 }
264}
265
Chris Lattner7041ee32005-01-11 05:56:49 +0000266//===----------------------------------------------------------------------===//
267// SelectionDAGISel code
268//===----------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +0000269
Bill Wendling98a366d2009-04-29 23:29:43 +0000270SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
Dan Gohmanad2afc22009-07-31 18:16:33 +0000271 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
Dan Gohman7c3234c2008-08-27 23:52:12 +0000272 FuncInfo(new FunctionLoweringInfo(TLI)),
273 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000274 SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo, OL)),
Dan Gohman7c3234c2008-08-27 23:52:12 +0000275 GFI(),
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000276 OptLevel(OL),
Dan Gohman7c3234c2008-08-27 23:52:12 +0000277 DAGSize(0)
278{}
279
280SelectionDAGISel::~SelectionDAGISel() {
281 delete SDL;
282 delete CurDAG;
283 delete FuncInfo;
284}
285
Duncan Sands83ec4b62008-06-06 12:08:01 +0000286unsigned SelectionDAGISel::MakeReg(MVT VT) {
Chris Lattner84bc5422007-12-31 04:13:23 +0000287 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
Chris Lattner1c08c712005-01-07 07:47:53 +0000288}
289
Chris Lattner495a0b52005-08-17 06:37:43 +0000290void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Jim Laskeyc7c3f112006-10-16 20:52:31 +0000291 AU.addRequired<AliasAnalysis>();
Dan Gohmana3477fe2009-07-31 23:36:22 +0000292 AU.addPreserved<AliasAnalysis>();
Gordon Henriksen5eca0752008-08-17 18:44:35 +0000293 AU.addRequired<GCModuleInfo>();
Dan Gohmana3477fe2009-07-31 23:36:22 +0000294 AU.addPreserved<GCModuleInfo>();
Devang Patel6e7a1612009-01-09 19:11:50 +0000295 AU.addRequired<DwarfWriter>();
Dan Gohmana3477fe2009-07-31 23:36:22 +0000296 AU.addPreserved<DwarfWriter>();
Dan Gohmanad2afc22009-07-31 18:16:33 +0000297 MachineFunctionPass::getAnalysisUsage(AU);
Chris Lattner495a0b52005-08-17 06:37:43 +0000298}
Chris Lattner1c08c712005-01-07 07:47:53 +0000299
Dan Gohmanad2afc22009-07-31 18:16:33 +0000300bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
301 Function &Fn = *mf.getFunction();
302
Dan Gohman4344a5d2008-09-09 23:05:00 +0000303 // Do some sanity-checking on the command-line options.
304 assert((!EnableFastISelVerbose || EnableFastISel) &&
305 "-fast-isel-verbose requires -fast-isel");
306 assert((!EnableFastISelAbort || EnableFastISel) &&
307 "-fast-isel-abort requires -fast-isel");
308
Devang Patel16f2ffd2009-04-16 02:33:41 +0000309 // Do not codegen any 'available_externally' functions at all, they have
310 // definitions outside the translation unit.
311 if (Fn.hasAvailableExternallyLinkage())
312 return false;
313
Dan Gohman5f43f922007-08-27 16:26:13 +0000314 // Get alias analysis for load/store combining.
315 AA = &getAnalysis<AliasAnalysis>();
316
Dan Gohman8a110532008-09-05 22:59:21 +0000317 TargetMachine &TM = TLI.getTargetMachine();
Dan Gohmanad2afc22009-07-31 18:16:33 +0000318 MF = &mf;
Dan Gohman8a110532008-09-05 22:59:21 +0000319 const TargetInstrInfo &TII = *TM.getInstrInfo();
320 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
321
Dan Gohman79ce2762009-01-15 19:20:50 +0000322 if (MF->getFunction()->hasGC())
323 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction());
Gordon Henriksence224772008-01-07 01:30:38 +0000324 else
Gordon Henriksen5eca0752008-08-17 18:44:35 +0000325 GFI = 0;
Dan Gohman79ce2762009-01-15 19:20:50 +0000326 RegInfo = &MF->getRegInfo();
Daniel Dunbarce63ffb2009-07-25 00:23:56 +0000327 DEBUG(errs() << "\n\n\n=== " << Fn.getName() << "\n");
Chris Lattner1c08c712005-01-07 07:47:53 +0000328
Duncan Sands1465d612009-01-28 13:14:17 +0000329 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
330 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
Owen Anderson5dcaceb2009-07-09 18:44:09 +0000331 CurDAG->init(*MF, MMI, DW);
Devang Patelb51d40c2009-02-03 18:46:32 +0000332 FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel);
Dan Gohman7c3234c2008-08-27 23:52:12 +0000333 SDL->init(GFI, *AA);
Chris Lattner1c08c712005-01-07 07:47:53 +0000334
Dale Johannesen1532f3d2008-04-02 00:25:04 +0000335 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
336 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
337 // Mark landing pad.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000338 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
Duncan Sands9fac0b52007-06-06 10:05:18 +0000339
Dan Gohman79ce2762009-01-15 19:20:50 +0000340 SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000341
Dan Gohman8a110532008-09-05 22:59:21 +0000342 // If the first basic block in the function has live ins that need to be
343 // copied into vregs, emit the copies into the top of the block before
344 // emitting the code for the block.
Dan Gohman79ce2762009-01-15 19:20:50 +0000345 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
Dan Gohman8a110532008-09-05 22:59:21 +0000346
Evan Chengad2070c2007-02-10 02:43:39 +0000347 // Add function live-ins to entry block live-in set.
Dan Gohman8a110532008-09-05 22:59:21 +0000348 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
349 E = RegInfo->livein_end(); I != E; ++I)
Dan Gohman79ce2762009-01-15 19:20:50 +0000350 MF->begin()->addLiveIn(I->first);
Evan Chengad2070c2007-02-10 02:43:39 +0000351
Duncan Sandsf4070822007-06-15 19:04:19 +0000352#ifndef NDEBUG
Dan Gohman7c3234c2008-08-27 23:52:12 +0000353 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
Duncan Sandsf4070822007-06-15 19:04:19 +0000354 "Not all catch info was assigned to a landing pad!");
355#endif
356
Dan Gohman7c3234c2008-08-27 23:52:12 +0000357 FuncInfo->clear();
358
Chris Lattner1c08c712005-01-07 07:47:53 +0000359 return true;
360}
361
Duncan Sandsf4070822007-06-15 19:04:19 +0000362static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
363 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000364 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000365 if (EHSelectorInst *EHSel = dyn_cast<EHSelectorInst>(I)) {
Duncan Sandsf4070822007-06-15 19:04:19 +0000366 // Apply the catch info to DestBB.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000367 AddCatchInfo(*EHSel, MMI, FLI.MBBMap[DestBB]);
Duncan Sandsf4070822007-06-15 19:04:19 +0000368#ifndef NDEBUG
Duncan Sands560a7372007-11-15 09:54:37 +0000369 if (!FLI.MBBMap[SrcBB]->isLandingPad())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000370 FLI.CatchInfoFound.insert(EHSel);
Duncan Sandsf4070822007-06-15 19:04:19 +0000371#endif
372 }
373}
374
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000375/// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
376/// whether object offset >= 0.
377static bool
Dan Gohman79ce2762009-01-15 19:20:50 +0000378IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) {
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000379 if (!isa<FrameIndexSDNode>(Op)) return false;
380
381 FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
382 int FrameIdx = FrameIdxNode->getIndex();
383 return MFI->isFixedObjectIndex(FrameIdx) &&
384 MFI->getObjectOffset(FrameIdx) >= 0;
385}
386
387/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
388/// possibly be overwritten when lowering the outgoing arguments in a tail
389/// call. Currently the implementation of this call is very conservative and
390/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
391/// virtual registers would be overwritten by direct lowering.
Dan Gohman475871a2008-07-27 21:46:04 +0000392static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
Dan Gohman79ce2762009-01-15 19:20:50 +0000393 MachineFrameInfo *MFI) {
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000394 RegisterSDNode * OpReg = NULL;
395 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
396 (Op.getOpcode()== ISD::CopyFromReg &&
397 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
398 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
399 (Op.getOpcode() == ISD::LOAD &&
400 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
401 (Op.getOpcode() == ISD::MERGE_VALUES &&
Gabor Greif99a6cb92008-08-26 22:36:50 +0000402 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
403 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000404 getOperand(1))))
405 return true;
406 return false;
407}
408
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000409/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +0000410/// DAG and fixes their tailcall attribute operand.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000411static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
Dan Gohmane9530ec2009-01-15 16:58:17 +0000412 const TargetLowering& TLI) {
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000413 SDNode * Ret = NULL;
Dan Gohman475871a2008-07-27 21:46:04 +0000414 SDValue Terminator = DAG.getRoot();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000415
416 // Find RET node.
417 if (Terminator.getOpcode() == ISD::RET) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000418 Ret = Terminator.getNode();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000419 }
420
421 // Fix tail call attribute of CALL nodes.
422 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
Dan Gohman0e5f1302008-07-07 23:02:41 +0000423 BI = DAG.allnodes_end(); BI != BE; ) {
424 --BI;
Dan Gohman095cc292008-09-13 01:54:27 +0000425 if (CallSDNode *TheCall = dyn_cast<CallSDNode>(BI)) {
Dan Gohman475871a2008-07-27 21:46:04 +0000426 SDValue OpRet(Ret, 0);
427 SDValue OpCall(BI, 0);
Dan Gohman095cc292008-09-13 01:54:27 +0000428 bool isMarkedTailCall = TheCall->isTailCall();
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000429 // If CALL node has tail call attribute set to true and the call is not
430 // eligible (no RET or the target rejects) the attribute is fixed to
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +0000431 // false. The TargetLowering::IsEligibleForTailCallOptimization function
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000432 // must correctly identify tail call optimizable calls.
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000433 if (!isMarkedTailCall) continue;
434 if (Ret==NULL ||
Dan Gohman095cc292008-09-13 01:54:27 +0000435 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
436 // Not eligible. Mark CALL node as non tail call. Note that we
437 // can modify the call node in place since calls are not CSE'd.
438 TheCall->setNotTailCall();
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000439 } else {
440 // Look for tail call clobbered arguments. Emit a series of
441 // copyto/copyfrom virtual register nodes to protect them.
Dan Gohman475871a2008-07-27 21:46:04 +0000442 SmallVector<SDValue, 32> Ops;
Dan Gohman095cc292008-09-13 01:54:27 +0000443 SDValue Chain = TheCall->getChain(), InFlag;
444 Ops.push_back(Chain);
445 Ops.push_back(TheCall->getCallee());
446 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
447 SDValue Arg = TheCall->getArg(i);
448 bool isByVal = TheCall->getArgFlags(i).isByVal();
449 MachineFunction &MF = DAG.getMachineFunction();
450 MachineFrameInfo *MFI = MF.getFrameInfo();
451 if (!isByVal &&
452 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
453 MVT VT = Arg.getValueType();
454 unsigned VReg = MF.getRegInfo().
455 createVirtualRegister(TLI.getRegClassFor(VT));
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000456 Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(),
Dale Johannesenc460ae92009-02-04 00:13:36 +0000457 VReg, Arg, InFlag);
Dan Gohman095cc292008-09-13 01:54:27 +0000458 InFlag = Chain.getValue(1);
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000459 Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(),
Dale Johannesenc460ae92009-02-04 00:13:36 +0000460 VReg, VT, InFlag);
Dan Gohman095cc292008-09-13 01:54:27 +0000461 Chain = Arg.getValue(1);
462 InFlag = Arg.getValue(2);
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000463 }
464 Ops.push_back(Arg);
Dan Gohman095cc292008-09-13 01:54:27 +0000465 Ops.push_back(TheCall->getArgFlagsVal(i));
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000466 }
467 // Link in chain of CopyTo/CopyFromReg.
468 Ops[0] = Chain;
469 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000470 }
471 }
472 }
473}
474
Dan Gohmanf350b272008-08-23 02:25:05 +0000475void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
476 BasicBlock::iterator Begin,
Dan Gohman5edd3612008-08-28 20:28:56 +0000477 BasicBlock::iterator End) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000478 SDL->setCurrentBasicBlock(BB);
Dan Gohmanf350b272008-08-23 02:25:05 +0000479
Dan Gohmanf350b272008-08-23 02:25:05 +0000480 // Lower all of the non-terminator instructions.
481 for (BasicBlock::iterator I = Begin; I != End; ++I)
482 if (!isa<TerminatorInst>(I))
Dan Gohman7c3234c2008-08-27 23:52:12 +0000483 SDL->visit(*I);
Dan Gohmanf350b272008-08-23 02:25:05 +0000484
485 // Ensure that all instructions which are used outside of their defining
486 // blocks are available as virtual registers. Invoke is handled elsewhere.
487 for (BasicBlock::iterator I = Begin; I != End; ++I)
Dan Gohmanad62f532009-04-23 23:13:24 +0000488 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
489 SDL->CopyToExportRegsIfNeeded(I);
Dan Gohmanf350b272008-08-23 02:25:05 +0000490
491 // Handle PHI nodes in successor blocks.
Dan Gohman3df24e62008-09-03 23:12:08 +0000492 if (End == LLVMBB->end()) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000493 HandlePHINodesInSuccessorBlocks(LLVMBB);
Dan Gohman3df24e62008-09-03 23:12:08 +0000494
495 // Lower the terminator after the copies are emitted.
496 SDL->visit(*LLVMBB->getTerminator());
497 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000498
Chris Lattnera651cf62005-01-17 19:43:36 +0000499 // Make sure the root of the DAG is up-to-date.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000500 CurDAG->setRoot(SDL->getControlRoot());
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000501
502 // Check whether calls in this block are real tail calls. Fix up CALL nodes
503 // with correct tailcall attribute so that the target can rely on the tailcall
504 // attribute indicating whether the call is really eligible for tail call
505 // optimization.
Dan Gohman1937e2f2008-09-16 01:42:28 +0000506 if (PerformTailCallOpt)
507 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
Dan Gohmanf350b272008-08-23 02:25:05 +0000508
509 // Final step, emit the lowered DAG as machine code.
510 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000511 SDL->clear();
Chris Lattner1c08c712005-01-07 07:47:53 +0000512}
513
Dan Gohmanf350b272008-08-23 02:25:05 +0000514void SelectionDAGISel::ComputeLiveOutVRegInfo() {
Chris Lattneread0d882008-06-17 06:09:18 +0000515 SmallPtrSet<SDNode*, 128> VisitedNodes;
516 SmallVector<SDNode*, 128> Worklist;
517
Gabor Greifba36cb52008-08-28 21:40:38 +0000518 Worklist.push_back(CurDAG->getRoot().getNode());
Chris Lattneread0d882008-06-17 06:09:18 +0000519
520 APInt Mask;
521 APInt KnownZero;
522 APInt KnownOne;
523
524 while (!Worklist.empty()) {
525 SDNode *N = Worklist.back();
526 Worklist.pop_back();
527
528 // If we've already seen this node, ignore it.
529 if (!VisitedNodes.insert(N))
530 continue;
531
532 // Otherwise, add all chain operands to the worklist.
533 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
534 if (N->getOperand(i).getValueType() == MVT::Other)
Gabor Greifba36cb52008-08-28 21:40:38 +0000535 Worklist.push_back(N->getOperand(i).getNode());
Chris Lattneread0d882008-06-17 06:09:18 +0000536
537 // If this is a CopyToReg with a vreg dest, process it.
538 if (N->getOpcode() != ISD::CopyToReg)
539 continue;
540
541 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
542 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
543 continue;
544
545 // Ignore non-scalar or non-integer values.
Dan Gohman475871a2008-07-27 21:46:04 +0000546 SDValue Src = N->getOperand(2);
Chris Lattneread0d882008-06-17 06:09:18 +0000547 MVT SrcVT = Src.getValueType();
548 if (!SrcVT.isInteger() || SrcVT.isVector())
549 continue;
550
Dan Gohmanf350b272008-08-23 02:25:05 +0000551 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
Chris Lattneread0d882008-06-17 06:09:18 +0000552 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
Dan Gohmanf350b272008-08-23 02:25:05 +0000553 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
Chris Lattneread0d882008-06-17 06:09:18 +0000554
555 // Only install this information if it tells us something.
556 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
557 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
Dan Gohmanf350b272008-08-23 02:25:05 +0000558 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
Chris Lattneread0d882008-06-17 06:09:18 +0000559 if (DestReg >= FLI.LiveOutRegInfo.size())
560 FLI.LiveOutRegInfo.resize(DestReg+1);
561 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
562 LOI.NumSignBits = NumSignBits;
Dan Gohmana80efce2009-03-27 23:55:04 +0000563 LOI.KnownOne = KnownOne;
564 LOI.KnownZero = KnownZero;
Chris Lattneread0d882008-06-17 06:09:18 +0000565 }
566 }
567}
568
Dan Gohmanf350b272008-08-23 02:25:05 +0000569void SelectionDAGISel::CodeGenAndEmitDAG() {
Dan Gohman462dc7f2008-07-21 20:00:07 +0000570 std::string GroupName;
571 if (TimePassesIsEnabled)
572 GroupName = "Instruction Selection and Scheduling";
573 std::string BlockName;
574 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
Duncan Sands25cf2272008-11-24 14:53:14 +0000575 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
576 ViewSUnitDAGs)
Daniel Dunbarf6ccee52009-07-24 08:24:36 +0000577 BlockName = CurDAG->getMachineFunction().getFunction()->getNameStr() + ":" +
578 BB->getBasicBlock()->getNameStr();
Dan Gohman462dc7f2008-07-21 20:00:07 +0000579
580 DOUT << "Initial selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000581 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000582
Dan Gohmanf350b272008-08-23 02:25:05 +0000583 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
Dan Gohman417e11b2007-10-08 15:12:17 +0000584
Chris Lattneraf21d552005-10-10 16:47:10 +0000585 // Run the DAG combiner in pre-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +0000586 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000587 NamedRegionTimer T("DAG Combining 1", GroupName);
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000588 CurDAG->Combine(Unrestricted, *AA, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000589 } else {
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000590 CurDAG->Combine(Unrestricted, *AA, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000591 }
Nate Begeman2300f552005-09-07 00:15:36 +0000592
Dan Gohman417e11b2007-10-08 15:12:17 +0000593 DOUT << "Optimized lowered selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000594 DEBUG(CurDAG->dump());
Duncan Sandsf00e74f2008-07-17 17:06:03 +0000595
Chris Lattner1c08c712005-01-07 07:47:53 +0000596 // Second step, hack on the DAG until it only uses operations and types that
597 // the target supports.
Duncan Sands7cb07872008-10-27 08:42:46 +0000598 if (!DisableLegalizeTypes) {
Dan Gohmanf350b272008-08-23 02:25:05 +0000599 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
600 BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000601
Duncan Sands25cf2272008-11-24 14:53:14 +0000602 bool Changed;
Dan Gohman462dc7f2008-07-21 20:00:07 +0000603 if (TimePassesIsEnabled) {
604 NamedRegionTimer T("Type Legalization", GroupName);
Duncan Sands25cf2272008-11-24 14:53:14 +0000605 Changed = CurDAG->LegalizeTypes();
Dan Gohman462dc7f2008-07-21 20:00:07 +0000606 } else {
Duncan Sands25cf2272008-11-24 14:53:14 +0000607 Changed = CurDAG->LegalizeTypes();
Dan Gohman462dc7f2008-07-21 20:00:07 +0000608 }
609
610 DOUT << "Type-legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000611 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000612
Duncan Sands25cf2272008-11-24 14:53:14 +0000613 if (Changed) {
614 if (ViewDAGCombineLT)
615 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
616
617 // Run the DAG combiner in post-type-legalize mode.
618 if (TimePassesIsEnabled) {
619 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000620 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
Duncan Sands25cf2272008-11-24 14:53:14 +0000621 } else {
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000622 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
Duncan Sands25cf2272008-11-24 14:53:14 +0000623 }
624
625 DOUT << "Optimized type-legalized selection DAG:\n";
626 DEBUG(CurDAG->dump());
627 }
Eli Friedman5c22c802009-05-23 12:35:30 +0000628
629 if (TimePassesIsEnabled) {
630 NamedRegionTimer T("Vector Legalization", GroupName);
631 Changed = CurDAG->LegalizeVectors();
632 } else {
633 Changed = CurDAG->LegalizeVectors();
634 }
635
636 if (Changed) {
637 if (TimePassesIsEnabled) {
638 NamedRegionTimer T("Type Legalization 2", GroupName);
639 Changed = CurDAG->LegalizeTypes();
640 } else {
641 Changed = CurDAG->LegalizeTypes();
642 }
643
644 if (ViewDAGCombineLT)
645 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
646
647 // Run the DAG combiner in post-type-legalize mode.
648 if (TimePassesIsEnabled) {
649 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
650 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
651 } else {
652 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
653 }
654
655 DOUT << "Optimized vector-legalized selection DAG:\n";
656 DEBUG(CurDAG->dump());
657 }
Chris Lattner70587ea2008-07-10 23:37:50 +0000658 }
Duncan Sandsf00e74f2008-07-17 17:06:03 +0000659
Dan Gohmanf350b272008-08-23 02:25:05 +0000660 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000661
Evan Chengebffb662008-07-01 17:59:20 +0000662 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000663 NamedRegionTimer T("DAG Legalization", GroupName);
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000664 CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000665 } else {
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000666 CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000667 }
Nate Begemanf15485a2006-03-27 01:32:24 +0000668
Bill Wendling832171c2006-12-07 20:04:42 +0000669 DOUT << "Legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000670 DEBUG(CurDAG->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000671
Dan Gohmanf350b272008-08-23 02:25:05 +0000672 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000673
Chris Lattneraf21d552005-10-10 16:47:10 +0000674 // Run the DAG combiner in post-legalize mode.
Evan Chengebffb662008-07-01 17:59:20 +0000675 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000676 NamedRegionTimer T("DAG Combining 2", GroupName);
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000677 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000678 } else {
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +0000679 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
Evan Chengebffb662008-07-01 17:59:20 +0000680 }
Nate Begeman2300f552005-09-07 00:15:36 +0000681
Dan Gohman417e11b2007-10-08 15:12:17 +0000682 DOUT << "Optimized legalized selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000683 DEBUG(CurDAG->dump());
Dan Gohman417e11b2007-10-08 15:12:17 +0000684
Dan Gohmanf350b272008-08-23 02:25:05 +0000685 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
Chris Lattneread0d882008-06-17 06:09:18 +0000686
Bill Wendling98a366d2009-04-29 23:29:43 +0000687 if (OptLevel != CodeGenOpt::None)
Dan Gohmanf350b272008-08-23 02:25:05 +0000688 ComputeLiveOutVRegInfo();
Evan Cheng552c4a82006-04-28 02:09:19 +0000689
Chris Lattnera33ef482005-03-30 01:10:47 +0000690 // Third, instruction select all of the operations to machine code, adding the
691 // code to the MachineBasicBlock.
Evan Chengebffb662008-07-01 17:59:20 +0000692 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000693 NamedRegionTimer T("Instruction Selection", GroupName);
Dan Gohmanf350b272008-08-23 02:25:05 +0000694 InstructionSelect();
Evan Chengebffb662008-07-01 17:59:20 +0000695 } else {
Dan Gohmanf350b272008-08-23 02:25:05 +0000696 InstructionSelect();
Evan Chengebffb662008-07-01 17:59:20 +0000697 }
Evan Chengdb8d56b2008-06-30 20:45:06 +0000698
Dan Gohman462dc7f2008-07-21 20:00:07 +0000699 DOUT << "Selected selection DAG:\n";
Dan Gohmanf350b272008-08-23 02:25:05 +0000700 DEBUG(CurDAG->dump());
Dan Gohman462dc7f2008-07-21 20:00:07 +0000701
Dan Gohmanf350b272008-08-23 02:25:05 +0000702 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
Dan Gohman462dc7f2008-07-21 20:00:07 +0000703
Dan Gohman5e843682008-07-14 18:19:29 +0000704 // Schedule machine code.
Dan Gohman47ac0f02009-02-11 04:27:20 +0000705 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
Dan Gohman5e843682008-07-14 18:19:29 +0000706 if (TimePassesIsEnabled) {
707 NamedRegionTimer T("Instruction Scheduling", GroupName);
Dan Gohman47ac0f02009-02-11 04:27:20 +0000708 Scheduler->Run(CurDAG, BB, BB->end());
Dan Gohman5e843682008-07-14 18:19:29 +0000709 } else {
Dan Gohman47ac0f02009-02-11 04:27:20 +0000710 Scheduler->Run(CurDAG, BB, BB->end());
Dan Gohman5e843682008-07-14 18:19:29 +0000711 }
712
Dan Gohman462dc7f2008-07-21 20:00:07 +0000713 if (ViewSUnitDAGs) Scheduler->viewGraph();
714
Evan Chengdb8d56b2008-06-30 20:45:06 +0000715 // Emit machine code to BB. This can change 'BB' to the last block being
716 // inserted into.
Evan Chengebffb662008-07-01 17:59:20 +0000717 if (TimePassesIsEnabled) {
Dan Gohman5e843682008-07-14 18:19:29 +0000718 NamedRegionTimer T("Instruction Creation", GroupName);
719 BB = Scheduler->EmitSchedule();
Evan Chengebffb662008-07-01 17:59:20 +0000720 } else {
Dan Gohman5e843682008-07-14 18:19:29 +0000721 BB = Scheduler->EmitSchedule();
722 }
723
724 // Free the scheduler state.
725 if (TimePassesIsEnabled) {
726 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
727 delete Scheduler;
728 } else {
729 delete Scheduler;
Evan Chengebffb662008-07-01 17:59:20 +0000730 }
Evan Chengdb8d56b2008-06-30 20:45:06 +0000731
Bill Wendling832171c2006-12-07 20:04:42 +0000732 DOUT << "Selected machine code:\n";
Chris Lattner1c08c712005-01-07 07:47:53 +0000733 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000734}
Chris Lattner1c08c712005-01-07 07:47:53 +0000735
Dan Gohman79ce2762009-01-15 19:20:50 +0000736void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
737 MachineFunction &MF,
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000738 MachineModuleInfo *MMI,
Devang Patel83489bb2009-01-13 00:35:13 +0000739 DwarfWriter *DW,
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000740 const TargetInstrInfo &TII) {
Dan Gohmana43abd12008-09-29 21:55:50 +0000741 // Initialize the Fast-ISel state, if needed.
742 FastISel *FastIS = 0;
743 if (EnableFastISel)
Dan Gohman79ce2762009-01-15 19:20:50 +0000744 FastIS = TLI.createFastISel(MF, MMI, DW,
Dan Gohmana43abd12008-09-29 21:55:50 +0000745 FuncInfo->ValueMap,
746 FuncInfo->MBBMap,
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000747 FuncInfo->StaticAllocaMap
748#ifndef NDEBUG
749 , FuncInfo->CatchInfoLost
750#endif
751 );
Dan Gohmana43abd12008-09-29 21:55:50 +0000752
753 // Iterate over all basic blocks in the function.
Evan Cheng39fd6e82008-08-07 00:43:25 +0000754 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
755 BasicBlock *LLVMBB = &*I;
Dan Gohman7c3234c2008-08-27 23:52:12 +0000756 BB = FuncInfo->MBBMap[LLVMBB];
Dan Gohmanf350b272008-08-23 02:25:05 +0000757
Dan Gohman3df24e62008-09-03 23:12:08 +0000758 BasicBlock::iterator const Begin = LLVMBB->begin();
759 BasicBlock::iterator const End = LLVMBB->end();
Evan Cheng9f118502008-09-08 16:01:27 +0000760 BasicBlock::iterator BI = Begin;
Dan Gohman5edd3612008-08-28 20:28:56 +0000761
762 // Lower any arguments needed in this block if this is the entry block.
Dan Gohman33134c42008-09-25 17:05:24 +0000763 bool SuppressFastISel = false;
764 if (LLVMBB == &Fn.getEntryBlock()) {
Dan Gohman5edd3612008-08-28 20:28:56 +0000765 LowerArguments(LLVMBB);
Dan Gohmanf350b272008-08-23 02:25:05 +0000766
Dan Gohman33134c42008-09-25 17:05:24 +0000767 // If any of the arguments has the byval attribute, forgo
768 // fast-isel in the entry block.
Dan Gohmana43abd12008-09-29 21:55:50 +0000769 if (FastIS) {
Dan Gohman33134c42008-09-25 17:05:24 +0000770 unsigned j = 1;
771 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
772 I != E; ++I, ++j)
Devang Patel05988662008-09-25 21:00:45 +0000773 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
Dan Gohman77ca41e2008-09-25 17:21:42 +0000774 if (EnableFastISelVerbose || EnableFastISelAbort)
775 cerr << "FastISel skips entry block due to byval argument\n";
Dan Gohman33134c42008-09-25 17:05:24 +0000776 SuppressFastISel = true;
777 break;
778 }
779 }
780 }
781
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000782 if (MMI && BB->isLandingPad()) {
783 // Add a label to mark the beginning of the landing pad. Deletion of the
784 // landing pad can thus be detected via the MachineModuleInfo.
785 unsigned LabelID = MMI->addLandingPad(BB);
786
787 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EH_LABEL);
Bill Wendlingb2884872009-02-03 01:55:42 +0000788 BuildMI(BB, SDL->getCurDebugLoc(), II).addImm(LabelID);
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000789
790 // Mark exception register as live in.
791 unsigned Reg = TLI.getExceptionAddressRegister();
792 if (Reg) BB->addLiveIn(Reg);
793
794 // Mark exception selector register as live in.
795 Reg = TLI.getExceptionSelectorRegister();
796 if (Reg) BB->addLiveIn(Reg);
797
798 // FIXME: Hack around an exception handling flaw (PR1508): the personality
799 // function and list of typeids logically belong to the invoke (or, if you
800 // like, the basic block containing the invoke), and need to be associated
801 // with it in the dwarf exception handling tables. Currently however the
802 // information is provided by an intrinsic (eh.selector) that can be moved
803 // to unexpected places by the optimizers: if the unwind edge is critical,
804 // then breaking it can result in the intrinsics being in the successor of
805 // the landing pad, not the landing pad itself. This results in exceptions
806 // not being caught because no typeids are associated with the invoke.
807 // This may not be the only way things can go wrong, but it is the only way
808 // we try to work around for the moment.
809 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
810
811 if (Br && Br->isUnconditional()) { // Critical edge?
812 BasicBlock::iterator I, E;
813 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
814 if (isa<EHSelectorInst>(I))
815 break;
816
817 if (I == E)
818 // No catch info found - try to extract some from the successor.
819 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
820 }
821 }
822
Dan Gohmanf350b272008-08-23 02:25:05 +0000823 // Before doing SelectionDAG ISel, see if FastISel has been requested.
Dan Gohmandd5b58a2008-10-14 23:54:11 +0000824 if (FastIS && !SuppressFastISel) {
Dan Gohmana43abd12008-09-29 21:55:50 +0000825 // Emit code for any incoming arguments. This must happen before
826 // beginning FastISel on the entry block.
827 if (LLVMBB == &Fn.getEntryBlock()) {
828 CurDAG->setRoot(SDL->getControlRoot());
829 CodeGenAndEmitDAG();
830 SDL->clear();
831 }
Dan Gohman241f4642008-10-04 00:56:36 +0000832 FastIS->startNewBlock(BB);
Dan Gohmana43abd12008-09-29 21:55:50 +0000833 // Do FastISel on as many instructions as possible.
834 for (; BI != End; ++BI) {
835 // Just before the terminator instruction, insert instructions to
836 // feed PHI nodes in successor blocks.
837 if (isa<TerminatorInst>(BI))
838 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
Dan Gohman4344a5d2008-09-09 23:05:00 +0000839 if (EnableFastISelVerbose || EnableFastISelAbort) {
Dan Gohman293d5f82008-09-09 22:06:46 +0000840 cerr << "FastISel miss: ";
841 BI->dump();
842 }
Torok Edwinf3689232009-07-12 20:07:01 +0000843 assert(!EnableFastISelAbort &&
844 "FastISel didn't handle a PHI in a successor");
Dan Gohmana43abd12008-09-29 21:55:50 +0000845 break;
Dan Gohmanf350b272008-08-23 02:25:05 +0000846 }
Dan Gohmana43abd12008-09-29 21:55:50 +0000847
848 // First try normal tablegen-generated "fast" selection.
849 if (FastIS->SelectInstruction(BI))
850 continue;
851
852 // Next, try calling the target to attempt to handle the instruction.
853 if (FastIS->TargetSelectInstruction(BI))
854 continue;
855
856 // Then handle certain instructions as single-LLVM-Instruction blocks.
857 if (isa<CallInst>(BI)) {
858 if (EnableFastISelVerbose || EnableFastISelAbort) {
859 cerr << "FastISel missed call: ";
860 BI->dump();
861 }
862
863 if (BI->getType() != Type::VoidTy) {
864 unsigned &R = FuncInfo->ValueMap[BI];
865 if (!R)
866 R = FuncInfo->CreateRegForValue(BI);
867 }
868
Devang Patel390f3ac2009-04-16 01:33:10 +0000869 SDL->setCurDebugLoc(FastIS->getCurDebugLoc());
Dan Gohmana43abd12008-09-29 21:55:50 +0000870 SelectBasicBlock(LLVMBB, BI, next(BI));
Dan Gohman241f4642008-10-04 00:56:36 +0000871 // If the instruction was codegen'd with multiple blocks,
872 // inform the FastISel object where to resume inserting.
873 FastIS->setCurrentBlock(BB);
Dan Gohmana43abd12008-09-29 21:55:50 +0000874 continue;
Dan Gohmanf350b272008-08-23 02:25:05 +0000875 }
Dan Gohmana43abd12008-09-29 21:55:50 +0000876
877 // Otherwise, give up on FastISel for the rest of the block.
878 // For now, be a little lenient about non-branch terminators.
879 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
880 if (EnableFastISelVerbose || EnableFastISelAbort) {
881 cerr << "FastISel miss: ";
882 BI->dump();
883 }
884 if (EnableFastISelAbort)
885 // The "fast" selector couldn't handle something and bailed.
886 // For the purpose of debugging, just abort.
Torok Edwinc23197a2009-07-14 16:55:14 +0000887 llvm_unreachable("FastISel didn't select the entire block");
Dan Gohmana43abd12008-09-29 21:55:50 +0000888 }
889 break;
Dan Gohmanf350b272008-08-23 02:25:05 +0000890 }
891 }
892
Dan Gohmand2ff6472008-09-02 20:17:56 +0000893 // Run SelectionDAG instruction selection on the remainder of the block
894 // not handled by FastISel. If FastISel is not run, this is the entire
Dan Gohman3df24e62008-09-03 23:12:08 +0000895 // block.
Devang Patel390f3ac2009-04-16 01:33:10 +0000896 if (BI != End) {
897 // If FastISel is run and it has known DebugLoc then use it.
898 if (FastIS && !FastIS->getCurDebugLoc().isUnknown())
899 SDL->setCurDebugLoc(FastIS->getCurDebugLoc());
Evan Cheng9f118502008-09-08 16:01:27 +0000900 SelectBasicBlock(LLVMBB, BI, End);
Devang Patel390f3ac2009-04-16 01:33:10 +0000901 }
Dan Gohmanf350b272008-08-23 02:25:05 +0000902
Dan Gohman7c3234c2008-08-27 23:52:12 +0000903 FinishBasicBlock();
Evan Cheng39fd6e82008-08-07 00:43:25 +0000904 }
Dan Gohmana43abd12008-09-29 21:55:50 +0000905
906 delete FastIS;
Dan Gohman0e5f1302008-07-07 23:02:41 +0000907}
908
Dan Gohmanfed90b62008-07-28 21:51:04 +0000909void
Dan Gohman7c3234c2008-08-27 23:52:12 +0000910SelectionDAGISel::FinishBasicBlock() {
Dan Gohmanf350b272008-08-23 02:25:05 +0000911
Dan Gohmanf350b272008-08-23 02:25:05 +0000912 DOUT << "Target-post-processed machine code:\n";
913 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +0000914
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000915 DOUT << "Total amount of phi nodes to update: "
Dan Gohman7c3234c2008-08-27 23:52:12 +0000916 << SDL->PHINodesToUpdate.size() << "\n";
917 DEBUG(for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i)
918 DOUT << "Node " << i << " : (" << SDL->PHINodesToUpdate[i].first
919 << ", " << SDL->PHINodesToUpdate[i].second << ")\n";);
Nate Begemanf15485a2006-03-27 01:32:24 +0000920
Chris Lattnera33ef482005-03-30 01:10:47 +0000921 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner1c08c712005-01-07 07:47:53 +0000922 // PHI nodes in successors.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000923 if (SDL->SwitchCases.empty() &&
924 SDL->JTCases.empty() &&
925 SDL->BitTestCases.empty()) {
926 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
927 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
Nate Begemanf15485a2006-03-27 01:32:24 +0000928 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
929 "This is not a machine PHI node that we are updating!");
Dan Gohman7c3234c2008-08-27 23:52:12 +0000930 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000931 false));
932 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begemanf15485a2006-03-27 01:32:24 +0000933 }
Dan Gohman7c3234c2008-08-27 23:52:12 +0000934 SDL->PHINodesToUpdate.clear();
Nate Begemanf15485a2006-03-27 01:32:24 +0000935 return;
Chris Lattner1c08c712005-01-07 07:47:53 +0000936 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000937
Dan Gohman7c3234c2008-08-27 23:52:12 +0000938 for (unsigned i = 0, e = SDL->BitTestCases.size(); i != e; ++i) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000939 // Lower header first, if it wasn't already lowered
Dan Gohman7c3234c2008-08-27 23:52:12 +0000940 if (!SDL->BitTestCases[i].Emitted) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000941 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000942 BB = SDL->BitTestCases[i].Parent;
943 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000944 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +0000945 SDL->visitBitTestHeader(SDL->BitTestCases[i]);
946 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000947 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000948 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000949 }
950
Dan Gohman7c3234c2008-08-27 23:52:12 +0000951 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000952 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +0000953 BB = SDL->BitTestCases[i].Cases[j].ThisBB;
954 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000955 // Emit the code
956 if (j+1 != ej)
Dan Gohman7c3234c2008-08-27 23:52:12 +0000957 SDL->visitBitTestCase(SDL->BitTestCases[i].Cases[j+1].ThisBB,
958 SDL->BitTestCases[i].Reg,
959 SDL->BitTestCases[i].Cases[j]);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000960 else
Dan Gohman7c3234c2008-08-27 23:52:12 +0000961 SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
962 SDL->BitTestCases[i].Reg,
963 SDL->BitTestCases[i].Cases[j]);
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000964
965
Dan Gohman7c3234c2008-08-27 23:52:12 +0000966 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +0000967 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +0000968 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000969 }
970
971 // Update PHI Nodes
Dan Gohman7c3234c2008-08-27 23:52:12 +0000972 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
973 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000974 MachineBasicBlock *PHIBB = PHI->getParent();
975 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
976 "This is not a machine PHI node that we are updating!");
977 // This is "default" BB. We have two jumps to it. From "header" BB and
978 // from last "case" BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000979 if (PHIBB == SDL->BitTestCases[i].Default) {
980 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000981 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000982 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Parent));
983 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000984 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +0000985 PHI->addOperand(MachineOperand::CreateMBB(SDL->BitTestCases[i].Cases.
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000986 back().ThisBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000987 }
988 // One of "cases" BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +0000989 for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size();
990 j != ej; ++j) {
991 MachineBasicBlock* cBB = SDL->BitTestCases[i].Cases[j].ThisBB;
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000992 if (cBB->succ_end() !=
993 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
Dan Gohman7c3234c2008-08-27 23:52:12 +0000994 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +0000995 false));
996 PHI->addOperand(MachineOperand::CreateMBB(cBB));
Anton Korobeynikov4198c582007-04-09 12:31:58 +0000997 }
998 }
999 }
1000 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001001 SDL->BitTestCases.clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001002
Nate Begeman9453eea2006-04-23 06:26:20 +00001003 // If the JumpTable record is filled in, then we need to emit a jump table.
1004 // Updating the PHI nodes is tricky in this case, since we need to determine
1005 // whether the PHI is a successor of the range check MBB or the jump table MBB
Dan Gohman7c3234c2008-08-27 23:52:12 +00001006 for (unsigned i = 0, e = SDL->JTCases.size(); i != e; ++i) {
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001007 // Lower header first, if it wasn't already lowered
Dan Gohman7c3234c2008-08-27 23:52:12 +00001008 if (!SDL->JTCases[i].first.Emitted) {
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001009 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +00001010 BB = SDL->JTCases[i].first.HeaderBB;
1011 SDL->setCurrentBasicBlock(BB);
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001012 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +00001013 SDL->visitJumpTableHeader(SDL->JTCases[i].second, SDL->JTCases[i].first);
1014 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +00001015 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +00001016 SDL->clear();
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001017 }
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001018
Nate Begeman37efe672006-04-22 18:53:45 +00001019 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +00001020 BB = SDL->JTCases[i].second.MBB;
1021 SDL->setCurrentBasicBlock(BB);
Nate Begeman37efe672006-04-22 18:53:45 +00001022 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +00001023 SDL->visitJumpTable(SDL->JTCases[i].second);
1024 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +00001025 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +00001026 SDL->clear();
Anton Korobeynikov3a84b9b2007-03-25 15:07:15 +00001027
Nate Begeman37efe672006-04-22 18:53:45 +00001028 // Update PHI Nodes
Dan Gohman7c3234c2008-08-27 23:52:12 +00001029 for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
1030 MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
Nate Begeman37efe672006-04-22 18:53:45 +00001031 MachineBasicBlock *PHIBB = PHI->getParent();
1032 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1033 "This is not a machine PHI node that we are updating!");
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001034 // "default" BB. We can go there only from header BB.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001035 if (PHIBB == SDL->JTCases[i].second.Default) {
1036 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00001037 false));
Dan Gohman7c3234c2008-08-27 23:52:12 +00001038 PHI->addOperand(MachineOperand::CreateMBB(SDL->JTCases[i].first.HeaderBB));
Nate Begemanf4360a42006-05-03 03:48:02 +00001039 }
Anton Korobeynikov4198c582007-04-09 12:31:58 +00001040 // JT BB. Just iterate over successors here
Nate Begemanf4360a42006-05-03 03:48:02 +00001041 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Dan Gohman7c3234c2008-08-27 23:52:12 +00001042 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pi].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00001043 false));
1044 PHI->addOperand(MachineOperand::CreateMBB(BB));
Nate Begeman37efe672006-04-22 18:53:45 +00001045 }
1046 }
Nate Begeman37efe672006-04-22 18:53:45 +00001047 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001048 SDL->JTCases.clear();
Nate Begeman37efe672006-04-22 18:53:45 +00001049
Chris Lattnerb2e806e2006-10-22 23:00:53 +00001050 // If the switch block involved a branch to one of the actual successors, we
1051 // need to update PHI nodes in that block.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001052 for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
1053 MachineInstr *PHI = SDL->PHINodesToUpdate[i].first;
Chris Lattnerb2e806e2006-10-22 23:00:53 +00001054 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1055 "This is not a machine PHI node that we are updating!");
1056 if (BB->isSuccessor(PHI->getParent())) {
Dan Gohman7c3234c2008-08-27 23:52:12 +00001057 PHI->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[i].second,
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00001058 false));
1059 PHI->addOperand(MachineOperand::CreateMBB(BB));
Chris Lattnerb2e806e2006-10-22 23:00:53 +00001060 }
1061 }
1062
Nate Begemanf15485a2006-03-27 01:32:24 +00001063 // If we generated any switch lowering information, build and codegen any
1064 // additional DAGs necessary.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001065 for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
Nate Begemanf15485a2006-03-27 01:32:24 +00001066 // Set the current basic block to the mbb we wish to insert the code into
Dan Gohman7c3234c2008-08-27 23:52:12 +00001067 BB = SDL->SwitchCases[i].ThisBB;
1068 SDL->setCurrentBasicBlock(BB);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001069
Nate Begemanf15485a2006-03-27 01:32:24 +00001070 // Emit the code
Dan Gohman7c3234c2008-08-27 23:52:12 +00001071 SDL->visitSwitchCase(SDL->SwitchCases[i]);
1072 CurDAG->setRoot(SDL->getRoot());
Dan Gohmanf350b272008-08-23 02:25:05 +00001073 CodeGenAndEmitDAG();
Dan Gohman7c3234c2008-08-27 23:52:12 +00001074 SDL->clear();
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001075
1076 // Handle any PHI nodes in successors of this chunk, as if we were coming
1077 // from the original BB before switch expansion. Note that PHI nodes can
1078 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1079 // handle them the right number of times.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001080 while ((BB = SDL->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001081 for (MachineBasicBlock::iterator Phi = BB->begin();
1082 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
1083 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
1084 for (unsigned pn = 0; ; ++pn) {
Dan Gohman7c3234c2008-08-27 23:52:12 +00001085 assert(pn != SDL->PHINodesToUpdate.size() &&
1086 "Didn't find PHI entry!");
1087 if (SDL->PHINodesToUpdate[pn].first == Phi) {
1088 Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
Chris Lattner9ce2e9d2007-12-30 00:57:42 +00001089 second, false));
Dan Gohman7c3234c2008-08-27 23:52:12 +00001090 Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001091 break;
1092 }
1093 }
Nate Begemanf15485a2006-03-27 01:32:24 +00001094 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001095
1096 // Don't process RHS if same block as LHS.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001097 if (BB == SDL->SwitchCases[i].FalseBB)
1098 SDL->SwitchCases[i].FalseBB = 0;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00001099
1100 // If we haven't handled the RHS, do so now. Otherwise, we're done.
Dan Gohman7c3234c2008-08-27 23:52:12 +00001101 SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
1102 SDL->SwitchCases[i].FalseBB = 0;
Nate Begemanf15485a2006-03-27 01:32:24 +00001103 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001104 assert(SDL->SwitchCases[i].TrueBB == 0 && SDL->SwitchCases[i].FalseBB == 0);
Chris Lattnera33ef482005-03-30 01:10:47 +00001105 }
Dan Gohman7c3234c2008-08-27 23:52:12 +00001106 SDL->SwitchCases.clear();
1107
1108 SDL->PHINodesToUpdate.clear();
Chris Lattner1c08c712005-01-07 07:47:53 +00001109}
Evan Chenga9c20912006-01-21 02:32:06 +00001110
Jim Laskey13ec7022006-08-01 14:21:23 +00001111
Dan Gohman0a3776d2009-02-06 18:26:51 +00001112/// Create the scheduler. If a specific scheduler was specified
1113/// via the SchedulerRegistry, use it, otherwise select the
1114/// one preferred by the target.
Dan Gohman5e843682008-07-14 18:19:29 +00001115///
Dan Gohman47ac0f02009-02-11 04:27:20 +00001116ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00001117 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey13ec7022006-08-01 14:21:23 +00001118
1119 if (!Ctor) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00001120 Ctor = ISHeuristic;
Jim Laskey9373beb2006-08-01 19:14:14 +00001121 RegisterScheduler::setDefault(Ctor);
Evan Cheng4ef10862006-01-23 07:01:07 +00001122 }
Jim Laskey13ec7022006-08-01 14:21:23 +00001123
Bill Wendlingbe8cc2a2009-04-29 00:15:41 +00001124 return Ctor(this, OptLevel);
Evan Chenga9c20912006-01-21 02:32:06 +00001125}
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001126
Dan Gohmanfc54c552009-01-15 22:18:12 +00001127ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1128 return new ScheduleHazardRecognizer();
Jim Laskey9ff542f2006-08-01 18:29:48 +00001129}
1130
Chris Lattner75548062006-10-11 03:58:02 +00001131//===----------------------------------------------------------------------===//
1132// Helper functions used by the generated instruction selector.
1133//===----------------------------------------------------------------------===//
1134// Calls to these methods are generated by tblgen.
1135
1136/// CheckAndMask - The isel is trying to match something like (and X, 255). If
1137/// the dag combiner simplified the 255, we still want to match. RHS is the
1138/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1139/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00001140bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohmandc9b3d02007-07-24 23:00:27 +00001141 int64_t DesiredMaskS) const {
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001142 const APInt &ActualMask = RHS->getAPIntValue();
1143 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00001144
1145 // If the actual mask exactly matches, success!
1146 if (ActualMask == DesiredMask)
1147 return true;
1148
1149 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001150 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00001151 return false;
1152
1153 // Otherwise, the DAG Combiner may have proven that the value coming in is
1154 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001155 APInt NeededMask = DesiredMask & ~ActualMask;
Dan Gohmanea859be2007-06-22 14:59:07 +00001156 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
Chris Lattner75548062006-10-11 03:58:02 +00001157 return true;
1158
1159 // TODO: check to see if missing bits are just not demanded.
1160
1161 // Otherwise, this pattern doesn't match.
1162 return false;
1163}
1164
1165/// CheckOrMask - The isel is trying to match something like (or X, 255). If
1166/// the dag combiner simplified the 255, we still want to match. RHS is the
1167/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1168/// specified in the .td file (e.g. 255).
Dan Gohman475871a2008-07-27 21:46:04 +00001169bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001170 int64_t DesiredMaskS) const {
1171 const APInt &ActualMask = RHS->getAPIntValue();
1172 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
Chris Lattner75548062006-10-11 03:58:02 +00001173
1174 // If the actual mask exactly matches, success!
1175 if (ActualMask == DesiredMask)
1176 return true;
1177
1178 // If the actual AND mask is allowing unallowed bits, this doesn't match.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001179 if (ActualMask.intersects(~DesiredMask))
Chris Lattner75548062006-10-11 03:58:02 +00001180 return false;
1181
1182 // Otherwise, the DAG Combiner may have proven that the value coming in is
1183 // either already zero or is not demanded. Check for known zero input bits.
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001184 APInt NeededMask = DesiredMask & ~ActualMask;
Chris Lattner75548062006-10-11 03:58:02 +00001185
Dan Gohman2e68b6f2008-02-25 21:11:39 +00001186 APInt KnownZero, KnownOne;
Dan Gohmanea859be2007-06-22 14:59:07 +00001187 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
Chris Lattner75548062006-10-11 03:58:02 +00001188
1189 // If all the missing bits in the or are already known to be set, match!
1190 if ((NeededMask & KnownOne) == NeededMask)
1191 return true;
1192
1193 // TODO: check to see if missing bits are just not demanded.
1194
1195 // Otherwise, this pattern doesn't match.
1196 return false;
1197}
1198
Jim Laskey9ff542f2006-08-01 18:29:48 +00001199
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001200/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1201/// by tblgen. Others should not call it.
1202void SelectionDAGISel::
Dan Gohmanf350b272008-08-23 02:25:05 +00001203SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
Dan Gohman475871a2008-07-27 21:46:04 +00001204 std::vector<SDValue> InOps;
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001205 std::swap(InOps, Ops);
1206
1207 Ops.push_back(InOps[0]); // input chain.
1208 Ops.push_back(InOps[1]); // input asm string.
1209
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001210 unsigned i = 2, e = InOps.size();
1211 if (InOps[e-1].getValueType() == MVT::Flag)
1212 --e; // Don't process a flag operand if it is here.
1213
1214 while (i != e) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001215 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
Dale Johannesen86b49f82008-09-24 01:07:17 +00001216 if ((Flags & 7) != 4 /*MEM*/) {
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001217 // Just skip over this operand, copying the operands verbatim.
Evan Cheng697cbbf2009-03-20 18:03:34 +00001218 Ops.insert(Ops.end(), InOps.begin()+i,
1219 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1220 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001221 } else {
Evan Cheng697cbbf2009-03-20 18:03:34 +00001222 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1223 "Memory operand with multiple values?");
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001224 // Otherwise, this is a memory operand. Ask the target to select it.
Dan Gohman475871a2008-07-27 21:46:04 +00001225 std::vector<SDValue> SelOps;
Dan Gohmanf350b272008-08-23 02:25:05 +00001226 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
Torok Edwin7d696d82009-07-11 13:10:19 +00001227 llvm_report_error("Could not match memory address. Inline asm"
1228 " failure!");
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001229 }
1230
1231 // Add this to the output node.
Dan Gohmanf350b272008-08-23 02:25:05 +00001232 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
Dale Johannesen86b49f82008-09-24 01:07:17 +00001233 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
Dan Gohmanf350b272008-08-23 02:25:05 +00001234 IntPtrTy));
Chris Lattner0e43f2b2006-02-24 02:13:54 +00001235 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1236 i += 2;
1237 }
1238 }
1239
1240 // Add the flag input back if present.
1241 if (e != InOps.size())
1242 Ops.push_back(InOps.back());
1243}
Devang Patel794fd752007-05-01 21:15:47 +00001244
Anton Korobeynikovc1c6ef82009-05-08 18:51:58 +00001245/// findFlagUse - Return use of MVT::Flag value produced by the specified
1246/// SDNode.
1247///
1248static SDNode *findFlagUse(SDNode *N) {
1249 unsigned FlagResNo = N->getNumValues()-1;
1250 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1251 SDUse &Use = I.getUse();
1252 if (Use.getResNo() == FlagResNo)
1253 return Use.getUser();
1254 }
1255 return NULL;
1256}
1257
1258/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1259/// This function recursively traverses up the operand chain, ignoring
1260/// certain nodes.
1261static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1262 SDNode *Root,
1263 SmallPtrSet<SDNode*, 16> &Visited) {
1264 if (Use->getNodeId() < Def->getNodeId() ||
1265 !Visited.insert(Use))
1266 return false;
1267
1268 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1269 SDNode *N = Use->getOperand(i).getNode();
1270 if (N == Def) {
1271 if (Use == ImmedUse || Use == Root)
1272 continue; // We are not looking for immediate use.
1273 assert(N != Root);
1274 return true;
1275 }
1276
1277 // Traverse up the operand chain.
1278 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
1279 return true;
1280 }
1281 return false;
1282}
1283
1284/// isNonImmUse - Start searching from Root up the DAG to check is Def can
1285/// be reached. Return true if that's the case. However, ignore direct uses
1286/// by ImmedUse (which would be U in the example illustrated in
1287/// IsLegalAndProfitableToFold) and by Root (which can happen in the store
1288/// case).
1289/// FIXME: to be really generic, we should allow direct use by any node
1290/// that is being folded. But realisticly since we only fold loads which
1291/// have one non-chain use, we only need to watch out for load/op/store
1292/// and load/op/cmp case where the root (store / cmp) may reach the load via
1293/// its chain operand.
1294static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
1295 SmallPtrSet<SDNode*, 16> Visited;
1296 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
1297}
1298
1299/// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
1300/// U can be folded during instruction selection that starts at Root and
1301/// folding N is profitable.
1302bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
1303 SDNode *Root) const {
1304 if (OptLevel == CodeGenOpt::None) return false;
1305
1306 // If Root use can somehow reach N through a path that that doesn't contain
1307 // U then folding N would create a cycle. e.g. In the following
1308 // diagram, Root can reach N through X. If N is folded into into Root, then
1309 // X is both a predecessor and a successor of U.
1310 //
1311 // [N*] //
1312 // ^ ^ //
1313 // / \ //
1314 // [U*] [X]? //
1315 // ^ ^ //
1316 // \ / //
1317 // \ / //
1318 // [Root*] //
1319 //
1320 // * indicates nodes to be folded together.
1321 //
1322 // If Root produces a flag, then it gets (even more) interesting. Since it
1323 // will be "glued" together with its flag use in the scheduler, we need to
1324 // check if it might reach N.
1325 //
1326 // [N*] //
1327 // ^ ^ //
1328 // / \ //
1329 // [U*] [X]? //
1330 // ^ ^ //
1331 // \ \ //
1332 // \ | //
1333 // [Root*] | //
1334 // ^ | //
1335 // f | //
1336 // | / //
1337 // [Y] / //
1338 // ^ / //
1339 // f / //
1340 // | / //
1341 // [FU] //
1342 //
1343 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1344 // (call it Fold), then X is a predecessor of FU and a successor of
1345 // Fold. But since Fold and FU are flagged together, this will create
1346 // a cycle in the scheduling graph.
1347
1348 MVT VT = Root->getValueType(Root->getNumValues()-1);
1349 while (VT == MVT::Flag) {
1350 SDNode *FU = findFlagUse(Root);
1351 if (FU == NULL)
1352 break;
1353 Root = FU;
1354 VT = Root->getValueType(Root->getNumValues()-1);
1355 }
1356
1357 return !isNonImmUse(Root, N, U);
1358}
1359
1360
Devang Patel19974732007-05-03 01:11:54 +00001361char SelectionDAGISel::ID = 0;