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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f945d09d53a4f2f392b8b51191d37de2f8acd566 / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: e0bec04e64fbeb466ced786a476f52c0d33031b8 [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topper79aa3412012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoonc635ebd2012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]19#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
Jyotsna Vermaf945d092013-05-02 15:39:30 +0000[diff] [blame^]21#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget& Subtarget;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]31 typedef unsigned Opcode_t;
32
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]33public:
34 explicit HexagonInstrInfo(HexagonSubtarget &ST);
35
36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
37 /// such, whenever a client has an instance of instruction info, it should
38 /// always be able to get register info as well (through this method).
39 ///
40 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
41
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
48 int &FrameIndex) const;
49
50 /// isStoreToStackSlot - If the specified machine instruction is a direct
51 /// store to a stack slot, return the virtual or physical register number of
52 /// the source reg along with the FrameIndex of the loaded stack slot. If
53 /// not, return 0. This predicate must return 0 if the instruction has
54 /// any side effects other than storing to the stack slot.
55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
56 int &FrameIndex) const;
57
58
59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
60 MachineBasicBlock *&FBB,
61 SmallVectorImpl<MachineOperand> &Cond,
62 bool AllowModify) const;
63
64 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
65
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
69 DebugLoc DL) const;
70
Krzysztof Parzyszekce55d912013-02-11 20:04:29 +0000[diff] [blame]71 virtual bool analyzeCompare(const MachineInstr *MI,
72 unsigned &SrcReg, unsigned &SrcReg2,
73 int &Mask, int &Value) const;
74
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]75 virtual void copyPhysReg(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I, DebugLoc DL,
77 unsigned DestReg, unsigned SrcReg,
78 bool KillSrc) const;
79
80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MBBI,
82 unsigned SrcReg, bool isKill, int FrameIndex,
83 const TargetRegisterClass *RC,
84 const TargetRegisterInfo *TRI) const;
85
86 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
87 SmallVectorImpl<MachineOperand> &Addr,
88 const TargetRegisterClass *RC,
89 SmallVectorImpl<MachineInstr*> &NewMIs) const;
90
91 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MBBI,
93 unsigned DestReg, int FrameIndex,
94 const TargetRegisterClass *RC,
95 const TargetRegisterInfo *TRI) const;
96
97 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
98 SmallVectorImpl<MachineOperand> &Addr,
99 const TargetRegisterClass *RC,
100 SmallVectorImpl<MachineInstr*> &NewMIs) const;
101
102 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
103 MachineInstr* MI,
104 const SmallVectorImpl<unsigned> &Ops,
105 int FrameIndex) const;
106
107 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
108 MachineInstr* MI,
109 const SmallVectorImpl<unsigned> &Ops,
110 MachineInstr* LoadMI) const {
111 return 0;
112 }
113
114 unsigned createVR(MachineFunction* MF, MVT VT) const;
115
116 virtual bool isPredicable(MachineInstr *MI) const;
117 virtual bool
118 PredicateInstruction(MachineInstr *MI,
119 const SmallVectorImpl<MachineOperand> &Cond) const;
120
Kay Tiong Khoo575e90e2012-06-13 15:53:04 +0000[diff] [blame]121 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]122 unsigned ExtraPredCycles,
123 const BranchProbability &Probability) const;
124
125 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
126 unsigned NumTCycles, unsigned ExtraTCycles,
127 MachineBasicBlock &FMBB,
128 unsigned NumFCycles, unsigned ExtraFCycles,
129 const BranchProbability &Probability) const;
130
131 virtual bool isPredicated(const MachineInstr *MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]132 virtual bool isPredicatedNew(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]133 virtual bool DefinesPredicate(MachineInstr *MI,
134 std::vector<MachineOperand> &Pred) const;
135 virtual bool
136 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
137 const SmallVectorImpl<MachineOperand> &Pred2) const;
138
139 virtual bool
140 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
141
142 virtual bool
143 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
144 const BranchProbability &Probability) const;
145
Jyotsna Verma2a885552013-03-29 21:09:53 +0000[diff] [blame]146 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
147 int FrameIx,
148 uint64_t Offset,
149 const MDNode *MDPtr,
150 DebugLoc DL) const;
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame]151 virtual DFAPacketizer*
152 CreateTargetScheduleState(const TargetMachine *TM,
153 const ScheduleDAG *DAG) const;
154
155 virtual bool isSchedulingBoundary(const MachineInstr *MI,
156 const MachineBasicBlock *MBB,
157 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]158 bool isValidOffset(const int Opcode, const int Offset) const;
159 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
160 bool isMemOp(const MachineInstr *MI) const;
161 bool isSpillPredRegOp(const MachineInstr *MI) const;
162 bool isU6_3Immediate(const int value) const;
163 bool isU6_2Immediate(const int value) const;
164 bool isU6_1Immediate(const int value) const;
165 bool isU6_0Immediate(const int value) const;
166 bool isS4_3Immediate(const int value) const;
167 bool isS4_2Immediate(const int value) const;
168 bool isS4_1Immediate(const int value) const;
169 bool isS4_0Immediate(const int value) const;
170 bool isS12_Immediate(const int value) const;
171 bool isU6_Immediate(const int value) const;
172 bool isS8_Immediate(const int value) const;
173 bool isS6_Immediate(const int value) const;
174
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]175 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
176 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]177 bool isConditionalALU32 (const MachineInstr* MI) const;
178 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]179 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Verma9feabc22013-03-05 18:51:42 +0000[diff] [blame]180 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma810848d2013-03-28 19:44:04 +0000[diff] [blame]181 bool isDotNewInst(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]182 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruthd410eab2012-04-23 18:25:57 +0000[diff] [blame]183 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pande26f61a12012-05-03 21:52:53 +0000[diff] [blame]184 bool isExtendable(const MachineInstr* MI) const;
185 bool isExtended(const MachineInstr* MI) const;
186 bool isPostIncrement(const MachineInstr* MI) const;
187 bool isNewValueStore(const MachineInstr* MI) const;
188 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pandeb3385702012-05-12 05:10:30 +0000[diff] [blame]189 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]190
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]191
192 void immediateExtend(MachineInstr *MI) const;
193 bool isConstExtended(MachineInstr *MI) const;
Jyotsna Vermaf945d092013-05-02 15:39:30 +0000[diff] [blame^]194 int getDotNewPredJumpOp(MachineInstr *MI,
195 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Vermaef94c6c2013-03-01 17:37:13 +0000[diff] [blame]196 unsigned getAddrMode(const MachineInstr* MI) const;
197 bool isOperandExtended(const MachineInstr *MI,
198 unsigned short OperandNum) const;
199 unsigned short getCExtOpNum(const MachineInstr *MI) const;
200 int getMinValue(const MachineInstr *MI) const;
201 int getMaxValue(const MachineInstr *MI) const;
202 bool NonExtEquivalentExists (const MachineInstr *MI) const;
203 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +0000[diff] [blame]204 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
205 bool PredOpcodeHasNot(Opcode_t Opcode) const;
206
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]207private:
208 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
209
210};
211
212}
213
214#endif