Ben Murdoch | 8b112d2 | 2011-06-08 16:22:53 +0100 | [diff] [blame] | 1 | // Copyright 2011 the V8 project authors. All rights reserved. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 4 | |
| 5 | #ifndef V8_ARM_CONSTANTS_ARM_H_ |
| 6 | #define V8_ARM_CONSTANTS_ARM_H_ |
| 7 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 8 | #include <stdint.h> |
| 9 | |
| 10 | #include "src/base/logging.h" |
| 11 | #include "src/base/macros.h" |
| 12 | #include "src/globals.h" |
| 13 | |
Ben Murdoch | 8b112d2 | 2011-06-08 16:22:53 +0100 | [diff] [blame] | 14 | // ARM EABI is required. |
| 15 | #if defined(__arm__) && !defined(__ARM_EABI__) |
| 16 | #error ARM EABI support is required. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 17 | #endif |
| 18 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 19 | namespace v8 { |
| 20 | namespace internal { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 21 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 22 | // Constant pool marker. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 23 | // Use UDF, the permanently undefined instruction. |
| 24 | const int kConstantPoolMarkerMask = 0xfff000f0; |
| 25 | const int kConstantPoolMarker = 0xe7f000f0; |
| 26 | const int kConstantPoolLengthMaxMask = 0xffff; |
| 27 | inline int EncodeConstantPoolLength(int length) { |
| 28 | DCHECK((length & kConstantPoolLengthMaxMask) == length); |
| 29 | return ((length & 0xfff0) << 4) | (length & 0xf); |
| 30 | } |
| 31 | inline int DecodeConstantPoolLength(int instr) { |
| 32 | DCHECK((instr & kConstantPoolMarkerMask) == kConstantPoolMarker); |
| 33 | return ((instr >> 4) & 0xfff0) | (instr & 0xf); |
| 34 | } |
| 35 | |
| 36 | // Used in code age prologue - ldr(pc, MemOperand(pc, -4)) |
| 37 | const int kCodeAgeJumpInstruction = 0xe51ff004; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 38 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 39 | // Number of registers in normal ARM mode. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 40 | const int kNumRegisters = 16; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 41 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 42 | // VFP support. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 43 | const int kNumVFPSingleRegisters = 32; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 44 | const int kNumVFPDoubleRegisters = 32; |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 45 | const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 46 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 47 | // PC is register 15. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 48 | const int kPCRegister = 15; |
| 49 | const int kNoRegister = -1; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 50 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 51 | // Used in embedded constant pool builder - max reach in bits for |
| 52 | // various load instructions (unsigned) |
| 53 | const int kLdrMaxReachBits = 12; |
| 54 | const int kVldrMaxReachBits = 10; |
| 55 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 56 | // ----------------------------------------------------------------------------- |
| 57 | // Conditions. |
| 58 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 59 | // Defines constants and accessor classes to assemble, disassemble and |
| 60 | // simulate ARM instructions. |
| 61 | // |
| 62 | // Section references in the code refer to the "ARM Architecture Reference |
| 63 | // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) |
| 64 | // |
| 65 | // Constants for specific fields are defined in their respective named enums. |
| 66 | // General constants are in an anonymous enum in class Instr. |
| 67 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 68 | // Values for the condition field as defined in section A3.2 |
| 69 | enum Condition { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 70 | kNoCondition = -1, |
| 71 | |
| 72 | eq = 0 << 28, // Z set Equal. |
| 73 | ne = 1 << 28, // Z clear Not equal. |
| 74 | cs = 2 << 28, // C set Unsigned higher or same. |
| 75 | cc = 3 << 28, // C clear Unsigned lower. |
| 76 | mi = 4 << 28, // N set Negative. |
| 77 | pl = 5 << 28, // N clear Positive or zero. |
| 78 | vs = 6 << 28, // V set Overflow. |
| 79 | vc = 7 << 28, // V clear No overflow. |
| 80 | hi = 8 << 28, // C set, Z clear Unsigned higher. |
| 81 | ls = 9 << 28, // C clear or Z set Unsigned lower or same. |
| 82 | ge = 10 << 28, // N == V Greater or equal. |
| 83 | lt = 11 << 28, // N != V Less than. |
| 84 | gt = 12 << 28, // Z clear, N == V Greater than. |
| 85 | le = 13 << 28, // Z set or N != V Less then or equal |
| 86 | al = 14 << 28, // Always. |
| 87 | |
| 88 | kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). |
| 89 | kNumberOfConditions = 16, |
| 90 | |
| 91 | // Aliases. |
| 92 | hs = cs, // C set Unsigned higher or same. |
| 93 | lo = cc // C clear Unsigned lower. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 94 | }; |
| 95 | |
| 96 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 97 | inline Condition NegateCondition(Condition cond) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 98 | DCHECK(cond != al); |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 99 | return static_cast<Condition>(cond ^ ne); |
| 100 | } |
| 101 | |
| 102 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 103 | // Commute a condition such that {a cond b == b cond' a}. |
| 104 | inline Condition CommuteCondition(Condition cond) { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 105 | switch (cond) { |
| 106 | case lo: |
| 107 | return hi; |
| 108 | case hi: |
| 109 | return lo; |
| 110 | case hs: |
| 111 | return ls; |
| 112 | case ls: |
| 113 | return hs; |
| 114 | case lt: |
| 115 | return gt; |
| 116 | case gt: |
| 117 | return lt; |
| 118 | case ge: |
| 119 | return le; |
| 120 | case le: |
| 121 | return ge; |
| 122 | default: |
| 123 | return cond; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 124 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | |
| 128 | // ----------------------------------------------------------------------------- |
| 129 | // Instructions encoding. |
| 130 | |
| 131 | // Instr is merely used by the Assembler to distinguish 32bit integers |
| 132 | // representing instructions from usual 32 bit values. |
| 133 | // Instruction objects are pointers to 32bit values, and provide methods to |
| 134 | // access the various ISA fields. |
| 135 | typedef int32_t Instr; |
| 136 | |
| 137 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 138 | // Opcodes for Data-processing instructions (instructions with a type 0 and 1) |
| 139 | // as defined in section A3.4 |
| 140 | enum Opcode { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 141 | AND = 0 << 21, // Logical AND. |
| 142 | EOR = 1 << 21, // Logical Exclusive OR. |
| 143 | SUB = 2 << 21, // Subtract. |
| 144 | RSB = 3 << 21, // Reverse Subtract. |
| 145 | ADD = 4 << 21, // Add. |
| 146 | ADC = 5 << 21, // Add with Carry. |
| 147 | SBC = 6 << 21, // Subtract with Carry. |
| 148 | RSC = 7 << 21, // Reverse Subtract with Carry. |
| 149 | TST = 8 << 21, // Test. |
| 150 | TEQ = 9 << 21, // Test Equivalence. |
| 151 | CMP = 10 << 21, // Compare. |
| 152 | CMN = 11 << 21, // Compare Negated. |
| 153 | ORR = 12 << 21, // Logical (inclusive) OR. |
| 154 | MOV = 13 << 21, // Move. |
| 155 | BIC = 14 << 21, // Bit Clear. |
| 156 | MVN = 15 << 21 // Move Not. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 160 | // The bits for bit 7-4 for some type 0 miscellaneous instructions. |
| 161 | enum MiscInstructionsBits74 { |
| 162 | // With bits 22-21 01. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 163 | BX = 1 << 4, |
| 164 | BXJ = 2 << 4, |
| 165 | BLX = 3 << 4, |
| 166 | BKPT = 7 << 4, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 167 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 168 | // With bits 22-21 11. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 169 | CLZ = 1 << 4 |
| 170 | }; |
| 171 | |
| 172 | |
| 173 | // Instruction encoding bits and masks. |
| 174 | enum { |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 175 | H = 1 << 5, // Halfword (or byte). |
| 176 | S6 = 1 << 6, // Signed (or unsigned). |
| 177 | L = 1 << 20, // Load (or store). |
| 178 | S = 1 << 20, // Set condition code (or leave unchanged). |
| 179 | W = 1 << 21, // Writeback base register (or leave unchanged). |
| 180 | A = 1 << 21, // Accumulate in multiply instruction (or not). |
| 181 | B = 1 << 22, // Unsigned byte (or word). |
| 182 | N = 1 << 22, // Long (or short). |
| 183 | U = 1 << 23, // Positive (or negative) offset/index. |
| 184 | P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). |
| 185 | I = 1 << 25, // Immediate shifter operand (or not). |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 186 | B0 = 1 << 0, |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 187 | B4 = 1 << 4, |
| 188 | B5 = 1 << 5, |
| 189 | B6 = 1 << 6, |
| 190 | B7 = 1 << 7, |
| 191 | B8 = 1 << 8, |
| 192 | B9 = 1 << 9, |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 193 | B12 = 1 << 12, |
| 194 | B16 = 1 << 16, |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 195 | B17 = 1 << 17, |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 196 | B18 = 1 << 18, |
| 197 | B19 = 1 << 19, |
| 198 | B20 = 1 << 20, |
| 199 | B21 = 1 << 21, |
| 200 | B22 = 1 << 22, |
| 201 | B23 = 1 << 23, |
| 202 | B24 = 1 << 24, |
| 203 | B25 = 1 << 25, |
| 204 | B26 = 1 << 26, |
| 205 | B27 = 1 << 27, |
| 206 | B28 = 1 << 28, |
| 207 | |
| 208 | // Instruction bit masks. |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 209 | kCondMask = 15 << 28, |
| 210 | kALUMask = 0x6f << 21, |
| 211 | kRdMask = 15 << 12, // In str instruction. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 212 | kCoprocessorMask = 15 << 8, |
| 213 | kOpCodeMask = 15 << 21, // In data-processing instructions. |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 214 | kImm24Mask = (1 << 24) - 1, |
| 215 | kImm16Mask = (1 << 16) - 1, |
| 216 | kImm8Mask = (1 << 8) - 1, |
| 217 | kOff12Mask = (1 << 12) - 1, |
| 218 | kOff8Mask = (1 << 8) - 1 |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 222 | enum BarrierOption { |
| 223 | OSHLD = 0x1, |
| 224 | OSHST = 0x2, |
| 225 | OSH = 0x3, |
| 226 | NSHLD = 0x5, |
| 227 | NSHST = 0x6, |
| 228 | NSH = 0x7, |
| 229 | ISHLD = 0x9, |
| 230 | ISHST = 0xa, |
| 231 | ISH = 0xb, |
| 232 | LD = 0xd, |
| 233 | ST = 0xe, |
| 234 | SY = 0xf, |
| 235 | }; |
| 236 | |
| 237 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 238 | // ----------------------------------------------------------------------------- |
| 239 | // Addressing modes and instruction variants. |
| 240 | |
| 241 | // Condition code updating mode. |
| 242 | enum SBit { |
| 243 | SetCC = 1 << 20, // Set condition code. |
| 244 | LeaveCC = 0 << 20 // Leave condition code unchanged. |
| 245 | }; |
| 246 | |
| 247 | |
| 248 | // Status register selection. |
| 249 | enum SRegister { |
| 250 | CPSR = 0 << 22, |
| 251 | SPSR = 1 << 22 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 255 | // Shifter types for Data-processing operands as defined in section A5.1.2. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 256 | enum ShiftOp { |
| 257 | LSL = 0 << 5, // Logical shift left. |
| 258 | LSR = 1 << 5, // Logical shift right. |
| 259 | ASR = 2 << 5, // Arithmetic shift right. |
| 260 | ROR = 3 << 5, // Rotate right. |
| 261 | |
| 262 | // RRX is encoded as ROR with shift_imm == 0. |
| 263 | // Use a special code to make the distinction. The RRX ShiftOp is only used |
| 264 | // as an argument, and will never actually be encoded. The Assembler will |
| 265 | // detect it and emit the correct ROR shift operand with shift_imm == 0. |
| 266 | RRX = -1, |
| 267 | kNumberOfShifts = 4 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 268 | }; |
| 269 | |
| 270 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 271 | // Status register fields. |
| 272 | enum SRegisterField { |
| 273 | CPSR_c = CPSR | 1 << 16, |
| 274 | CPSR_x = CPSR | 1 << 17, |
| 275 | CPSR_s = CPSR | 1 << 18, |
| 276 | CPSR_f = CPSR | 1 << 19, |
| 277 | SPSR_c = SPSR | 1 << 16, |
| 278 | SPSR_x = SPSR | 1 << 17, |
| 279 | SPSR_s = SPSR | 1 << 18, |
| 280 | SPSR_f = SPSR | 1 << 19 |
| 281 | }; |
| 282 | |
| 283 | // Status register field mask (or'ed SRegisterField enum values). |
| 284 | typedef uint32_t SRegisterFieldMask; |
| 285 | |
| 286 | |
| 287 | // Memory operand addressing mode. |
| 288 | enum AddrMode { |
| 289 | // Bit encoding P U W. |
| 290 | Offset = (8|4|0) << 21, // Offset (without writeback to base). |
| 291 | PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. |
| 292 | PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. |
| 293 | NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). |
| 294 | NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. |
| 295 | NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. |
| 296 | }; |
| 297 | |
| 298 | |
| 299 | // Load/store multiple addressing mode. |
| 300 | enum BlockAddrMode { |
| 301 | // Bit encoding P U W . |
| 302 | da = (0|0|0) << 21, // Decrement after. |
| 303 | ia = (0|4|0) << 21, // Increment after. |
| 304 | db = (8|0|0) << 21, // Decrement before. |
| 305 | ib = (8|4|0) << 21, // Increment before. |
| 306 | da_w = (0|0|1) << 21, // Decrement after with writeback to base. |
| 307 | ia_w = (0|4|1) << 21, // Increment after with writeback to base. |
| 308 | db_w = (8|0|1) << 21, // Decrement before with writeback to base. |
| 309 | ib_w = (8|4|1) << 21, // Increment before with writeback to base. |
| 310 | |
| 311 | // Alias modes for comparison when writeback does not matter. |
| 312 | da_x = (0|0|0) << 21, // Decrement after. |
| 313 | ia_x = (0|4|0) << 21, // Increment after. |
| 314 | db_x = (8|0|0) << 21, // Decrement before. |
Ben Murdoch | 8b112d2 | 2011-06-08 16:22:53 +0100 | [diff] [blame] | 315 | ib_x = (8|4|0) << 21, // Increment before. |
| 316 | |
| 317 | kBlockAddrModeMask = (8|4|1) << 21 |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | |
| 321 | // Coprocessor load/store operand size. |
| 322 | enum LFlag { |
| 323 | Long = 1 << 22, // Long load/store coprocessor. |
| 324 | Short = 0 << 22 // Short load/store coprocessor. |
| 325 | }; |
| 326 | |
| 327 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 328 | // NEON data type |
| 329 | enum NeonDataType { |
| 330 | NeonS8 = 0x1, // U = 0, imm3 = 0b001 |
| 331 | NeonS16 = 0x2, // U = 0, imm3 = 0b010 |
| 332 | NeonS32 = 0x4, // U = 0, imm3 = 0b100 |
| 333 | NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001 |
| 334 | NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010 |
| 335 | NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100 |
| 336 | NeonDataTypeSizeMask = 0x7, |
| 337 | NeonDataTypeUMask = 1 << 24 |
| 338 | }; |
| 339 | |
| 340 | enum NeonListType { |
| 341 | nlt_1 = 0x7, |
| 342 | nlt_2 = 0xA, |
| 343 | nlt_3 = 0x6, |
| 344 | nlt_4 = 0x2 |
| 345 | }; |
| 346 | |
| 347 | enum NeonSize { |
| 348 | Neon8 = 0x0, |
| 349 | Neon16 = 0x1, |
| 350 | Neon32 = 0x2, |
| 351 | Neon64 = 0x3 |
| 352 | }; |
| 353 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 354 | // ----------------------------------------------------------------------------- |
| 355 | // Supervisor Call (svc) specific support. |
| 356 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 357 | // Special Software Interrupt codes when used in the presence of the ARM |
| 358 | // simulator. |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 359 | // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for |
| 360 | // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 361 | enum SoftwareInterruptCodes { |
| 362 | // transition to C code |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 363 | kCallRtRedirected = 0x10, |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 364 | // break point |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 365 | kBreakpoint = 0x20, |
Teng-Hui Zhu | 3e5fa29 | 2010-11-09 16:16:48 -0800 | [diff] [blame] | 366 | // stop |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 367 | kStopCode = 1 << 23 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 368 | }; |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 369 | const uint32_t kStopCodeMask = kStopCode - 1; |
| 370 | const uint32_t kMaxStopCode = kStopCode - 1; |
| 371 | const int32_t kDefaultStopCode = -1; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 372 | |
| 373 | |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 374 | // Type of VFP register. Determines register encoding. |
| 375 | enum VFPRegPrecision { |
| 376 | kSinglePrecision = 0, |
| 377 | kDoublePrecision = 1 |
| 378 | }; |
| 379 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 380 | |
| 381 | // VFP FPSCR constants. |
| 382 | enum VFPConversionMode { |
| 383 | kFPSCRRounding = 0, |
| 384 | kDefaultRoundToZero = 1 |
Russell Brenner | 90bac25 | 2010-11-18 13:33:46 -0800 | [diff] [blame] | 385 | }; |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 386 | |
Ben Murdoch | e0cee9b | 2011-05-25 10:26:03 +0100 | [diff] [blame] | 387 | // This mask does not include the "inexact" or "input denormal" cumulative |
| 388 | // exceptions flags, because we usually don't want to check for it. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 389 | const uint32_t kVFPExceptionMask = 0xf; |
| 390 | const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; |
| 391 | const uint32_t kVFPOverflowExceptionBit = 1 << 2; |
| 392 | const uint32_t kVFPUnderflowExceptionBit = 1 << 3; |
| 393 | const uint32_t kVFPInexactExceptionBit = 1 << 4; |
| 394 | const uint32_t kVFPFlushToZeroMask = 1 << 24; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 395 | const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 396 | |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 397 | const uint32_t kVFPNConditionFlagBit = 1 << 31; |
| 398 | const uint32_t kVFPZConditionFlagBit = 1 << 30; |
| 399 | const uint32_t kVFPCConditionFlagBit = 1 << 29; |
| 400 | const uint32_t kVFPVConditionFlagBit = 1 << 28; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 401 | |
| 402 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 403 | // VFP rounding modes. See ARM DDI 0406B Page A2-29. |
| 404 | enum VFPRoundingMode { |
| 405 | RN = 0 << 22, // Round to Nearest. |
| 406 | RP = 1 << 22, // Round towards Plus Infinity. |
| 407 | RM = 2 << 22, // Round towards Minus Infinity. |
| 408 | RZ = 3 << 22, // Round towards zero. |
| 409 | |
| 410 | // Aliases. |
| 411 | kRoundToNearest = RN, |
| 412 | kRoundToPlusInf = RP, |
| 413 | kRoundToMinusInf = RM, |
| 414 | kRoundToZero = RZ |
| 415 | }; |
| 416 | |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 417 | const uint32_t kVFPRoundingModeMask = 3 << 22; |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 418 | |
Ben Murdoch | e0cee9b | 2011-05-25 10:26:03 +0100 | [diff] [blame] | 419 | enum CheckForInexactConversion { |
| 420 | kCheckForInexactConversion, |
| 421 | kDontCheckForInexactConversion |
| 422 | }; |
| 423 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 424 | // ----------------------------------------------------------------------------- |
| 425 | // Hints. |
| 426 | |
| 427 | // Branch hints are not used on the ARM. They are defined so that they can |
| 428 | // appear in shared function signatures, but will be ignored in ARM |
| 429 | // implementations. |
| 430 | enum Hint { no_hint }; |
| 431 | |
| 432 | // Hints are not used on the arm. Negating is trivial. |
| 433 | inline Hint NegateHint(Hint ignored) { return no_hint; } |
| 434 | |
| 435 | |
| 436 | // ----------------------------------------------------------------------------- |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 437 | // Instruction abstraction. |
| 438 | |
| 439 | // The class Instruction enables access to individual fields defined in the ARM |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 440 | // architecture instruction set encoding as described in figure A3-1. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 441 | // Note that the Assembler uses typedef int32_t Instr. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 442 | // |
| 443 | // Example: Test whether the instruction at ptr does set the condition code |
| 444 | // bits. |
| 445 | // |
| 446 | // bool InstructionSetsConditionCodes(byte* ptr) { |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 447 | // Instruction* instr = Instruction::At(ptr); |
| 448 | // int type = instr->TypeValue(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 449 | // return ((type == 0) || (type == 1)) && instr->HasS(); |
| 450 | // } |
| 451 | // |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 452 | class Instruction { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 453 | public: |
| 454 | enum { |
| 455 | kInstrSize = 4, |
| 456 | kInstrSizeLog2 = 2, |
| 457 | kPCReadOffset = 8 |
| 458 | }; |
| 459 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 460 | // Helper macro to define static accessors. |
| 461 | // We use the cast to char* trick to bypass the strict anti-aliasing rules. |
| 462 | #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ |
| 463 | static inline return_type Name(Instr instr) { \ |
| 464 | char* temp = reinterpret_cast<char*>(&instr); \ |
| 465 | return reinterpret_cast<Instruction*>(temp)->Name(); \ |
| 466 | } |
| 467 | |
| 468 | #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) |
| 469 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 470 | // Get the raw instruction bits. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 471 | inline Instr InstructionBits() const { |
| 472 | return *reinterpret_cast<const Instr*>(this); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | // Set the raw instruction bits to value. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 476 | inline void SetInstructionBits(Instr value) { |
| 477 | *reinterpret_cast<Instr*>(this) = value; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 478 | } |
| 479 | |
| 480 | // Read one particular bit out of the instruction bits. |
| 481 | inline int Bit(int nr) const { |
| 482 | return (InstructionBits() >> nr) & 1; |
| 483 | } |
| 484 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 485 | // Read a bit field's value out of the instruction bits. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 486 | inline int Bits(int hi, int lo) const { |
| 487 | return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); |
| 488 | } |
| 489 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 490 | // Read a bit field out of the instruction bits. |
| 491 | inline int BitField(int hi, int lo) const { |
| 492 | return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); |
| 493 | } |
| 494 | |
| 495 | // Static support. |
| 496 | |
| 497 | // Read one particular bit out of the instruction bits. |
| 498 | static inline int Bit(Instr instr, int nr) { |
| 499 | return (instr >> nr) & 1; |
| 500 | } |
| 501 | |
| 502 | // Read the value of a bit field out of the instruction bits. |
| 503 | static inline int Bits(Instr instr, int hi, int lo) { |
| 504 | return (instr >> lo) & ((2 << (hi - lo)) - 1); |
| 505 | } |
| 506 | |
| 507 | |
| 508 | // Read a bit field out of the instruction bits. |
| 509 | static inline int BitField(Instr instr, int hi, int lo) { |
| 510 | return instr & (((2 << (hi - lo)) - 1) << lo); |
| 511 | } |
| 512 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 513 | |
| 514 | // Accessors for the different named fields used in the ARM encoding. |
| 515 | // The naming of these accessor corresponds to figure A3-1. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 516 | // |
| 517 | // Two kind of accessors are declared: |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 518 | // - <Name>Field() will return the raw field, i.e. the field's bits at their |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 519 | // original place in the instruction encoding. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 520 | // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as |
| 521 | // 0xC0810002 ConditionField(instr) will return 0xC0000000. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 522 | // - <Name>Value() will return the field value, shifted back to bit 0. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 523 | // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as |
| 524 | // 0xC0810002 ConditionField(instr) will return 0xC. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 525 | |
| 526 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 527 | // Generally applicable fields |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 528 | inline Condition ConditionValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 529 | return static_cast<Condition>(Bits(31, 28)); |
| 530 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 531 | inline Condition ConditionField() const { |
| 532 | return static_cast<Condition>(BitField(31, 28)); |
| 533 | } |
| 534 | DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); |
| 535 | DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 536 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 537 | inline int TypeValue() const { return Bits(27, 25); } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 538 | inline int SpecialValue() const { return Bits(27, 23); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 539 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 540 | inline int RnValue() const { return Bits(19, 16); } |
| 541 | DECLARE_STATIC_ACCESSOR(RnValue); |
| 542 | inline int RdValue() const { return Bits(15, 12); } |
| 543 | DECLARE_STATIC_ACCESSOR(RdValue); |
| 544 | |
| 545 | inline int CoprocessorValue() const { return Bits(11, 8); } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 546 | // Support for VFP. |
| 547 | // Vn(19-16) | Vd(15-12) | Vm(3-0) |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 548 | inline int VnValue() const { return Bits(19, 16); } |
| 549 | inline int VmValue() const { return Bits(3, 0); } |
| 550 | inline int VdValue() const { return Bits(15, 12); } |
| 551 | inline int NValue() const { return Bit(7); } |
| 552 | inline int MValue() const { return Bit(5); } |
| 553 | inline int DValue() const { return Bit(22); } |
| 554 | inline int RtValue() const { return Bits(15, 12); } |
| 555 | inline int PValue() const { return Bit(24); } |
| 556 | inline int UValue() const { return Bit(23); } |
| 557 | inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } |
| 558 | inline int Opc2Value() const { return Bits(19, 16); } |
| 559 | inline int Opc3Value() const { return Bits(7, 6); } |
| 560 | inline int SzValue() const { return Bit(8); } |
| 561 | inline int VLValue() const { return Bit(20); } |
| 562 | inline int VCValue() const { return Bit(8); } |
| 563 | inline int VAValue() const { return Bits(23, 21); } |
| 564 | inline int VBValue() const { return Bits(6, 5); } |
| 565 | inline int VFPNRegValue(VFPRegPrecision pre) { |
| 566 | return VFPGlueRegValue(pre, 16, 7); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 567 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 568 | inline int VFPMRegValue(VFPRegPrecision pre) { |
| 569 | return VFPGlueRegValue(pre, 0, 5); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 570 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 571 | inline int VFPDRegValue(VFPRegPrecision pre) { |
| 572 | return VFPGlueRegValue(pre, 12, 22); |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 573 | } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 574 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 575 | // Fields used in Data processing instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 576 | inline int OpcodeValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 577 | return static_cast<Opcode>(Bits(24, 21)); |
| 578 | } |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 579 | inline Opcode OpcodeField() const { |
| 580 | return static_cast<Opcode>(BitField(24, 21)); |
| 581 | } |
| 582 | inline int SValue() const { return Bit(20); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 583 | // with register |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 584 | inline int RmValue() const { return Bits(3, 0); } |
| 585 | DECLARE_STATIC_ACCESSOR(RmValue); |
| 586 | inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } |
| 587 | inline ShiftOp ShiftField() const { |
| 588 | return static_cast<ShiftOp>(BitField(6, 5)); |
| 589 | } |
| 590 | inline int RegShiftValue() const { return Bit(4); } |
| 591 | inline int RsValue() const { return Bits(11, 8); } |
| 592 | inline int ShiftAmountValue() const { return Bits(11, 7); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 593 | // with immediate |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 594 | inline int RotateValue() const { return Bits(11, 8); } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 595 | DECLARE_STATIC_ACCESSOR(RotateValue); |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 596 | inline int Immed8Value() const { return Bits(7, 0); } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 597 | DECLARE_STATIC_ACCESSOR(Immed8Value); |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 598 | inline int Immed4Value() const { return Bits(19, 16); } |
| 599 | inline int ImmedMovwMovtValue() const { |
| 600 | return Immed4Value() << 12 | Offset12Value(); } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 601 | DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 602 | |
| 603 | // Fields used in Load/Store instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 604 | inline int PUValue() const { return Bits(24, 23); } |
| 605 | inline int PUField() const { return BitField(24, 23); } |
| 606 | inline int BValue() const { return Bit(22); } |
| 607 | inline int WValue() const { return Bit(21); } |
| 608 | inline int LValue() const { return Bit(20); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 609 | // with register uses same fields as Data processing instructions above |
| 610 | // with immediate |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 611 | inline int Offset12Value() const { return Bits(11, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 612 | // multiple |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 613 | inline int RlistValue() const { return Bits(15, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 614 | // extra loads and stores |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 615 | inline int SignValue() const { return Bit(6); } |
| 616 | inline int HValue() const { return Bit(5); } |
| 617 | inline int ImmedHValue() const { return Bits(11, 8); } |
| 618 | inline int ImmedLValue() const { return Bits(3, 0); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 619 | |
| 620 | // Fields used in Branch instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 621 | inline int LinkValue() const { return Bit(24); } |
| 622 | inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 623 | |
| 624 | // Fields used in Software interrupt instructions |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 625 | inline SoftwareInterruptCodes SvcValue() const { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 626 | return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); |
| 627 | } |
| 628 | |
| 629 | // Test for special encodings of type 0 instructions (extra loads and stores, |
| 630 | // as well as multiplications). |
| 631 | inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } |
| 632 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 633 | // Test for miscellaneous instructions encodings of type 0 instructions. |
| 634 | inline bool IsMiscType0() const { return (Bit(24) == 1) |
| 635 | && (Bit(23) == 0) |
| 636 | && (Bit(20) == 0) |
| 637 | && ((Bit(7) == 0)); } |
| 638 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 639 | // Test for a nop instruction, which falls under type 1. |
| 640 | inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; } |
| 641 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 642 | // Test for a stop instruction. |
| 643 | inline bool IsStop() const { |
| 644 | return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); |
| 645 | } |
| 646 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 647 | // Special accessors that test for existence of a value. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 648 | inline bool HasS() const { return SValue() == 1; } |
| 649 | inline bool HasB() const { return BValue() == 1; } |
| 650 | inline bool HasW() const { return WValue() == 1; } |
| 651 | inline bool HasL() const { return LValue() == 1; } |
| 652 | inline bool HasU() const { return UValue() == 1; } |
| 653 | inline bool HasSign() const { return SignValue() == 1; } |
| 654 | inline bool HasH() const { return HValue() == 1; } |
| 655 | inline bool HasLink() const { return LinkValue() == 1; } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 656 | |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 657 | // Decode the double immediate from a vmov instruction. |
Ben Murdoch | 3bec4d2 | 2010-07-22 14:51:16 +0100 | [diff] [blame] | 658 | double DoubleImmedVmov() const; |
| 659 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 660 | // Instructions are read of out a code stream. The only way to get a |
| 661 | // reference to an instruction is to convert a pointer. There is no way |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 662 | // to allocate or create instances of class Instruction. |
| 663 | // Use the At(pc) function to create references to Instruction. |
| 664 | static Instruction* At(byte* pc) { |
| 665 | return reinterpret_cast<Instruction*>(pc); |
| 666 | } |
| 667 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 668 | |
| 669 | private: |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 670 | // Join split register codes, depending on single or double precision. |
| 671 | // four_bit is the position of the least-significant bit of the four |
| 672 | // bit specifier. one_bit is the position of the additional single bit |
| 673 | // specifier. |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 674 | inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { |
Kristian Monsen | 80d68ea | 2010-09-08 11:05:35 +0100 | [diff] [blame] | 675 | if (pre == kSinglePrecision) { |
| 676 | return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); |
| 677 | } |
| 678 | return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); |
| 679 | } |
| 680 | |
Steve Block | 1e0659c | 2011-05-24 12:43:12 +0100 | [diff] [blame] | 681 | // We need to prevent the creation of instances of class Instruction. |
| 682 | DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 683 | }; |
| 684 | |
| 685 | |
| 686 | // Helper functions for converting between register numbers and names. |
| 687 | class Registers { |
| 688 | public: |
| 689 | // Return the name of the register. |
| 690 | static const char* Name(int reg); |
| 691 | |
| 692 | // Lookup the register number for the name provided. |
| 693 | static int Number(const char* name); |
| 694 | |
| 695 | struct RegisterAlias { |
| 696 | int reg; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 697 | const char* name; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 698 | }; |
| 699 | |
| 700 | private: |
| 701 | static const char* names_[kNumRegisters]; |
| 702 | static const RegisterAlias aliases_[]; |
| 703 | }; |
| 704 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 705 | // Helper functions for converting between VFP register numbers and names. |
| 706 | class VFPRegisters { |
| 707 | public: |
| 708 | // Return the name of the register. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 709 | static const char* Name(int reg, bool is_double); |
| 710 | |
| 711 | // Lookup the register number for the name provided. |
| 712 | // Set flag pointed by is_double to true if register |
| 713 | // is double-precision. |
| 714 | static int Number(const char* name, bool* is_double); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 715 | |
| 716 | private: |
| 717 | static const char* names_[kNumVFPRegisters]; |
| 718 | }; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 719 | |
| 720 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 721 | } // namespace internal |
| 722 | } // namespace v8 |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 723 | |
| 724 | #endif // V8_ARM_CONSTANTS_ARM_H_ |