Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <mipi_dsi.h> |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 32 | #include <mdp5.h> |
| 33 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 34 | #include <platform/iomap.h> |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 35 | #include <arch/defines.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 36 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 37 | #if (DISPLAY_TYPE_MDSS == 0) |
| 38 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 39 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 40 | #endif |
| 41 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 42 | #define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4 |
| 43 | #define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140 |
| 44 | #define MMSS_DSI_PHY_CTRL_0 0x0170 |
| 45 | #define MMSS_DSI_PHY_CTRL_1 0x0174 |
| 46 | #define MMSS_DSI_PHY_CTRL_2 0x0178 |
| 47 | #define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184 |
| 48 | #define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188 |
| 49 | #define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4 |
| 50 | #define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4 |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 51 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_0 0x00 |
| 52 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_1 0x04 |
| 53 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_2 0x08 |
| 54 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_3 0x0c |
| 55 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_4 0x10 |
| 56 | #define MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x18 |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 57 | #define MMSS_DSI_PHY_LDO_CTRL 0x01dc |
| 58 | |
| 59 | #define TOTAL_TIMING_CTRL_CONFIG 12 |
| 60 | #define TOTAL_BIST_CTRL_CONFIG 6 |
| 61 | /* 4 data lanes and 1 clock lanes */ |
| 62 | #define TOTAL_LANE_COUNT 5 |
| 63 | #define CONFIG_REG_FOR_EACH_LANE 9 |
| 64 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 65 | static void mipi_dsi_calibration(uint32_t ctl_base) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 66 | { |
| 67 | uint32_t i = 0; |
| 68 | uint32_t term_cnt = 5000; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 69 | int32_t cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 70 | |
| 71 | /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 72 | writel(0x01, ctl_base + 0x0518); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 73 | |
| 74 | /* DSI1_DSIPHY_CAL_SW_CFG2 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 75 | writel(0x0, ctl_base + 0x0534); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 76 | /* DSI1_DSIPHY_CAL_HW_CFG1 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 77 | writel(0x5a, ctl_base + 0x053c); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 78 | /* DSI1_DSIPHY_CAL_HW_CFG3 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 79 | writel(0x10, ctl_base + 0x0544); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 80 | /* DSI1_DSIPHY_CAL_HW_CFG4 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 81 | writel(0x01, ctl_base + 0x0548); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 82 | /* DSI1_DSIPHY_CAL_HW_CFG0 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 83 | writel(0x01, ctl_base + 0x0538); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 84 | |
| 85 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 86 | writel(0x01, ctl_base + 0x0528); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 87 | |
| 88 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 89 | writel(0x00, ctl_base + 0x0528); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 90 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 91 | cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 92 | while (cal_busy & 0x10) { |
| 93 | i++; |
| 94 | if (i > term_cnt) { |
| 95 | dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY," |
| 96 | "exceeded polling TIMEOUT!\n"); |
| 97 | break; |
| 98 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 99 | cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 100 | } |
| 101 | } |
| 102 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 103 | #if (DISPLAY_TYPE_MDSS == 0) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 104 | int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo) |
| 105 | { |
| 106 | struct mipi_dsi_phy_ctrl *pd; |
| 107 | uint32_t i, off = 0; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 108 | int mdp_rev; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 109 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 110 | mdp_rev = mdp_get_revision(); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 111 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 112 | if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) { |
| 113 | writel(0x00000001, DSIPHY_SW_RESET); |
| 114 | writel(0x00000000, DSIPHY_SW_RESET); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 115 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 116 | pd = (pinfo->dsi_phy_config); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 117 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 118 | off = 0x02cc; /* regulator ctrl 0 */ |
| 119 | for (i = 0; i < 4; i++) { |
| 120 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 121 | off += 4; |
| 122 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 123 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 124 | off = 0x0260; /* phy timig ctrl 0 */ |
| 125 | for (i = 0; i < 11; i++) { |
| 126 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 127 | off += 4; |
| 128 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 129 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 130 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 131 | length should > data lane HS timing length */ |
| 132 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 133 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 134 | off = 0x0290; /* ctrl 0 */ |
| 135 | for (i = 0; i < 4; i++) { |
| 136 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 137 | off += 4; |
| 138 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 139 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 140 | off = 0x02a0; /* strength 0 */ |
| 141 | for (i = 0; i < 4; i++) { |
| 142 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 143 | off += 4; |
| 144 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 145 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 146 | if (1 == pinfo->num_of_lanes) |
| 147 | pd->pll[10] |= 0x8; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 148 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 149 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 150 | for (i = 1; i < 21; i++) { |
| 151 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 152 | off += 4; |
| 153 | } |
| 154 | |
| 155 | /* pll ctrl 0 */ |
| 156 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 157 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 158 | /* lane swp ctrol */ |
| 159 | if (pinfo->lane_swap) |
| 160 | writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac); |
| 161 | } else { |
| 162 | writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */ |
| 163 | writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */ |
| 164 | writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */ |
| 165 | writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */ |
| 166 | writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */ |
| 167 | writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */ |
| 168 | writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */ |
| 169 | |
| 170 | pd = (pinfo->dsi_phy_config); |
| 171 | |
| 172 | off = 0x0480; /* strength 0 - 2 */ |
| 173 | for (i = 0; i < 3; i++) { |
| 174 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 175 | off += 4; |
| 176 | } |
| 177 | |
| 178 | off = 0x0470; /* ctrl 0 - 3 */ |
| 179 | for (i = 0; i < 4; i++) { |
| 180 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 181 | off += 4; |
| 182 | } |
| 183 | |
| 184 | off = 0x0500; /* regulator ctrl 0 - 4 */ |
| 185 | for (i = 0; i < 5; i++) { |
| 186 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 187 | off += 4; |
| 188 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 189 | mipi_dsi_calibration(MIPI_DSI_BASE); |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 190 | |
| 191 | off = 0x0204; /* pll ctrl 1 - 19, skip 0 */ |
| 192 | for (i = 1; i < 20; i++) { |
| 193 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 194 | off += 4; |
| 195 | } |
| 196 | |
| 197 | /* pll ctrl 0 */ |
| 198 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 199 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 200 | |
| 201 | /* Check that PHY is ready */ |
| 202 | while (!(readl(DSIPHY_PLL_RDY) & 0x01)) |
| 203 | udelay(1); |
| 204 | |
| 205 | writel(0x202D, DSI_CLKOUT_TIMING_CTRL); |
| 206 | |
| 207 | off = 0x0440; /* phy timing ctrl 0 - 11 */ |
| 208 | for (i = 0; i < 12; i++) { |
| 209 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 210 | off += 4; |
| 211 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 212 | } |
| 213 | return 0; |
| 214 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 215 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 216 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 217 | void mdss_dsi_phy_sw_reset(uint32_t ctl_base) |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 218 | { |
| 219 | /* start phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 220 | writel(0x0001, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 221 | udelay(1000); |
| 222 | |
| 223 | /* end phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 224 | writel(0x0000, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 225 | udelay(100); |
| 226 | } |
| 227 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 228 | static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, |
| 229 | uint32_t phy_base, uint32_t reg_base) |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 230 | { |
| 231 | /* DSI0 and DSI1 have a common regulator */ |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 232 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) { |
| 233 | /* LDO ctrl */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 234 | writel(0x1d, phy_base + MMSS_DSI_PHY_LDO_CTRL); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 235 | } else { |
| 236 | /* Regulator ctrl 1 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 237 | writel(pd->regulator[1], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_1); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 238 | /* Regulator ctrl 2 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 239 | writel(pd->regulator[2], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_2); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 240 | /* Regulator ctrl 3 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 241 | writel(pd->regulator[3], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_3); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 242 | /* Regulator ctrl 4 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 243 | writel(pd->regulator[4], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_4); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 244 | /* Regulator ctrl - CAL_PWR_CFG */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 245 | writel(pd->regulator[6], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 246 | /* LDO ctrl */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 247 | writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 248 | /* Regulator ctrl 0 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 249 | writel(pd->regulator[0], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_0); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 250 | dmb(); |
| 251 | } |
| 252 | } |
| 253 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 254 | static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 255 | uint32_t phy_base) |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 256 | { |
| 257 | /* DSI0 and DSI1 have a common regulator */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 258 | uint32_t off = 0x0280; /* phy regulator ctrl settings */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 259 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 260 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) { |
| 261 | /* Regulator ctrl 0 */ |
| 262 | writel(0x00, DSI0_PHY_BASE + off + (4 * 0)); |
| 263 | /* Regulator ctrl - CAL_PWD_CFG */ |
| 264 | writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6)); |
| 265 | /* Add h/w recommended delay */ |
| 266 | udelay(1000); |
| 267 | /* Regulator ctrl - TEST */ |
| 268 | writel(pd->regulator[5], DSI0_PHY_BASE + off + (4 * 5)); |
| 269 | /* Regulator ctrl 3 */ |
| 270 | writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3)); |
| 271 | /* Regulator ctrl 2 */ |
| 272 | writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2)); |
| 273 | /* Regulator ctrl 1 */ |
| 274 | writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1)); |
| 275 | /* Regulator ctrl 4 */ |
| 276 | writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4)); |
| 277 | /* LDO ctrl */ |
| 278 | if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1) /* 8916/8939 */ |
| 279 | writel(0x05, phy_base + 0x01dc); |
| 280 | else if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103) /* 8994 */ |
| 281 | writel(0x1d, phy_base + 0x01dc); |
| 282 | else |
| 283 | writel(0x0d, phy_base + 0x01dc); |
| 284 | dmb(); |
| 285 | } else { |
| 286 | /* Regulator ctrl 0 */ |
| 287 | writel(0x00, DSI0_PHY_BASE + off + (4 * 0)); |
| 288 | /* Regulator ctrl - CAL_PWD_CFG */ |
| 289 | writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6)); |
| 290 | /* Add h/w recommended delay */ |
| 291 | udelay(1000); |
| 292 | /* Regulator ctrl 1 */ |
| 293 | writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1)); |
| 294 | /* Regulator ctrl 2 */ |
| 295 | writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2)); |
| 296 | /* Regulator ctrl 3 */ |
| 297 | writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3)); |
| 298 | /* Regulator ctrl 4 */ |
| 299 | writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4)); |
| 300 | /* LDO ctrl */ |
| 301 | writel(0x00, phy_base + 0x01dc); |
| 302 | /* Regulator ctrl 0 */ |
| 303 | writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0)); |
| 304 | dmb(); |
| 305 | } |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 306 | } |
| 307 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 308 | int mdss_dsi_v2_phy_init(struct mipi_panel_info *mipi, uint32_t ctl_base) |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 309 | { |
| 310 | struct mdss_dsi_phy_ctrl *pd; |
| 311 | uint32_t i, ln, off = 0, offset; |
| 312 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 313 | pd = mipi->mdss_dsi_phy_db; |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 314 | /* DSI PHY configuration */ |
| 315 | off = 0x480; |
| 316 | writel(pd->strength[0], ctl_base + off + (4 * 0)); |
| 317 | writel(pd->strength[1], ctl_base + off + (4 * 2)); |
| 318 | |
| 319 | off = 0x470; |
| 320 | writel(0x10, ctl_base + off + (4 * 3)); |
| 321 | writel(0x5F, ctl_base + off + (4 * 0)); |
| 322 | |
| 323 | off = 0x500; |
Xiaoming Zhou | 7c9e1ee | 2013-07-18 10:51:41 -0400 | [diff] [blame] | 324 | /* use LDO mode */ |
| 325 | writel(0x25, ctl_base + 0x4B0); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 326 | for (i = 0; i < 5; i++) |
| 327 | writel(pd->regulator[i], ctl_base + off + (4 * i)); |
| 328 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 329 | mipi_dsi_calibration(ctl_base); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 330 | |
| 331 | /* 4 lanes + clk lane configuration */ |
| 332 | /* lane config n * (0 - 4) & DataPath setup */ |
| 333 | for (ln = 0; ln < 5; ln++) { |
| 334 | off = 0x0300 + (ln * 0x40); |
| 335 | for (i = 0; i < 9; i++) { |
| 336 | offset = i + (ln * 9); |
| 337 | writel(pd->laneCfg[offset], ctl_base + off); |
| 338 | dmb(); |
| 339 | off += 4; |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | off = 0x440; |
| 344 | for (i = 0; i < 12; i++) |
| 345 | writel(pd->timing[i], ctl_base + off + (4 * i)); |
| 346 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 347 | if (1 == mipi->num_of_lanes) |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 348 | writel(0x8, ctl_base + 0x200 + (4 * 11)); |
| 349 | |
| 350 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 351 | if (mipi->lane_swap) |
| 352 | writel(mipi->lane_swap, ctl_base + 0x0ac); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 353 | |
| 354 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 355 | length should > data lane HS timing length */ |
| 356 | writel(0x41b, ctl_base + 0x0c0); |
| 357 | return 0; |
| 358 | } |
| 359 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 360 | static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi, |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 361 | uint32_t ctl_base, uint32_t phy_base) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 362 | { |
| 363 | struct mdss_dsi_phy_ctrl *pd; |
| 364 | uint32_t i, off = 0, ln, offset; |
| 365 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 366 | if (mdp_get_revision() == MDP_REV_304) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 367 | return mdss_dsi_v2_phy_init(mipi, ctl_base); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 368 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 369 | pd = (mipi->mdss_dsi_phy_db); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 370 | |
| 371 | /* Strength ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 372 | writel(pd->strength[0], phy_base + 0x0184); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 373 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 374 | mdss_dsi_phy_regulator_init(pd, phy_base); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 375 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 376 | off = 0x0140; /* phy timing ctrl 0 - 11 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 377 | for (i = 0; i < 12; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 378 | writel(pd->timing[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 379 | dmb(); |
| 380 | off += 4; |
| 381 | } |
| 382 | |
| 383 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 384 | writel(0x00, phy_base + 0x0174); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 385 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 386 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 387 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 388 | dmb(); |
| 389 | /* 4 lanes + clk lane configuration */ |
| 390 | /* lane config n * (0 - 4) & DataPath setup */ |
| 391 | for (ln = 0; ln < 5; ln++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 392 | off = (ln * 0x40); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 393 | for (i = 0; i < 9; i++) { |
| 394 | offset = i + (ln * 9); |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 395 | writel(pd->laneCfg[offset], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 396 | dmb(); |
| 397 | off += 4; |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 402 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 403 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 404 | /* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 405 | if (phy_base == DSI0_PHY_BASE || |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 406 | (readl(mipi->ctl_base) == DSI_HW_REV_103_1)) |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 407 | writel(0x01, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 408 | else |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 409 | writel(0x00, phy_base + 0x01d4); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 410 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 411 | dmb(); |
| 412 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 413 | off = 0x01b4; /* phy BIST ctrl 0 - 5 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 414 | for (i = 0; i < 6; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 415 | writel(pd->bistCtrl[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 416 | off += 4; |
| 417 | } |
| 418 | dmb(); |
| 419 | |
| 420 | /* DSI_0_CLKOUT_TIMING_CTRL */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 421 | writel(0x41b, ctl_base + 0x0c4); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 422 | dmb(); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 423 | return 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 424 | |
| 425 | } |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 426 | |
| 427 | void mdss_dsi_phy_contention_detection( |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 428 | struct mipi_panel_info *mipi, |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 429 | uint32_t phy_base) |
| 430 | { |
| 431 | struct mdss_dsi_phy_ctrl *pd; |
| 432 | |
| 433 | if (mdp_get_revision() == MDP_REV_304) |
| 434 | return; |
| 435 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 436 | pd = (mipi->mdss_dsi_phy_db); |
Aravind Venkateswaran | 51e5755 | 2014-12-09 13:23:19 -0800 | [diff] [blame] | 437 | writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1); |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 438 | dmb(); |
| 439 | } |
| 440 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 441 | static int mdss_dsi_phy_20nm_init(struct mipi_panel_info *mipi, |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 442 | uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base) |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 443 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 444 | struct mdss_dsi_phy_ctrl *pd = mipi->mdss_dsi_phy_db; |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 445 | uint32_t i, off = 0, ln, offset; |
| 446 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 447 | mdss_dsi_20nm_phy_regulator_init(pd, phy_base, reg_base); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 448 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 449 | /* Strength ctrl 0 */ |
| 450 | writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0); |
| 451 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 452 | writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 453 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 454 | for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) { |
| 455 | off = (ln * 0x40); |
| 456 | for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) { |
| 457 | offset = i + (ln * CONFIG_REG_FOR_EACH_LANE); |
| 458 | writel(pd->laneCfg[offset], phy_base + off); |
| 459 | dmb(); |
| 460 | } |
| 461 | } |
| 462 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 463 | off = MMSS_DSI_PHY_TIMING_CTRL_0; |
| 464 | for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) { |
| 465 | writel(pd->timing[i], phy_base + off); |
| 466 | dmb(); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 467 | } |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 468 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 469 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1); |
| 470 | dmb(); |
| 471 | writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 472 | dmb(); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 473 | return 0; |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 474 | } |
| 475 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 476 | int mdss_dsi_phy_init(struct mipi_panel_info *mipi) |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 477 | { |
| 478 | int ret; |
| 479 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame^] | 480 | if (mipi->mdss_dsi_phy_db->is_pll_20nm) { |
| 481 | ret = mdss_dsi_phy_20nm_init(mipi, mipi->ctl_base, |
| 482 | mipi->phy_base, mipi->reg_base); |
| 483 | if (mipi->dual_dsi) |
| 484 | ret = mdss_dsi_phy_20nm_init(mipi, mipi->sctl_base, |
| 485 | mipi->sphy_base, mipi->reg_base); |
| 486 | } else { |
| 487 | ret = mdss_dsi_phy_28nm_init(mipi, |
| 488 | mipi->ctl_base, mipi->phy_base); |
| 489 | if (mipi->dual_dsi) |
| 490 | ret = mdss_dsi_phy_28nm_init(mipi, mipi->sctl_base, |
| 491 | mipi->sphy_base); |
| 492 | } |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 493 | |
| 494 | return ret; |
| 495 | } |