Vishnuvardhan Prodduturi | 2c7fd9e | 2018-02-05 17:24:40 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, 2017-2018, The Linux Foundation. All rights reserved. |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 36 | #include <pm8x41_wled.h> |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 37 | #include <board.h> |
| 38 | #include <mdp3.h> |
| 39 | #include <scm.h> |
| 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
Casey Piper | d2af07b | 2015-04-01 18:01:58 -0700 | [diff] [blame] | 43 | #include <regulator.h> |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 44 | |
| 45 | #include "include/panel.h" |
| 46 | #include "include/display_resource.h" |
Veera Sundaram Sankaran | 87f8813 | 2015-01-28 11:32:44 -0800 | [diff] [blame] | 47 | #include "gcdb_display.h" |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 48 | |
| 49 | #define VCO_DELAY_USEC 1000 |
| 50 | #define GPIO_STATE_LOW 0 |
| 51 | #define GPIO_STATE_HIGH 2 |
| 52 | #define RESET_GPIO_SEQ_LEN 3 |
| 53 | #define PWM_DUTY_US 13 |
| 54 | #define PWM_PERIOD_US 27 |
Shivaraj Shetty | 89fc8ed | 2015-01-23 15:03:35 +0530 | [diff] [blame] | 55 | #define PM8916_VER 0x20000 |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 56 | |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 57 | /*---------------------------------------------------------------------------*/ |
| 58 | /* GPIO configuration */ |
| 59 | /*---------------------------------------------------------------------------*/ |
| 60 | static struct gpio_pin bob_gpio = { |
| 61 | "pm8941_gpios", 12, 2, 1, 0, 1 |
| 62 | }; |
Krishna Manikandan | cf693b2 | 2017-12-05 18:14:52 +0530 | [diff] [blame] | 63 | static bool display_efuse = false; |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 64 | |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 65 | static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base) |
| 66 | { |
| 67 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 68 | mdelay(1); |
| 69 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 70 | mdelay(1); |
| 71 | } |
| 72 | |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 73 | static void dsi_pll_toggle_lock_detect_8909(uint32_t pll_base) |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 74 | { |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 75 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 76 | udelay(1); |
| 77 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 78 | udelay(512); |
| 79 | } |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 80 | |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 81 | static void dsi_pll_sw_reset_8909(uint32_t pll_base) |
| 82 | { |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 83 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 84 | udelay(1); |
| 85 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | static uint32_t dsi_pll_enable_seq_1_8909(uint32_t pll_base) |
| 89 | { |
| 90 | uint32_t rc; |
| 91 | |
| 92 | dsi_pll_sw_reset_8909(pll_base); |
| 93 | /* |
| 94 | * Add hardware recommended delays between register writes for |
| 95 | * the updates to take effect. These delays are necessary for the |
| 96 | * PLL to successfully lock |
| 97 | */ |
| 98 | |
| 99 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 100 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 101 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 102 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 103 | udelay(500); |
| 104 | |
| 105 | dsi_pll_toggle_lock_detect_8909(pll_base); |
| 106 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 107 | |
| 108 | return rc; |
| 109 | } |
| 110 | |
| 111 | static uint32_t dsi_pll_enable_seq_2_8909(uint32_t pll_base) |
| 112 | { |
| 113 | uint32_t rc; |
| 114 | |
| 115 | dsi_pll_sw_reset_8909(pll_base); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 116 | |
| 117 | /* |
| 118 | * Add hardware recommended delays between register writes for |
| 119 | * the updates to take effect. These delays are necessary for the |
| 120 | * PLL to successfully lock |
| 121 | */ |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 122 | writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 123 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 124 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 125 | udelay(3); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 126 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 127 | udelay(500); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 128 | |
Padmanabhan Komanduru | 048df21 | 2015-05-28 15:21:22 +0530 | [diff] [blame] | 129 | dsi_pll_toggle_lock_detect_8909(pll_base); |
| 130 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 131 | |
| 132 | return rc; |
| 133 | } |
| 134 | |
| 135 | static uint32_t dsi_pll_enable_seq_3_8909(uint32_t pll_base) |
| 136 | { |
| 137 | uint32_t rc; |
| 138 | |
| 139 | dsi_pll_sw_reset_8909(pll_base); |
| 140 | |
| 141 | /* |
| 142 | * Add hardware recommended delays between register writes for |
| 143 | * the updates to take effect. These delays are necessary for the |
| 144 | * PLL to successfully lock |
| 145 | */ |
| 146 | writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ |
| 147 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 148 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 149 | udelay(3); |
| 150 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 151 | udelay(500); |
| 152 | |
| 153 | dsi_pll_toggle_lock_detect_8909(pll_base); |
| 154 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 155 | |
| 156 | return rc; |
| 157 | } |
| 158 | |
| 159 | static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base) |
| 160 | { |
| 161 | uint32_t pll_locked = 0; |
| 162 | uint32_t counter = 0; |
| 163 | |
| 164 | do { |
| 165 | pll_locked = dsi_pll_enable_seq_1_8909(pll_base); |
| 166 | |
| 167 | dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); |
| 168 | ++counter; |
| 169 | } while (!pll_locked && (counter < 3)); |
| 170 | |
| 171 | if (!pll_locked) { |
| 172 | counter = 0; |
| 173 | do { |
| 174 | pll_locked = dsi_pll_enable_seq_2_8909(pll_base); |
| 175 | |
| 176 | dprintf(SPEW, "GF P1 pll locked status is %d\n", |
| 177 | pll_locked); |
| 178 | ++counter; |
| 179 | } while (!pll_locked && (counter < 3)); |
| 180 | } |
| 181 | |
| 182 | if (!pll_locked) { |
| 183 | counter = 0; |
| 184 | do { |
| 185 | pll_locked = dsi_pll_enable_seq_3_8909(pll_base); |
| 186 | |
| 187 | dprintf(SPEW, "GF P2 pll locked status is %d\n", |
| 188 | pll_locked); |
| 189 | ++counter; |
| 190 | } while (!pll_locked && (counter < 3)); |
| 191 | } |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 192 | |
| 193 | return pll_locked; |
| 194 | } |
| 195 | |
| 196 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 197 | { |
Shivaraj Shetty | be6b6fd | 2014-12-12 13:48:29 +0530 | [diff] [blame] | 198 | uint32_t hw_id = board_hardware_id(); |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 199 | uint32_t platform = board_platform_id(); |
| 200 | uint32_t platform_subtype = board_hardware_subtype(); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 201 | |
| 202 | if (bl->bl_interface_type == BL_DCS) |
| 203 | return 0; |
| 204 | |
Baochu Xu | 34bb8e6 | 2017-12-05 14:22:06 +0800 | [diff] [blame] | 205 | if (!(((HW_PLATFORM_SUBTYPE_8909_PM660 == platform_subtype) || |
Swetha Vucha | e3baf91 | 2017-12-20 15:49:28 +0530 | [diff] [blame] | 206 | (HW_PLATFORM_SUBTYPE_8909_PM660_V1 == platform_subtype) || |
| 207 | (HW_PLATFORM_SUBTYPE_8909_COMPAL_ALPHA == platform_subtype)) && |
Sachin Bhayare | 39da0ce | 2017-09-15 16:10:28 +0530 | [diff] [blame] | 208 | ((MSM8909W == platform) || (APQ8009W == platform)) && |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 209 | (HW_PLATFORM_MTP == hw_id))) { |
| 210 | struct pm8x41_mpp mpp; |
| 211 | struct board_pmic_data pmic_info; |
| 212 | int rc; |
Shivaraj Shetty | be6b6fd | 2014-12-12 13:48:29 +0530 | [diff] [blame] | 213 | |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 214 | board_pmic_info(&pmic_info, 1); |
| 215 | if (pmic_info.pmic_version == PM8916_VER) |
| 216 | mpp.base = PM8x41_MMP4_BASE; |
| 217 | else |
| 218 | mpp.base = PM8x41_MMP2_BASE; |
| 219 | |
| 220 | mpp.vin = MPP_VIN0; |
| 221 | if (enable) { |
| 222 | pm_pwm_enable(false); |
| 223 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 224 | if (rc < 0) |
| 225 | mpp.mode = MPP_HIGH; |
| 226 | else { |
| 227 | mpp.mode = MPP_DTEST1; |
| 228 | pm_pwm_enable(true); |
| 229 | } |
| 230 | pm8x41_config_output_mpp(&mpp); |
| 231 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 232 | } else { |
| 233 | pm_pwm_enable(false); |
| 234 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 235 | } |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 236 | mdelay(20); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 237 | } |
Sandeep Panda | ae8d68e | 2014-12-29 20:07:22 +0530 | [diff] [blame] | 238 | if (enable) { |
| 239 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 240 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 241 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 242 | gpio_set(bkl_gpio.pin_id, 2); |
Wenjun Zhang | a083eea | 2018-02-01 03:32:03 -0500 | [diff] [blame] | 243 | |
| 244 | if (HW_PLATFORM_SUBTYPE_8909_PM660_V1 == platform_subtype) { |
| 245 | gpio_tlmm_config(spi_bkl_gpio.pin_id, 0, |
| 246 | spi_bkl_gpio.pin_direction, |
| 247 | spi_bkl_gpio.pin_pull, |
| 248 | spi_bkl_gpio.pin_strength, |
| 249 | spi_bkl_gpio.pin_state); |
| 250 | gpio_set(spi_bkl_gpio.pin_id, 2); |
| 251 | } |
Sandeep Panda | ae8d68e | 2014-12-29 20:07:22 +0530 | [diff] [blame] | 252 | } |
| 253 | |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | |
| 257 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 258 | { |
| 259 | int32_t ret = 0; |
| 260 | struct mdss_dsi_pll_config *pll_data; |
| 261 | dprintf(SPEW, "target_panel_clock\n"); |
| 262 | |
| 263 | pll_data = pinfo->mipi.dsi_pll_config; |
| 264 | pll_data->vco_delay = VCO_DELAY_USEC; |
| 265 | |
| 266 | if (enable) { |
| 267 | mdp_gdsc_ctrl(enable); |
| 268 | mdss_bus_clocks_enable(); |
| 269 | mdp_clock_enable(); |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 270 | |
| 271 | /* |
| 272 | * Enable auto functional gating |
| 273 | * on DSI CMD AXI fetch from DDR |
| 274 | */ |
Sachin Bhayare | a8deb5c | 2015-07-16 11:49:08 +0530 | [diff] [blame] | 275 | writel(0x3fbff, MDP_CGC_EN); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 276 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 277 | if (ret) { |
| 278 | dprintf(CRITICAL, |
| 279 | "%s: Failed to restore MDP security configs", |
| 280 | __func__); |
| 281 | mdp_clock_disable(); |
| 282 | mdss_bus_clocks_disable(); |
| 283 | mdp_gdsc_ctrl(0); |
| 284 | return ret; |
| 285 | } |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 286 | mdss_dsi_uniphy_pll_sw_reset_8909(pinfo->mipi.pll_base); |
| 287 | mdss_dsi_auto_pll_config(pinfo->mipi.pll_base, |
Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 288 | pinfo->mipi.ctl_base, pll_data); |
Padmanabhan Komanduru | c0766c8 | 2015-04-27 16:39:15 -0700 | [diff] [blame] | 289 | if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_base)) |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 290 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 291 | gcc_dsi_clocks_enable(pll_data->pclk_m, |
| 292 | pll_data->pclk_n, |
| 293 | pll_data->pclk_d); |
| 294 | } else if(!target_cont_splash_screen()) { |
| 295 | gcc_dsi_clocks_disable(); |
| 296 | mdp_clock_disable(); |
| 297 | mdss_bus_clocks_disable(); |
| 298 | mdp_gdsc_ctrl(enable); |
| 299 | } |
| 300 | |
| 301 | return 0; |
| 302 | } |
| 303 | |
| 304 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 305 | struct msm_panel_info *pinfo) |
| 306 | { |
| 307 | int ret = NO_ERROR; |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 308 | uint32_t bob_pmic_gpio = bob_gpio.pin_id; |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 309 | uint32_t hw_id = board_hardware_id(); |
| 310 | uint32_t hw_subtype = board_hardware_subtype(); |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 311 | uint32_t platform = board_platform_id(); |
| 312 | |
Baochu Xu | 34bb8e6 | 2017-12-05 14:22:06 +0800 | [diff] [blame] | 313 | if (((HW_PLATFORM_SUBTYPE_8909_PM660 == hw_subtype) || |
Swetha Vucha | e3baf91 | 2017-12-20 15:49:28 +0530 | [diff] [blame] | 314 | (HW_PLATFORM_SUBTYPE_8909_PM660_V1 == hw_subtype) || |
| 315 | (HW_PLATFORM_SUBTYPE_8909_COMPAL_ALPHA == hw_subtype)) && |
Sachin Bhayare | 39da0ce | 2017-09-15 16:10:28 +0530 | [diff] [blame] | 316 | ((MSM8909W == platform) || (APQ8009W == platform)) && |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 317 | (HW_PLATFORM_MTP == hw_id)) { |
| 318 | struct pm8x41_gpio bobgpio_param = { |
| 319 | .direction = PM_GPIO_DIR_OUT, |
| 320 | .vin_sel = 0, |
| 321 | .out_strength = PM_GPIO_OUT_DRIVE_MED, |
| 322 | .function = PM_GPIO_FUNC_HIGH, |
| 323 | .pull = PM_GPIO_PULLDOWN_10, |
| 324 | .inv_int_pol = PM_GPIO_INVERT, |
| 325 | }; |
| 326 | |
| 327 | pm8x41_gpio_config(bob_pmic_gpio, &bobgpio_param); |
Sachin Bhayare | fa26bc1 | 2018-04-12 19:17:57 +0530 | [diff] [blame] | 328 | enable_gpio.pin_id = 59; |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 329 | } |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 330 | |
| 331 | if (enable) { |
| 332 | if (pinfo->mipi.use_enable_gpio) { |
| 333 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 334 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 335 | enable_gpio.pin_strength, |
| 336 | enable_gpio.pin_state); |
| 337 | |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 338 | gpio_set(enable_gpio.pin_id, 2); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 339 | } |
| 340 | |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 341 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 342 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 343 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 344 | |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 345 | gpio_set(reset_gpio.pin_id, 2); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 346 | |
| 347 | /* reset */ |
| 348 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 349 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 350 | gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 351 | else |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 352 | gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 353 | mdelay(resetseq->sleep[i]); |
| 354 | } |
| 355 | } else if(!target_cont_splash_screen()) { |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 356 | gpio_set(reset_gpio.pin_id, 0); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 357 | if (pinfo->mipi.use_enable_gpio) |
Shivaraj Shetty | af4c607 | 2014-11-04 16:25:31 +0530 | [diff] [blame] | 358 | gpio_set(enable_gpio.pin_id, 0); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | return ret; |
| 362 | } |
| 363 | |
Veera Sundaram Sankaran | 87f8813 | 2015-01-28 11:32:44 -0800 | [diff] [blame] | 364 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 365 | { |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 366 | uint32_t hw_id = board_hardware_id(); |
| 367 | uint32_t hw_subtype = board_hardware_subtype(); |
| 368 | uint32_t platform = board_platform_id(); |
| 369 | |
| 370 | if (enable) { |
Baochu Xu | 34bb8e6 | 2017-12-05 14:22:06 +0800 | [diff] [blame] | 371 | if (((HW_PLATFORM_SUBTYPE_8909_PM660 == hw_subtype) || |
Swetha Vucha | e3baf91 | 2017-12-20 15:49:28 +0530 | [diff] [blame] | 372 | (HW_PLATFORM_SUBTYPE_8909_PM660_V1 == hw_subtype) || |
| 373 | (HW_PLATFORM_SUBTYPE_8909_COMPAL_ALPHA == hw_subtype)) && |
Sachin Bhayare | 39da0ce | 2017-09-15 16:10:28 +0530 | [diff] [blame] | 374 | ((MSM8909W == platform) || (APQ8009W == platform)) && |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 375 | (HW_PLATFORM_MTP == hw_id)) |
| 376 | regulator_enable(REG_LDO12 | REG_LDO5 | REG_LDO11 | REG_LDO18); |
Wenjun Zhang | a083eea | 2018-02-01 03:32:03 -0500 | [diff] [blame] | 377 | else if (pinfo->type == SPI_PANEL) |
| 378 | { |
| 379 | regulator_enable(REG_LDO11 | REG_LDO18); |
| 380 | } |
Ashish Garg | 22001a9 | 2017-08-07 14:46:54 +0530 | [diff] [blame] | 381 | else |
| 382 | regulator_enable(REG_LDO2 | REG_LDO6 | REG_LDO17); |
| 383 | } |
Shivaraj Shetty | 01734d3 | 2014-11-20 12:24:01 +0530 | [diff] [blame] | 384 | |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 385 | return NO_ERROR; |
| 386 | } |
| 387 | |
Dhaval Patel | 7709c41 | 2015-05-12 10:09:41 -0700 | [diff] [blame] | 388 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 389 | { |
| 390 | memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE); |
| 391 | memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE); |
| 392 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE); |
| 393 | memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE); |
| 394 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE); |
| 395 | return NO_ERROR; |
| 396 | } |
| 397 | |
Sachin Bhayare | 015045f | 2017-01-25 17:52:17 +0530 | [diff] [blame] | 398 | static bool target_splash_disable(void) |
| 399 | { |
| 400 | uint32_t hw_id = board_hardware_id(); |
| 401 | uint32_t platform_subtype = board_hardware_subtype(); |
| 402 | uint32_t platform = board_platform_id(); |
| 403 | |
| 404 | if ((APQ8009 == platform) && |
| 405 | (((HW_PLATFORM_MTP == hw_id) && |
| 406 | (HW_PLATFORM_SUBTYPE_DSDA2 == platform_subtype)) || |
| 407 | ((HW_PLATFORM_RCM == hw_id) && |
Parth Dixit | acec6bf | 2017-02-27 19:06:39 +0530 | [diff] [blame] | 408 | ((HW_PLATFORM_SUBTYPE_SAP == platform_subtype)|| |
Vishnuvardhan Prodduturi | 2c7fd9e | 2018-02-05 17:24:40 +0530 | [diff] [blame] | 409 | (HW_PLATFORM_SUBTYPE_SAP_NOPMI == platform_subtype))) || |
| 410 | ((HW_PLATFORM_MTP == hw_id) && |
| 411 | (HW_PLATFORM_SUBTYPE_INTRINSIC_SOM == platform_subtype)))) { |
Sachin Bhayare | 015045f | 2017-01-25 17:52:17 +0530 | [diff] [blame] | 412 | dprintf(INFO, "Splash disabled\n"); |
| 413 | return true; |
| 414 | } else { |
| 415 | return false; |
| 416 | } |
| 417 | } |
| 418 | |
Krishna Manikandan | cf693b2 | 2017-12-05 18:14:52 +0530 | [diff] [blame] | 419 | bool is_display_disabled(void) |
| 420 | { |
| 421 | return display_efuse; |
| 422 | } |
| 423 | |
| 424 | bool display_efuse_check(void) |
| 425 | { |
| 426 | int i; |
| 427 | uint32_t efuse = 0; |
| 428 | uint32_t board_id = board_platform_id(); |
| 429 | |
| 430 | for (i = 0; i < ARRAY_SIZE(efuse_data);i++) |
| 431 | if (board_id == efuse_data[i].board_id) { |
| 432 | efuse = readl((efuse_data[i].start_address + efuse_data[i].offset)); |
| 433 | display_efuse = (efuse & (efuse_data[i].mask)) >> (efuse_data[i].shift); |
| 434 | } |
| 435 | |
| 436 | dprintf(INFO,"Efuse register: display disable flag = %d\n",display_efuse); |
| 437 | return display_efuse; |
| 438 | } |
| 439 | |
| 440 | void efuse_display_enable(char *pbuf, uint16_t buf_size) |
| 441 | { |
| 442 | char *default_str; |
| 443 | int prefix_display_len = strlen(pbuf); |
| 444 | if (display_efuse) |
| 445 | default_str = ";display_disabled:1"; |
| 446 | pbuf += prefix_display_len; |
| 447 | buf_size -= prefix_display_len; |
| 448 | strlcpy(pbuf, default_str, buf_size); |
| 449 | } |
| 450 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 451 | bool target_display_panel_node(char *pbuf, uint16_t buf_size) |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 452 | { |
Sachin Bhayare | 015045f | 2017-01-25 17:52:17 +0530 | [diff] [blame] | 453 | int ret = true; |
| 454 | |
| 455 | if (!target_splash_disable()) |
| 456 | ret = gcdb_display_cmdline_arg(pbuf, buf_size); |
| 457 | |
Krishna Manikandan | cf693b2 | 2017-12-05 18:14:52 +0530 | [diff] [blame] | 458 | if (display_efuse_check()){ |
| 459 | if (target_splash_disable()){ |
| 460 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 461 | efuse_display_enable(pbuf, buf_size); |
| 462 | } else |
| 463 | efuse_display_enable(pbuf, buf_size); |
| 464 | } |
| 465 | |
Sachin Bhayare | 015045f | 2017-01-25 17:52:17 +0530 | [diff] [blame] | 466 | return ret; |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | void target_display_init(const char *panel_name) |
| 470 | { |
| 471 | uint32_t panel_loop = 0; |
| 472 | uint32_t ret = 0; |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 473 | struct oem_panel_data oem; |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 474 | |
Krishna Manikandan | cf693b2 | 2017-12-05 18:14:52 +0530 | [diff] [blame] | 475 | if (display_efuse_check()) |
| 476 | return; |
| 477 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 478 | set_panel_cmd_string(panel_name); |
| 479 | oem = mdss_dsi_get_oem_data(); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 480 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 481 | if (!strcmp(oem.panel, NO_PANEL_CONFIG) |
| 482 | || !strcmp(oem.panel, SIM_VIDEO_PANEL) |
| 483 | || !strcmp(oem.panel, SIM_CMD_PANEL) |
| 484 | || oem.skip) { |
Sandeep Panda | 63933f9 | 2014-11-26 19:13:44 +0530 | [diff] [blame] | 485 | dprintf(INFO, "Selected %s: Skip panel configuration\n", |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 486 | oem.panel); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 487 | return; |
| 488 | } |
| 489 | |
Sachin Bhayare | 015045f | 2017-01-25 17:52:17 +0530 | [diff] [blame] | 490 | if (target_splash_disable()) |
| 491 | return; |
| 492 | |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 493 | do { |
| 494 | target_force_cont_splash_disable(false); |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 495 | ret = gcdb_display_init(oem.panel, MDP_REV_305, MIPI_FB_ADDR); |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 496 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 497 | break; |
| 498 | } else { |
| 499 | target_force_cont_splash_disable(true); |
| 500 | msm_display_off(); |
| 501 | } |
| 502 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 503 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 504 | if (!oem.cont_splash) { |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 505 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 506 | target_force_cont_splash_disable(true); |
| 507 | } |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | void target_display_shutdown(void) |
| 511 | { |
| 512 | gcdb_display_shutdown(); |
| 513 | } |