Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
Channagoud Kadabi | 4517eb1 | 2015-09-02 18:43:13 -0700 | [diff] [blame] | 28 | #include <arch/defines.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 29 | #include <platform/iomap.h> |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 30 | #include <qusb2_phy.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 31 | #include <reg.h> |
| 32 | #include <bits.h> |
| 33 | #include <debug.h> |
Veera Sundaram Sankaran | 0018151 | 2014-12-09 11:23:39 -0800 | [diff] [blame] | 34 | #include <qtimer.h> |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 35 | #include <platform.h> |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 36 | |
Channagoud Kadabi | 12b9693 | 2014-09-23 15:18:11 -0700 | [diff] [blame] | 37 | __WEAK int platform_is_msm8994() |
| 38 | { |
| 39 | return 0; |
| 40 | } |
| 41 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 42 | __WEAK int platform_is_msm8996() |
| 43 | { |
| 44 | return 0; |
| 45 | } |
| 46 | |
Parth Dixit | adf539f | 2016-09-16 23:26:16 +0530 | [diff] [blame] | 47 | __WEAK int platform_is_msm8996sg() |
| 48 | { |
| 49 | return 0; |
| 50 | } |
| 51 | |
Karthik Jadala | 8e6b219 | 2017-02-08 12:59:16 +0530 | [diff] [blame] | 52 | __WEAK int platform_is_mdm9650() |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 53 | { |
| 54 | return 0; |
| 55 | } |
| 56 | |
Gaurav Nebhwani | e0e4ed9 | 2016-03-21 12:52:28 +0530 | [diff] [blame] | 57 | __WEAK int platform_is_msm8953() |
| 58 | { |
| 59 | return 0; |
| 60 | } |
| 61 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 62 | __WEAK int platform_is_sdx20() |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 63 | { |
| 64 | return 0; |
| 65 | } |
| 66 | |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 67 | void qusb2_phy_reset(void) |
| 68 | { |
| 69 | uint32_t val; |
Channagoud Kadabi | d1e2cc2 | 2015-08-13 12:48:37 -0700 | [diff] [blame] | 70 | /* Default tune value */ |
| 71 | uint8_t tune2 = 0xB3; |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 72 | int retry = 100; |
| 73 | int se_clock = 1; |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 74 | int status_reg = 0; |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 75 | |
Channagoud Kadabi | d33824f | 2015-09-24 15:17:53 -0700 | [diff] [blame] | 76 | /* Disable the ref clock before phy reset */ |
| 77 | #if GCC_RX2_USB2_CLKREF_EN |
| 78 | writel((readl(GCC_RX2_USB2_CLKREF_EN) & ~0x1), GCC_RX2_USB2_CLKREF_EN); |
| 79 | dmb(); |
| 80 | #endif |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 81 | /* Block Reset */ |
| 82 | val = readl(GCC_QUSB2_PHY_BCR) | BIT(0); |
| 83 | writel(val, GCC_QUSB2_PHY_BCR); |
| 84 | udelay(10); |
| 85 | writel(val & ~BIT(0), GCC_QUSB2_PHY_BCR); |
| 86 | |
Channagoud Kadabi | 4517eb1 | 2015-09-02 18:43:13 -0700 | [diff] [blame] | 87 | /* configure the abh2 phy to wait state */ |
| 88 | writel(0x11, PERIPH_SS_AHB2PHY_TOP_CFG); |
| 89 | dmb(); |
| 90 | |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 91 | /* set CLAMP_N_EN and stay with disabled USB PHY */ |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 92 | if(platform_is_sdx20()) |
| 93 | writel(0x23, QUSB2PHY_PWR_CTRL1_SDX20); |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 94 | else |
| 95 | writel(0x23, QUSB2PHY_PORT_POWERDOWN); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 96 | |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 97 | /* TCSR register bit 0 indicates whether single ended clock |
| 98 | * or differential clock configuration is enabled. Based on the |
| 99 | * configuration set the PLL_TEST register. |
| 100 | */ |
| 101 | #if TCSR_PHY_CLK_SCHEME_SEL |
| 102 | se_clock = readl(TCSR_PHY_CLK_SCHEME_SEL) & 0x1; |
| 103 | #endif |
Karthik Jadala | 8e6b219 | 2017-02-08 12:59:16 +0530 | [diff] [blame] | 104 | if (platform_is_msm8996() || platform_is_mdm9650() || platform_is_msm8953()) |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 105 | { |
Parth Dixit | adf539f | 2016-09-16 23:26:16 +0530 | [diff] [blame] | 106 | if(platform_is_msm8996sg()) |
| 107 | writel(0xD0, QUSB2PHY_PORT_TUNE1); |
| 108 | else |
| 109 | writel(0xF8, QUSB2PHY_PORT_TUNE1); |
| 110 | |
Channagoud Kadabi | d1e2cc2 | 2015-08-13 12:48:37 -0700 | [diff] [blame] | 111 | /* Upper nibble of tune2 register should be updated based on the fuse value. |
| 112 | * Read the bits 21..24 from fuse and update the upper nibble with this value |
| 113 | */ |
| 114 | #if QFPROM_CORR_CALIB_ROW12_MSB |
| 115 | uint8_t fuse_val = (readl(QFPROM_CORR_CALIB_ROW12_MSB) & 0x1E00000) >> 21; |
| 116 | /* If fuse value is non zero then update the upper nibble with the fuse value |
| 117 | * otherwise use the default value |
| 118 | */ |
| 119 | if (fuse_val) |
| 120 | tune2 = (tune2 & 0x0f) | (fuse_val << 4); |
| 121 | #endif |
| 122 | writel(tune2, QUSB2PHY_PORT_TUNE2); |
Channagoud Kadabi | f0d9ef0 | 2015-09-24 14:52:02 -0700 | [diff] [blame] | 123 | writel(0x83, QUSB2PHY_PORT_TUNE3); |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 124 | writel(0xC0, QUSB2PHY_PORT_TUNE4); |
Parth Dixit | adf539f | 2016-09-16 23:26:16 +0530 | [diff] [blame] | 125 | if(platform_is_msm8996sg()) |
| 126 | writel(0x02, QUSB2PHY_PORT_TUNE5); |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 127 | writel(0x30, QUSB2PHY_PLL_TUNE); |
| 128 | writel(0x79, QUSB2PHY_PLL_USER_CTL1); |
| 129 | writel(0x21, QUSB2PHY_PLL_USER_CTL2); |
| 130 | writel(0x14, QUSB2PHY_PORT_TEST2); |
Channagoud Kadabi | f0d9ef0 | 2015-09-24 14:52:02 -0700 | [diff] [blame] | 131 | writel(0x9F, QUSB2PHY_PLL_AUTOPGM_CTL1); |
| 132 | writel(0x00, QUSB2PHY_PLL_PWR_CTL); |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 133 | } |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 134 | else if (platform_is_sdx20()) |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 135 | { |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 136 | /* HPG init sequence 0x13 for CML and 0x03 for CMOS */ |
| 137 | if (se_clock) |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 138 | writel(0x03, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDX20); |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 139 | else |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 140 | writel(0x13, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO_SDX20); |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 141 | |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 142 | writel(0x7C, QUSB2PHY_PLL_CLOCK_INVERTERS_SDX20); |
| 143 | writel(0x80, QUSB2PHY_PLL_CMODE_SDX20); |
| 144 | writel(0x0a, QUSB2PHY_PLL_LOCK_DELAY_SDX20); |
| 145 | writel(0x19, QUSB2PHY_PLL_DIGITAL_TIMERS_TWO_SDX20); |
| 146 | writel(0xa5, QUSB2PHY_TUNE1_SDX20); |
| 147 | writel(0x09, QUSB2PHY_TUNE2_SDX20); |
| 148 | writel(0x00, QUSB2PHY_IMP_CTRL1_SDX20); |
| 149 | writel(0x22, QUSB2PHY_PWR_CTRL1_SDX20); |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 150 | } |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 151 | else |
| 152 | { |
| 153 | /* Set HS impedance to 42ohms */ |
| 154 | writel(0xA0, QUSB2PHY_PORT_TUNE1); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 155 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 156 | /* Set TX current to 19mA, TX SR and TX bias current to 1, 1 */ |
| 157 | writel(0xA5, QUSB2PHY_PORT_TUNE2); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 158 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 159 | /* Increase autocalibration bias circuit settling time |
| 160 | * and enable utocalibration */ |
| 161 | writel(0x81, QUSB2PHY_PORT_TUNE3); |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 162 | |
Channagoud Kadabi | 7164ddf | 2015-04-09 16:27:36 -0700 | [diff] [blame] | 163 | writel(0x85, QUSB2PHY_PORT_TUNE4); |
| 164 | } |
| 165 | |
Tanya Finkel | e7aa427 | 2014-08-08 23:41:34 +0300 | [diff] [blame] | 166 | /* Enable ULPI mode */ |
Channagoud Kadabi | 12b9693 | 2014-09-23 15:18:11 -0700 | [diff] [blame] | 167 | if (platform_is_msm8994()) |
| 168 | writel(0x0, QUSB2PHY_PORT_UTMI_CTRL2); |
Channagoud Kadabi | d33824f | 2015-09-24 15:17:53 -0700 | [diff] [blame] | 169 | |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 170 | /* set CLAMP_N_EN and USB PHY is enabled*/ |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 171 | if (platform_is_sdx20()){ |
| 172 | writel(0x22, QUSB2PHY_PWR_CTRL1_SDX20); |
| 173 | writel(0x04, QUSB2PHY_DEBUG_CTRL2_SDX20); |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 174 | udelay(88); |
| 175 | } |
| 176 | else{ |
| 177 | writel(0x22, QUSB2PHY_PORT_POWERDOWN); |
| 178 | udelay(150); |
| 179 | } |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 180 | |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 181 | /* By default consider differential clock configuration and if TCSR |
| 182 | * register bit 0 is not set then use single ended setting |
| 183 | */ |
| 184 | if (se_clock) |
| 185 | { |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 186 | /* PLL TEST is not valid for sdx20 */ |
| 187 | if(!platform_is_sdx20()) |
Jeevan Shriram | f27525d | 2017-01-10 15:53:12 -0800 | [diff] [blame] | 188 | writel(0x80, QUSB2PHY_PLL_TEST); |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 189 | } |
| 190 | else |
| 191 | { |
| 192 | /* turn the ref clock on for differential clocks */ |
| 193 | #if GCC_RX2_USB2_CLKREF_EN |
| 194 | writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN); |
| 195 | dmb(); |
| 196 | #endif |
| 197 | } |
| 198 | udelay(100); |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 199 | |
| 200 | /* Check PLL status */ |
anisha agarwal | 35eb803 | 2017-03-21 13:12:12 -0700 | [diff] [blame] | 201 | if (platform_is_sdx20()){ |
| 202 | status_reg = QUSB2PHY_DEBUG_STAT5_SDX20; |
Runmin Wang | dc8e973 | 2016-10-06 11:14:08 -0700 | [diff] [blame] | 203 | } |
| 204 | else{ |
| 205 | status_reg = QUSB2PHY_PLL_STATUS; |
| 206 | } |
| 207 | |
| 208 | while (!(readl(status_reg) & QUSB2PHY_PLL_LOCK)) |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 209 | { |
| 210 | retry--; |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 211 | if (!retry) |
| 212 | { |
| 213 | dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS)); |
| 214 | break; |
| 215 | } |
Channagoud Kadabi | e80224a | 2015-10-15 21:55:07 -0700 | [diff] [blame] | 216 | /* As per recommendation form hw team wait for 5 us before reading the status */ |
| 217 | udelay(5); |
Channagoud Kadabi | 0a98d00 | 2015-10-07 11:57:53 -0700 | [diff] [blame] | 218 | } |
Joonwoo Park | 8ef6919 | 2014-06-09 16:54:15 -0700 | [diff] [blame] | 219 | } |