Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation, Inc. nor the names of its |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PM8x41_HW_H_ |
| 30 | #define _PM8x41_HW_H_ |
| 31 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 32 | /* SMBB Registers */ |
| 33 | #define SMBB_MISC_BOOT_DONE 0x1642 |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 34 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 35 | /* SMBB bit values */ |
| 36 | #define BOOT_DONE_BIT 7 |
| 37 | |
Deepa Dinamani | 7564f2a | 2013-02-05 17:55:51 -0800 | [diff] [blame] | 38 | #define REVID_REVISION4 0x103 |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 39 | |
Kuogee Hsieh | 1183511 | 2013-10-04 15:50:36 -0700 | [diff] [blame] | 40 | /* LPG Registers */ |
| 41 | #define LPG_SLAVE_ID 0x10000 /* slave_id == 1 */ |
| 42 | #define LPG_PERIPHERAL_BASE (0x0B100 | LPG_SLAVE_ID) |
| 43 | /* Peripheral base address for LPG channel */ |
| 44 | #define LPG_N_PERIPHERAL_BASE(x) (LPG_PERIPHERAL_BASE + ((x) - 1) * 0x100) |
| 45 | |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 46 | /* GPIO Registers */ |
| 47 | #define GPIO_PERIPHERAL_BASE 0xC000 |
| 48 | /* Peripheral base address for GPIO_X */ |
| 49 | #define GPIO_N_PERIPHERAL_BASE(x) (GPIO_PERIPHERAL_BASE + ((x) - 1) * 0x100) |
| 50 | |
| 51 | /* Register offsets within GPIO */ |
| 52 | #define GPIO_STATUS 0x08 |
| 53 | #define GPIO_MODE_CTL 0x40 |
| 54 | #define GPIO_DIG_VIN_CTL 0x41 |
| 55 | #define GPIO_DIG_PULL_CTL 0x42 |
| 56 | #define GPIO_DIG_OUT_CTL 0x45 |
| 57 | #define GPIO_EN_CTL 0x46 |
| 58 | |
| 59 | /* GPIO bit values */ |
| 60 | #define PERPH_EN_BIT 7 |
| 61 | #define GPIO_STATUS_VAL_BIT 0 |
| 62 | |
| 63 | |
| 64 | /* PON Peripheral registers */ |
sundarajan srinivasan | d0f59e8 | 2013-02-12 19:17:02 -0800 | [diff] [blame] | 65 | #define PON_PON_REASON1 0x808 |
Ameya Thakur | b0a62ab | 2013-06-25 13:43:10 -0700 | [diff] [blame] | 66 | #define PON_WARMBOOT_STATUS1 0x80A |
| 67 | #define PON_WARMBOOT_STATUS2 0x80B |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 68 | #define PON_INT_RT_STS 0x810 |
| 69 | #define PON_INT_SET_TYPE 0x811 |
| 70 | #define PON_INT_POLARITY_HIGH 0x812 |
| 71 | #define PON_INT_POLARITY_LOW 0x813 |
| 72 | #define PON_INT_LATCHED_CLR 0x814 |
| 73 | #define PON_INT_EN_SET 0x815 |
| 74 | #define PON_INT_LATCHED_STS 0x818 |
| 75 | #define PON_INT_PENDING_STS 0x819 |
| 76 | #define PON_RESIN_N_RESET_S1_TIMER 0x844 /* bits 0:3 : S1_TIMER */ |
| 77 | #define PON_RESIN_N_RESET_S2_TIMER 0x845 /* bits 0:2 : S2_TIMER */ |
| 78 | #define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */ |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 79 | #define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */ |
Deepa Dinamani | 3c9865d | 2013-03-08 14:03:19 -0800 | [diff] [blame] | 80 | #define PON_PS_HOLD_RESET_CTL2 0x85B |
Xiaocheng Li | 73c5712 | 2013-09-14 17:32:00 +0800 | [diff] [blame] | 81 | #define PMIC_WD_RESET_S2_CTL2 0x857 |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 82 | |
| 83 | /* PON Peripheral register bit values */ |
Deepa Dinamani | c7f8758 | 2013-02-01 15:24:49 -0800 | [diff] [blame] | 84 | #define RESIN_ON_INT_BIT 1 |
Deepa Dinamani | 9a61293 | 2012-08-14 16:15:03 -0700 | [diff] [blame] | 85 | #define RESIN_BARK_INT_BIT 4 |
| 86 | #define S2_RESET_EN_BIT 7 |
| 87 | |
| 88 | #define S2_RESET_TYPE_WARM 0x1 |
| 89 | #define PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE 0x7 |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 90 | |
Deepa Dinamani | c342f12 | 2013-06-12 15:41:31 -0700 | [diff] [blame] | 91 | /* MPP registers */ |
| 92 | #define MPP_DIG_VIN_CTL 0x41 |
| 93 | #define MPP_MODE_CTL 0x40 |
| 94 | #define MPP_EN_CTL 0x46 |
| 95 | |
| 96 | #define MPP_MODE_CTL_MODE_SHIFT 4 |
| 97 | #define MPP_EN_CTL_ENABLE_SHIFT 7 |
| 98 | |
Channagoud Kadabi | d091f70 | 2013-01-07 16:17:37 -0800 | [diff] [blame] | 99 | void pm8x41_reg_write(uint32_t addr, uint8_t val); |
| 100 | uint8_t pm8x41_reg_read(uint32_t addr); |
| 101 | |
| 102 | /* SPMI Macros */ |
| 103 | #define REG_READ(_a) pm8x41_reg_read(_a) |
| 104 | #define REG_WRITE(_a, _v) pm8x41_reg_write(_a, _v) |
| 105 | |
| 106 | #define REG_OFFSET(_addr) ((_addr) & 0xFF) |
| 107 | #define PERIPH_ID(_addr) (((_addr) & 0xFF00) >> 8) |
| 108 | #define SLAVE_ID(_addr) ((_addr) >> 16) |
| 109 | |
Channagoud Kadabi | 0e60b7d | 2012-11-01 22:56:08 +0530 | [diff] [blame] | 110 | #define LDO_RANGE_CTRL 0x40 |
| 111 | #define LDO_STEP_CTRL 0x41 |
| 112 | #define LDO_POWER_MODE 0x45 |
| 113 | #define LDO_EN_CTL_REG 0x46 |
| 114 | |
Amol Jadi | c3231ff | 2013-07-23 14:35:31 -0700 | [diff] [blame] | 115 | /* USB3 phy clock */ |
| 116 | #define DIFF_CLK1_EN_CTL 0x5746 |
| 117 | #define DIFF_CLK1_EN_BIT 7 |
| 118 | |
Channagoud Kadabi | 1372b90 | 2013-10-28 16:20:51 -0700 | [diff] [blame] | 119 | /* SMBB registers */ |
| 120 | #define PM8XXX_IBAT_ATC_A 0x1054 |
| 121 | #define PM8XXX_VBAT_DET 0x105D |
| 122 | #define PM8XXX_SEC_ACCESS 0x10D0 |
| 123 | #define PM8XXX_COMP_OVR0 0x10ED |
| 124 | #define PM8XXX_VCP 0x1247 |
| 125 | #define PM8XXX_TRKL_CHG_TEST 0x10E2 |
| 126 | #define PM8XXX_VBAT_IN_TSTS 0x1010 |
| 127 | |
| 128 | /* Macros for broken battery */ |
| 129 | #define VBAT_DET_LO_4_30V 0x35 |
| 130 | #define SEC_ACCESS 0xa5 |
| 131 | #define OVR0_DIS_VTRKL_FAULT 0x08 |
| 132 | #define CHG_TRICKLE_FORCED_ON 0x01 |
| 133 | #define VBAT_DET_HI_RT_STS 0x02 |
| 134 | #define VCP_ENABLE 0x01 |
| 135 | |
| 136 | int pm8xxx_is_battery_broken(void); |
| 137 | |
Deepa Dinamani | 2279965 | 2012-07-21 12:26:22 -0700 | [diff] [blame] | 138 | #endif |