Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 1 | /* |
Aparna Mallavarapu | 2269a2f | 2013-01-07 19:44:48 +0530 | [diff] [blame] | 2 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
Neeti Desai | 992ed6c | 2012-09-20 11:59:12 -0700 | [diff] [blame] | 11 | * * Neither the name of The Linux Foundation nor |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <platform/iomap.h> |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 32 | #include <platform/clock.h> |
| 33 | #include <uart_dm.h> |
| 34 | #include <gsbi.h> |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 35 | #include <mmc.h> |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 36 | #include <clock.h> |
Neeti Desai | 992ed6c | 2012-09-20 11:59:12 -0700 | [diff] [blame] | 37 | #include <board.h> |
| 38 | #include <smem.h> |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 39 | |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 40 | /* Set rate and enable the clock */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 41 | static void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr) |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 42 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 43 | unsigned int val = 0; |
| 44 | |
| 45 | /* Activate the reset for the M/N Counter */ |
| 46 | val = 1 << 7; |
| 47 | writel(val, ns_addr); |
| 48 | |
| 49 | /* Write the MD value into the MD register */ |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 50 | if (md_addr != 0x0) |
| 51 | writel(md, md_addr); |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 52 | |
| 53 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 54 | val = 1 << 7; |
| 55 | val |= ns; |
| 56 | writel(val, ns_addr); |
| 57 | |
| 58 | /* De-activate the reset for M/N Counter */ |
| 59 | val = 1 << 7; |
| 60 | val = ~val; |
| 61 | val = val & readl(ns_addr); |
| 62 | writel(val, ns_addr); |
| 63 | |
| 64 | /* Enable the Clock Root */ |
| 65 | val = 1 << 11; |
| 66 | val = val | readl(ns_addr); |
| 67 | writel(val, ns_addr); |
| 68 | |
| 69 | /* Enable the Clock Branch */ |
| 70 | val = 1 << 9; |
| 71 | val = val | readl(ns_addr); |
| 72 | writel(val, ns_addr); |
| 73 | |
| 74 | /* Enable the M/N Counter */ |
| 75 | val = 1 << 8; |
| 76 | val = val | readl(ns_addr); |
| 77 | writel(val, ns_addr); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 78 | } |
| 79 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 80 | /* Write the M,N,D values and enable the MMSS Clocks */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 81 | void config_mmss_clk(uint32_t ns, |
| 82 | uint32_t md, |
| 83 | uint32_t cc, |
| 84 | uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr) |
| 85 | { |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 86 | unsigned int val = 0; |
| 87 | |
| 88 | clock_config(ns, md, ns_addr, md_addr); |
| 89 | |
| 90 | /* Enable MND counter */ |
| 91 | val = cc | (1 << 5); |
| 92 | val = val | readl(cc_addr); |
| 93 | writel(val, cc_addr); |
| 94 | |
| 95 | /* Enable the root of the clock tree */ |
| 96 | val = 1 << 2; |
| 97 | val = val | readl(cc_addr); |
| 98 | writel(val, cc_addr); |
| 99 | |
| 100 | /* Enable the Pixel Clock */ |
| 101 | val = 1 << 0; |
| 102 | val = val | readl(cc_addr); |
| 103 | writel(val, cc_addr); |
| 104 | |
| 105 | /* Force On */ |
| 106 | val = 1 << 31; |
| 107 | val = val | readl(cc_addr); |
| 108 | writel(val, cc_addr); |
| 109 | } |
| 110 | |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 111 | void hsusb_clock_init(void) |
| 112 | { |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 113 | clk_get_set_enable("usb_hs_clk", 60000000, 1); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 114 | } |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 115 | |
| 116 | /* Configure UART clock - based on the gsbi id */ |
| 117 | void clock_config_uart_dm(uint8_t id) |
| 118 | { |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 119 | char gsbi_uart_clk_id[64]; |
| 120 | char gsbi_p_clk_id[64]; |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 121 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 122 | snprintf(gsbi_uart_clk_id, 64,"gsbi%u_uart_clk", id); |
| 123 | clk_get_set_enable(gsbi_uart_clk_id, 1843200, 1); |
| 124 | |
| 125 | snprintf(gsbi_p_clk_id, 64,"gsbi%u_pclk", id); |
| 126 | clk_get_set_enable(gsbi_p_clk_id, 0, 1); |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /* Configure i2c clock */ |
| 130 | void clock_config_i2c(uint8_t id, uint32_t freq) |
| 131 | { |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 132 | char gsbi_qup_clk_id[64]; |
| 133 | char gsbi_p_clk_id[64]; |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 134 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 135 | snprintf(gsbi_qup_clk_id, 64,"gsbi%u_qup_clk", id); |
| 136 | clk_get_set_enable(gsbi_qup_clk_id, 24000000, 1); |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 137 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 138 | snprintf(gsbi_p_clk_id, 64,"gsbi%u_pclk", id); |
| 139 | clk_get_set_enable(gsbi_p_clk_id, 0, 1); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | /* Turn on MDP related clocks and pll's for MDP */ |
| 143 | void mdp_clock_init(void) |
| 144 | { |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 145 | /* Set MDP clock to 200MHz */ |
| 146 | clk_get_set_enable("mdp_clk", 200000000, 1); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 147 | |
| 148 | /* Seems to lose pixels without this from status 0x051E0048 */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 149 | clk_get_set_enable("lut_mdp", 0, 1); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | /* Initialize all clocks needed by Display */ |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 153 | void mmss_clock_init(void) |
| 154 | { |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 155 | /* Configure Pixel clock */ |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 156 | config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, |
| 157 | DSI_PIXEL_NS_REG, DSI_PIXEL_MD_REG, DSI_PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 158 | |
| 159 | /* Configure DSI clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 160 | config_mmss_clk(DSI_NS_VAL, DSI_MD_VAL, DSI_CC_VAL, DSI_NS_REG, |
| 161 | DSI_MD_REG, DSI_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 162 | |
| 163 | /* Configure Byte clock */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 164 | config_mmss_clk(BYTE_NS_VAL, 0x0, BYTE_CC_VAL, DSI1_BYTE_NS_REG, 0x0, |
| 165 | DSI1_BYTE_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 166 | |
| 167 | /* Configure ESC clock */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 168 | config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, DSI1_ESC_NS_REG, 0x0, |
| 169 | DSI1_ESC_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 170 | } |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 171 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 172 | void liquid_mmss_clock_init(void) |
| 173 | { |
| 174 | /* Configure Pixel clock = 78.75 MHZ */ |
| 175 | config_mmss_clk(0x2003, 0x01FB, 0x0005, |
| 176 | DSI_PIXEL_NS_REG, DSI_PIXEL_MD_REG, DSI_PIXEL_CC_REG); |
| 177 | |
| 178 | /* Configure DSI clock = 236.25 MHZ */ |
| 179 | config_mmss_clk(0x03, 0x03FB, 0x05, |
| 180 | DSI_NS_REG, DSI_MD_REG, DSI_CC_REG); |
| 181 | |
| 182 | /* Configure Byte clock = 59.06 MHZ */ |
| 183 | config_mmss_clk(0x0B01, 0x0, 0x80ff0025, |
| 184 | DSI1_BYTE_NS_REG, 0x0, DSI1_BYTE_CC_REG); |
| 185 | |
| 186 | /* Configure ESC clock = 13.5 MHZ */ |
| 187 | config_mmss_clk(0x1B00, 0x0, 0x005, |
| 188 | DSI1_ESC_NS_REG, 0x0, DSI1_ESC_CC_REG); |
| 189 | } |
| 190 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 191 | void mmss_clock_disable(void) |
| 192 | { |
Siddhartha Agrawal | d296ff3 | 2012-08-22 11:43:53 -0700 | [diff] [blame] | 193 | writel(0x80000000, DSI1_BYTE_CC_REG); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 194 | writel(0x0, DSI_PIXEL_CC_REG); |
Siddhartha Agrawal | d296ff3 | 2012-08-22 11:43:53 -0700 | [diff] [blame] | 195 | writel(0x0, DSI1_BYTE_NS_REG); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 196 | writel(0x0, DSI1_ESC_CC_REG); |
Siddhartha Agrawal | d296ff3 | 2012-08-22 11:43:53 -0700 | [diff] [blame] | 197 | writel(0x0, DSI1_ESC_NS_REG); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 198 | |
| 199 | /* Disable root clock */ |
| 200 | writel(0x0, DSI_CC_REG); |
| 201 | } |
| 202 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 203 | /* Intialize MMC clock */ |
| 204 | void clock_init_mmc(uint32_t interface) |
| 205 | { |
| 206 | /* Nothing to be done. */ |
| 207 | } |
| 208 | |
| 209 | /* Configure MMC clock */ |
| 210 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 211 | { |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 212 | char sdc_clk[64]; |
| 213 | unsigned rate; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 214 | uint32_t reg = 0; |
| 215 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 216 | snprintf(sdc_clk, 64, "sdc%u_clk", interface); |
| 217 | |
Channagoud Kadabi | 17b6594 | 2013-03-14 16:30:42 -0700 | [diff] [blame] | 218 | /* Disalbe MCI_CLK before changing the sdcc clock */ |
| 219 | mmc_boot_mci_clk_disable(); |
| 220 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 221 | switch(freq) |
| 222 | { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 223 | case MMC_CLK_400KHZ: |
Shashank Mittal | 5d40355 | 2012-03-14 21:11:38 -0700 | [diff] [blame] | 224 | rate = 144000; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 225 | break; |
| 226 | case MMC_CLK_48MHZ: |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 227 | case MMC_CLK_50MHZ: /* Max supported is 48MHZ */ |
| 228 | rate = 48000000; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 229 | break; |
Channagoud Kadabi | ce291ac | 2013-04-02 11:22:53 -0700 | [diff] [blame] | 230 | case MMC_CLK_96MHZ: |
| 231 | rate = 96000000; |
| 232 | break; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 233 | default: |
| 234 | ASSERT(0); |
| 235 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | clk_get_set_enable(sdc_clk, rate, 1); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 239 | |
Channagoud Kadabi | 17b6594 | 2013-03-14 16:30:42 -0700 | [diff] [blame] | 240 | /* Enable MCI clk */ |
| 241 | mmc_boot_mci_clk_enable(); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 242 | } |
Shashank Mittal | 1fcde7a | 2011-07-25 13:41:50 -0700 | [diff] [blame] | 243 | |
| 244 | /* Configure crypto engine clock */ |
| 245 | void ce_clock_init(void) |
| 246 | { |
Channagoud Kadabi | f672900 | 2013-01-16 16:42:57 -0800 | [diff] [blame] | 247 | uint32_t platform_id; |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 248 | |
Channagoud Kadabi | f672900 | 2013-01-16 16:42:57 -0800 | [diff] [blame] | 249 | platform_id = board_platform_id(); |
| 250 | |
| 251 | if ((platform_id == APQ8064) || (platform_id == APQ8064AA) |
| 252 | || (platform_id == APQ8064AB)) |
Neeti Desai | 992ed6c | 2012-09-20 11:59:12 -0700 | [diff] [blame] | 253 | { |
| 254 | /* Enable HCLK for CE3 */ |
| 255 | clk_get_set_enable("ce3_pclk", 0, 1); |
| 256 | |
| 257 | /* Enable core clk for CE3 */ |
| 258 | clk_get_set_enable("ce3_clk", 0, 1); |
| 259 | } |
Channagoud Kadabi | f672900 | 2013-01-16 16:42:57 -0800 | [diff] [blame] | 260 | else |
| 261 | { |
| 262 | /* Enable HCLK for CE1 */ |
| 263 | clk_get_set_enable("ce1_pclk", 0, 1); |
| 264 | |
| 265 | /* Enable core clk for CE3 */ |
| 266 | clk_get_set_enable("ce1_clk", 0, 1); |
| 267 | } |
Shashank Mittal | 1fcde7a | 2011-07-25 13:41:50 -0700 | [diff] [blame] | 268 | } |
Deepa Dinamani | 3467b71 | 2012-02-10 14:56:06 -0800 | [diff] [blame] | 269 | /* Async Reset CE1 */ |
| 270 | void ce_async_reset() |
| 271 | { |
| 272 | /* Enable Async reset bit for HCLK CE1 */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 273 | writel((1<<7) | (1 << 4), CE1_HCLK_CTL_REG); |
Deepa Dinamani | 3467b71 | 2012-02-10 14:56:06 -0800 | [diff] [blame] | 274 | /* Enable Async reset bit for core clk for CE1 */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 275 | writel((1<<7) | (1 << 4), CE1_CORE_CLK_CTL_REG); |
Deepa Dinamani | 3467b71 | 2012-02-10 14:56:06 -0800 | [diff] [blame] | 276 | |
| 277 | /* Add a small delay between switching the |
| 278 | * async intput from high to low |
| 279 | */ |
| 280 | udelay(2); |
| 281 | |
| 282 | /* Disable Async reset bit for HCLK for CE1 */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 283 | writel((1 << 4), CE1_HCLK_CTL_REG); |
Deepa Dinamani | 3467b71 | 2012-02-10 14:56:06 -0800 | [diff] [blame] | 284 | /* Disable Async reset bit for core clk for CE1 */ |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 285 | writel((1 << 4), CE1_CORE_CLK_CTL_REG); |
Deepa Dinamani | 3467b71 | 2012-02-10 14:56:06 -0800 | [diff] [blame] | 286 | |
| 287 | return; |
| 288 | } |
| 289 | |