| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 29 | #ifndef _PLATFORM_MSM8994_IOMAP_H_ |
| 30 | #define _PLATFORM_MSM8994_IOMAP_H_ |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 31 | |
| Channagoud Kadabi | 4983cf0 | 2014-05-06 17:34:52 -0700 | [diff] [blame] | 32 | #define MSM_SHARED_BASE 0x06A00000 |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 33 | |
| 34 | #define MSM_IOMAP_BASE 0xF9000000 |
| 35 | #define MSM_IOMAP_END 0xFEFFFFFF |
| 36 | |
| 37 | #define SYSTEM_IMEM_BASE 0xFE800000 |
| 38 | #define MSM_SHARED_IMEM_BASE 0xFE87F000 |
| 39 | #define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C) |
| 40 | |
| 41 | #define BS_INFO_OFFSET (0x6B0) |
| 42 | #define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET) |
| 43 | |
| 44 | |
| 45 | #define KPSS_BASE 0xF9000000 |
| 46 | |
| 47 | #define MSM_GIC_DIST_BASE KPSS_BASE |
| 48 | #define MSM_GIC_CPU_BASE (KPSS_BASE + 0x00002000) |
| 49 | #define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000) |
| 50 | #define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000) |
| 51 | #define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000) |
| 52 | #define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000) |
| 53 | #define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000) |
| 54 | #define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000) |
| Sundarajan Srinivasan | 19b95c7 | 2014-07-24 16:37:04 -0700 | [diff] [blame] | 55 | #define APCS_ALIAS0_IPC_INTERRUPT (KPSS_BASE + 0x0000D008) |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 56 | #define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE |
| 57 | |
| 58 | #define PERIPH_SS_BASE 0xF9800000 |
| 59 | |
| 60 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
| 61 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
| 62 | #define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000) |
| 63 | #define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
| 64 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
| 65 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900) |
| 66 | #define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000) |
| 67 | #define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900) |
| 68 | |
| 69 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000) |
| 70 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000) |
| 71 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000) |
| 72 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000) |
| 73 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000) |
| 74 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000) |
| 75 | |
| 76 | #define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x0015E000) |
| 77 | |
| 78 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
| Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 79 | #define USB2_PHY_SEL 0xFD4AB000 |
| 80 | |
| 81 | /* QUSB2 PHY */ |
| 82 | #define QUSB2_PHY_BASE (PERIPH_SS_BASE + 0x00339000) |
| 83 | |
| 84 | #define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4) |
| Tanya Finkel | 1fa8fe1 | 2014-08-07 15:07:25 +0300 | [diff] [blame] | 85 | #define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4) |
| 86 | #define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080) |
| 87 | #define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084) |
| 88 | #define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088) |
| 89 | #define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C) |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 90 | |
| Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 91 | #define MSM_USB30_BASE 0xF9200000 |
| 92 | #define MSM_USB30_QSCRATCH_BASE 0xF92F8800 |
| 93 | |
| 94 | /* SS QMP (Qulacomm Multi Protocol) */ |
| 95 | #define QMP_PHY_BASE 0xF9B38000 |
| 96 | |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 97 | /* Clocks */ |
| 98 | #define CLK_CTL_BASE 0xFC400000 |
| 99 | |
| 100 | /* GPLL */ |
| 101 | #define GPLL0_MODE (CLK_CTL_BASE + 0x0000) |
| 102 | #define GPLL4_MODE (CLK_CTL_BASE + 0x1DC0) |
| 103 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
| 104 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484) |
| 105 | |
| 106 | /* UART */ |
| 107 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4) |
| 108 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704) |
| 109 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C) |
| 110 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710) |
| 111 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714) |
| 112 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718) |
| 113 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C) |
| 114 | #define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944) |
| 115 | #define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0xA44) |
| 116 | #define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0xA4C) |
| 117 | #define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0xA50) |
| 118 | #define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0xA54) |
| 119 | #define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0xA58) |
| 120 | #define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0xA5C) |
| 121 | |
| 122 | /* USB */ |
| 123 | #define USB_HS_BCR (CLK_CTL_BASE + 0x480) |
| 124 | |
| 125 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 126 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 127 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 128 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 129 | |
| Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 130 | /* USB3 clocks */ |
| 131 | #define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0x03FC) |
| 132 | #define USB2B_PHY_SLEEP_CBCR (CLK_CTL_BASE + 0x04AC) |
| 133 | #define USB2B_PHY_BCR (CLK_CTL_BASE + 0x04A8) |
| 134 | #define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0x03D4) |
| 135 | #define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0x03D8) |
| 136 | #define USB30_MASTER_M (CLK_CTL_BASE + 0x03DC) |
| 137 | #define USB30_MASTER_N (CLK_CTL_BASE + 0x03E0) |
| 138 | #define USB30_MASTER_D (CLK_CTL_BASE + 0x03E4) |
| 139 | #define USB30_MASTER_CBCR (CLK_CTL_BASE + 0x03C8) |
| 140 | #define USB_30_BCR (CLK_CTL_BASE + 0x03C0) |
| 141 | #define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0x03E8) |
| 142 | #define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0x03EC) |
| 143 | #define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0x03D0) |
| 144 | #define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0x03CC) |
| 145 | #define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x1414) |
| 146 | #define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x1418) |
| 147 | #define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x1408) |
| 148 | #define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x140C) |
| 149 | #define USB30_PHY_BCR (CLK_CTL_BASE + 0x1400) |
| 150 | #define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x1404) |
| 151 | #define GCC_USB30_GDSCR (CLK_CTL_BASE + 0x03C4) |
| Sundarajan Srinivasan | 0ebf2fc | 2014-04-23 16:45:18 -0700 | [diff] [blame] | 152 | #define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x04B8) |
| Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 153 | #define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x1A84) |
| Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 154 | |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 155 | /* SDCC */ |
| 156 | #define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */ |
| 157 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */ |
| 158 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8) |
| 159 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */ |
| 160 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */ |
| 161 | #define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */ |
| 162 | #define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */ |
| 163 | #define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */ |
| 164 | |
| 165 | /* SDCC3 */ |
| 166 | #define SDCC3_BCR (CLK_CTL_BASE + 0x540) /* block reset */ |
| 167 | #define SDCC3_APPS_CBCR (CLK_CTL_BASE + 0x544) /* branch control */ |
| 168 | #define SDCC3_AHB_CBCR (CLK_CTL_BASE + 0x548) |
| 169 | #define SDCC3_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x54C) |
| 170 | #define SDCC3_CMD_RCGR (CLK_CTL_BASE + 0x550) /* cmd */ |
| 171 | #define SDCC3_CFG_RCGR (CLK_CTL_BASE + 0x554) /* cfg */ |
| 172 | #define SDCC3_M (CLK_CTL_BASE + 0x558) /* m */ |
| 173 | #define SDCC3_N (CLK_CTL_BASE + 0x55C) /* n */ |
| 174 | #define SDCC3_D (CLK_CTL_BASE + 0x560) /* d */ |
| 175 | |
| 176 | |
| 177 | #define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780) |
| 178 | |
| 179 | #define UFS_BASE (0xFC590000 + 0x00004000) |
| 180 | |
| 181 | #define SPMI_BASE 0xFC4C0000 |
| 182 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 183 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
| 184 | |
| Channagoud Kadabi | 27ff934 | 2014-06-16 11:19:29 -0700 | [diff] [blame] | 185 | #define MSM_CE2_BAM_BASE 0xFD444000 |
| 186 | #define MSM_CE2_BASE 0xFD45A000 |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 187 | |
| 188 | #define TLMM_BASE_ADDR 0xFD510000 |
| 189 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) |
| 190 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) |
| 191 | |
| 192 | #define MPM2_MPM_CTRL_BASE 0xFC4A1000 |
| 193 | #define MPM2_MPM_PS_HOLD 0xFC4AB000 |
| 194 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
| 195 | |
| 196 | /* DRV strength for sdcc */ |
| 197 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044) |
| 198 | |
| 199 | /* SDHCI */ |
| 200 | #define SDCC_MCI_HC_MODE (0x00000078) |
| 201 | #define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC) |
| 202 | #define SDCC_HC_PWRCTL_MASK_REG (0x000000E0) |
| 203 | #define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4) |
| 204 | #define SDCC_HC_PWRCTL_CTL_REG (0x000000E8) |
| 205 | |
| 206 | /* Boot config */ |
| 207 | #define SEC_CTRL_CORE_BASE 0xFC4B8000 |
| 208 | #define BOOT_CONFIG_OFFSET 0x00006034 |
| 209 | #define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE+BOOT_CONFIG_OFFSET) |
| 210 | |
| 211 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
| 212 | |
| Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 213 | #define TCSR_PHSS_USB2_PHY_SEL 0xFD4AB000 |
| 214 | #define PLATFORM_QMP_OFFSET 0x8 |
| 215 | |
| Channagoud Kadabi | 9e57488 | 2014-06-24 16:15:23 -0700 | [diff] [blame] | 216 | #define SMEM_TARG_INFO_ADDR 0xFE805FF0 |
| Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame] | 217 | |
| Dhaval Patel | ddce301 | 2014-08-12 14:08:31 -0700 | [diff] [blame] | 218 | /* MDSS */ |
| 219 | #define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000 |
| Channagoud Kadabi | 5f42b27 | 2014-08-21 18:40:39 -0700 | [diff] [blame^] | 220 | #define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x502C) |
| Dhaval Patel | ddce301 | 2014-08-12 14:08:31 -0700 | [diff] [blame] | 221 | #define MIPI_DSI_BASE (0xFD998000) |
| 222 | #define MIPI_DSI0_BASE (MIPI_DSI_BASE) |
| 223 | #define MIPI_DSI1_BASE (0xFD9A0000) |
| 224 | #define DSI0_PHY_BASE (0xFD998500) |
| 225 | #define DSI1_PHY_BASE (0xFD9A0500) |
| 226 | #define DSI0_PLL_BASE (0xFD998300) |
| 227 | #define DSI1_PLL_BASE (0xFD9A0300) |
| 228 | #define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off)) |
| 229 | |
| 230 | #define MDP_BASE (0xfd900000) |
| 231 | |
| 232 | #define REG_MDP(off) (MDP_BASE + (off)) |
| 233 | #define MDP_HW_REV REG_MDP(0x1000) |
| 234 | #define MDP_INTR_EN REG_MDP(0x1010) |
| 235 | #define MDP_INTR_CLEAR REG_MDP(0x1018) |
| 236 | #define MDP_HIST_INTR_EN REG_MDP(0x101C) |
| 237 | |
| 238 | #define MDP_DISP_INTF_SEL REG_MDP(0x1004) |
| 239 | #define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0) |
| 240 | #define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC) |
| 241 | #define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8) |
| 242 | |
| 243 | #define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000) |
| 244 | #define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800) |
| 245 | |
| 246 | #define MDP_CTL_0_BASE REG_MDP(0x2000) |
| 247 | #define MDP_CTL_1_BASE REG_MDP(0x2200) |
| 248 | |
| 249 | #define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4) |
| 250 | #define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8) |
| 251 | #define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0) |
| 252 | |
| 253 | /* can not find following two registers */ |
| 254 | #define MDP_REG_PPB0_CNTL REG_MDP(0x1420) |
| 255 | #define MDP_REG_PPB0_CONFIG REG_MDP(0x1424) |
| 256 | |
| 257 | #define MDP_INTF_0_BASE REG_MDP(0x6b000) |
| 258 | #define MDP_INTF_1_BASE REG_MDP(0x6b800) |
| 259 | #define MDP_INTF_2_BASE REG_MDP(0x6c000) |
| 260 | |
| 261 | |
| 262 | #define MDP_CLK_CTRL0 REG_MDP(0x12AC) |
| 263 | #define MDP_CLK_CTRL1 REG_MDP(0x12B4) |
| 264 | #define MDP_CLK_CTRL2 REG_MDP(0x12BC) |
| 265 | #define MDP_CLK_CTRL3 REG_MDP(0x13A8) |
| 266 | #define MDP_CLK_CTRL4 REG_MDP(0x13B0) |
| 267 | #define MDP_CLK_CTRL5 REG_MDP(0x13B8) |
| 268 | #define MDP_CLK_CTRL6 REG_MDP(0x12C4) |
| 269 | #define MDP_CLK_CTRL7 REG_MDP(0x13D0) |
| 270 | |
| 271 | #define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080) |
| 272 | #define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130) |
| 273 | |
| 274 | #define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x13d8) |
| 275 | #define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x13dc) |
| 276 | |
| 277 | #define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004) |
| 278 | #define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8) |
| 279 | #define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0) |
| 280 | #define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124) |
| 281 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160) |
| 282 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164) |
| 283 | #define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178) |
| 284 | #define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C) |
| 285 | #define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0) |
| 286 | #define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4) |
| 287 | #define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xc80B8) |
| 288 | #define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xc80BC) |
| 289 | #define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0) |
| 290 | #define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4) |
| 291 | #define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xc80C8) |
| 292 | #define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xc80CC) |
| 293 | #define VBIF_VBIF_ABIT_SHORT REG_MDP(0xc8070) |
| 294 | #define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xc8074) |
| 295 | #define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xc80A8) |
| 296 | |
| 297 | #define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000) |
| 298 | #define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000) |
| 299 | #define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000) |
| 300 | #define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000) |
| 301 | #define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000) |
| 302 | #define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000) |
| 303 | #define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000) |
| 304 | #define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000) |
| 305 | |
| 306 | #define DMA_CMD_OFFSET 0x048 |
| 307 | #define DMA_CMD_LENGTH 0x04C |
| 308 | |
| 309 | #define INT_CTRL 0x110 |
| 310 | #define CMD_MODE_DMA_SW_TRIGGER 0x090 |
| 311 | |
| 312 | #define EOT_PACKET_CTRL 0x0CC |
| 313 | #define MISR_CMD_CTRL 0x0A0 |
| 314 | #define MISR_VIDEO_CTRL 0x0A4 |
| 315 | #define VIDEO_MODE_CTRL 0x010 |
| 316 | #define HS_TIMER_CTRL 0x0BC |
| Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame] | 317 | |
| 318 | #define SOFT_RESET 0x118 |
| 319 | #define CLK_CTRL 0x11C |
| 320 | #define TRIG_CTRL 0x084 |
| 321 | #define CTRL 0x004 |
| 322 | #define COMMAND_MODE_DMA_CTRL 0x03C |
| 323 | #define COMMAND_MODE_MDP_CTRL 0x040 |
| 324 | #define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044 |
| 325 | #define COMMAND_MODE_MDP_STREAM0_CTRL 0x058 |
| 326 | #define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C |
| 327 | #define COMMAND_MODE_MDP_STREAM1_CTRL 0x060 |
| 328 | #define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064 |
| 329 | #define ERR_INT_MASK0 0x10C |
| 330 | |
| 331 | #define LANE_SWAP_CTL 0x0B0 |
| 332 | #define TIMING_CTL 0x0C4 |
| 333 | |
| 334 | #define VIDEO_MODE_ACTIVE_H 0x024 |
| 335 | #define VIDEO_MODE_ACTIVE_V 0x028 |
| 336 | #define VIDEO_MODE_TOTAL 0x02C |
| 337 | #define VIDEO_MODE_HSYNC 0x030 |
| 338 | #define VIDEO_MODE_VSYNC 0x034 |
| 339 | #define VIDEO_MODE_VSYNC_VPOS 0x038 |
| 340 | |
| Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 341 | #endif |