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gerrit-public.fairphone.software / kernel / lk / 77346f7b4c86d114e6689000a04dcd509ccd86f6 / . / platform / msm8996 / include / platform / iomap.h
blob: d3ba81afba439da0d699f970bb858eb92395e2c1 [file] [log] [blame]
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_THULIUM_IOMAP_H_
30#define _PLATFORM_THULIUM_IOMAP_H_
31
32#define MSM_SHARED_BASE 0x86000000
33
34#define MSM_IOMAP_HMSS_START 0x09800000
35
36#define MSM_IOMAP_BASE 0x00000000
37#define MSM_IOMAP_END 0x10000000
38
39#define MSM_SHARED_IMEM_BASE 0x066BF000
40#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]41#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + 0x6B0)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]42
43#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
44#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
45
46#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
47#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
48
Sridhar Parasurambe12c3d2015-01-16 13:42:26 -0800[diff] [blame]49#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS 0x00068000
50#define RPM_SS_MSG_RAM_START_ADDRESS_BASE RPM_SS_MSG_RAM_START_ADDRESS_BASE_PHYS
51#define RPM_SS_MSG_RAM_START_ADDRESS_BASE_SIZE 0x00006000
52
Sridhar Parasuram103702f2015-01-26 18:07:55 -0800[diff] [blame]53#define APCS_HLOS_IPC_INTERRUPT_0 0x9820010
54
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]55#define PERIPH_SS_BASE 0x07400000
56
57#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
58#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
59#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
60#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
61
62#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
63#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
64#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
65#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
66#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
67#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
68
69#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
70
71/* USB3.0 */
72#define MSM_USB30_BASE 0x6A00000
73#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
74/* SS QMP (Qulacomm Multi Protocol) */
75#define QMP_PHY_BASE 0x7410000
76
77/* QUSB2 PHY */
78#define QUSB2_PHY_BASE 0x7411000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]79#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]80
Channagoud Kadabi4517eb12015-09-02 18:43:13 -0700[diff] [blame]81#define AHB2_PHY_BASE 0x7416000
82#define PERIPH_SS_AHB2PHY_TOP_CFG (AHB2_PHY_BASE + 0x10)
83
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]84/* Clocks */
85#define CLK_CTL_BASE 0x300000
86
87/* GPLL */
88#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
89#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
90#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
91#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
92
93/* UART Clocks */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]94#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x25004)
95#define BLSP2_UART2_APPS_CBCR (CLK_CTL_BASE + 0x29004)
Channagoud Kadabi35503c42014-11-14 16:22:43 -0800[diff] [blame]96#define BLSP2_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x2900C)
97#define BLSP2_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x29010)
98#define BLSP2_UART2_APPS_M (CLK_CTL_BASE + 0x29014)
99#define BLSP2_UART2_APPS_N (CLK_CTL_BASE + 0x29018)
100#define BLSP2_UART2_APPS_D (CLK_CTL_BASE + 0x2901C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]101
102/* USB3 clocks */
103#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]104#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]105#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]106#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
107#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]108#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
109#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
110#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
111#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
112#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]113#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF028)
114#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF02C)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]115#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
116
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]117#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
118#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
119#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
120#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
121#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
122#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]123#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
Channagoud Kadabidf233d22015-02-11 11:56:48 -0800[diff] [blame]124#define GCC_AGGRE2_USB3_AXI_CBCR (CLK_CTL_BASE + 0x83018)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]125
126/* SDCC */
127#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
128#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
129#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
130#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
131#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
132#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
133#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
134#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
135
136/* SDCC2 */
137#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
138#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
139#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
140#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
141#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
142#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
143#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
144#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
145
146#define UFS_BASE 0x624000
147
148#define SPMI_BASE 0x4000000
149#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
150#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
Channagoud Kadabi7b20dea2014-11-11 13:27:33 -0800[diff] [blame]151#define PMIC_ARB_CORE 0x400F000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]152
Channagoud Kadabi037c8b82015-02-05 12:09:32 -0800[diff] [blame]153#define MSM_CE_BAM_BASE 0x644000
154#define MSM_CE_BASE 0x67A000
155#define GCC_CE1_BCR (CLK_CTL_BASE + 0x00041000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]156
157#define TLMM_BASE_ADDR 0x1010000
158#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
159#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
160
161#define MPM2_MPM_CTRL_BASE 0x4A1000
162#define MPM2_MPM_PS_HOLD 0x4AB000
163#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
164
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]165/* QSEECOM: Secure app region notification */
166#define APP_REGION_ADDR 0x86600000
Zhen Kong327fac52015-06-12 17:04:24 -0700[diff] [blame]167#define APP_REGION_SIZE 0x2200000
Dinesh K Garg6bbbb702015-01-30 11:13:31 -0800[diff] [blame]168
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]169/* DRV strength for sdcc */
Channagoud Kadabi99d23702015-02-02 20:52:17 -0800[diff] [blame]170#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0012C000)
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]171
172/* SDHCI - power control registers */
173#define SDCC_MCI_HC_MODE (0x00000078)
174#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
175#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
176#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
177#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
178
179/* Boot config */
180#define SEC_CTRL_CORE_BASE 0x70000
181#define BOOT_CONFIG_OFFSET 0x00006044
182#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
183
Channagoud Kadabi652a6f62014-11-17 17:23:23 -0800[diff] [blame]184/* QMP rev registers */
185#define USB3_PHY_REVISION_ID0 (QMP_PHY_BASE + 0x788)
186#define USB3_PHY_REVISION_ID1 (QMP_PHY_BASE + 0x78C)
187#define USB3_PHY_REVISION_ID2 (QMP_PHY_BASE + 0x790)
188#define USB3_PHY_REVISION_ID3 (QMP_PHY_BASE + 0x794)
189
190/* Dummy macro needed for compilation only */
191#define PLATFORM_QMP_OFFSET 0x0
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]192
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]193/* RPMB send receive buffer needs to be mapped
194 * as device memory, define the start address
195 * and size in MB
196 */
Channagoud Kadabi7dccf842015-08-11 16:21:40 -0700[diff] [blame]197#define RPMB_SND_RCV_BUF 0x91400000
Channagoud Kadabi428a2132015-06-17 17:32:01 -0700[diff] [blame]198#define RPMB_SND_RCV_BUF_SZ 0x2
Channagoud Kadabi2bab29b2015-02-11 13:26:03 -0800[diff] [blame]199
Channagoud Kadabi23edc0c2015-03-27 18:31:32 -0700[diff] [blame]200#define TCSR_BOOT_MISC_DETECT 0x007B3000
Dhaval Patel0f3cbeb2015-03-17 11:52:12 -0700[diff] [blame]201
202#define MSM_MMSS_CLK_CTL_BASE 0x8C0000
203#define MMSS_MISC_AHB_CBCR (MSM_MMSS_CLK_CTL_BASE + 0x5018)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]204
205#define MIPI_DSI_BASE (0x994000)
206#define MIPI_DSI0_BASE (MIPI_DSI_BASE)
207#define MIPI_DSI1_BASE (0x996000)
208#define DSI0_PHY_BASE (0x994400)
209#define DSI1_PHY_BASE (0x996400)
210#define DSI0_PLL_BASE (0x994800)
211#define DSI1_PLL_BASE (0x996800)
212#define DSI0_REGULATOR_BASE (0x994000)
213#define DSI1_REGULATOR_BASE (0x996000)
214
215#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
216#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
217
218#define MDP_BASE (0x900000)
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]219#define REG_MDP(off) (MDP_BASE + (off))
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]220
221#ifdef MDP_PP_0_BASE
222#undef MDP_PP_0_BASE
223#endif
224#define MDP_PP_0_BASE REG_MDP(0x71000)
225
226#ifdef MDP_PP_1_BASE
227#undef MDP_PP_1_BASE
228#endif
229#define MDP_PP_1_BASE REG_MDP(0x71800)
230
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]231#define MDP_DSC_0_BASE REG_MDP(0x81000)
232#define MDP_DSC_1_BASE REG_MDP(0x81400)
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]233
234#ifdef MDP_HW_REV
235#undef MDP_HW_REV
236#endif
237#define MDP_HW_REV REG_MDP(0x1000)
238
239#ifdef MDP_INTR_EN
240#undef MDP_INTR_EN
241#endif
242#define MDP_INTR_EN REG_MDP(0x1010)
243
244#ifdef MDP_INTR_CLEAR
245#undef MDP_INTR_CLEAR
246#endif
247#define MDP_INTR_CLEAR REG_MDP(0x1018)
248
249#ifdef MDP_HIST_INTR_EN
250#undef MDP_HIST_INTR_EN
251#endif
252#define MDP_HIST_INTR_EN REG_MDP(0x101C)
253
254#ifdef MDP_DISP_INTF_SEL
255#undef MDP_DISP_INTF_SEL
256#endif
257#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
258
259#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
260#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
261#endif
262#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
263
264#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
265#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
266#endif
267#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
268
269#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
270#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
271#endif
272#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
273
274#ifdef MDP_INTF_0_TIMING_ENGINE_EN
275#undef MDP_INTF_0_TIMING_ENGINE_EN
276#endif
277#define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x6b000)
278
279#ifdef MDP_INTF_1_TIMING_ENGINE_EN
280#undef MDP_INTF_1_TIMING_ENGINE_EN
281#endif
282#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x6b800)
283
284#ifdef MDP_INTF_2_TIMING_ENGINE_EN
285#undef MDP_INTF_2_TIMING_ENGINE_EN
286#endif
287#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x6C000)
288
289#ifdef MDP_CTL_0_BASE
290#undef MDP_CTL_0_BASE
291#endif
292#define MDP_CTL_0_BASE REG_MDP(0x2000)
293
294#ifdef MDP_CTL_1_BASE
295#undef MDP_CTL_1_BASE
296#endif
297#define MDP_CTL_1_BASE REG_MDP(0x2200)
298
299#ifdef MDP_REG_SPLIT_DISPLAY_EN
300#undef MDP_REG_SPLIT_DISPLAY_EN
301#endif
302#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
303
304#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
305#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
306#endif
307#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
308
309#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
310#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
311#endif
312#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
313
314#ifdef MDP_INTF_0_BASE
315#undef MDP_INTF_0_BASE
316#endif
317#define MDP_INTF_0_BASE REG_MDP(0x6b000)
318
319#ifdef MDP_INTF_1_BASE
320#undef MDP_INTF_1_BASE
321#endif
322#define MDP_INTF_1_BASE REG_MDP(0x6b800)
323
324#ifdef MDP_INTF_2_BASE
325#undef MDP_INTF_2_BASE
326#endif
327#define MDP_INTF_2_BASE REG_MDP(0x6c000)
328
329#ifdef MDP_CLK_CTRL0
330#undef MDP_CLK_CTRL0
331#endif
332#define MDP_CLK_CTRL0 REG_MDP(0x12AC)
333
334#ifdef MDP_CLK_CTRL1
335#undef MDP_CLK_CTRL1
336#endif
337#define MDP_CLK_CTRL1 REG_MDP(0x12B4)
338
339#ifdef MDP_CLK_CTRL2
340#undef MDP_CLK_CTRL2
341#endif
342#define MDP_CLK_CTRL2 REG_MDP(0x12BC)
343
344#ifdef MDP_CLK_CTRL3
345#undef MDP_CLK_CTRL3
346#endif
347#define MDP_CLK_CTRL3 REG_MDP(0x13A8)
348
349#ifdef MDP_CLK_CTRL4
350#undef MDP_CLK_CTRL4
351#endif
352#define MDP_CLK_CTRL4 REG_MDP(0x13B0)
353
354#ifdef MDP_CLK_CTRL5
355#undef MDP_CLK_CTRL5
356#endif
357#define MDP_CLK_CTRL5 REG_MDP(0x13B8)
358
359#ifdef MDP_CLK_CTRL6
360#undef MDP_CLK_CTRL6
361#endif
362#define MDP_CLK_CTRL6 REG_MDP(0x12C4)
363
364#ifdef MDP_CLK_CTRL7
365#undef MDP_CLK_CTRL7
366#endif
367#define MDP_CLK_CTRL7 REG_MDP(0x13D0)
368
369#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
370#undef MMSS_MDP_SMP_ALLOC_W_BASE
371#endif
372#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
373
374#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
375#undef MMSS_MDP_SMP_ALLOC_R_BASE
376#endif
377#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
378
379#ifdef MDP_QOS_REMAPPER_CLASS_0
380#undef MDP_QOS_REMAPPER_CLASS_0
381#endif
382#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
383
384#ifdef MDP_QOS_REMAPPER_CLASS_1
385#undef MDP_QOS_REMAPPER_CLASS_1
386#endif
387#define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x11E4)
388
389#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
390#undef VBIF_VBIF_DDR_FORCE_CLK_ON
391#endif
392#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xb0004)
393
394#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
395#undef VBIF_VBIF_DDR_OUT_MAX_BURST
396#endif
397#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xb00D8)
398
399#ifdef VBIF_VBIF_DDR_ARB_CTRL
400#undef VBIF_VBIF_DDR_ARB_CTRL
401#endif
402#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xb00F0)
403
404#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
405#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
406#endif
407#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xb0124)
408
409#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
410#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
411#endif
412#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xb0160)
413
414#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
415#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
416#endif
417#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xb0164)
418
419#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
420#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
421#endif
422#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xb0178)
423
424#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
425#undef VBIF_VBIF_DDR_OUT_AX_AOOO
426#endif
427#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xb017C)
428
429#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
430#undef VBIF_VBIF_IN_RD_LIM_CONF0
431#endif
432#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xb00B0)
433
434#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
435#undef VBIF_VBIF_IN_RD_LIM_CONF1
436#endif
437#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xb00B4)
438
439#ifdef VBIF_VBIF_IN_RD_LIM_CONF2
440#undef VBIF_VBIF_IN_RD_LIM_CONF2
441#endif
442#define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0xb00B8)
443
444#ifdef VBIF_VBIF_IN_RD_LIM_CONF3
445#undef VBIF_VBIF_IN_RD_LIM_CONF3
446#endif
447#define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0xb00BC)
448
449#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
450#undef VBIF_VBIF_IN_WR_LIM_CONF0
451#endif
452#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xb00C0)
453
454#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
455#undef VBIF_VBIF_IN_WR_LIM_CONF1
456#endif
457#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xb00C4)
458
459#ifdef VBIF_VBIF_IN_WR_LIM_CONF2
460#undef VBIF_VBIF_IN_WR_LIM_CONF2
461#endif
462#define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0xb00C8)
463
464#ifdef VBIF_VBIF_IN_WR_LIM_CONF3
465#undef VBIF_VBIF_IN_WR_LIM_CONF3
466#endif
467#define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0xb00CC)
468
469#ifdef VBIF_VBIF_ABIT_SHORT
470#undef VBIF_VBIF_ABIT_SHORT
471#endif
472#define VBIF_VBIF_ABIT_SHORT REG_MDP(0xb0070)
473
474#ifdef VBIF_VBIF_ABIT_SHORT_CONF
475#undef VBIF_VBIF_ABIT_SHORT_CONF
476#endif
477#define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0xb0074)
478
479#ifdef VBIF_VBIF_GATE_OFF_WRREQ_EN
480#undef VBIF_VBIF_GATE_OFF_WRREQ_EN
481#endif
482#define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0xb00A8)
483
484#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
485#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
486#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
487#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
488#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
489#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
490#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
491#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
492
493#define DMA_CMD_OFFSET 0x048
494#define DMA_CMD_LENGTH 0x04C
495
496#define INT_CTRL 0x110
497#define CMD_MODE_DMA_SW_TRIGGER 0x090
498
499#define EOT_PACKET_CTRL 0x0CC
500#define MISR_CMD_CTRL 0x0A0
501#define MISR_VIDEO_CTRL 0x0A4
502#define VIDEO_MODE_CTRL 0x010
503#define HS_TIMER_CTRL 0x0BC
504
505#define SOFT_RESET 0x118
506#define CLK_CTRL 0x11C
507#define TRIG_CTRL 0x084
508#define CTRL 0x004
509#define COMMAND_MODE_DMA_CTRL 0x03C
510#define COMMAND_MODE_MDP_CTRL 0x040
511#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
512#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
513#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
514#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
515#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
516#define ERR_INT_MASK0 0x10C
517
518#define LANE_CTL 0x0AC
519#define LANE_SWAP_CTL 0x0B0
520#define TIMING_CTL 0x0C4
521
522#define VIDEO_MODE_ACTIVE_H 0x024
523#define VIDEO_MODE_ACTIVE_V 0x028
524#define VIDEO_MODE_TOTAL 0x02C
525#define VIDEO_MODE_HSYNC 0x030
526#define VIDEO_MODE_VSYNC 0x034
527#define VIDEO_MODE_VSYNC_VPOS 0x038
528
Kuogee Hsiehd58c8092015-07-07 10:31:34 -0700[diff] [blame]529#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
530#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
531#define CMD_COMPRESSION_MODE_CTRL 0x2A8
532#define CMD_COMPRESSION_MODE_CTRL_2 0x2Ac
533#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
534
Dhaval Patel87eefaa2015-03-16 11:13:41 -0700[diff] [blame]535#define QPNP_LED_CTRL_BASE 0xD000
536#define QPNP_BLUE_LPG_CTRL_BASE 0xB100
537#define QPNP_GREEN_LPG_CTRL_BASE 0xB200
538#define QPNP_RED_LPG_CTRL_BASE 0xB300
539
Channagoud Kadabi2324bd52015-07-13 15:02:20 -0700[diff] [blame]540#define APSS_WDOG_BASE 0x9830000
541#define APPS_WDOG_BARK_VAL_REG (APSS_WDOG_BASE + 0x10)
542#define APPS_WDOG_BITE_VAL_REG (APSS_WDOG_BASE + 0x14)
543#define APPS_WDOG_RESET_REG (APSS_WDOG_BASE + 0x04)
544#define APPS_WDOG_CTL_REG (APSS_WDOG_BASE + 0x08)
545
546#define DDR_START platform_get_ddr_start()
547#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
548#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2200000
549#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x2000000
550#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
Channagoud Kadabied60a8b2014-06-27 15:35:09 -0700[diff] [blame]551#endif