blob: c650f7fa88fa6cfec7f2d301b777acd115f9920b [file] [log] [blame]
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +05301/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <reg.h>
32#include <target.h>
33#include <platform.h>
34#include <uart_dm.h>
35#include <mmc.h>
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080036#include <platform/gpio.h>
37#include <dev/keys.h>
38#include <spmi_v2.h>
39#include <pm8x41.h>
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053040#include <board.h>
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080041#include <baseband.h>
42#include <hsusb.h>
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +053043#include <scm.h>
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080044#include <platform/gpio.h>
45#include <platform/gpio.h>
46#include <platform/irqs.h>
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053047
Matthew Qinf3ebf182014-04-08 11:38:14 +080048#if LONG_PRESS_POWER_ON
49#include <shutdown_detect.h>
50#endif
51
Matthew Qin7f5ab932014-04-08 15:25:54 +080052#if PON_VIB_SUPPORT
53#include <vibrator.h>
54#endif
55
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053056#define PMIC_ARB_CHANNEL_NUM 0
57#define PMIC_ARB_OWNER_ID 0
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080058#define TLMM_VOL_UP_BTN_GPIO 107
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053059
Matthew Qin7f5ab932014-04-08 15:25:54 +080060#if PON_VIB_SUPPORT
61#define VIBRATE_TIME 250
62#endif
63
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +053064#define FASTBOOT_MODE 0x77665500
65
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080066static void set_sdc_power_ctrl(void);
67
68struct mmc_device *dev;
69
70static uint32_t mmc_pwrctl_base[] =
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053071 { MSM_SDC1_BASE, MSM_SDC2_BASE };
72
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080073static uint32_t mmc_sdhci_base[] =
74 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
75
76static uint32_t mmc_sdc_pwrctl_irq[] =
77 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
78
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053079void target_early_init(void)
80{
81#if WITH_DEBUG_UART
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080082 uart_dm_init(2, 0, BLSP1_UART1_BASE);
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053083#endif
84}
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080085
86void target_sdc_init()
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053087{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080088 struct mmc_config_data config;
89
90 /* Set drive strength & pull ctrl values */
91 set_sdc_power_ctrl();
92
93 config.bus_width = DATA_BUS_WIDTH_8BIT;
Aparna Mallavarapu53b09402014-03-26 14:46:43 +053094 config.max_clk_rate = MMC_CLK_177MHZ;
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080095
96 /* Try slot 1*/
97 config.slot = 1;
98 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
99 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
100 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
101 config.hs400_support = 0;
102
103 if (!(dev = mmc_init(&config))) {
104 /* Try slot 2 */
105 config.slot = 2;
Aparna Mallavarapu53b09402014-03-26 14:46:43 +0530106 config.max_clk_rate = MMC_CLK_200MHZ;
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800107 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
108 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
109 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
110
111 if (!(dev = mmc_init(&config))) {
112 dprintf(CRITICAL, "mmc init failed!");
113 ASSERT(0);
114 }
115 }
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530116}
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800117
118void *target_mmc_device()
119{
120 return (void *) dev;
121}
122
123/* Return 1 if vol_up pressed */
124static int target_volume_up()
125{
126 uint8_t status = 0;
127
128 gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
129
130 /* Wait for the gpio config to take effect - debounce time */
131 thread_sleep(10);
132
133 /* Get status of GPIO */
134 status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
135
136 /* Active low signal. */
137 return !status;
138}
139
140/* Return 1 if vol_down pressed */
141uint32_t target_volume_down()
142{
143 /* Volume down button tied in with PMIC RESIN. */
144 return pm8x41_resin_status();
145}
146
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530147static void target_keystatus()
148{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800149 keys_init();
150
151 if(target_volume_down())
152 keys_post_event(KEY_VOLUMEDOWN, 1);
153
154 if(target_volume_up())
155 keys_post_event(KEY_VOLUMEUP, 1);
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530156}
157
158void target_init(void)
159{
160 uint32_t base_addr;
161 uint8_t slot;
162
163 dprintf(INFO, "target_init()\n");
164
165 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
166
167 target_keystatus();
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800168 set_sdc_power_ctrl();
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530169
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800170 target_sdc_init();
171 if (partition_read_table())
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530172 {
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800173 dprintf(CRITICAL, "Error reading the partition table info\n");
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530174 ASSERT(0);
175 }
Matthew Qinf3ebf182014-04-08 11:38:14 +0800176
177#if LONG_PRESS_POWER_ON
178 shutdown_detect();
179#endif
Matthew Qin7f5ab932014-04-08 15:25:54 +0800180
181#if PON_VIB_SUPPORT
182 /* turn on vibrator to indicate that phone is booting up to end user */
183 vib_timed_turn_on(VIBRATE_TIME);
184#endif
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530185}
186
187void target_serialno(unsigned char *buf)
188{
189 uint32_t serialno;
190 if (target_is_emmc_boot()) {
191 serialno = mmc_get_psn();
192 snprintf((char *)buf, 13, "%x", serialno);
193 }
194}
195
196unsigned board_machtype(void)
197{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800198 return LINUX_MACHTYPE_UNKNOWN;
199}
200
201unsigned check_reboot_mode(void)
202{
203 uint32_t restart_reason = 0;
204
205 /* Read reboot reason and scrub it */
206 restart_reason = readl(RESTART_REASON_ADDR);
207 writel(0x00, RESTART_REASON_ADDR);
208
209 return restart_reason;
210}
211
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +0530212static int scm_dload_mode(int mode)
213{
214 int ret = 0;
215 uint32_t dload_type;
216
217 dprintf(SPEW, "DLOAD mode: %d\n", mode);
218 if (mode == NORMAL_DLOAD)
219 dload_type = SCM_DLOAD_MODE;
220 else if(mode == EMERGENCY_DLOAD)
221 dload_type = SCM_EDLOAD_MODE;
222 else
223 dload_type = 0;
224
225 ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
226 if (ret)
227 dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
228
229 ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
230 if (ret)
231 dprintf(CRITICAL, "Failed to disable the wdog debug \n");
232
233 return ret;
234}
Matthew Qin6ba6ed12014-04-08 11:29:48 +0800235/* Configure PMIC and Drop PS_HOLD for shutdown */
236void shutdown_device()
237{
238 dprintf(CRITICAL, "Going down for shutdown.\n");
239
240 /* Configure PMIC for shutdown */
241 pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
242
243 /* Drop PS_HOLD for MSM */
244 writel(0x00, MPM2_MPM_PS_HOLD);
245
246 mdelay(5000);
247
248 dprintf(CRITICAL, "shutdown failed\n");
249
250 ASSERT(0);
251}
252
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800253void reboot_device(unsigned reboot_reason)
254{
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +0530255 uint8_t reset_type = 0;
256 uint32_t ret = 0;
257
258 /* Need to clear the SW_RESET_ENTRY register and
259 * write to the BOOT_MISC_REG for known reset cases
260 */
261 if(reboot_reason != DLOAD)
262 scm_dload_mode(NORMAL_MODE);
263
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800264 writel(reboot_reason, RESTART_REASON_ADDR);
265
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +0530266 /* For Reboot-bootloader and Dload cases do a warm reset
267 * For Reboot cases do a hard reset
268 */
269 if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD))
270 reset_type = PON_PSHOLD_WARM_RESET;
271 else
272 reset_type = PON_PSHOLD_HARD_RESET;
273
274 pm8x41_reset_configure(reset_type);
275
276 ret = scm_halt_pmic_arbiter();
277 if (ret)
278 dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret);
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800279
280 /* Drop PS_HOLD for MSM */
281 writel(0x00, MPM2_MPM_PS_HOLD);
282
283 mdelay(5000);
284
285 dprintf(CRITICAL, "Rebooting failed\n");
286}
287
288/* Detect the target type */
289void target_detect(struct board_data *board)
290{
291 /*
292 * already fill the board->target on board.c
293 */
294}
295
296void target_baseband_detect(struct board_data *board)
297{
298 uint32_t platform;
299
300 platform = board->platform;
301 switch(platform)
302 {
303 case MSM8916:
304 board->baseband = BASEBAND_MSM;
305 break;
306 default:
307 dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
308 ASSERT(0);
309 };
310}
311
312unsigned target_baseband()
313{
314 return board_baseband();
315}
316
317int emmc_recovery_init(void)
318{
319 return _emmc_recovery_init();
320}
321
322static void set_sdc_power_ctrl()
323{
324 /* Drive strength configs for sdc pins */
325 struct tlmm_cfgs sdc1_hdrv_cfg[] =
326 {
327 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
328 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
329 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
330 };
331
332 /* Pull configs for sdc pins */
333 struct tlmm_cfgs sdc1_pull_cfg[] =
334 {
335 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
336 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
337 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
338 };
339
340 /* Set the drive strength & pull control values */
341 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
342 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
343}
344
345void target_usb_init(void)
346{
347 uint32_t val;
348
349 /* Select and enable external configuration with USB PHY */
350 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
351
352 /* Enable sess_vld */
353 val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
354 writel(val, USB_GENCONFIG_2);
355
356 /* Enable external vbus configuration in the LINK */
357 val = readl(USB_USBCMD);
358 val |= SESS_VLD_CTRL;
359 writel(val, USB_USBCMD);
360}
361
Padmanabhan Komandurucd5645e2014-03-25 20:34:18 +0530362/* Returns 1 if target supports continuous splash screen. */
363int target_cont_splash_screen()
364{
365 uint8_t splash_screen = 0;
366 switch (board_hardware_id())
367 {
368 case HW_PLATFORM_MTP:
369 case HW_PLATFORM_SURF:
370 dprintf(SPEW, "Target_cont_splash=1\n");
371 splash_screen = 1;
372 break;
373 default:
374 dprintf(SPEW, "Target_cont_splash=0\n");
375 splash_screen = 0;
376 break;
377 }
378 return splash_screen;
379}
380
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800381void target_usb_stop(void)
382{
383 /* Disable VBUS mimicing in the controller. */
384 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
385}
386
387
388void target_uninit(void)
389{
Matthew Qin7f5ab932014-04-08 15:25:54 +0800390#if PON_VIB_SUPPORT
391 /* wait for the vibrator timer is expried */
392 wait_vib_timeout();
393#endif
394
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800395 mmc_put_card_to_sleep(dev);
396 sdhci_mode_disable(&dev->host);
397}
398
399/* Do any target specific intialization needed before entering fastboot mode */
400void target_fastboot_init(void)
401{
402 /* Set the BOOT_DONE flag in PM8916 */
403 pm8x41_set_boot_done();
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530404}
Aparna Mallavarapuacb6ede2014-03-21 19:22:00 +0530405
406int set_download_mode(enum dload_mode mode)
407{
408 int ret = 0;
409 ret = scm_dload_mode(mode);
410
411 pm8x41_clear_pmic_watchdog();
412
413 return ret;
414}