Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 1 | /* |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 2 | * * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | #ifndef __PLATFORM_MSM8X60_CLOCK_H |
| 30 | #define __PLATFORM_MSM8X60_CLOCK_H |
| 31 | |
Ajay Dudani | 8534b1a | 2011-01-26 11:35:39 -0800 | [diff] [blame] | 32 | #define MSM_MMSS_CLK_CTL_SIZE 4096 |
| 33 | #define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off)) |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 34 | |
| 35 | #define AHB_NS_REG REG_MM(0x0004) |
| 36 | #define AXI_NS_REG REG_MM(0x0014) |
| 37 | #define MM_PLL0_CONFIG_REG REG_MM(0x0310) |
| 38 | #define MM_PLL0_L_VAL_REG REG_MM(0x0304) |
| 39 | #define MM_PLL0_M_VAL_REG REG_MM(0x0308) |
| 40 | #define MM_PLL0_MODE_REG REG_MM(0x0300) |
| 41 | #define MM_PLL0_N_VAL_REG REG_MM(0x030C) |
| 42 | #define MM_PLL0_STATUS_REG REG_MM(0x0318) |
| 43 | #define MM_PLL1_CONFIG_REG REG_MM(0x032C) |
| 44 | #define MM_PLL1_L_VAL_REG REG_MM(0x0320) |
| 45 | #define MM_PLL1_M_VAL_REG REG_MM(0x0324) |
| 46 | #define MM_PLL1_MODE_REG REG_MM(0x031C) |
| 47 | #define MM_PLL1_N_VAL_REG REG_MM(0x0328) |
| 48 | #define MM_PLL1_STATUS_REG REG_MM(0x0334) |
| 49 | #define MM_PLL2_CONFIG_REG REG_MM(0x0348) |
| 50 | #define MM_PLL2_L_VAL_REG REG_MM(0x033C) |
| 51 | #define MM_PLL2_M_VAL_REG REG_MM(0x0340) |
| 52 | #define MM_PLL2_MODE_REG REG_MM(0x0338) |
| 53 | #define MM_PLL2_N_VAL_REG REG_MM(0x0344) |
| 54 | #define MM_PLL2_STATUS_REG REG_MM(0x0350) |
| 55 | |
| 56 | /* LCD related clock defines */ |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 57 | #define MMSS_AHB_NS_REG REG_MM(0x04) |
| 58 | #define MMSS_AHB_EN_REG REG_MM(0x08) |
| 59 | #define MMSS_AXI_NS_REG REG_MM(0x14) |
| 60 | #define MMSS_MAXI_EN_REG REG_MM(0x18) |
| 61 | #define MMSS_MAXI_EN2_REG REG_MM(0x20) |
| 62 | #define MMSS_SAXI_EN_REG REG_MM(0x30) |
| 63 | #define DSI_NS_REG REG_MM(0x54) |
| 64 | #define DSI_MD_REG REG_MM(0x50) |
| 65 | #define DSI_CC_REG REG_MM(0x4C) |
| 66 | #define MISC_CC2_REG REG_MM(0x5C) |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 67 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 68 | #define MDP_CC_REG REG_MM(0xC0) |
| 69 | #define MDP_MD_REG REG_MM(0xC4) |
| 70 | #define MDP_NS_REG REG_MM(0xD0) |
| 71 | #define MMSS_PIXEL_MD_REG REG_MM(0xD8) |
| 72 | #define MMSS_PIXEL_NS_REG REG_MM(0xDC) |
| 73 | #define MMSS_PIXEL_CC_REG REG_MM(0xD4) |
| 74 | |
| 75 | /* MMSS DSI Pixel Registers not MMSS Pixel */ |
| 76 | #define PIXEL_MD_REG REG_MM(0x134) |
| 77 | #define PIXEL_NS_REG REG_MM(0x138) |
| 78 | #define PIXEL_CC_REG REG_MM(0x130) |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 79 | |
| 80 | /* Configured at 200 MHz */ |
| 81 | #define MDP_NS_VAL 0x3F000008 |
| 82 | #define MDP_MD_VAL 0x000001FB |
| 83 | #define MDP_CC_VAL 0x00000400 |
| 84 | |
| 85 | /* Configured at 53.99 MHz */ |
| 86 | #define PIXEL_NS_VAL 0xFE4F4002 |
| 87 | #define PIXEL_MD_VAL 0x00A9FDA6 |
| 88 | #define PIXEL_CC_VAL 0x00000080 |
| 89 | |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 90 | /* Configured at 25 MHz (AUO Panel) */ |
| 91 | #define PIXEL_NS_VAL_25M 0xFFF10002 |
| 92 | #define PIXEL_MD_VAL_25M 0x0001FFF0 |
| 93 | #define PIXEL_CC_VAL_25M 0x00000080 |
| 94 | |
| 95 | /* PIXEL clock index */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 96 | #define PIXEL_CLK_INDEX_54M 0 /* 53.99MHz */ |
| 97 | #define PIXEL_CLK_INDEX_25M 1 /* 25MHz */ |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 98 | |
Shashank Mittal | c648e71 | 2010-10-06 18:37:42 -0700 | [diff] [blame] | 99 | #define MSM_CLK_CTL_BASE 0x00900000 |
| 100 | #define BB_PLL8_L_VAL_REG (MSM_CLK_CTL_BASE + 0x3144) |
| 101 | #define BB_PLL8_M_VAL_REG (MSM_CLK_CTL_BASE + 0x3148) |
| 102 | #define BB_PLL8_MODE_REG (MSM_CLK_CTL_BASE + 0x3140) |
| 103 | #define BB_PLL8_N_VAL_REG (MSM_CLK_CTL_BASE + 0x314C) |
Subbaraman Narayanamurthy | 05872db | 2011-02-28 11:34:58 -0800 | [diff] [blame] | 104 | #define CE2_HCLK_CTL (MSM_CLK_CTL_BASE + 0x2740) |
Shashank Mittal | c648e71 | 2010-10-06 18:37:42 -0700 | [diff] [blame] | 105 | |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 106 | /* NS/MD value for UART */ |
| 107 | #define UART_DM_CLK_NS_115200 0xFD940043 |
| 108 | #define UART_DM_CLK_MD_115200 0x0006FD8E |
| 109 | |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 110 | #define UART_DM_CLK_RX_TX_BIT_RATE 0xEE |
| 111 | |
| 112 | /* GSBI/I2C QUP APPS CLK definitions */ |
| 113 | #define I2C_CLK_MD_24MHz 0x000100FB |
| 114 | #define I2C_CLK_NS_24MHz 0x00FC005B |
Shashank Mittal | c648e71 | 2010-10-06 18:37:42 -0700 | [diff] [blame] | 115 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 116 | /* NS/MD value for MMC */ |
| 117 | #define SDC_CLK_NS_400KHZ 0x0010005B |
| 118 | #define SDC_CLK_MD_400KHZ 0x0001000F |
| 119 | |
| 120 | #define SDC_CLK_NS_48MHZ 0x00FE005B |
| 121 | #define SDC_CLK_MD_48MHZ 0x000100FD |
| 122 | |
Channagoud Kadabi | e488412 | 2011-09-21 23:54:44 +0530 | [diff] [blame] | 123 | /* HDMI Clocks */ |
| 124 | #define SW_RESET_AHB_REG REG_MM(0x020C) |
| 125 | #define SW_RESET_CORE_REG REG_MM(0x0210) |
| 126 | #define TV_CC_REG REG_MM(0x00EC) |
| 127 | #define TV_NS_REG REG_MM(0x00F4) |
| 128 | #define TV_MD_REG REG_MM(0x00F0) |
| 129 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 130 | enum clk_sources { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame^] | 131 | PLL_0 = 0, |
| 132 | PLL_1, |
| 133 | PLL_2, |
| 134 | PLL_3, |
| 135 | PLL_4, |
| 136 | PLL_5, |
| 137 | PLL_6, |
| 138 | PLL_7, |
| 139 | PLL_8, |
| 140 | MXO, |
| 141 | PXO, |
| 142 | CXO, |
| 143 | NUM_SRC |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 146 | void hsusb_clock_init(void); |
| 147 | void clock_config_uart_dm(uint8_t id); |
| 148 | void clock_config_i2c(uint8_t id, uint32_t freq); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 149 | void mdp_clock_init(void); |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 150 | void mmss_pixel_clock_configure(uint32_t pclk_index); |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 151 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 152 | #endif |