Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <string.h> |
| 32 | #include <smem.h> |
| 33 | #include <err.h> |
| 34 | #include <msm_panel.h> |
| 35 | #include <mipi_dsi.h> |
| 36 | #include <pm8x41.h> |
| 37 | #include <pm8x41_wled.h> |
| 38 | #include <qpnp_wled.h> |
| 39 | #include <board.h> |
| 40 | #include <mdp5.h> |
| 41 | #include <scm.h> |
| 42 | #include <regulator.h> |
| 43 | #include <platform/clock.h> |
| 44 | #include <platform/gpio.h> |
| 45 | #include <platform/iomap.h> |
| 46 | #include <target/display.h> |
| 47 | #include <qtimer.h> |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 48 | #include <platform.h> |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 49 | |
| 50 | #include "include/panel.h" |
| 51 | #include "include/display_resource.h" |
| 52 | #include "gcdb_display.h" |
| 53 | |
| 54 | /*---------------------------------------------------------------------------*/ |
| 55 | /* GPIO configuration */ |
| 56 | /*---------------------------------------------------------------------------*/ |
| 57 | static struct gpio_pin reset_gpio = { |
| 58 | "msmgpio", 0, 3, 1, 0, 1 |
| 59 | }; |
| 60 | |
| 61 | static struct gpio_pin enable_gpio = { |
| 62 | "msmgpio", 90, 3, 1, 0, 1 |
| 63 | }; |
| 64 | |
| 65 | static struct gpio_pin bkl_gpio = { |
| 66 | "msmgpio", 91, 3, 1, 0, 1 |
| 67 | }; |
| 68 | |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 69 | static struct gpio_pin lcd_mode_gpio = { |
| 70 | "msmgpio", 107, 3, 1, 0, 1 |
| 71 | }; |
| 72 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 73 | #define VCO_DELAY_USEC 1000 |
| 74 | #define GPIO_STATE_LOW 0 |
| 75 | #define GPIO_STATE_HIGH 2 |
| 76 | #define RESET_GPIO_SEQ_LEN 3 |
| 77 | #define PMIC_WLED_SLAVE_ID 3 |
| 78 | |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 79 | #define DSI0_BASE_ADJUST -0x4000 |
| 80 | #define DSI0_PHY_BASE_ADJUST -0x4100 |
| 81 | #define DSI0_PHY_PLL_BASE_ADJUST -0x3900 |
| 82 | #define DSI0_PHY_REGULATOR_BASE_ADJUST -0x3C00 |
| 83 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 84 | static void mdss_dsi_uniphy_pll_sw_reset_8952(uint32_t pll_base) |
| 85 | { |
| 86 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 87 | mdelay(1); |
| 88 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 89 | mdelay(1); |
| 90 | } |
| 91 | |
| 92 | static void dsi_pll_toggle_lock_detect_8952(uint32_t pll_base) |
| 93 | { |
| 94 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 95 | udelay(1); |
| 96 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 97 | udelay(512); |
| 98 | } |
| 99 | |
| 100 | static void dsi_pll_sw_reset_8952(uint32_t pll_base) |
| 101 | { |
| 102 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 103 | udelay(1); |
| 104 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 105 | udelay(1); |
| 106 | } |
| 107 | |
| 108 | static uint32_t dsi_pll_lock_status_8956(uint32_t pll_base) |
| 109 | { |
| 110 | uint32_t counter, status; |
| 111 | |
| 112 | status = readl(pll_base + 0x00c0) & 0x01; |
| 113 | for (counter = 0; counter < 5 && !status; counter++) { |
| 114 | udelay(100); |
| 115 | status = readl(pll_base + 0x00c0) & 0x01; |
| 116 | } |
| 117 | |
| 118 | return status; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | static uint32_t gf_1_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 122 | { |
| 123 | uint32_t rc; |
| 124 | |
| 125 | dsi_pll_sw_reset_8952(pll_base); |
| 126 | |
| 127 | /* |
| 128 | * Add hardware recommended delays between register writes for |
| 129 | * the updates to take effect. These delays are necessary for the |
| 130 | * PLL to successfully lock |
| 131 | */ |
| 132 | writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ |
| 133 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 134 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 135 | udelay(3); |
| 136 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 137 | udelay(500); |
| 138 | |
| 139 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 140 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 141 | |
| 142 | return rc; |
| 143 | } |
| 144 | |
| 145 | static uint32_t gf_2_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 146 | { |
| 147 | uint32_t rc; |
| 148 | |
| 149 | dsi_pll_sw_reset_8952(pll_base); |
| 150 | |
| 151 | /* |
| 152 | * Add hardware recommended delays between register writes for |
| 153 | * the updates to take effect. These delays are necessary for the |
| 154 | * PLL to successfully lock |
| 155 | */ |
| 156 | writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ |
| 157 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 158 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 159 | udelay(3); |
| 160 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 161 | udelay(500); |
| 162 | |
| 163 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 164 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 165 | |
| 166 | return rc; |
| 167 | } |
| 168 | |
| 169 | static uint32_t tsmc_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 170 | { |
| 171 | uint32_t rc; |
| 172 | |
| 173 | dsi_pll_sw_reset_8952(pll_base); |
| 174 | /* |
| 175 | * Add hardware recommended delays between register writes for |
| 176 | * the updates to take effect. These delays are necessary for the |
| 177 | * PLL to successfully lock |
| 178 | */ |
| 179 | |
| 180 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 181 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 182 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 183 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 184 | udelay(500); |
| 185 | |
| 186 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 187 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 188 | |
| 189 | return rc; |
| 190 | } |
| 191 | |
| 192 | |
| 193 | static uint32_t dsi_pll_enable_seq_8952(uint32_t pll_base) |
| 194 | { |
| 195 | uint32_t pll_locked = 0; |
| 196 | uint32_t counter = 0; |
| 197 | |
| 198 | do { |
| 199 | pll_locked = tsmc_dsi_pll_enable_sequence_8952(pll_base); |
| 200 | |
| 201 | dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); |
| 202 | ++counter; |
| 203 | } while (!pll_locked && (counter < 3)); |
| 204 | |
| 205 | if(!pll_locked) { |
| 206 | counter = 0; |
| 207 | do { |
| 208 | pll_locked = gf_1_dsi_pll_enable_sequence_8952(pll_base); |
| 209 | |
| 210 | dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked); |
| 211 | ++counter; |
| 212 | } while (!pll_locked && (counter < 3)); |
| 213 | } |
| 214 | |
| 215 | if(!pll_locked) { |
| 216 | counter = 0; |
| 217 | do { |
| 218 | pll_locked = gf_2_dsi_pll_enable_sequence_8952(pll_base); |
| 219 | |
| 220 | dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked); |
| 221 | ++counter; |
| 222 | } while (!pll_locked && (counter < 3)); |
| 223 | } |
| 224 | |
| 225 | return pll_locked; |
| 226 | } |
| 227 | |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 228 | static uint32_t dsi_pll_enable_seq_8956(uint32_t pll_base) |
| 229 | { |
| 230 | /* |
| 231 | * PLL power up sequence |
| 232 | * Add necessary delays recommended by h/w team |
| 233 | */ |
| 234 | |
| 235 | /* Lock Detect setting */ |
| 236 | writel(0x0d, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 237 | writel(0x34, pll_base + 0x0070); /* PLL CAL_CFG1 */ |
| 238 | writel(0x10, pll_base + 0x005c); /* LKDetect CFG0 */ |
| 239 | writel(0x1a, pll_base + 0x0060); /* LKDetect CFG1 */ |
| 240 | |
| 241 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 242 | udelay(300); |
| 243 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 244 | udelay(300); |
| 245 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 246 | udelay(300); |
| 247 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 248 | udelay(300); |
| 249 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 250 | udelay(1000); |
| 251 | |
| 252 | return dsi_pll_lock_status_8956(pll_base); |
| 253 | } |
| 254 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 255 | static int msm8952_wled_backlight_ctrl(uint8_t enable) |
| 256 | { |
| 257 | uint8_t slave_id = PMIC_WLED_SLAVE_ID; /* pmi */ |
| 258 | |
| 259 | pm8x41_wled_config_slave_id(slave_id); |
| 260 | qpnp_wled_enable_backlight(enable); |
| 261 | qpnp_ibb_enable(enable); |
| 262 | return NO_ERROR; |
| 263 | } |
| 264 | |
| 265 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 266 | { |
| 267 | uint32_t ret = NO_ERROR; |
| 268 | |
| 269 | if (bl->bl_interface_type == BL_DCS) |
| 270 | return ret; |
| 271 | |
| 272 | ret = msm8952_wled_backlight_ctrl(enable); |
| 273 | |
| 274 | return ret; |
| 275 | } |
| 276 | |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 277 | static int32_t mdss_dsi_pll_config(uint32_t pll_base, uint32_t ctl_base, |
| 278 | struct mdss_dsi_pll_config *pll_data) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 279 | { |
| 280 | int32_t ret = 0; |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 281 | if (!platform_is_msm8956()) |
| 282 | mdss_dsi_uniphy_pll_sw_reset_8952(pll_base); |
| 283 | else |
| 284 | dsi_pll_sw_reset_8952(pll_base); |
| 285 | mdss_dsi_auto_pll_config(pll_base, ctl_base, pll_data); |
| 286 | if (platform_is_msm8956()) |
| 287 | ret = dsi_pll_enable_seq_8956(pll_base); |
| 288 | else |
| 289 | ret = dsi_pll_enable_seq_8952(pll_base); |
| 290 | |
| 291 | return ret; |
| 292 | } |
| 293 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 294 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 295 | { |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 296 | int32_t ret = 0, flags; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 297 | struct mdss_dsi_pll_config *pll_data; |
| 298 | dprintf(SPEW, "target_panel_clock\n"); |
| 299 | |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 300 | if (pinfo->dest == DISPLAY_2) { |
| 301 | flags = MMSS_DSI_CLKS_FLAG_DSI1; |
| 302 | if (pinfo->mipi.dual_dsi) |
| 303 | flags |= MMSS_DSI_CLKS_FLAG_DSI0; |
| 304 | } else { |
| 305 | flags = MMSS_DSI_CLKS_FLAG_DSI0; |
| 306 | if (pinfo->mipi.dual_dsi) |
| 307 | flags |= MMSS_DSI_CLKS_FLAG_DSI1; |
| 308 | } |
| 309 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 310 | pll_data = pinfo->mipi.dsi_pll_config; |
| 311 | pll_data->vco_delay = VCO_DELAY_USEC; |
| 312 | |
| 313 | if (enable) { |
| 314 | mdp_gdsc_ctrl(enable); |
| 315 | mdss_bus_clocks_enable(); |
| 316 | mdp_clock_enable(); |
| 317 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 318 | if (ret) { |
| 319 | dprintf(CRITICAL, |
| 320 | "%s: Failed to restore MDP security configs", |
| 321 | __func__); |
| 322 | mdp_clock_disable(); |
| 323 | mdss_bus_clocks_disable(); |
| 324 | mdp_gdsc_ctrl(0); |
| 325 | return ret; |
| 326 | } |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 327 | |
| 328 | ret = mdss_dsi_pll_config(pinfo->mipi.pll_base, |
| 329 | pinfo->mipi.ctl_base, pll_data); |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 330 | if (!ret) |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 331 | dprintf(CRITICAL, "Not able to enable master pll\n"); |
| 332 | |
Padmanabhan Komanduru | 2a6c345 | 2015-09-09 18:46:06 +0530 | [diff] [blame] | 333 | if (platform_is_msm8956() && pinfo->mipi.dual_dsi && |
| 334 | !platform_is_msm8976_v_1_1()) { |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 335 | ret = mdss_dsi_pll_config(pinfo->mipi.spll_base, |
| 336 | pinfo->mipi.sctl_base, pll_data); |
| 337 | if (!ret) |
| 338 | dprintf(CRITICAL, "Not able to enable second pll\n"); |
| 339 | } |
| 340 | |
Padmanabhan Komanduru | 2a6c345 | 2015-09-09 18:46:06 +0530 | [diff] [blame] | 341 | gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll, |
| 342 | pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 343 | } else if(!target_cont_splash_screen()) { |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 344 | gcc_dsi_clocks_disable(flags); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 345 | mdp_clock_disable(); |
| 346 | mdss_bus_clocks_disable(); |
| 347 | mdp_gdsc_ctrl(enable); |
| 348 | } |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 354 | struct msm_panel_info *pinfo) |
| 355 | { |
| 356 | int ret = NO_ERROR; |
Sujeev Dias | 6bc9fa3 | 2015-08-03 23:13:44 -0700 | [diff] [blame] | 357 | uint32_t hw_id = board_hardware_id(); |
| 358 | uint32_t hw_subtype = board_hardware_subtype(); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 359 | |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 360 | if (platform_is_msm8956()) { |
| 361 | reset_gpio.pin_id = 25; |
| 362 | bkl_gpio.pin_id = 66; |
Padmanabhan Komanduru | b323132 | 2015-11-12 16:54:21 +0530 | [diff] [blame^] | 363 | } else if (platform_is_msm8937()) { |
| 364 | reset_gpio.pin_id = 60; |
| 365 | bkl_gpio.pin_id = 98; |
| 366 | enable_gpio.pin_id = 99; |
Sujeev Dias | 6bc9fa3 | 2015-08-03 23:13:44 -0700 | [diff] [blame] | 367 | } else if ((hw_id == HW_PLATFORM_QRD) && |
| 368 | (hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS)) { |
| 369 | enable_gpio.pin_id = 19; |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 370 | } |
| 371 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 372 | if (enable) { |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 373 | if (pinfo->mipi.use_enable_gpio && !platform_is_msm8956()) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 374 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 375 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 376 | enable_gpio.pin_strength, |
| 377 | enable_gpio.pin_state); |
| 378 | |
| 379 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 380 | } |
| 381 | |
| 382 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 383 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 384 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 385 | |
| 386 | gpio_set_dir(bkl_gpio.pin_id, 2); |
| 387 | |
| 388 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 389 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 390 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 391 | |
| 392 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 393 | |
| 394 | /* reset */ |
| 395 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 396 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 397 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 398 | else |
| 399 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 400 | mdelay(resetseq->sleep[i]); |
| 401 | } |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 402 | |
| 403 | if (platform_is_msm8956()) { |
| 404 | gpio_tlmm_config(lcd_mode_gpio.pin_id, 0, |
| 405 | lcd_mode_gpio.pin_direction, lcd_mode_gpio.pin_pull, |
| 406 | lcd_mode_gpio.pin_strength, lcd_mode_gpio.pin_state); |
| 407 | |
| 408 | if (pinfo->lcdc.split_display || pinfo->lcdc.dst_split) |
| 409 | gpio_set_dir(lcd_mode_gpio.pin_id, GPIO_STATE_LOW); |
| 410 | else |
| 411 | gpio_set_dir(lcd_mode_gpio.pin_id, GPIO_STATE_HIGH); |
| 412 | } |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 413 | } else if(!target_cont_splash_screen()) { |
| 414 | gpio_set_dir(reset_gpio.pin_id, 0); |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 415 | if (pinfo->mipi.use_enable_gpio && !platform_is_msm8956()) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 416 | gpio_set_dir(enable_gpio.pin_id, 0); |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 417 | if (platform_is_msm8956()) |
| 418 | gpio_set_dir(lcd_mode_gpio.pin_id, 0); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | return ret; |
| 422 | } |
| 423 | |
| 424 | static void wled_init(struct msm_panel_info *pinfo) |
| 425 | { |
| 426 | struct qpnp_wled_config_data config = {0}; |
| 427 | struct labibb_desc *labibb; |
| 428 | int display_type = 0; |
| 429 | |
| 430 | labibb = pinfo->labibb; |
| 431 | |
| 432 | if (labibb) |
| 433 | display_type = labibb->amoled_panel; |
| 434 | |
| 435 | config.display_type = display_type; |
| 436 | config.lab_init_volt = 4600000; /* fixed, see pmi register */ |
| 437 | config.ibb_init_volt = 1400000; /* fixed, see pmi register */ |
| 438 | |
| 439 | if (labibb && labibb->force_config) { |
| 440 | config.lab_min_volt = labibb->lab_min_volt; |
| 441 | config.lab_max_volt = labibb->lab_max_volt; |
| 442 | config.ibb_min_volt = labibb->ibb_min_volt; |
| 443 | config.ibb_max_volt = labibb->ibb_max_volt; |
| 444 | config.pwr_up_delay = labibb->pwr_up_delay; |
| 445 | config.pwr_down_delay = labibb->pwr_down_delay; |
| 446 | config.ibb_discharge_en = labibb->ibb_discharge_en; |
| 447 | } else { |
| 448 | /* default */ |
| 449 | config.pwr_up_delay = 3; |
| 450 | config.pwr_down_delay = 3; |
| 451 | config.ibb_discharge_en = 1; |
| 452 | if (display_type) { /* amoled */ |
| 453 | config.lab_min_volt = 4600000; |
| 454 | config.lab_max_volt = 4600000; |
| 455 | config.ibb_min_volt = 4000000; |
| 456 | config.ibb_max_volt = 4000000; |
| 457 | } else { /* lcd */ |
| 458 | config.lab_min_volt = 5500000; |
| 459 | config.lab_max_volt = 5500000; |
| 460 | config.ibb_min_volt = 5500000; |
| 461 | config.ibb_max_volt = 5500000; |
| 462 | } |
| 463 | } |
| 464 | |
| 465 | dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__, |
| 466 | config.display_type, |
| 467 | config.lab_min_volt, config.lab_max_volt, |
| 468 | config.ibb_min_volt, config.ibb_max_volt, |
| 469 | config.lab_init_volt, config.ibb_init_volt, |
| 470 | config.pwr_up_delay, config.pwr_down_delay, |
| 471 | config.ibb_discharge_en); |
| 472 | |
| 473 | /* QPNP WLED init for display backlight */ |
| 474 | pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID); |
| 475 | |
| 476 | qpnp_wled_init(&config); |
| 477 | } |
| 478 | |
Dhaval Patel | 7709c41 | 2015-05-12 10:09:41 -0700 | [diff] [blame] | 479 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 480 | { |
| 481 | memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE); |
| 482 | memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE); |
| 483 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE); |
| 484 | memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE); |
| 485 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE); |
| 486 | return NO_ERROR; |
| 487 | } |
| 488 | |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 489 | int target_display_get_base_offset(uint32_t base) |
| 490 | { |
Padmanabhan Komanduru | b323132 | 2015-11-12 16:54:21 +0530 | [diff] [blame^] | 491 | if(platform_is_msm8956() || platform_is_msm8937()) { |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 492 | if (base == MIPI_DSI0_BASE) |
| 493 | return DSI0_BASE_ADJUST; |
| 494 | else if (base == DSI0_PHY_BASE) |
| 495 | return DSI0_PHY_BASE_ADJUST; |
| 496 | else if (base == DSI0_PLL_BASE) |
| 497 | return DSI0_PHY_PLL_BASE_ADJUST; |
| 498 | else if (base == DSI0_REGULATOR_BASE) |
| 499 | return DSI0_PHY_REGULATOR_BASE_ADJUST; |
| 500 | } |
| 501 | |
| 502 | return 0; |
| 503 | } |
| 504 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 505 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
| 506 | { |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 507 | uint32_t ldo_num = REG_LDO6 | REG_LDO17; |
| 508 | |
| 509 | if (platform_is_msm8956()) |
| 510 | ldo_num |= REG_LDO1; |
| 511 | else |
| 512 | ldo_num |= REG_LDO2; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 513 | |
| 514 | if (enable) { |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 515 | regulator_enable(ldo_num); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 516 | mdelay(10); |
| 517 | wled_init(pinfo); |
| 518 | qpnp_ibb_enable(true); /*5V boost*/ |
| 519 | mdelay(50); |
| 520 | } else { |
Padmanabhan Komanduru | fa2899b | 2015-06-30 16:25:33 +0530 | [diff] [blame] | 521 | /* |
| 522 | * LDO1, LDO2 and LDO6 are shared with other subsystems. |
| 523 | * Do not disable them. |
| 524 | */ |
| 525 | regulator_disable(REG_LDO17); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | return NO_ERROR; |
| 529 | } |
| 530 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 531 | bool target_display_panel_node(char *pbuf, uint16_t buf_size) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 532 | { |
Padmanabhan Komanduru | 6664df2 | 2015-08-28 15:21:25 +0530 | [diff] [blame] | 533 | return gcdb_display_cmdline_arg(pbuf, buf_size); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 534 | } |
| 535 | |
| 536 | void target_display_init(const char *panel_name) |
| 537 | { |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 538 | struct oem_panel_data oem; |
Ray Zhang | f95f5b9 | 2015-06-25 15:34:29 +0800 | [diff] [blame] | 539 | int32_t ret = 0; |
| 540 | uint32_t panel_loop = 0; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 541 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 542 | set_panel_cmd_string(panel_name); |
| 543 | oem = mdss_dsi_get_oem_data(); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 544 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 545 | if (!strcmp(oem.panel, NO_PANEL_CONFIG) |
| 546 | || !strcmp(oem.panel, SIM_VIDEO_PANEL) |
| 547 | || !strcmp(oem.panel, SIM_CMD_PANEL) |
| 548 | || oem.skip) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 549 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 550 | oem.panel); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 551 | return; |
| 552 | } |
| 553 | |
Ray Zhang | f95f5b9 | 2015-06-25 15:34:29 +0800 | [diff] [blame] | 554 | do { |
| 555 | target_force_cont_splash_disable(false); |
| 556 | ret = gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR); |
| 557 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 558 | break; |
| 559 | } else { |
| 560 | target_force_cont_splash_disable(true); |
| 561 | msm_display_off(); |
| 562 | } |
| 563 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 564 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 565 | if (!oem.cont_splash) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 566 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 567 | target_force_cont_splash_disable(true); |
| 568 | } |
| 569 | } |
| 570 | |
| 571 | void target_display_shutdown(void) |
| 572 | { |
| 573 | gcdb_display_shutdown(); |
| 574 | } |