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gerrit-public.fairphone.software / kernel / lk / d86b38e3ad91518c0ccf9d6727ae0e4fb442799b / . / platform / msm8952 / include / platform / iomap.h
blob: ce9807674b5610be65fa4542801a8538656f5e77 [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSM8952_IOMAP_H_
30#define _PLATFORM_MSM8952_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]37#define DDR_START get_ddr_start()
38#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
39#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
40#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
41#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
42
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]43#define MSM_SHARED_BASE 0x86300000
44#define MSM_SHARED_IMEM_BASE 0x08600000
45
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48
49#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
50
51#define APPS_SS_BASE 0x0B000000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]52#define APPS_SS_END 0x0B200000
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]53
54#define MSM_GIC_DIST_BASE APPS_SS_BASE
55#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
56#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
57#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
58#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
Aparna Mallavarapufa5f8a72015-03-31 06:21:36 +0530[diff] [blame]59#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]60
61#define PERIPH_SS_BASE 0x07800000
62
63#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
64#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
65
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]66/* UART */
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]67#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
68#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
69#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
70
71#define CLK_CTL_BASE 0x1800000
72
Matthew Qin7afa8492015-06-26 17:05:18 +0800[diff] [blame]73#define PMI_SLAVE_ID 3
74#define PMI_ADDR_BASE (PMI_SLAVE_ID << 16)
75
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]76#define SPMI_BASE 0x02000000
77#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
78#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
79#define PMIC_ARB_CORE 0x200F000
80
81#define TLMM_BASE_ADDR 0x1000000
82#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
83#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
84
85#define MPM2_MPM_CTRL_BASE 0x004A0000
86#define MPM2_MPM_PS_HOLD 0x004AB000
87#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
88
89/* CRYPTO ENGINE */
90#define MSM_CE1_BASE 0x073A000
91#define MSM_CE1_BAM_BASE 0x0704000
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]92#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
93#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
94#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
95#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
96#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
97#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]98
99/* GPLL */
100#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
101#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
102#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]103#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
Unnati Gandhi81b77062015-05-28 14:23:39 +0530[diff] [blame]104#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
Padmanabhan Komanduru2655ea62015-06-08 12:23:32 +0530[diff] [blame]105#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]106
107/* SDCC */
108#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
109#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
110#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
111#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
112#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
113#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
114#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
115#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
116#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
117
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]118/* SDHCI */
119#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
120#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
121
122#define SDCC_MCI_HC_MODE (0x00000078)
123#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
124#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
125#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
126#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
127
128#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
129#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
130#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
131#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
132#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
133#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
134#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
135#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
136
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]137/* UART */
138#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
139#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
140#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
141#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
142#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
143#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
144#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
145
146/* USB */
147#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
148#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
149#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
150#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
151#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
152
Parth Dixit23d23442015-07-30 18:47:38 +0530[diff] [blame]153
154/* RPMB send receive buffer needs to be mapped
155 * as device memory, define the start address
156 * and size in MB
157 */
158#define RPMB_SND_RCV_BUF 0x90000000
159#define RPMB_SND_RCV_BUF_SZ 0x1
160
161/* QSEECOM: Secure app region notification */
162#define APP_REGION_ADDR 0x85E00000
163#define APP_REGION_SIZE 0x500000
164
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]165/* MDSS */
166#define MIPI_DSI_BASE (0x1A98000)
167#define MIPI_DSI0_BASE MIPI_DSI_BASE
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]168#define MIPI_DSI1_BASE (0x1A96000)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]169#define DSI0_PHY_BASE (0x1A98500)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]170#define DSI1_PHY_BASE (0x1A96400)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]171#define DSI0_PLL_BASE (0x1A98300)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]172#define DSI1_PLL_BASE (0x1A96A00)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]173#define DSI0_REGULATOR_BASE (0x1A98780)
174#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
175#define MDP_BASE (0x1A00000)
176#define REG_MDP(off) (MDP_BASE + (off))
177
178#ifdef MDP_HW_REV
179#undef MDP_HW_REV
180#endif
181#define MDP_HW_REV REG_MDP(0x1000)
182
183#ifdef MDP_INTR_EN
184#undef MDP_INTR_EN
185#endif
186#define MDP_INTR_EN REG_MDP(0x1010)
187
188#ifdef MDP_INTR_CLEAR
189#undef MDP_INTR_CLEAR
190#endif
191#define MDP_INTR_CLEAR REG_MDP(0x1018)
192
193#ifdef MDP_HIST_INTR_EN
194#undef MDP_HIST_INTR_EN
195#endif
196#define MDP_HIST_INTR_EN REG_MDP(0x101C)
197
198#ifdef MDP_VP_0_VIG_0_BASE
199#undef MDP_VP_0_VIG_0_BASE
200#endif
201#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
202
203#ifdef MDP_VP_0_VIG_1_BASE
204#undef MDP_VP_0_VIG_1_BASE
205#endif
206#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
207
208#ifdef MDP_VP_0_RGB_0_BASE
209#undef MDP_VP_0_RGB_0_BASE
210#endif
211#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
212
213#ifdef MDP_VP_0_RGB_1_BASE
214#undef MDP_VP_0_RGB_1_BASE
215#endif
216#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
217
218#ifdef MDP_VP_0_DMA_0_BASE
219#undef MDP_VP_0_DMA_0_BASE
220#endif
221#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
222
223#ifdef MDP_VP_0_DMA_1_BASE
224#undef MDP_VP_0_DMA_1_BASE
225#endif
226#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
227
228#ifdef MDP_VP_0_MIXER_0_BASE
229#undef MDP_VP_0_MIXER_0_BASE
230#endif
231#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
232
233#ifdef MDP_VP_0_MIXER_1_BASE
234#undef MDP_VP_0_MIXER_1_BASE
235#endif
236#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
237
238#ifdef MDP_DISP_INTF_SEL
239#undef MDP_DISP_INTF_SEL
240#endif
241#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
242
243#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
244#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
245#endif
246#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
247
248#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
249#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
250#endif
251#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
252
253#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
254#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
255#endif
256#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
257
258#ifdef MDP_CTL_0_BASE
259#undef MDP_CTL_0_BASE
260#endif
261#define MDP_CTL_0_BASE REG_MDP(0x2000)
262
263#ifdef MDP_CTL_1_BASE
264#undef MDP_CTL_1_BASE
265#endif
266#define MDP_CTL_1_BASE REG_MDP(0x2200)
267
268#ifdef MDP_CLK_CTRL0
269#undef MDP_CLK_CTRL0
270#endif
271#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
272
273#ifdef MDP_CLK_CTRL1
274#undef MDP_CLK_CTRL1
275#endif
276#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
277
278#ifdef MDP_CLK_CTRL2
279#undef MDP_CLK_CTRL2
280#endif
281#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
282
283#ifdef MDP_CLK_CTRL3
284#undef MDP_CLK_CTRL3
285#endif
286#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
287
288#ifdef MDP_CLK_CTRL4
289#undef MDP_CLK_CTRL4
290#endif
291#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
292
293#ifdef MDP_CLK_CTRL5
294#undef MDP_CLK_CTRL5
295#endif
296#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
297
298#ifdef MDP_INTF_1_BASE
299#undef MDP_INTF_1_BASE
300#endif
301#define MDP_INTF_1_BASE REG_MDP(0x12700)
302
Padmanabhan Komanduruf912cfb2015-06-08 16:36:58 +0530[diff] [blame]303#ifdef MDP_INTF_2_BASE
304#undef MDP_INTF_2_BASE
305#endif
306#define MDP_INTF_2_BASE REG_MDP(0x12F00)
307
308#ifdef MDP_REG_SPLIT_DISPLAY_EN
309#undef MDP_REG_SPLIT_DISPLAY_EN
310#endif
311#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
312
313#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
314#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
315#endif
316#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
317
318#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
319#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
320#endif
321#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
322
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]323#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
324#undef MMSS_MDP_SMP_ALLOC_W_BASE
325#endif
326#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
327
328#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
329#undef MMSS_MDP_SMP_ALLOC_R_BASE
330#endif
331#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
332
333#ifdef MDP_QOS_REMAPPER_CLASS_0
334#undef MDP_QOS_REMAPPER_CLASS_0
335#endif
336#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
337
338#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
339#undef VBIF_VBIF_DDR_FORCE_CLK_ON
340#endif
341#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
342
343#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
344#undef VBIF_VBIF_DDR_OUT_MAX_BURST
345#endif
346#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
347
348#ifdef VBIF_VBIF_DDR_ARB_CTRL
349#undef VBIF_VBIF_DDR_ARB_CTRL
350#endif
351#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
352
353#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
354#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
355#endif
356#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
357
358#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
359#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
360#endif
361#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
362
363#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
364#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
365#endif
366#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
367
368#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
369#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
370#endif
371#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
372
373#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
374#undef VBIF_VBIF_DDR_OUT_AX_AOOO
375#endif
376#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
377
378#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
379#undef VBIF_VBIF_IN_RD_LIM_CONF0
380#endif
381#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
382
383#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
384#undef VBIF_VBIF_IN_RD_LIM_CONF1
385#endif
386#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
387
388#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
389#undef VBIF_VBIF_IN_WR_LIM_CONF0
390#endif
391#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
392
393#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
394#undef VBIF_VBIF_IN_WR_LIM_CONF1
395#endif
396#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
397
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]398#ifdef MDP_INTF_2_TIMING_ENGINE_EN
399#undef MDP_INTF_2_TIMING_ENGINE_EN
400#endif
401#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12F00)
402
403#ifdef MDP_PP_0_BASE
404#undef MDP_PP_0_BASE
405#endif
406#define MDP_PP_0_BASE REG_MDP(0x71000)
407
408#ifdef MDP_PP_1_BASE
409#undef MDP_PP_1_BASE
410#endif
411#define MDP_PP_1_BASE REG_MDP(0x71800)
412
413#ifdef MDSS_MDP_REG_DCE_SEL
414#undef MDSS_MDP_REG_DCE_SEL
415#endif
416#define MDSS_MDP_REG_DCE_SEL REG_MDP(0x1428)
417
418#ifdef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
419#undef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
420#endif
421#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP 0x0CC
422
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]423#ifdef MDP_DSC_0_BASE
424#undef MDP_DSC_0_BASE
425#endif
426#define MDP_DSC_0_BASE REG_MDP(0x81000)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]427
Ujwal Patel41a665a2015-07-17 13:51:30 -0700[diff] [blame]428#ifdef MDP_DSC_1_BASE
429#undef MDP_DSC_1_BASE
430#endif
431#define MDP_DSC_1_BASE REG_MDP(0x81400)
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]432
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]433#define SOFT_RESET 0x118
434#define CLK_CTRL 0x11C
435#define TRIG_CTRL 0x084
436#define CTRL 0x004
437#define COMMAND_MODE_DMA_CTRL 0x03C
438#define COMMAND_MODE_MDP_CTRL 0x040
439#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
440#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
441#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
442#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
443#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
444#define ERR_INT_MASK0 0x10C
445
446#define LANE_CTL 0x0AC
447#define LANE_SWAP_CTL 0x0B0
448#define TIMING_CTL 0x0C4
449
450#define VIDEO_MODE_ACTIVE_H 0x024
451#define VIDEO_MODE_ACTIVE_V 0x028
452#define VIDEO_MODE_TOTAL 0x02C
453#define VIDEO_MODE_HSYNC 0x030
454#define VIDEO_MODE_VSYNC 0x034
455#define VIDEO_MODE_VSYNC_VPOS 0x038
456
457#define DMA_CMD_OFFSET 0x048
458#define DMA_CMD_LENGTH 0x04C
459
460#define INT_CTRL 0x110
461#define CMD_MODE_DMA_SW_TRIGGER 0x090
462
463#define EOT_PACKET_CTRL 0x0CC
464#define MISR_CMD_CTRL 0x0A0
465#define MISR_VIDEO_CTRL 0x0A4
466#define VIDEO_MODE_CTRL 0x010
467#define HS_TIMER_CTRL 0x0BC
468
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]469#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
470#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
471#define CMD_COMPRESSION_MODE_CTRL 0x2A8
472#define CMD_COMPRESSION_MODE_CTRL_2 0x2AC
473#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
474
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]475#define TCSR_TZ_WONCE 0x193D000
476#define TCSR_BOOT_MISC_DETECT 0x193D100
Aparna Mallavarapu59914502015-06-01 15:31:28 +0530[diff] [blame]477
478#define APPS_WDOG_BARK_VAL_REG 0x0B017010
479#define APPS_WDOG_BITE_VAL_REG 0x0B017014
480#define APPS_WDOG_RESET_REG 0x0B017008
481#define APPS_WDOG_CTL_REG 0x0B017004
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]482#endif