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Ajay Dudani232ce812009-12-02 00:14:11 -08001/*
Ajay Dudani232ce812009-12-02 00:14:11 -08002 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
Ajay Dudania6c845b2010-03-03 18:44:07 -08004 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
Ajay Dudani232ce812009-12-02 00:14:11 -08005 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 * * Neither the name of Google, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
26 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
29 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33
34/* TODO:
35 * - style cleanup
36 * - do we need to do *all* of this at boot?
37 */
38
Ajay Dudania6c845b2010-03-03 18:44:07 -080039.text
Ajay Dudani232ce812009-12-02 00:14:11 -080040.code 32
41
42#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
43#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
44
45/*
46 ; LVT Ring Osc counter
47 ; used to determine sense amp settings
48 ; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
49*/
50.equ CLK_CTL_BASE, 0xA8600000
51.equ A_GLBL_CLK_ENA, 0x0000
52.equ A_PRPH_WEB_NS_REG,0x0080
53.equ A_MSM_CLK_RINGOSC,0x00D0
54.equ A_TCXO_CNT, 0x00D4
55.equ A_TCXO_CNT_DONE, 0x00D8
56.equ A_RINGOSC_CNT, 0x00DC
57.equ A_MISC_CLK_CTL, 0x0108
58.equ CLK_TEST, 0xA8600114
59.equ SPSS_CSR_BASE, 0xAC100000
60.equ A_SCRINGOSC, 0x0510
61
62//;; Number of TCXO cycles to count ring oscillations
63.equ TCXO_CNT_VAL, 0x100
64
Ajay Dudania6c845b2010-03-03 18:44:07 -080065//; Halcyon addresses
66.equ TCSR_CONF_FUSE_1, 0xAB600060 //; TCSR_CONF_FUSE_1 register
67.equ TCSR_CONF_FUSE_4, 0xAB60006C //; TCSR_CONF_FUSE_4 register
Ajay Dudani232ce812009-12-02 00:14:11 -080068
Ajay Dudania6c845b2010-03-03 18:44:07 -080069//; SCORPION_L1_ACC (1:0) Fuses bit location
70.equ L1_ACC_BIT_0, 12 //;12th bit of TCSR_CONF_FUSE_4
71.equ L1_ACC_BIT_1, 13 //;13th bit of TCSR_CONF_FUSE_4
72//; SCORPION_L2_ACC (2:0) Fuses bit location
73.equ L2_ACC_BIT_0, 25 //;25th bit of TCSR_CONF_FUSE_1
74.equ L2_ACC_BIT_1, 10 //;10th bit of TCSR_CONF_FUSE_4
75.equ L2_ACC_BIT_2, 11 //;11th bit of TCSR_CONF_FUSE_4
76
77//; CP15: PVR2F0 values according to SCORPION_L1_ACC (1:0)
78.equ PVR2F0_00, 0x00000000
79.equ PVR2F0_01, 0x04000000
80.equ PVR2F0_10, 0x08000000
81.equ PVR2F0_11, 0x0C000000
82
83//; CP15: PVR2F1 values according to SCORPION_L1_ACC (1:0)
84.equ PVR2F1_00, 0x00000008
85.equ PVR2F1_01, 0x00000008
86.equ PVR2F1_10, 0x00000208
87.equ PVR2F1_11, 0x00000208
88
89//; CP15: PVR0F2 values according to SCORPION_L1_ACC (1:0)
90.equ PVR0F2_00, 0x00000000
91.equ PVR0F2_01, 0x00000000
92.equ PVR0F2_10, 0x00000200
93.equ PVR0F2_11, 0x00000200
94
95//; CP15: PVR0F0 values according to SCORPION_L1_ACC (1:0)
96.equ PVR0F0_00, 0x7F000000
97.equ PVR0F0_01, 0x7F000400
98.equ PVR0F0_10, 0x7F000000
99.equ PVR0F0_11, 0x7F000400
100
101//; CP15: L2VR3F1 values according to SCORPION_L2_ACC (2:0)
102.equ L2VR3F1_000, 0x00FFFF60
103.equ L2VR3F1_001, 0x00FFFF40
104.equ L2VR3F1_010, 0x00FFFC60
105.equ L2VR3F1_011, 0x00FFFC40
106.equ L2VR3F1_100, 0x00FCFF60
107.equ L2VR3F1_101, 0x00FCFF40
108.equ L2VR3F1_110, 0x00FCFC60
109.equ L2VR3F1_111, 0x00FCFC40
Ajay Dudani232ce812009-12-02 00:14:11 -0800110
111.globl SET_SA
112SET_SA:
Ajay Dudani232ce812009-12-02 00:14:11 -0800113
114 //;--------------------------------------------------------------------
115 //; Fuse bits used to determine sense amp settings
116 //;--------------------------------------------------------------------
117
Ajay Dudania6c845b2010-03-03 18:44:07 -0800118 //; Reading L1_ACC
119 LDR r4, = 0x0
Ajay Dudani232ce812009-12-02 00:14:11 -0800120
Ajay Dudania6c845b2010-03-03 18:44:07 -0800121 //; Read L1_ACC_BIT_0
122 LDR r1, =TCSR_CONF_FUSE_4
123 LDR r2, =L1_ACC_BIT_0
124 LDR r3, [r1]
125 MOV r3, r3, LSR r2
126 AND r3, r3, #1
127 ORR r4, r3, r4
128
129 //; Read L1_ACC_BIT_1
130 LDR r1, =TCSR_CONF_FUSE_4
131 LDR r2, =L1_ACC_BIT_1
132 LDR r3, [r1]
133 MOV r3, r3, LSR r2
134 AND r3, r3, #1
135 MOV r3, r3, LSL #1
136 ORR r4, r3, r4
137
138l1_ck_0:
139 //; if L1_[1:0] == 00
140 LDR r5, = 0x0
141 CMP r4, r5
142 BNE l1_ck_1
143 LDR r0, =PVR0F0_00
144 LDR r1, =PVR0F2_00
145 LDR r2, =PVR2F0_00
146 LDR r3, =PVR2F1_00
Ajay Dudani232ce812009-12-02 00:14:11 -0800147 B WRITE_L1_SA_SETTINGS
148
Ajay Dudania6c845b2010-03-03 18:44:07 -0800149l1_ck_1:
150 //; if L1_[1:0] == 01
Ajay Dudani232ce812009-12-02 00:14:11 -0800151 LDR r1, = 0x01
152 CMP r4, r1
Ajay Dudania6c845b2010-03-03 18:44:07 -0800153 BNE l1_ck_2
154 LDR r0, =PVR0F0_01
155 LDR r1, =PVR0F2_01
156 LDR r2, =PVR2F0_01
157 LDR r3, =PVR2F1_01
Ajay Dudani232ce812009-12-02 00:14:11 -0800158 B WRITE_L1_SA_SETTINGS
159
Ajay Dudania6c845b2010-03-03 18:44:07 -0800160l1_ck_2:
161 //; if L1_[2:0] == 10
162 LDR r1, = 0x02
Ajay Dudani232ce812009-12-02 00:14:11 -0800163 CMP r4, r1
Ajay Dudania6c845b2010-03-03 18:44:07 -0800164 BNE l1_ck_3
165 LDR r0, =PVR0F0_10
166 LDR r1, =PVR0F2_10
167 LDR r2, =PVR2F0_10
168 LDR r3, =PVR2F1_10
Ajay Dudani232ce812009-12-02 00:14:11 -0800169 B WRITE_L1_SA_SETTINGS
170
Ajay Dudania6c845b2010-03-03 18:44:07 -0800171l1_ck_3:
172 //; if L1_[2:0] == 11
173 LDR r1, = 0x03
Ajay Dudani232ce812009-12-02 00:14:11 -0800174 CMP r4, r1
Ajay Dudania6c845b2010-03-03 18:44:07 -0800175 LDR r0, =PVR0F0_11
176 LDR r1, =PVR0F2_11
177 LDR r2, =PVR2F0_11
178 LDR r3, =PVR2F1_11
Ajay Dudani232ce812009-12-02 00:14:11 -0800179 B WRITE_L1_SA_SETTINGS
180
Ajay Dudani232ce812009-12-02 00:14:11 -0800181
182WRITE_L1_SA_SETTINGS:
183
Ajay Dudania6c845b2010-03-03 18:44:07 -0800184 //;WCP15_PVR0F0 r0
185 MCR p15, 0x0, r0, c15, c15, 0x0 //; write R0 to PVR0F0
Ajay Dudani232ce812009-12-02 00:14:11 -0800186
Ajay Dudania6c845b2010-03-03 18:44:07 -0800187 //;WCP15_PVR0F2 r1
188 MCR p15, 0x0, r1, c15, c15, 0x2 //; write R1 to PVR0F2
Ajay Dudani232ce812009-12-02 00:14:11 -0800189
Ajay Dudania6c845b2010-03-03 18:44:07 -0800190 //;WCP15_PVR2F0 r2
Ajay Dudani79d0d402010-04-21 12:38:45 -0700191 MCR p15, 0x2, r2, c15, c15, 0x0 //; write R2 to PVR2F0
Ajay Dudani232ce812009-12-02 00:14:11 -0800192
Shashank Mittalec498ac2010-07-02 14:23:38 -0700193 // Disable predecode repair cache on certain Scorpion revisions
194 // (Raptor V2 and earlier, or Halcyon V1)
195 MRC p15, 0, r1, c0, c0, 0 //; MIDR
196 BIC r2, r1, #0xf0 //; check for Halcyon V1
Ajay Dudani9b794582010-10-19 19:56:17 -0700197 LDR r4, =0x511f0000
198 CMP r2, r4
Shashank Mittalec498ac2010-07-02 14:23:38 -0700199 BNE PVR2F1
200
201DPRC:
202 MRC p15, 0, r1, c15, c15, 2 //; PVR0F2
203 ORR r1, r1, #0x10 //; enable bit 4
204 MCR p15, 0, r1, c15, c15, 2 //; disable predecode repair cache
205
206PVR2F1:
Ajay Dudania6c845b2010-03-03 18:44:07 -0800207 //;WCP15_PVR2F1 r3
208 MCR p15, 0x2, r3, c15, c15, 0x1 //; write R3 to PVR2F1
Ajay Dudani232ce812009-12-02 00:14:11 -0800209
Ajay Dudania6c845b2010-03-03 18:44:07 -0800210 //; Reading L2_ACC
211 LDR r4, = 0x0
Ajay Dudani232ce812009-12-02 00:14:11 -0800212
Ajay Dudania6c845b2010-03-03 18:44:07 -0800213 //; Read L2_ACC_BIT_0
214 LDR r1, =TCSR_CONF_FUSE_1
215 LDR r2, =L2_ACC_BIT_0
216 LDR r3, [r1]
217 MOV r3, r3, LSR r2
218 AND r3, r3, #1
219 ORR r4, r3, r4
Ajay Dudani232ce812009-12-02 00:14:11 -0800220
Ajay Dudania6c845b2010-03-03 18:44:07 -0800221 //; Read L2_ACC_BIT_1
222 LDR r1, =TCSR_CONF_FUSE_4
223 LDR r2, =L2_ACC_BIT_1
224 LDR r3, [r1]
225 MOV r3, r3, LSR r2
226 AND r3, r3, #1
227 MOV r3, r3, LSL #1
228 ORR r4, r3, r4
Ajay Dudani232ce812009-12-02 00:14:11 -0800229
Ajay Dudania6c845b2010-03-03 18:44:07 -0800230 //; Read L2_ACC_BIT_2
231 LDR r1, =TCSR_CONF_FUSE_4
232 LDR r2, =L2_ACC_BIT_2
233 LDR r3, [r1]
234 MOV r3, r3, LSR r2
235 AND r3, r3, #1
236 MOV r3, r3, LSL #2
237 ORR r4, r3, r4
238
239l2_ck_0:
240 //; if L2_[2:0] == 000
241 LDR r5, = 0x0
242 CMP r4, r5
243 BNE l2_ck_1
244 LDR r0, =L2VR3F1_000
245 B WRITE_L2_SA_SETTINGS
246
247l2_ck_1:
248 //; if L2_[2:0] == 001
249 LDR r5, = 0x1
250 CMP r4, r5
251 BNE l2_ck_2
252 LDR r0, =L2VR3F1_001
253 B WRITE_L2_SA_SETTINGS
254
255l2_ck_2:
256 //; if L2_[2:0] == 010
257 LDR r5, = 0x2
258 CMP r4, r5
259 BNE l2_ck_3
260 LDR r0, =L2VR3F1_010
261 B WRITE_L2_SA_SETTINGS
262
263l2_ck_3:
264 //; if L2_[2:0] == 011
265 LDR r5, = 0x3
266 CMP r4, r5
267 BNE l2_ck_4
268 LDR r0, =L2VR3F1_011
269 B WRITE_L2_SA_SETTINGS
270
271l2_ck_4:
272 //; if L2_[2:0] == 100
273 LDR r5, = 0x4
274 CMP r4, r5
275 BNE l2_ck_5
276 LDR r0, =L2VR3F1_100
277 B WRITE_L2_SA_SETTINGS
278
279l2_ck_5:
280 //; if L2_[2:0] == 101
281 LDR r5, = 0x5
282 CMP r4, r5
283 BNE l2_ck_6
284 LDR r0, =L2VR3F1_101
285 B WRITE_L2_SA_SETTINGS
286
287l2_ck_6:
288 //; if L2_[2:0] == 110
289 LDR r5, = 0x6
290 CMP r4, r5
291 BNE l2_ck_7
292 LDR r0, =L2VR3F1_110
293 B WRITE_L2_SA_SETTINGS
294
295l2_ck_7:
296 //; if L2_[2:0] == 111
297 LDR r5, = 0x7
298 CMP r4, r5
299 LDR r0, =L2VR3F1_111
300 B WRITE_L2_SA_SETTINGS
Ajay Dudani232ce812009-12-02 00:14:11 -0800301
302WRITE_L2_SA_SETTINGS:
Ajay Dudania6c845b2010-03-03 18:44:07 -0800303 //;WCP15_L2VR3F1 r0
304 MCR p15, 0x3, r0, c15, c15, 0x1 //;write r0 to L2VR3F1
Chandan Uddarajub56cab52010-03-28 20:06:57 -0700305 DSB
Chandan Uddaraju385081b2010-03-28 00:38:10 -0700306 ISB
Ajay Dudaniac77c9a2010-03-22 10:34:59 -0700307
Ajay Dudani232ce812009-12-02 00:14:11 -0800308 LDR r0, =0 //;make sure the registers we touched
309 LDR r1, =0 //;are cleared when we return
310 LDR r2, =0
311 LDR r3, =0
312 LDR r4, =0
313 LDR r5, =0
314
315 //; routine complete
Ajay Dudani083d0dd2010-07-08 13:16:13 -0700316 B _cpu_early_init_complete
Ajay Dudani232ce812009-12-02 00:14:11 -0800317
Ajay Dudani232ce812009-12-02 00:14:11 -0800318.ltorg
319
320
321.globl __cpu_early_init
322__cpu_early_init:
323 //; Zero out r0 for use throughout this code. All other GPRs
324 //; (r1-r3) are set throughout this code to help establish
325 //; a consistent startup state for any code that follows.
326 //; Users should add code at the end of this routine to establish
327 //; their own stack address (r13), add translation page tables, enable
328 //; the caches, etc.
329 MOV r0, #0x0
330
331
332 //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
333 //; API to dynamically configure cache for slow/nominal/fast parts
334
335 //; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
336 //; This must be done early in code (prior to enabling the caches)
337 MOV r1, #0x2
338 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
339 ORR r1, r1, #0x00004000
340 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
341 ADD r1, r1, #0x00004000
342 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
343 ADD r1, r1, #0x00004000
344 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
345
346 //; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
347 //; and have all address bits (AM) participate.
348 //; Different settings can be used to improve performance
349 // MOVW r1, #0x01FF
350.word 0xe30011ff // hardcoded MOVW instruction due to lack of compiler support
351 // MOVT r1, #0x01FF
352.word 0xe34011ff // hardcoded MOVT instruction due to lack of compiler support
353 MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
354
355
356 //; Initialize all I$ Victim Registers to 0 for startup
357 MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
358 MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
359 MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
360 MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
361 MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
362 MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
363 MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
364 MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
365
366 //; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
367 MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
368 MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
369 MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
370 MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
371 MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
372 MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
373 MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
374 MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
375
376 //; Initialize all D$ Victim Registers to 0
377 MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
378 MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
379 MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
380 MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
381 MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
382 MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
383 MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
384 MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
385
386 //; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
387 MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
388 MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
389 MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
390 MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
391 MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
392 MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
393 MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
394 MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
395
396 //; Initialize ASID to zero
397 MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
398
399 //; ICIALL to invalidate entire I-Cache
400 MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
401
402 //; DCIALL to invalidate entire D-Cache
403 MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
404
Chandan Uddaraju66292822010-03-11 18:07:42 -0800405 //; Initialize ADFSR to zero
406 MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0
407
408 //; Initialize EFSR to zero
409 MCR p15, 7, r0, c15, c0, 1 //; EFSR r0
Ajay Dudani232ce812009-12-02 00:14:11 -0800410
411 //; The VBAR (Vector Base Address Register) should be initialized
412 //; early in your code. We are setting it to zero
413 MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
414
415 //; Ensure the MCR's above have completed their operation before continuing
416 DSB
417 ISB
418
Ajay Dudani3640a0a2010-09-27 10:29:55 -0700419 //; Setup CCPR - Cache Coherency Policy Register
420 //; setup CCPR[L1ISHP, L2ISHP] both to 0b00 (no forcing)
421 //; setup CCPR[L1OSHP, L2OSHP] both to 0b10 (force non-cacheable)
422 MOVW r2, #0x88
423 MCR p15, 0, r2, c10, c4, 2
424
Ajay Dudani232ce812009-12-02 00:14:11 -0800425 //;-------------------------------------------------------------------
426 //; There are a number of registers that must be set prior to enabling
427 //; the MMU. The DCAR is one of these registers. We are setting
428 //; it to zero (no access) to easily detect improper setup in subsequent
429 //; code sequences
430 //;-------------------------------------------------------------------
431 //; Setup DACR (Domain Access Control Register) to zero
432 MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
433
434 //; Setup DCLKCR to allow normal D-Cache line fills
435 MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
436
437 //; Setup the TLBLKCR
438 //; Victim = 6'b000000; Floor = 6'b000000;
439 //; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
440 MOV r1, #0x02
441 MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
442
443 //;Make sure TLBLKCR is complete before continuing
444 ISB
445
446 //; Invalidate the UTLB
447 MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
448
449 //; Make sure UTLB request has been presented to macro before continuing
450 ISB
451
Ajay Dudani232ce812009-12-02 00:14:11 -0800452SYSI2:
453 //; setup L2CR1 to some default Instruction and data prefetching values
454 //; Users may want specific settings for various performance enhancements
455 //; In Halcyon we do not have broadcasting barriers. So we need to turn
456 // ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
Ajay Dudanid8a91a82010-02-26 15:04:09 -0800457 LDR r2, =0x133
Ajay Dudani232ce812009-12-02 00:14:11 -0800458 MCR p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
459
460
461 //; Enable Z bit to enable branch prediction (default is off)
462 MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
463 ORR r2, r2, #0x00000800
464 MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
465
466 //; Make sure Link stack is initialized with branch and links to sequential addresses
467 //; This aids in creating a predictable startup environment
Ajay Dudani083d0dd2010-07-08 13:16:13 -0700468 BL SEQ1
469SEQ1: BL SEQ2
470SEQ2: BL SEQ3
471SEQ3: BL SEQ4
472SEQ4: BL SEQ5
473SEQ5: BL SEQ6
474SEQ6: BL SEQ7
475SEQ7: BL SEQ8
476SEQ8:
Ajay Dudani232ce812009-12-02 00:14:11 -0800477
478 //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
479 //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
480 //; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
481 MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
482
483
484 //; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
485 //; Any read to DBGPRSR clear the STICKYPD bit
486 //; ISB guarantees the read completes before attempting to
487 //; execute a CP14 instruction.
488 MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
489 ISB
490
491 //; Initialize the Watchpoint Control Registers to zero (optional)
492 //;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
493 //;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
494
495
496 //;----------------------------------------------------------------------
497 //; The saved Program Status Registers (SPSRs) should be setup
498 //; prior to any automatic mode switches. The following
499 //; code sets these registers up to a known state. Users will need to
500 //; customize these settings to meet their needs.
501 //;----------------------------------------------------------------------
502 MOV r2, #0x1f
David Ngdb6b6a82010-02-18 14:16:37 -0800503 MOV r1, #0xd7 //;ABT mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800504 msr cpsr_c, r1 //;ABT mode
505 msr spsr_cxfs, r2 //;clear the spsr
David Ngdb6b6a82010-02-18 14:16:37 -0800506 MOV r1, #0xdb //;UND mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800507 msr cpsr_c, r1 //;UND mode
508 msr spsr_cxfs, r2 //;clear the spsr
David Ngdb6b6a82010-02-18 14:16:37 -0800509 MOV r1, #0xd1 //;FIQ mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800510 msr cpsr_c, r1 //;FIQ mode
511 msr spsr_cxfs, r2 //;clear the spsr
David Ngdb6b6a82010-02-18 14:16:37 -0800512 MOV r1, #0xd2 //;IRQ mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800513 msr cpsr_c, r1 //;IRQ mode
514 msr spsr_cxfs, r2 //;clear the spsr
David Ngdb6b6a82010-02-18 14:16:37 -0800515 MOV r1, #0xd6 //;Monitor mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800516 msr cpsr_c, r1 //;Monitor mode
517 msr spsr_cxfs, r2 //;clear the spsr
David Ngdb6b6a82010-02-18 14:16:37 -0800518 MOV r1, #0xd3 //;SVC mode
Ajay Dudani232ce812009-12-02 00:14:11 -0800519 msr cpsr_c, r1 //;SVC mode
520 msr spsr_cxfs, r2 //;clear the spsr
521
522
523 //;----------------------------------------------------------------------
524 //; Enabling Error reporting is something users may want to do at
525 //; some other point in time. We have chosen some default settings
526 //; that should be reviewed. Most of these registers come up in an
527 //; unpredictable state after reset.
528 //;----------------------------------------------------------------------
529//;Start of error and control setting
530
531 //; setup L2CR0 with various L2/TCM control settings
532 //; enable out of order bus attributes and error reporting
533 //; this register comes up unpredictable after reset
534 // MOVW r1, #0x0F0F
535.word 0xe3001f0f // hardcoded MOVW instruction due to lack of compiler support
536 // MOVT r1, #0xC005
537.word 0xe34c1005 // hardcoded MOVW instruction due to lack of compiler support
538 MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
539
540 //; setup L2CPUCR
541 //; MOV r2, #0xFF
542 //; Enable I and D cache parity
543 //;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
544 //;tag, and data parity errors
545 MOV r2, #0xe0
546 MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
547
548 //; setup SPCR
549 //; enable all error reporting (reset value is unpredicatble for most bits)
550 MOV r3, #0x0F
551 MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
552
553 //; setup DMACHCRs (reset value unpredictable)
554 //; control setting and enable all error reporting
555 MOV r1, #0x0F
556
557 //; DMACHCR0 = 0000000F
558 MOV r2, #0x00 //; channel 0
559 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
560 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
561
562 //; DMACHCR1 = 0000000F
563 MOV r2, #0x01 //; channel 1
564 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
565 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
566
567 //; DMACHCR2 = 0000000F
568 MOV r2, #0x02 //; channel 2
569 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
570 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
571
572 //; DMACHCR3 = 0000000F
573 MOV r2, #0x03 //; channel 3
574 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
575 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
576
577 //; Set ACTLR (reset unpredictable)
578 //; Set AVIVT control, error reporting, etc.
579 //; MOV r3, #0x07
580 //; Enable I and D cache parity
581 //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
582 //;ACTLR[5:4] = 2'h3 - enable parity
583 //;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
584 //;Value to be written #0xC0037
585 // MOVW r3, #0x0037
586.word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
587 // MOVT r3, #0x000C
588.word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
Ajay Dudani232ce812009-12-02 00:14:11 -0800589 MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
590
591//;End of error and control setting
592
593 //;----------------------------------------------------------------------
594 //; Unlock ETM and read StickyPD to halt the ETM clocks from running.
595 //; This is required for power saving whether the ETM is used or not.
596 //;----------------------------------------------------------------------
597
598 //;Clear ETMOSLSR[LOCK] bit
599 MOV r1, #0x00000000
600 MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
601
602 //;Clear ETMPDSR[STICKYPD] bit
603 MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
604
605/*
606#ifdef APPSBL_ETM_ENABLE
607 ;----------------------------------------------------------------------
608 ; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
609 ;----------------------------------------------------------------------
610
611 ; enable ETM clock if disabled
612 MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
613 ORR r1, r1, #0x00000008
614 MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
615 ISB
616
617 ; set trigger event to counter1 being zero
618 MOV r3, #0x00000040
619 MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
620
621 ; clear ETMSR
622 MOV r2, #0x00000000
623 MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
624
625 ; clear trace enable single address comparator usage
626 MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
627
628 ; set trace enable to always
629 MOV r2, #0x0000006F
630 MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
631
632 ; clear trace enable address range comparator usage and exclude nothing
633 MOV r2, #0x01000000
634 MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
635
636 ; set view data to always
637 MOV r2, #0x0000006F
638 MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
639
640 ; clear view data single address comparator usage
641 MOV r2, #0x00000000
642 MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
643
644 ; clear view data address range comparator usage and exclude nothing
645 MOV r2, #0x00010000
646 MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
647
648 ; set counter1 to 194
649 MOV r2, #0x000000C2
650 MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
651
652 ; set counter1 to never reload
653 MOV r2, #0x0000406F
654 MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
655
656 ; set counter1 to decrement every cycle
657 MOV r2, #0x0000006F
658 MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
659
660 ; Set trace synchronization frequency 1024 bytes
661 MOV r2, #0x00000400
662 MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
663
664 ; Program etm control register
665 ; - Set the CPU to ETM clock ratio to 1:1
666 ; - Set the ETM to perform data address tracing
667 MOV r2, #0x00002008
668 MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
669 ISB
670#endif *//* APPSBL_ETM_ENABLE */
671
672/*
673#ifdef APPSBL_VFP_ENABLE
674 ;----------------------------------------------------------------------
675 ; Perform the following operations if you intend to make use of
676 ; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
677 ; indicating the VFP unit is present (i.e.Cortex-A8). .
678 ; Some tools will require full double precision floating point support
679 ; which will become available in Scorpion pass 2
680 ;----------------------------------------------------------------------
681 ; allow full access to CP 10 and 11 space for VFP/NEON use
682 MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
683 ORR r1, r1, #0x00F00000 ; enable full access for p10,11
684 MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
685
686 ;make sure the CPACR is complete before continuing
687 ISB
688
689 ; Enable VFP itself (certain OSes may want to dynamically set/clear
690 ; the enable bit based on the application being executed
691 MOV r1, #0x40000000
692 FMXR FPEXC, r1
693#endif *//* APPSBL_VFP_ENABLE */
694
695 /* we have no stack, so just tail-call into the SET_SA routine... */
696 b SET_SA
697
698
699.ltorg