Jeevan Shriram | f0a9848 | 2015-01-14 14:40:08 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #ifndef _PLATFORM_MSM_SHARED_MDP_5_H_ |
| 31 | #define _PLATFORM_MSM_SHARED_MDP_5_H_ |
| 32 | |
| 33 | #include <msm_panel.h> |
| 34 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 35 | #define PIPE_SSPP_SRC0_ADDR 0x14 |
| 36 | #define PIPE_SSPP_SRC_YSTRIDE 0x24 |
| 37 | #define PIPE_SSPP_SRC_IMG_SIZE 0x04 |
| 38 | #define PIPE_SSPP_SRC_SIZE 0x00 |
| 39 | #define PIPE_SSPP_SRC_OUT_SIZE 0x0C |
| 40 | #define PIPE_SSPP_SRC_XY 0x08 |
| 41 | #define PIPE_SSPP_OUT_XY 0x10 |
| 42 | #define PIPE_SSPP_SRC_FORMAT 0x30 |
| 43 | #define PIPE_SSPP_SRC_UNPACK_PATTERN 0x34 |
| 44 | #define PIPE_SSPP_SRC_OP_MODE 0x38 |
Dhaval Patel | 142daad | 2013-10-18 18:58:09 -0700 | [diff] [blame] | 45 | #define REQPRIORITY_FIFO_WATERMARK0 0x50 |
| 46 | #define REQPRIORITY_FIFO_WATERMARK1 0x54 |
| 47 | #define REQPRIORITY_FIFO_WATERMARK2 0x58 |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 48 | #define PIPE_SW_PIXEL_EXT_C0_REQ 0x108 |
| 49 | #define PIPE_SW_PIXEL_EXT_C1C2_REQ 0x118 |
| 50 | #define PIPE_SW_PIXEL_EXT_C3_REQ 0x128 |
| 51 | #define PIPE_COMP0_3_PHASE_STEP_X 0x210 |
| 52 | #define PIPE_COMP0_3_PHASE_STEP_Y 0x214 |
| 53 | #define PIPE_COMP1_2_PHASE_STEP_X 0x218 |
| 54 | #define PIPE_COMP1_2_PHASE_STEP_Y 0x21c |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 55 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 56 | #define LAYER_0_OUT_SIZE 0x04 |
| 57 | #define LAYER_0_OP_MODE 0x00 |
| 58 | #define LAYER_0_BORDER_COLOR_0 0x08 |
| 59 | #define LAYER_0_BLEND_OP 0x20 |
| 60 | #define LAYER_0_BLEND0_FG_ALPHA 0x24 |
| 61 | #define LAYER_1_BLEND_OP 0x50 |
| 62 | #define LAYER_1_BLEND0_FG_ALPHA 0x54 |
| 63 | #define LAYER_2_BLEND_OP 0x80 |
| 64 | #define LAYER_2_BLEND0_FG_ALPHA 0x84 |
| 65 | #define LAYER_3_BLEND_OP 0xB0 |
| 66 | #define LAYER_3_BLEND0_FG_ALPHA 0xB4 |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 67 | |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 68 | /* HW Revisions for different MDSS targets */ |
| 69 | #define MDSS_GET_MAJOR(rev) ((rev) >> 28) |
| 70 | #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) |
| 71 | #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) |
| 72 | #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 73 | |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 74 | #define MDSS_IS_MAJOR_MINOR_MATCHING(a, b) \ |
| 75 | (MDSS_GET_MAJOR_MINOR((a)) == MDSS_GET_MAJOR_MINOR((b))) |
| 76 | |
| 77 | #define MDSS_MDP_REV(major, minor, step) \ |
| 78 | ((((major) & 0x000F) << 28) | \ |
| 79 | (((minor) & 0x0FFF) << 16) | \ |
| 80 | ((step) & 0xFFFF)) |
| 81 | |
| 82 | #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ |
| 83 | #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ |
| 84 | #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ |
| 85 | #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ |
| 86 | #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ |
| 87 | #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ |
Dhaval Patel | ddce301 | 2014-08-12 14:08:31 -0700 | [diff] [blame] | 88 | #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 89 | #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 90 | #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1.0 */ |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 91 | #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 92 | #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ |
Jeevan Shriram | f0a9848 | 2015-01-14 14:40:08 -0800 | [diff] [blame] | 93 | #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 94 | #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 95 | #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 96 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 97 | #define MDSS_MAX_LINE_BUF_WIDTH 2048 |
| 98 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 99 | #define MDP_HW_REV REG_MDP(0x0100) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 100 | #define MDP_INTR_EN REG_MDP(0x0110) |
| 101 | #define MDP_INTR_CLEAR REG_MDP(0x0118) |
| 102 | #define MDP_HIST_INTR_EN REG_MDP(0x011C) |
| 103 | |
| 104 | #define MDP_DISP_INTF_SEL REG_MDP(0x0104) |
| 105 | #define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x03E0) |
| 106 | #define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x02EC) |
| 107 | #define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x04F8) |
| 108 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 109 | #define MDP_INTF_0_TIMING_ENGINE_EN REG_MDP(0x12500) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 110 | #define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700) |
Aravind Venkateswaran | 982bdd8 | 2014-12-08 12:03:11 -0800 | [diff] [blame] | 111 | #define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12900) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 112 | #define MDP_INTF_3_TIMING_ENGINE_EN REG_MDP(0x12B00) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 113 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 114 | #define MDP_CTL_0_BASE REG_MDP(0x600) |
| 115 | #define MDP_CTL_1_BASE REG_MDP(0x700) |
| 116 | |
Siddhartha Agrawal | 869809e | 2014-09-25 10:18:59 -0700 | [diff] [blame] | 117 | #define MDP_PP_0_BASE REG_MDP(0x12D00) |
| 118 | #define MDP_PP_1_BASE REG_MDP(0x12E00) |
| 119 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 120 | #define CTL_LAYER_0 0x00 |
| 121 | #define CTL_LAYER_1 0x04 |
| 122 | #define CTL_TOP 0x14 |
| 123 | #define CTL_FLUSH 0x18 |
| 124 | #define CTL_START 0x1C |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 125 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 126 | #define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x3F4) |
| 127 | #define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x3F8) |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 128 | #define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x4F0) |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 129 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 130 | #define MDP_INTF_0_BASE REG_MDP(0x12500) |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 131 | #define MDP_INTF_1_BASE REG_MDP(0x12700) |
| 132 | #define MDP_INTF_2_BASE REG_MDP(0x12900) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 133 | #define MDP_INTF_3_BASE REG_MDP(0x12B00) |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 134 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 135 | #define MDP_INTF_CONFIG 0x04 |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 136 | #define MDP_HSYNC_CTL 0x08 |
| 137 | #define MDP_VSYNC_PERIOD_F0 0x0C |
| 138 | #define MDP_VSYNC_PERIOD_F1 0x10 |
| 139 | #define MDP_VSYNC_PULSE_WIDTH_F0 0x14 |
| 140 | #define MDP_VSYNC_PULSE_WIDTH_F1 0x18 |
| 141 | #define MDP_DISPLAY_HCTL 0x3C |
| 142 | #define MDP_DISPLAY_V_START_F0 0x1C |
| 143 | #define MDP_DISPLAY_V_START_F1 0x20 |
| 144 | #define MDP_DISPLAY_V_END_F0 0x24 |
| 145 | #define MDP_DISPLAY_V_END_F1 0x28 |
| 146 | #define MDP_ACTIVE_HCTL 0x40 |
| 147 | #define MDP_ACTIVE_V_START_F0 0x2C |
| 148 | #define MDP_ACTIVE_V_START_F1 0x30 |
| 149 | #define MDP_ACTIVE_V_END_F0 0x34 |
| 150 | #define MDP_ACTIVE_V_END_F1 0x38 |
| 151 | #define MDP_UNDERFFLOW_COLOR 0x48 |
| 152 | #define MDP_PANEL_FORMAT 0x90 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 153 | #define MDP_PROG_FETCH_START 0x170 |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 154 | |
| 155 | #define MDP_CLK_CTRL0 REG_MDP(0x03AC) |
| 156 | #define MDP_CLK_CTRL1 REG_MDP(0x03B4) |
| 157 | #define MDP_CLK_CTRL2 REG_MDP(0x03BC) |
| 158 | #define MDP_CLK_CTRL3 REG_MDP(0x04A8) |
| 159 | #define MDP_CLK_CTRL4 REG_MDP(0x04B0) |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 160 | #define MDP_CLK_CTRL5 REG_MDP(0x04B8) |
Dhaval Patel | 7e39ae0 | 2013-10-25 10:30:48 -0700 | [diff] [blame] | 161 | #define MDP_CLK_CTRL6 REG_MDP(0x03C4) |
| 162 | #define MDP_CLK_CTRL7 REG_MDP(0x04D0) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 163 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 164 | #define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x0180) |
| 165 | #define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x0230) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 166 | |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 167 | /* source pipe opmode bits for flip */ |
| 168 | #define MDSS_MDP_OP_MODE_FLIP_UD BIT(14) |
| 169 | #define MDSS_MDP_OP_MODE_FLIP_LR BIT(13) |
| 170 | |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 171 | #define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x02E0) |
Dhaval Patel | 7e39ae0 | 2013-10-25 10:30:48 -0700 | [diff] [blame] | 172 | #define MDP_QOS_REMAPPER_CLASS_1 REG_MDP(0x02E4) |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 173 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 174 | #define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0x24004) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 175 | #define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0x240D8) |
Siddhartha Agrawal | f058d62 | 2013-01-28 16:21:03 -0800 | [diff] [blame] | 176 | #define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0x240F0) |
| 177 | #define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0x24124) |
| 178 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0x24160) |
| 179 | #define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0x24164) |
| 180 | #define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0x24178) |
| 181 | #define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0x2417C) |
Dhaval Patel | 7e39ae0 | 2013-10-25 10:30:48 -0700 | [diff] [blame] | 182 | #define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0x240B0) |
| 183 | #define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0x240B4) |
| 184 | #define VBIF_VBIF_IN_RD_LIM_CONF2 REG_MDP(0x240B8) |
| 185 | #define VBIF_VBIF_IN_RD_LIM_CONF3 REG_MDP(0x240BC) |
| 186 | #define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0x240C0) |
| 187 | #define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0x240C4) |
| 188 | #define VBIF_VBIF_IN_WR_LIM_CONF2 REG_MDP(0x240C8) |
| 189 | #define VBIF_VBIF_IN_WR_LIM_CONF3 REG_MDP(0x240CC) |
| 190 | #define VBIF_VBIF_ABIT_SHORT REG_MDP(0x24070) |
| 191 | #define VBIF_VBIF_ABIT_SHORT_CONF REG_MDP(0x24074) |
| 192 | #define VBIF_VBIF_GATE_OFF_WRREQ_EN REG_MDP(0x240A8) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 193 | |
Siddhartha Agrawal | 869809e | 2014-09-25 10:18:59 -0700 | [diff] [blame] | 194 | #define MDSS_MDP_REG_PP_FBC_MODE 0x034 |
| 195 | #define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038 |
| 196 | #define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C |
| 197 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 198 | void mdp_set_revision(int rev); |
| 199 | int mdp_get_revision(); |
| 200 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 201 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, struct fbcon_config *fb); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 202 | int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 203 | unsigned short num_of_lanes); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 204 | int mdp_dsi_video_on(struct msm_panel_info *pinfo); |
| 205 | int mdp_dma_on(struct msm_panel_info *pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 206 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 207 | int mdp_edp_on(struct msm_panel_info *pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 208 | int mdp_edp_off(void); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 209 | void mdp_disable(void); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 210 | void mdp_gdsc_ctrl(uint8_t enable); |
| 211 | int mdp_get_revision(); |
| 212 | uint8_t target_is_edp(); |
| 213 | void target_edp_panel_init(struct msm_panel_info *pinfo); |
| 214 | int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo); |
| 215 | int target_edp_panel_enable(void); |
| 216 | int target_edp_panel_disable(void); |
| 217 | int target_edp_bl_ctrl(int enable); |
| 218 | int mdss_hdmi_init(void); |
| 219 | int mdss_hdmi_on(struct msm_panel_info *pinfo); |
| 220 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb); |
Ajay Singh Parmar | 392f07a | 2014-11-19 15:06:19 -0800 | [diff] [blame] | 221 | void mdss_hdmi_get_vic(char *buf); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 222 | int msm_display_off(); |
| 223 | void display_shutdown(void); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 224 | #endif |