Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 15 | * |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 27 | */ |
| 28 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 29 | #include <err.h> |
| 30 | #include <assert.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 31 | #include <debug.h> |
| 32 | #include <reg.h> |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 33 | #include <platform/timer.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 34 | #include <platform/iomap.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 35 | #include <mmc.h> |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 36 | #include <clock.h> |
| 37 | #include <platform/clock.h> |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 38 | #include <blsp_qup.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 39 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 40 | void hsusb_clock_init(void) |
| 41 | { |
| 42 | int ret; |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 43 | struct clk *iclk, *cclk; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 44 | |
| 45 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 46 | if(ret) |
| 47 | { |
| 48 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 49 | ASSERT(0); |
| 50 | } |
| 51 | |
| 52 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 53 | if(ret) |
| 54 | { |
| 55 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 56 | ASSERT(0); |
| 57 | } |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 58 | |
| 59 | mdelay(20); |
| 60 | |
| 61 | iclk = clk_get("usb_iface_clk"); |
| 62 | cclk = clk_get("usb_core_clk"); |
| 63 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 64 | clk_disable(iclk); |
| 65 | clk_disable(cclk); |
| 66 | |
| 67 | mdelay(20); |
| 68 | |
| 69 | /* Start the block reset for usb */ |
| 70 | writel(1, USB_HS_BCR); |
| 71 | |
| 72 | mdelay(20); |
| 73 | |
| 74 | /* Take usb block out of reset */ |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 75 | writel(0, USB_HS_BCR); |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 76 | |
| 77 | mdelay(20); |
| 78 | |
| 79 | ret = clk_enable(iclk); |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 80 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 81 | if(ret) |
| 82 | { |
| 83 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 84 | ASSERT(0); |
| 85 | } |
| 86 | |
| 87 | ret = clk_enable(cclk); |
| 88 | |
| 89 | if(ret) |
| 90 | { |
| 91 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 92 | ASSERT(0); |
| 93 | } |
| 94 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 95 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 96 | |
| 97 | void clock_init_mmc(uint32_t interface) |
| 98 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 99 | char clk_name[64]; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 100 | int ret; |
| 101 | |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 102 | snprintf(clk_name, 64, "sdc%u_iface_clk", interface); |
| 103 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 104 | /* enable interface clock */ |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 105 | ret = clk_get_set_enable(clk_name, 0, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 106 | if(ret) |
| 107 | { |
| 108 | dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret); |
| 109 | ASSERT(0); |
| 110 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | /* Configure MMC clock */ |
| 114 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 115 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 116 | int ret; |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 117 | uint32_t reg; |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 118 | char clk_name[64]; |
| 119 | |
| 120 | snprintf(clk_name, 64, "sdc%u_core_clk", interface); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 121 | |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 122 | /* Disalbe MCI_CLK before changing the sdcc clock */ |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 123 | #ifndef MMC_SDHCI_SUPPORT |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 124 | mmc_boot_mci_clk_disable(); |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 125 | #endif |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 126 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 127 | if(freq == MMC_CLK_400KHZ) |
| 128 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 129 | ret = clk_get_set_enable(clk_name, 400000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 130 | } |
Channagoud Kadabi | 181f1dd | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 131 | else if(freq == MMC_CLK_25MHZ) |
| 132 | { |
| 133 | ret = clk_get_set_enable(clk_name, 25000000, 1); |
| 134 | } |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 135 | else if(freq == MMC_CLK_50MHZ) |
| 136 | { |
Neeti Desai | ddc771b | 2012-08-28 18:17:04 -0700 | [diff] [blame] | 137 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 138 | } |
Channagoud Kadabi | 8495f88 | 2013-04-02 11:20:28 -0700 | [diff] [blame] | 139 | else if(freq == MMC_CLK_96MHZ) |
| 140 | { |
| 141 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 142 | } |
Channagoud Kadabi | 181f1dd | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 143 | else if(freq == MMC_CLK_192MHZ) |
| 144 | { |
| 145 | ret = clk_get_set_enable(clk_name, 192000000, 1); |
| 146 | } |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 147 | else if(freq == MMC_CLK_200MHZ) |
| 148 | { |
| 149 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 150 | } |
Channagoud Kadabi | 181f1dd | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 151 | else if(freq == MMC_CLK_400MHZ) |
| 152 | { |
| 153 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
| 154 | } |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 155 | else |
| 156 | { |
Channagoud Kadabi | cb6cf69 | 2013-08-02 11:53:13 -0700 | [diff] [blame] | 157 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 158 | ASSERT(0); |
| 159 | } |
| 160 | |
| 161 | |
| 162 | if(ret) |
| 163 | { |
Channagoud Kadabi | cb6cf69 | 2013-08-02 11:53:13 -0700 | [diff] [blame] | 164 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 165 | ASSERT(0); |
| 166 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 167 | |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 168 | /* Enalbe MCI clock */ |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 169 | #ifndef MMC_SDHCI_SUPPORT |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 170 | mmc_boot_mci_clk_enable(); |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 171 | #endif |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 172 | } |
| 173 | |
Channagoud Kadabi | 181f1dd | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 174 | /* Configure clocks needed for CDCLP533 circuit */ |
| 175 | void clock_config_cdc(uint32_t interface) |
| 176 | { |
| 177 | int ret = 0; |
| 178 | char clk_name[64]; |
| 179 | |
Channagoud Kadabi | 2704edd | 2014-04-01 14:43:03 -0700 | [diff] [blame] | 180 | /* CDC clocks are not supported for 8974 v1 & v2 |
| 181 | * only pro msm's support it |
| 182 | */ |
| 183 | if (platform_is_8974()) |
| 184 | return; |
| 185 | |
Channagoud Kadabi | 181f1dd | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 186 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface); |
| 187 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 188 | if (ret) |
| 189 | { |
| 190 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 191 | ASSERT(0); |
| 192 | } |
| 193 | |
| 194 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface); |
| 195 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 196 | if (ret) |
| 197 | { |
| 198 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 199 | ASSERT(0); |
| 200 | } |
| 201 | } |
| 202 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 203 | /* Configure UART clock based on the UART block id*/ |
| 204 | void clock_config_uart_dm(uint8_t id) |
| 205 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 206 | int ret; |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 207 | |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 208 | |
| 209 | ret = clk_get_set_enable("uart2_iface_clk", 0, 1); |
| 210 | if(ret) |
| 211 | { |
| 212 | dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret); |
| 213 | ASSERT(0); |
| 214 | } |
| 215 | |
| 216 | ret = clk_get_set_enable("uart2_core_clk", 7372800, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 217 | if(ret) |
| 218 | { |
| 219 | dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret); |
| 220 | ASSERT(0); |
| 221 | } |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 222 | } |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 223 | |
| 224 | /* Function to asynchronously reset CE. |
| 225 | * Function assumes that all the CE clocks are off. |
| 226 | */ |
| 227 | static void ce_async_reset(uint8_t instance) |
| 228 | { |
| 229 | if (instance == 1) |
| 230 | { |
| 231 | /* TODO: Add support for instance 1. */ |
| 232 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 233 | ASSERT(0); |
| 234 | } |
| 235 | else if (instance == 2) |
| 236 | { |
| 237 | /* Start the block reset for CE */ |
| 238 | writel(1, GCC_CE2_BCR); |
| 239 | |
| 240 | udelay(2); |
| 241 | |
| 242 | /* Take CE block out of reset */ |
| 243 | writel(0, GCC_CE2_BCR); |
| 244 | |
| 245 | udelay(2); |
| 246 | } |
| 247 | else |
| 248 | { |
| 249 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 250 | ASSERT(0); |
| 251 | } |
| 252 | } |
| 253 | |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 254 | void clock_ce_enable(uint8_t instance) |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 255 | { |
| 256 | int ret; |
| 257 | char clk_name[64]; |
| 258 | |
| 259 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 260 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 261 | if(ret) |
| 262 | { |
| 263 | dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret); |
| 264 | ASSERT(0); |
| 265 | } |
| 266 | |
| 267 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 268 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 269 | if(ret) |
| 270 | { |
| 271 | dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret); |
| 272 | ASSERT(0); |
| 273 | } |
| 274 | |
| 275 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 276 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 277 | if(ret) |
| 278 | { |
| 279 | dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret); |
| 280 | ASSERT(0); |
| 281 | } |
| 282 | |
| 283 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 284 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 285 | if(ret) |
| 286 | { |
| 287 | dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret); |
| 288 | ASSERT(0); |
| 289 | } |
| 290 | |
| 291 | /* Wait for 48 * #pipes cycles. |
| 292 | * This is necessary as immediately after an access control reset (boot up) |
| 293 | * or a debug re-enable, the Crypto core sequentially clears its internal |
| 294 | * pipe key storage memory. If pipe key initialization writes are attempted |
| 295 | * during this time, they may be overwritten by the internal clearing logic. |
| 296 | */ |
| 297 | udelay(1); |
| 298 | } |
| 299 | |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 300 | void clock_ce_disable(uint8_t instance) |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 301 | { |
| 302 | struct clk *ahb_clk; |
| 303 | struct clk *cclk; |
| 304 | struct clk *axi_clk; |
| 305 | struct clk *src_clk; |
| 306 | char clk_name[64]; |
| 307 | |
| 308 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 309 | src_clk = clk_get(clk_name); |
| 310 | |
| 311 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 312 | ahb_clk = clk_get(clk_name); |
| 313 | |
| 314 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 315 | axi_clk = clk_get(clk_name); |
| 316 | |
| 317 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 318 | cclk = clk_get(clk_name); |
| 319 | |
| 320 | clk_disable(ahb_clk); |
| 321 | clk_disable(axi_clk); |
| 322 | clk_disable(cclk); |
| 323 | clk_disable(src_clk); |
| 324 | |
| 325 | /* Some delay for the clocks to stabalize. */ |
| 326 | udelay(1); |
| 327 | } |
| 328 | |
| 329 | void clock_config_ce(uint8_t instance) |
| 330 | { |
| 331 | /* Need to enable the clock before disabling since the clk_disable() |
| 332 | * has a check to default to nop when the clk_enable() is not called |
| 333 | * on that particular clock. |
| 334 | */ |
| 335 | clock_ce_enable(instance); |
| 336 | |
| 337 | clock_ce_disable(instance); |
| 338 | |
| 339 | ce_async_reset(instance); |
| 340 | |
| 341 | clock_ce_enable(instance); |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 342 | |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 343 | } |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 344 | |
| 345 | void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id) |
| 346 | { |
| 347 | uint8_t ret = 0; |
| 348 | char clk_name[64]; |
| 349 | |
| 350 | struct clk *qup_clk; |
| 351 | |
| 352 | snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id); |
| 353 | |
| 354 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 355 | |
| 356 | if (ret) { |
| 357 | dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name); |
| 358 | return; |
| 359 | } |
| 360 | |
| 361 | snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id, |
| 362 | (qup_id + 1)); |
| 363 | |
| 364 | qup_clk = clk_get(clk_name); |
| 365 | |
| 366 | if (!qup_clk) { |
| 367 | dprintf(CRITICAL, "Failed to get %s\n", clk_name); |
| 368 | return; |
| 369 | } |
| 370 | |
| 371 | ret = clk_enable(qup_clk); |
| 372 | |
| 373 | if (ret) { |
| 374 | dprintf(CRITICAL, "Failed to enable %s\n", clk_name); |
| 375 | return; |
| 376 | } |
| 377 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 378 | |
| 379 | void mdp_gdsc_ctrl(uint8_t enable) |
| 380 | { |
| 381 | uint32_t reg = 0; |
| 382 | reg = readl(MDP_GDSCR); |
| 383 | if (enable) { |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 384 | if (!(reg & GDSC_POWER_ON_BIT)) { |
Siddhartha Agrawal | 267fc3f | 2013-03-25 17:03:50 -0700 | [diff] [blame] | 385 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 386 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 387 | writel(reg, MDP_GDSCR); |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 388 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 389 | } else { |
| 390 | dprintf(INFO, "MDP GDSC already enabled\n"); |
Siddhartha Agrawal | 267fc3f | 2013-03-25 17:03:50 -0700 | [diff] [blame] | 391 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 392 | } else { |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 393 | reg |= BIT(0); |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 394 | writel(reg, MDP_GDSCR); |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 395 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 396 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 397 | } |
| 398 | |
| 399 | /* Configure MDP clock */ |
| 400 | void mdp_clock_init(void) |
| 401 | { |
| 402 | int ret; |
| 403 | |
Siddhartha Agrawal | 6bf6c15 | 2013-05-29 20:47:20 -0700 | [diff] [blame] | 404 | /* Set MDP clock to 240MHz */ |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 405 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 406 | if(ret) |
| 407 | { |
| 408 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 409 | ASSERT(0); |
| 410 | } |
| 411 | |
Siddhartha Agrawal | 6bf6c15 | 2013-05-29 20:47:20 -0700 | [diff] [blame] | 412 | ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1); |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 413 | if(ret) |
| 414 | { |
| 415 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 416 | ASSERT(0); |
| 417 | } |
| 418 | |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 419 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 420 | if(ret) |
| 421 | { |
| 422 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 423 | ASSERT(0); |
| 424 | } |
| 425 | |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 426 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 427 | if(ret) |
| 428 | { |
| 429 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 430 | ASSERT(0); |
| 431 | } |
| 432 | |
| 433 | ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1); |
| 434 | if(ret) |
| 435 | { |
| 436 | dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret); |
| 437 | ASSERT(0); |
| 438 | } |
| 439 | } |
| 440 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 441 | void mdp_clock_disable(uint32_t dual_dsi) |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 442 | { |
| 443 | writel(0x0, DSI_BYTE0_CBCR); |
| 444 | writel(0x0, DSI_PIXEL0_CBCR); |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 445 | if (dual_dsi) { |
| 446 | writel(0x0, DSI_BYTE1_CBCR); |
| 447 | writel(0x0, DSI_PIXEL1_CBCR); |
| 448 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 449 | clk_disable(clk_get("mdss_vsync_clk")); |
| 450 | clk_disable(clk_get("mdss_mdp_clk")); |
| 451 | clk_disable(clk_get("mdss_mdp_lut_clk")); |
| 452 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 453 | clk_disable(clk_get("mdp_ahb_clk")); |
| 454 | |
| 455 | } |
| 456 | |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 457 | /* Initialize all clocks needed by Display */ |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 458 | void mmss_clock_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi) |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 459 | { |
| 460 | int ret; |
| 461 | |
| 462 | /* Configure Byte clock */ |
| 463 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 464 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 465 | writel(0x1, DSI_BYTE0_CBCR); |
| 466 | |
| 467 | /* Configure ESC clock */ |
| 468 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 469 | if(ret) |
| 470 | { |
| 471 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 472 | ASSERT(0); |
| 473 | } |
| 474 | |
| 475 | /* Configure MMSSNOC AXI clock */ |
| 476 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 477 | if(ret) |
| 478 | { |
| 479 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 480 | ASSERT(0); |
| 481 | } |
| 482 | |
| 483 | /* Configure MMSSNOC AXI clock */ |
| 484 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 485 | if(ret) |
| 486 | { |
| 487 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 488 | ASSERT(0); |
| 489 | } |
| 490 | |
| 491 | /* Configure AXI clock */ |
| 492 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 493 | if(ret) |
| 494 | { |
| 495 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 496 | ASSERT(0); |
| 497 | } |
| 498 | |
| 499 | /* Configure Pixel clock */ |
Asaf Penso | fd099cf | 2013-05-20 11:12:38 +0300 | [diff] [blame] | 500 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 501 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 502 | writel(0x1, DSI_PIXEL0_CBCR); |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 503 | |
| 504 | if (dual_dsi) { |
| 505 | /* Configure Byte 1 clock */ |
| 506 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 507 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 508 | writel(0x1, DSI_BYTE1_CBCR); |
| 509 | |
| 510 | /* Configure ESC clock */ |
| 511 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 512 | if(ret) |
| 513 | { |
| 514 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 515 | ASSERT(0); |
| 516 | } |
| 517 | |
| 518 | /* Configure Pixel clock */ |
| 519 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 520 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 521 | writel(0x1, DSI_PIXEL1_CBCR); |
| 522 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 523 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 524 | |
Arpita Banerjee | 8435ef9 | 2013-05-30 15:03:23 -0700 | [diff] [blame] | 525 | void mmss_clock_auto_pll_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi, |
| 526 | uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 527 | { |
| 528 | int ret; |
| 529 | |
| 530 | /* Configure Byte clock -autopll- This will not change because |
| 531 | byte clock does not need any divider*/ |
| 532 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 533 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 534 | writel(0x1, DSI_BYTE0_CBCR); |
| 535 | |
| 536 | /* Configure ESC clock */ |
| 537 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 538 | if(ret) |
| 539 | { |
| 540 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 541 | ASSERT(0); |
| 542 | } |
| 543 | |
| 544 | /* Configure MMSSNOC AXI clock */ |
| 545 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 546 | if(ret) |
| 547 | { |
| 548 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 549 | ASSERT(0); |
| 550 | } |
| 551 | |
| 552 | /* Configure S0 AXI clock */ |
| 553 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 554 | if(ret) |
| 555 | { |
| 556 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 557 | ASSERT(0); |
| 558 | } |
| 559 | |
| 560 | /* Configure AXI clock */ |
| 561 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 562 | if(ret) |
| 563 | { |
| 564 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 565 | ASSERT(0); |
| 566 | } |
| 567 | |
| 568 | /* Configure Pixel clock */ |
| 569 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
| 570 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 571 | writel(0x1, DSI_PIXEL0_CBCR); |
| 572 | |
| 573 | writel(pclk0_m, DSI_PIXEL0_M); |
| 574 | writel(pclk0_n, DSI_PIXEL0_N); |
| 575 | writel(pclk0_d, DSI_PIXEL0_D); |
| 576 | |
| 577 | if (dual_dsi) { |
| 578 | /* Configure Byte 1 clock */ |
| 579 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 580 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 581 | writel(0x1, DSI_BYTE1_CBCR); |
| 582 | |
| 583 | /* Configure ESC clock */ |
| 584 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 585 | if(ret) |
| 586 | { |
| 587 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 588 | ASSERT(0); |
| 589 | } |
| 590 | |
| 591 | /* Configure Pixel clock */ |
| 592 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 593 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 594 | writel(0x1, DSI_PIXEL1_CBCR); |
| 595 | |
| 596 | writel(pclk0_m, DSI_PIXEL0_M); |
| 597 | writel(pclk0_n, DSI_PIXEL0_N); |
| 598 | writel(pclk0_d, DSI_PIXEL0_D); |
| 599 | } |
| 600 | } |
| 601 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 602 | void mmss_clock_disable(uint32_t dual_dsi) |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 603 | { |
| 604 | |
| 605 | /* Disable ESC clock */ |
| 606 | clk_disable(clk_get("mdss_esc0_clk")); |
| 607 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 608 | if (dual_dsi) { |
| 609 | /* Disable ESC clock */ |
| 610 | clk_disable(clk_get("mdss_esc1_clk")); |
| 611 | } |
| 612 | |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 613 | /* Disable MDSS AXI clock */ |
| 614 | clk_disable(clk_get("mdss_axi_clk")); |
| 615 | |
| 616 | /* Disable MMSSNOC S0AXI clock */ |
| 617 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 618 | |
| 619 | /* Disable MMSSNOC AXI clock */ |
| 620 | clk_disable(clk_get("mmss_mmssnoc_axi_clk")); |
| 621 | |
| 622 | } |
Amol Jadi | 38450af | 2013-07-23 15:01:48 -0700 | [diff] [blame] | 623 | |
| 624 | /* enables usb30 interface and master clocks */ |
| 625 | void clock_usb30_init(void) |
| 626 | { |
| 627 | int ret; |
| 628 | |
| 629 | /* interface clock */ |
| 630 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 631 | if(ret) |
| 632 | { |
| 633 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 634 | ASSERT(0); |
| 635 | } |
| 636 | |
| 637 | /* master clock */ |
| 638 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 639 | if(ret) |
| 640 | { |
| 641 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 642 | ASSERT(0); |
| 643 | } |
| 644 | } |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 645 | |
| 646 | void edp_clk_enable(void) |
| 647 | { |
| 648 | int ret; |
| 649 | |
Kuogee Hsieh | e99937a | 2013-06-06 14:21:48 -0700 | [diff] [blame] | 650 | /* Configure MMSSNOC AXI clock */ |
| 651 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 652 | if(ret) |
| 653 | { |
| 654 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 655 | ASSERT(0); |
| 656 | } |
| 657 | |
| 658 | /* Configure MMSSNOC AXI clock */ |
| 659 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 660 | if(ret) |
| 661 | { |
| 662 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 663 | ASSERT(0); |
| 664 | } |
| 665 | |
| 666 | /* Configure AXI clock */ |
| 667 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 668 | if(ret) |
| 669 | { |
| 670 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 671 | ASSERT(0); |
| 672 | } |
| 673 | |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 674 | ret = clk_get_set_enable("edp_pixel_clk", 138500000, 1); |
| 675 | if (ret) { |
| 676 | dprintf(CRITICAL, "failed to set edp_pixel_clk ret = %d\n", |
| 677 | ret); |
| 678 | ASSERT(0); |
| 679 | } |
| 680 | |
| 681 | ret = clk_get_set_enable("edp_link_clk", 270000000, 1); |
| 682 | if (ret) { |
| 683 | dprintf(CRITICAL, "failed to set edp_link_clk ret = %d\n", ret); |
| 684 | ASSERT(0); |
| 685 | } |
Kuogee Hsieh | e99937a | 2013-06-06 14:21:48 -0700 | [diff] [blame] | 686 | |
| 687 | ret = clk_get_set_enable("edp_aux_clk", 19200000, 1); |
| 688 | if (ret) { |
| 689 | dprintf(CRITICAL, "failed to set edp_aux_clk ret = %d\n", ret); |
| 690 | ASSERT(0); |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | void edp_clk_disable(void) |
| 695 | { |
| 696 | |
| 697 | writel(0x0, MDSS_EDPPIXEL_CBCR); |
| 698 | writel(0x0, MDSS_EDPLINK_CBCR); |
| 699 | clk_disable(clk_get("edp_pixel_clk")); |
| 700 | clk_disable(clk_get("edp_link_clk")); |
| 701 | clk_disable(clk_get("edp_aux_clk")); |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 702 | } |