Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * GPIO driver for Marvell SoCs |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 7 | * Andrew Lunn <andrew@lunn.ch> |
| 8 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
| 9 | * |
| 10 | * This file is licensed under the terms of the GNU General Public |
| 11 | * License version 2. This program is licensed "as is" without any |
| 12 | * warranty of any kind, whether express or implied. |
| 13 | * |
| 14 | * This driver is a fairly straightforward GPIO driver for the |
| 15 | * complete family of Marvell EBU SoC platforms (Orion, Dove, |
| 16 | * Kirkwood, Discovery, Armada 370/XP). The only complexity of this |
| 17 | * driver is the different register layout that exists between the |
| 18 | * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP |
| 19 | * platforms (MV78200 from the Discovery family and the Armada |
| 20 | * XP). Therefore, this driver handles three variants of the GPIO |
| 21 | * block: |
| 22 | * - the basic variant, called "orion-gpio", with the simplest |
| 23 | * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and |
| 24 | * non-SMP Discovery systems |
| 25 | * - the mv78200 variant for MV78200 Discovery systems. This variant |
| 26 | * turns the edge mask and level mask registers into CPU0 edge |
| 27 | * mask/level mask registers, and adds CPU1 edge mask/level mask |
| 28 | * registers. |
| 29 | * - the armadaxp variant for Armada XP systems. This variant keeps |
| 30 | * the normal cause/edge mask/level mask registers when the global |
| 31 | * interrupts are used, but adds per-CPU cause/edge mask/level mask |
| 32 | * registers n a separate memory area for the per-CPU GPIO |
| 33 | * interrupts. |
| 34 | */ |
| 35 | |
Ralph Sennhauser | d2cabc4 | 2017-03-17 18:44:06 +0100 | [diff] [blame] | 36 | #include <linux/bitops.h> |
Gregory CLEMENT | 6ec015d | 2017-05-19 18:09:20 +0200 | [diff] [blame] | 37 | #include <linux/clk.h> |
| 38 | #include <linux/err.h> |
| 39 | #include <linux/gpio.h> |
| 40 | #include <linux/init.h> |
| 41 | #include <linux/io.h> |
| 42 | #include <linux/irq.h> |
| 43 | #include <linux/irqchip/chained_irq.h> |
| 44 | #include <linux/irqdomain.h> |
| 45 | #include <linux/of_device.h> |
| 46 | #include <linux/of_irq.h> |
| 47 | #include <linux/pinctrl/consumer.h> |
| 48 | #include <linux/platform_device.h> |
| 49 | #include <linux/pwm.h> |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 50 | #include <linux/regmap.h> |
Gregory CLEMENT | 6ec015d | 2017-05-19 18:09:20 +0200 | [diff] [blame] | 51 | #include <linux/slab.h> |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 52 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 53 | #include "gpiolib.h" |
| 54 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 55 | /* |
| 56 | * GPIO unit register offsets. |
| 57 | */ |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 58 | #define GPIO_OUT_OFF 0x0000 |
| 59 | #define GPIO_IO_CONF_OFF 0x0004 |
| 60 | #define GPIO_BLINK_EN_OFF 0x0008 |
| 61 | #define GPIO_IN_POL_OFF 0x000c |
| 62 | #define GPIO_DATA_IN_OFF 0x0010 |
| 63 | #define GPIO_EDGE_CAUSE_OFF 0x0014 |
| 64 | #define GPIO_EDGE_MASK_OFF 0x0018 |
| 65 | #define GPIO_LEVEL_MASK_OFF 0x001c |
| 66 | #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 |
| 67 | |
| 68 | /* |
| 69 | * PWM register offsets. |
| 70 | */ |
| 71 | #define PWM_BLINK_ON_DURATION_OFF 0x0 |
| 72 | #define PWM_BLINK_OFF_DURATION_OFF 0x4 |
| 73 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 74 | |
| 75 | /* The MV78200 has per-CPU registers for edge mask and level mask */ |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 76 | #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 77 | #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) |
| 78 | |
Ralph Sennhauser | 7077f4c | 2017-03-16 07:33:56 +0100 | [diff] [blame] | 79 | /* |
| 80 | * The Armada XP has per-CPU registers for interrupt cause, interrupt |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 81 | * mask and interrupt level mask. Those are relative to the |
Ralph Sennhauser | 7077f4c | 2017-03-16 07:33:56 +0100 | [diff] [blame] | 82 | * percpu_membase. |
| 83 | */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 84 | #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) |
| 85 | #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) |
| 86 | #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) |
| 87 | |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 88 | #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 |
| 89 | #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 90 | #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 |
| 91 | |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 92 | #define MVEBU_MAX_GPIO_PER_BANK 32 |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 93 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 94 | struct mvebu_pwm { |
| 95 | void __iomem *membase; |
| 96 | unsigned long clk_rate; |
| 97 | struct gpio_desc *gpiod; |
| 98 | struct pwm_chip chip; |
| 99 | spinlock_t lock; |
| 100 | struct mvebu_gpio_chip *mvchip; |
| 101 | |
| 102 | /* Used to preserve GPIO/PWM registers across suspend/resume */ |
| 103 | u32 blink_select; |
| 104 | u32 blink_on_duration; |
| 105 | u32 blink_off_duration; |
| 106 | }; |
| 107 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 108 | struct mvebu_gpio_chip { |
| 109 | struct gpio_chip chip; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 110 | struct regmap *regs; |
| 111 | struct regmap *percpu_regs; |
Dan Carpenter | d535922 | 2013-11-07 10:50:19 +0300 | [diff] [blame] | 112 | int irqbase; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 113 | struct irq_domain *domain; |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 114 | int soc_variant; |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 115 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 116 | /* Used for PWM support */ |
| 117 | struct clk *clk; |
| 118 | struct mvebu_pwm *mvpwm; |
| 119 | |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 120 | /* Used to preserve GPIO registers across suspend/resume */ |
Ralph Sennhauser | f4c240c | 2017-03-16 07:34:00 +0100 | [diff] [blame] | 121 | u32 out_reg; |
| 122 | u32 io_conf_reg; |
| 123 | u32 blink_en_reg; |
| 124 | u32 in_pol_reg; |
| 125 | u32 edge_mask_regs[4]; |
| 126 | u32 level_mask_regs[4]; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | /* |
| 130 | * Functions returning addresses of individual registers for a given |
| 131 | * GPIO controller. |
| 132 | */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 133 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 134 | static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, |
| 135 | struct regmap **map, unsigned int *offset) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 136 | { |
| 137 | int cpu; |
| 138 | |
Laurent Navet | f4dcd2d9 | 2013-03-20 13:15:56 +0100 | [diff] [blame] | 139 | switch (mvchip->soc_variant) { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 140 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
| 141 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 142 | *map = mvchip->regs; |
| 143 | *offset = GPIO_EDGE_CAUSE_OFF; |
| 144 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 145 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
| 146 | cpu = smp_processor_id(); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 147 | *map = mvchip->percpu_regs; |
| 148 | *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); |
| 149 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 150 | default: |
| 151 | BUG(); |
| 152 | } |
| 153 | } |
| 154 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 155 | static u32 |
| 156 | mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) |
| 157 | { |
| 158 | struct regmap *map; |
| 159 | unsigned int offset; |
| 160 | u32 val; |
| 161 | |
| 162 | mvebu_gpioreg_edge_cause(mvchip, &map, &offset); |
| 163 | regmap_read(map, offset, &val); |
| 164 | |
| 165 | return val; |
| 166 | } |
| 167 | |
| 168 | static void |
| 169 | mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) |
| 170 | { |
| 171 | struct regmap *map; |
| 172 | unsigned int offset; |
| 173 | |
| 174 | mvebu_gpioreg_edge_cause(mvchip, &map, &offset); |
| 175 | regmap_write(map, offset, val); |
| 176 | } |
| 177 | |
| 178 | static inline void |
| 179 | mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, |
| 180 | struct regmap **map, unsigned int *offset) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 181 | { |
| 182 | int cpu; |
| 183 | |
Laurent Navet | f4dcd2d9 | 2013-03-20 13:15:56 +0100 | [diff] [blame] | 184 | switch (mvchip->soc_variant) { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 185 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 186 | *map = mvchip->regs; |
| 187 | *offset = GPIO_EDGE_MASK_OFF; |
| 188 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 189 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
| 190 | cpu = smp_processor_id(); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 191 | *map = mvchip->regs; |
| 192 | *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); |
| 193 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 194 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
| 195 | cpu = smp_processor_id(); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 196 | *map = mvchip->percpu_regs; |
| 197 | *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); |
| 198 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 199 | default: |
| 200 | BUG(); |
| 201 | } |
| 202 | } |
| 203 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 204 | static u32 |
| 205 | mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) |
| 206 | { |
| 207 | struct regmap *map; |
| 208 | unsigned int offset; |
| 209 | u32 val; |
| 210 | |
| 211 | mvebu_gpioreg_edge_mask(mvchip, &map, &offset); |
| 212 | regmap_read(map, offset, &val); |
| 213 | |
| 214 | return val; |
| 215 | } |
| 216 | |
| 217 | static void |
| 218 | mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) |
| 219 | { |
| 220 | struct regmap *map; |
| 221 | unsigned int offset; |
| 222 | |
| 223 | mvebu_gpioreg_edge_mask(mvchip, &map, &offset); |
| 224 | regmap_write(map, offset, val); |
| 225 | } |
| 226 | |
| 227 | static void |
| 228 | mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, |
| 229 | struct regmap **map, unsigned int *offset) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 230 | { |
| 231 | int cpu; |
| 232 | |
Laurent Navet | f4dcd2d9 | 2013-03-20 13:15:56 +0100 | [diff] [blame] | 233 | switch (mvchip->soc_variant) { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 234 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 235 | *map = mvchip->regs; |
| 236 | *offset = GPIO_LEVEL_MASK_OFF; |
| 237 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 238 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
| 239 | cpu = smp_processor_id(); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 240 | *map = mvchip->regs; |
| 241 | *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); |
| 242 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 243 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
| 244 | cpu = smp_processor_id(); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 245 | *map = mvchip->percpu_regs; |
| 246 | *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); |
| 247 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 248 | default: |
| 249 | BUG(); |
| 250 | } |
| 251 | } |
| 252 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 253 | static u32 |
| 254 | mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) |
| 255 | { |
| 256 | struct regmap *map; |
| 257 | unsigned int offset; |
| 258 | u32 val; |
| 259 | |
| 260 | mvebu_gpioreg_level_mask(mvchip, &map, &offset); |
| 261 | regmap_read(map, offset, &val); |
| 262 | |
| 263 | return val; |
| 264 | } |
| 265 | |
| 266 | static void |
| 267 | mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) |
| 268 | { |
| 269 | struct regmap *map; |
| 270 | unsigned int offset; |
| 271 | |
| 272 | mvebu_gpioreg_level_mask(mvchip, &map, &offset); |
| 273 | regmap_write(map, offset, val); |
| 274 | } |
| 275 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 276 | /* |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 277 | * Functions returning addresses of individual registers for a given |
| 278 | * PWM controller. |
| 279 | */ |
| 280 | static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) |
| 281 | { |
| 282 | return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; |
| 283 | } |
| 284 | |
| 285 | static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) |
| 286 | { |
| 287 | return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; |
| 288 | } |
| 289 | |
| 290 | /* |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 291 | * Functions implementing the gpio_chip methods |
| 292 | */ |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 293 | static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 294 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 295 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 296 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 297 | regmap_update_bits(mvchip->regs, GPIO_OUT_OFF, |
| 298 | BIT(pin), value ? BIT(pin) : 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 299 | } |
| 300 | |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 301 | static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 302 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 303 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 304 | u32 u; |
| 305 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 306 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u); |
| 307 | |
| 308 | if (u & BIT(pin)) { |
| 309 | u32 data_in, in_pol; |
| 310 | |
| 311 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in); |
| 312 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol); |
| 313 | u = data_in ^ in_pol; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 314 | } else { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 315 | regmap_read(mvchip->regs, GPIO_OUT_OFF, &u); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | return (u >> pin) & 1; |
| 319 | } |
| 320 | |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 321 | static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, |
| 322 | int value) |
Jamie Lentin | e913376 | 2012-10-28 12:23:24 +0000 | [diff] [blame] | 323 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 324 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Jamie Lentin | e913376 | 2012-10-28 12:23:24 +0000 | [diff] [blame] | 325 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 326 | regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF, |
| 327 | BIT(pin), value ? BIT(pin) : 0); |
Jamie Lentin | e913376 | 2012-10-28 12:23:24 +0000 | [diff] [blame] | 328 | } |
| 329 | |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 330 | static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 331 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 332 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 333 | int ret; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 334 | |
Ralph Sennhauser | 7077f4c | 2017-03-16 07:33:56 +0100 | [diff] [blame] | 335 | /* |
| 336 | * Check with the pinctrl driver whether this pin is usable as |
| 337 | * an input GPIO |
| 338 | */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 339 | ret = pinctrl_gpio_direction_input(chip->base + pin); |
| 340 | if (ret) |
| 341 | return ret; |
| 342 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 343 | regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF, |
| 344 | BIT(pin), 1); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 349 | static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 350 | int value) |
| 351 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 352 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 353 | int ret; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 354 | |
Ralph Sennhauser | 7077f4c | 2017-03-16 07:33:56 +0100 | [diff] [blame] | 355 | /* |
| 356 | * Check with the pinctrl driver whether this pin is usable as |
| 357 | * an output GPIO |
| 358 | */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 359 | ret = pinctrl_gpio_direction_output(chip->base + pin); |
| 360 | if (ret) |
| 361 | return ret; |
| 362 | |
Jamie Lentin | e913376 | 2012-10-28 12:23:24 +0000 | [diff] [blame] | 363 | mvebu_gpio_blink(chip, pin, 0); |
Thomas Petazzoni | c57d75c | 2012-10-23 10:17:05 +0200 | [diff] [blame] | 364 | mvebu_gpio_set(chip, pin, value); |
| 365 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 366 | regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF, |
| 367 | BIT(pin), 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
Ralph Sennhauser | d276de7 | 2017-03-16 07:33:58 +0100 | [diff] [blame] | 372 | static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 373 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 374 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Ralph Sennhauser | 163ad36 | 2017-03-16 07:33:59 +0100 | [diff] [blame] | 375 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 376 | return irq_create_mapping(mvchip->domain, pin); |
| 377 | } |
| 378 | |
| 379 | /* |
| 380 | * Functions implementing the irq_chip methods |
| 381 | */ |
| 382 | static void mvebu_gpio_irq_ack(struct irq_data *d) |
| 383 | { |
| 384 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 385 | struct mvebu_gpio_chip *mvchip = gc->private; |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 386 | u32 mask = d->mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 387 | |
| 388 | irq_gc_lock(gc); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 389 | mvebu_gpio_write_edge_cause(mvchip, ~mask); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 390 | irq_gc_unlock(gc); |
| 391 | } |
| 392 | |
| 393 | static void mvebu_gpio_edge_irq_mask(struct irq_data *d) |
| 394 | { |
| 395 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 396 | struct mvebu_gpio_chip *mvchip = gc->private; |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 397 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 398 | u32 mask = d->mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 399 | |
| 400 | irq_gc_lock(gc); |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 401 | ct->mask_cache_priv &= ~mask; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 402 | mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 403 | irq_gc_unlock(gc); |
| 404 | } |
| 405 | |
| 406 | static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) |
| 407 | { |
| 408 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 409 | struct mvebu_gpio_chip *mvchip = gc->private; |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 410 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 411 | u32 mask = d->mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 412 | |
| 413 | irq_gc_lock(gc); |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 414 | ct->mask_cache_priv |= mask; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 415 | mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 416 | irq_gc_unlock(gc); |
| 417 | } |
| 418 | |
| 419 | static void mvebu_gpio_level_irq_mask(struct irq_data *d) |
| 420 | { |
| 421 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 422 | struct mvebu_gpio_chip *mvchip = gc->private; |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 423 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 424 | u32 mask = d->mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 425 | |
| 426 | irq_gc_lock(gc); |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 427 | ct->mask_cache_priv &= ~mask; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 428 | mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 429 | irq_gc_unlock(gc); |
| 430 | } |
| 431 | |
| 432 | static void mvebu_gpio_level_irq_unmask(struct irq_data *d) |
| 433 | { |
| 434 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 435 | struct mvebu_gpio_chip *mvchip = gc->private; |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 436 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 437 | u32 mask = d->mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 438 | |
| 439 | irq_gc_lock(gc); |
Gregory CLEMENT | 6181954 | 2015-04-02 17:11:11 +0200 | [diff] [blame] | 440 | ct->mask_cache_priv |= mask; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 441 | mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 442 | irq_gc_unlock(gc); |
| 443 | } |
| 444 | |
| 445 | /***************************************************************************** |
| 446 | * MVEBU GPIO IRQ |
| 447 | * |
| 448 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same |
| 449 | * value of the line or the opposite value. |
| 450 | * |
| 451 | * Level IRQ handlers: DATA_IN is used directly as cause register. |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 452 | * Interrupt are masked by LEVEL_MASK registers. |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 453 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 454 | * Interrupt are masked by EDGE_MASK registers. |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 455 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 456 | * the polarity to catch the next line transaction. |
| 457 | * This is a race condition that might not perfectly |
| 458 | * work on some use cases. |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 459 | * |
| 460 | * Every eight GPIO lines are grouped (OR'ed) before going up to main |
| 461 | * cause register. |
| 462 | * |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 463 | * EDGE cause mask |
| 464 | * data-in /--------| |-----| |----\ |
| 465 | * -----| |----- ---- to main cause reg |
| 466 | * X \----------------| |----/ |
| 467 | * polarity LEVEL mask |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 468 | * |
| 469 | ****************************************************************************/ |
| 470 | |
| 471 | static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
| 472 | { |
| 473 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 474 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
| 475 | struct mvebu_gpio_chip *mvchip = gc->private; |
| 476 | int pin; |
| 477 | u32 u; |
| 478 | |
| 479 | pin = d->hwirq; |
| 480 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 481 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &u); |
| 482 | if ((u & BIT(pin)) == 0) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 483 | return -EINVAL; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 484 | |
| 485 | type &= IRQ_TYPE_SENSE_MASK; |
| 486 | if (type == IRQ_TYPE_NONE) |
| 487 | return -EINVAL; |
| 488 | |
| 489 | /* Check if we need to change chip and handler */ |
| 490 | if (!(ct->type & type)) |
| 491 | if (irq_setup_alt_chip(d, type)) |
| 492 | return -EINVAL; |
| 493 | |
| 494 | /* |
| 495 | * Configure interrupt polarity. |
| 496 | */ |
Laurent Navet | f4dcd2d9 | 2013-03-20 13:15:56 +0100 | [diff] [blame] | 497 | switch (type) { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 498 | case IRQ_TYPE_EDGE_RISING: |
| 499 | case IRQ_TYPE_LEVEL_HIGH: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 500 | regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF, |
| 501 | BIT(pin), 0); |
Axel Lin | 7cf8c9f | 2012-09-30 16:23:27 +0800 | [diff] [blame] | 502 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 503 | case IRQ_TYPE_EDGE_FALLING: |
| 504 | case IRQ_TYPE_LEVEL_LOW: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 505 | regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF, |
| 506 | BIT(pin), 1); |
Axel Lin | 7cf8c9f | 2012-09-30 16:23:27 +0800 | [diff] [blame] | 507 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 508 | case IRQ_TYPE_EDGE_BOTH: { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 509 | u32 data_in, in_pol, val; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 510 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 511 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol); |
| 512 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 513 | |
| 514 | /* |
| 515 | * set initial polarity based on current input level |
| 516 | */ |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 517 | if ((data_in ^ in_pol) & BIT(pin)) |
| 518 | val = BIT(pin); /* falling */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 519 | else |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 520 | val = 0; /* raising */ |
| 521 | |
| 522 | regmap_update_bits(mvchip->regs, GPIO_IN_POL_OFF, |
| 523 | BIT(pin), val); |
Axel Lin | 7cf8c9f | 2012-09-30 16:23:27 +0800 | [diff] [blame] | 524 | break; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 525 | } |
| 526 | } |
| 527 | return 0; |
| 528 | } |
| 529 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 530 | static void mvebu_gpio_irq_handler(struct irq_desc *desc) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 531 | { |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 532 | struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); |
Thomas Petazzoni | 01ca59f | 2014-02-07 12:29:19 +0100 | [diff] [blame] | 533 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 534 | u32 cause, type, data_in, level_mask, edge_cause, edge_mask; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 535 | int i; |
| 536 | |
| 537 | if (mvchip == NULL) |
| 538 | return; |
| 539 | |
Thomas Petazzoni | 01ca59f | 2014-02-07 12:29:19 +0100 | [diff] [blame] | 540 | chained_irq_enter(chip, desc); |
| 541 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 542 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in); |
| 543 | level_mask = mvebu_gpio_read_level_mask(mvchip); |
| 544 | edge_cause = mvebu_gpio_read_edge_cause(mvchip); |
| 545 | edge_mask = mvebu_gpio_read_edge_mask(mvchip); |
| 546 | |
| 547 | cause = (data_in ^ level_mask) | (edge_cause & edge_mask); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 548 | |
| 549 | for (i = 0; i < mvchip->chip.ngpio; i++) { |
| 550 | int irq; |
| 551 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 552 | irq = irq_find_mapping(mvchip->domain, i); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 553 | |
Ralph Sennhauser | d2cabc4 | 2017-03-17 18:44:06 +0100 | [diff] [blame] | 554 | if (!(cause & BIT(i))) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 555 | continue; |
| 556 | |
Javier Martinez Canillas | fb90c22 | 2013-06-14 18:40:44 +0200 | [diff] [blame] | 557 | type = irq_get_trigger_type(irq); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 558 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
| 559 | /* Swap polarity (race with GPIO line) */ |
| 560 | u32 polarity; |
| 561 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 562 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &polarity); |
Ralph Sennhauser | d2cabc4 | 2017-03-17 18:44:06 +0100 | [diff] [blame] | 563 | polarity ^= BIT(i); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 564 | regmap_write(mvchip->regs, GPIO_IN_POL_OFF, polarity); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 565 | } |
Thomas Petazzoni | 01ca59f | 2014-02-07 12:29:19 +0100 | [diff] [blame] | 566 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 567 | generic_handle_irq(irq); |
| 568 | } |
Thomas Petazzoni | 01ca59f | 2014-02-07 12:29:19 +0100 | [diff] [blame] | 569 | |
| 570 | chained_irq_exit(chip, desc); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 571 | } |
| 572 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 573 | /* |
| 574 | * Functions implementing the pwm_chip methods |
| 575 | */ |
| 576 | static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) |
| 577 | { |
| 578 | return container_of(chip, struct mvebu_pwm, chip); |
| 579 | } |
| 580 | |
| 581 | static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
| 582 | { |
| 583 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); |
| 584 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; |
| 585 | struct gpio_desc *desc; |
| 586 | unsigned long flags; |
| 587 | int ret = 0; |
| 588 | |
| 589 | spin_lock_irqsave(&mvpwm->lock, flags); |
| 590 | |
| 591 | if (mvpwm->gpiod) { |
| 592 | ret = -EBUSY; |
| 593 | } else { |
| 594 | desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm); |
| 595 | if (!desc) { |
| 596 | ret = -ENODEV; |
| 597 | goto out; |
| 598 | } |
| 599 | |
| 600 | ret = gpiod_request(desc, "mvebu-pwm"); |
| 601 | if (ret) |
| 602 | goto out; |
| 603 | |
| 604 | ret = gpiod_direction_output(desc, 0); |
| 605 | if (ret) { |
| 606 | gpiod_free(desc); |
| 607 | goto out; |
| 608 | } |
| 609 | |
| 610 | mvpwm->gpiod = desc; |
| 611 | } |
| 612 | out: |
| 613 | spin_unlock_irqrestore(&mvpwm->lock, flags); |
| 614 | return ret; |
| 615 | } |
| 616 | |
| 617 | static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
| 618 | { |
| 619 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); |
| 620 | unsigned long flags; |
| 621 | |
| 622 | spin_lock_irqsave(&mvpwm->lock, flags); |
| 623 | gpiod_free(mvpwm->gpiod); |
| 624 | mvpwm->gpiod = NULL; |
| 625 | spin_unlock_irqrestore(&mvpwm->lock, flags); |
| 626 | } |
| 627 | |
| 628 | static void mvebu_pwm_get_state(struct pwm_chip *chip, |
| 629 | struct pwm_device *pwm, |
| 630 | struct pwm_state *state) { |
| 631 | |
| 632 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); |
| 633 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; |
| 634 | unsigned long long val; |
| 635 | unsigned long flags; |
| 636 | u32 u; |
| 637 | |
| 638 | spin_lock_irqsave(&mvpwm->lock, flags); |
| 639 | |
| 640 | val = (unsigned long long) |
| 641 | readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); |
| 642 | val *= NSEC_PER_SEC; |
| 643 | do_div(val, mvpwm->clk_rate); |
| 644 | if (val > UINT_MAX) |
| 645 | state->duty_cycle = UINT_MAX; |
| 646 | else if (val) |
| 647 | state->duty_cycle = val; |
| 648 | else |
| 649 | state->duty_cycle = 1; |
| 650 | |
| 651 | val = (unsigned long long) |
| 652 | readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); |
| 653 | val *= NSEC_PER_SEC; |
| 654 | do_div(val, mvpwm->clk_rate); |
| 655 | if (val < state->duty_cycle) { |
| 656 | state->period = 1; |
| 657 | } else { |
| 658 | val -= state->duty_cycle; |
| 659 | if (val > UINT_MAX) |
| 660 | state->period = UINT_MAX; |
| 661 | else if (val) |
| 662 | state->period = val; |
| 663 | else |
| 664 | state->period = 1; |
| 665 | } |
| 666 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 667 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &u); |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 668 | if (u) |
| 669 | state->enabled = true; |
| 670 | else |
| 671 | state->enabled = false; |
| 672 | |
| 673 | spin_unlock_irqrestore(&mvpwm->lock, flags); |
| 674 | } |
| 675 | |
| 676 | static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
| 677 | struct pwm_state *state) |
| 678 | { |
| 679 | struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); |
| 680 | struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; |
| 681 | unsigned long long val; |
| 682 | unsigned long flags; |
| 683 | unsigned int on, off; |
| 684 | |
| 685 | val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; |
| 686 | do_div(val, NSEC_PER_SEC); |
| 687 | if (val > UINT_MAX) |
| 688 | return -EINVAL; |
| 689 | if (val) |
| 690 | on = val; |
| 691 | else |
| 692 | on = 1; |
| 693 | |
| 694 | val = (unsigned long long) mvpwm->clk_rate * |
| 695 | (state->period - state->duty_cycle); |
| 696 | do_div(val, NSEC_PER_SEC); |
| 697 | if (val > UINT_MAX) |
| 698 | return -EINVAL; |
| 699 | if (val) |
| 700 | off = val; |
| 701 | else |
| 702 | off = 1; |
| 703 | |
| 704 | spin_lock_irqsave(&mvpwm->lock, flags); |
| 705 | |
| 706 | writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm)); |
| 707 | writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm)); |
| 708 | if (state->enabled) |
| 709 | mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); |
| 710 | else |
| 711 | mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); |
| 712 | |
| 713 | spin_unlock_irqrestore(&mvpwm->lock, flags); |
| 714 | |
| 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | static const struct pwm_ops mvebu_pwm_ops = { |
| 719 | .request = mvebu_pwm_request, |
| 720 | .free = mvebu_pwm_free, |
| 721 | .get_state = mvebu_pwm_get_state, |
| 722 | .apply = mvebu_pwm_apply, |
| 723 | .owner = THIS_MODULE, |
| 724 | }; |
| 725 | |
| 726 | static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) |
| 727 | { |
| 728 | struct mvebu_pwm *mvpwm = mvchip->mvpwm; |
| 729 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 730 | regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, |
| 731 | &mvpwm->blink_select); |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 732 | mvpwm->blink_on_duration = |
| 733 | readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); |
| 734 | mvpwm->blink_off_duration = |
| 735 | readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); |
| 736 | } |
| 737 | |
| 738 | static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) |
| 739 | { |
| 740 | struct mvebu_pwm *mvpwm = mvchip->mvpwm; |
| 741 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 742 | regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, |
| 743 | mvpwm->blink_select); |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 744 | writel_relaxed(mvpwm->blink_on_duration, |
| 745 | mvebu_pwmreg_blink_on_duration(mvpwm)); |
| 746 | writel_relaxed(mvpwm->blink_off_duration, |
| 747 | mvebu_pwmreg_blink_off_duration(mvpwm)); |
| 748 | } |
| 749 | |
| 750 | static int mvebu_pwm_probe(struct platform_device *pdev, |
| 751 | struct mvebu_gpio_chip *mvchip, |
| 752 | int id) |
| 753 | { |
| 754 | struct device *dev = &pdev->dev; |
| 755 | struct mvebu_pwm *mvpwm; |
| 756 | struct resource *res; |
| 757 | u32 set; |
| 758 | |
| 759 | if (!of_device_is_compatible(mvchip->chip.of_node, |
| 760 | "marvell,armada-370-xp-gpio")) |
| 761 | return 0; |
| 762 | |
| 763 | if (IS_ERR(mvchip->clk)) |
| 764 | return PTR_ERR(mvchip->clk); |
| 765 | |
| 766 | /* |
| 767 | * There are only two sets of PWM configuration registers for |
| 768 | * all the GPIO lines on those SoCs which this driver reserves |
| 769 | * for the first two GPIO chips. So if the resource is missing |
| 770 | * we can't treat it as an error. |
| 771 | */ |
| 772 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); |
| 773 | if (!res) |
| 774 | return 0; |
| 775 | |
| 776 | /* |
| 777 | * Use set A for lines of GPIO chip with id 0, B for GPIO chip |
| 778 | * with id 1. Don't allow further GPIO chips to be used for PWM. |
| 779 | */ |
| 780 | if (id == 0) |
| 781 | set = 0; |
| 782 | else if (id == 1) |
| 783 | set = U32_MAX; |
| 784 | else |
| 785 | return -EINVAL; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 786 | regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF, 0); |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 787 | |
| 788 | mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); |
| 789 | if (!mvpwm) |
| 790 | return -ENOMEM; |
| 791 | mvchip->mvpwm = mvpwm; |
| 792 | mvpwm->mvchip = mvchip; |
| 793 | |
| 794 | mvpwm->membase = devm_ioremap_resource(dev, res); |
| 795 | if (IS_ERR(mvpwm->membase)) |
| 796 | return PTR_ERR(mvpwm->membase); |
| 797 | |
| 798 | mvpwm->clk_rate = clk_get_rate(mvchip->clk); |
| 799 | if (!mvpwm->clk_rate) { |
| 800 | dev_err(dev, "failed to get clock rate\n"); |
| 801 | return -EINVAL; |
| 802 | } |
| 803 | |
| 804 | mvpwm->chip.dev = dev; |
| 805 | mvpwm->chip.ops = &mvebu_pwm_ops; |
| 806 | mvpwm->chip.npwm = mvchip->chip.ngpio; |
| 807 | |
| 808 | spin_lock_init(&mvpwm->lock); |
| 809 | |
| 810 | return pwmchip_add(&mvpwm->chip); |
| 811 | } |
| 812 | |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 813 | #ifdef CONFIG_DEBUG_FS |
| 814 | #include <linux/seq_file.h> |
| 815 | |
| 816 | static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 817 | { |
Linus Walleij | bbe7600 | 2015-12-07 11:09:24 +0100 | [diff] [blame] | 818 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 819 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; |
| 820 | int i; |
| 821 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 822 | regmap_read(mvchip->regs, GPIO_OUT_OFF, &out); |
| 823 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &io_conf); |
| 824 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &blink); |
| 825 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &in_pol); |
| 826 | regmap_read(mvchip->regs, GPIO_DATA_IN_OFF, &data_in); |
| 827 | cause = mvebu_gpio_read_edge_cause(mvchip); |
| 828 | edg_msk = mvebu_gpio_read_edge_mask(mvchip); |
| 829 | lvl_msk = mvebu_gpio_read_level_mask(mvchip); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 830 | |
| 831 | for (i = 0; i < chip->ngpio; i++) { |
| 832 | const char *label; |
| 833 | u32 msk; |
| 834 | bool is_out; |
| 835 | |
| 836 | label = gpiochip_is_requested(chip, i); |
| 837 | if (!label) |
| 838 | continue; |
| 839 | |
Ralph Sennhauser | d2cabc4 | 2017-03-17 18:44:06 +0100 | [diff] [blame] | 840 | msk = BIT(i); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 841 | is_out = !(io_conf & msk); |
| 842 | |
| 843 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); |
| 844 | |
| 845 | if (is_out) { |
| 846 | seq_printf(s, " out %s %s\n", |
| 847 | out & msk ? "hi" : "lo", |
| 848 | blink & msk ? "(blink )" : ""); |
| 849 | continue; |
| 850 | } |
| 851 | |
| 852 | seq_printf(s, " in %s (act %s) - IRQ", |
| 853 | (data_in ^ in_pol) & msk ? "hi" : "lo", |
| 854 | in_pol & msk ? "lo" : "hi"); |
| 855 | if (!((edg_msk | lvl_msk) & msk)) { |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 856 | seq_puts(s, " disabled\n"); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 857 | continue; |
| 858 | } |
| 859 | if (edg_msk & msk) |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 860 | seq_puts(s, " edge "); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 861 | if (lvl_msk & msk) |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 862 | seq_puts(s, " level"); |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 863 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); |
| 864 | } |
| 865 | } |
| 866 | #else |
| 867 | #define mvebu_gpio_dbg_show NULL |
| 868 | #endif |
| 869 | |
Jingoo Han | 271b17b | 2014-05-07 18:06:08 +0900 | [diff] [blame] | 870 | static const struct of_device_id mvebu_gpio_of_match[] = { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 871 | { |
| 872 | .compatible = "marvell,orion-gpio", |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 873 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 874 | }, |
| 875 | { |
| 876 | .compatible = "marvell,mv78200-gpio", |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 877 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 878 | }, |
| 879 | { |
| 880 | .compatible = "marvell,armadaxp-gpio", |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 881 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 882 | }, |
| 883 | { |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 884 | .compatible = "marvell,armada-370-xp-gpio", |
| 885 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
| 886 | }, |
| 887 | { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 888 | /* sentinel */ |
| 889 | }, |
| 890 | }; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 891 | |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 892 | static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) |
| 893 | { |
| 894 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); |
| 895 | int i; |
| 896 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 897 | regmap_read(mvchip->regs, GPIO_OUT_OFF, &mvchip->out_reg); |
| 898 | regmap_read(mvchip->regs, GPIO_IO_CONF_OFF, &mvchip->io_conf_reg); |
| 899 | regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF, &mvchip->blink_en_reg); |
| 900 | regmap_read(mvchip->regs, GPIO_IN_POL_OFF, &mvchip->in_pol_reg); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 901 | |
| 902 | switch (mvchip->soc_variant) { |
| 903 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 904 | regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF, |
| 905 | &mvchip->edge_mask_regs[0]); |
| 906 | regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF, |
| 907 | &mvchip->level_mask_regs[0]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 908 | break; |
| 909 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
| 910 | for (i = 0; i < 2; i++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 911 | regmap_read(mvchip->regs, |
| 912 | GPIO_EDGE_MASK_MV78200_OFF(i), |
| 913 | &mvchip->edge_mask_regs[i]); |
| 914 | regmap_read(mvchip->regs, |
| 915 | GPIO_LEVEL_MASK_MV78200_OFF(i), |
| 916 | &mvchip->level_mask_regs[i]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 917 | } |
| 918 | break; |
| 919 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
| 920 | for (i = 0; i < 4; i++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 921 | regmap_read(mvchip->regs, |
| 922 | GPIO_EDGE_MASK_ARMADAXP_OFF(i), |
| 923 | &mvchip->edge_mask_regs[i]); |
| 924 | regmap_read(mvchip->regs, |
| 925 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i), |
| 926 | &mvchip->level_mask_regs[i]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 927 | } |
| 928 | break; |
| 929 | default: |
| 930 | BUG(); |
| 931 | } |
| 932 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 933 | if (IS_ENABLED(CONFIG_PWM)) |
| 934 | mvebu_pwm_suspend(mvchip); |
| 935 | |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 936 | return 0; |
| 937 | } |
| 938 | |
| 939 | static int mvebu_gpio_resume(struct platform_device *pdev) |
| 940 | { |
| 941 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); |
| 942 | int i; |
| 943 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 944 | regmap_write(mvchip->regs, GPIO_OUT_OFF, mvchip->out_reg); |
| 945 | regmap_write(mvchip->regs, GPIO_IO_CONF_OFF, mvchip->io_conf_reg); |
| 946 | regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF, mvchip->blink_en_reg); |
| 947 | regmap_write(mvchip->regs, GPIO_IN_POL_OFF, mvchip->in_pol_reg); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 948 | |
| 949 | switch (mvchip->soc_variant) { |
| 950 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 951 | regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, |
| 952 | mvchip->edge_mask_regs[0]); |
| 953 | regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, |
| 954 | mvchip->level_mask_regs[0]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 955 | break; |
| 956 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
| 957 | for (i = 0; i < 2; i++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 958 | regmap_write(mvchip->regs, |
| 959 | GPIO_EDGE_MASK_MV78200_OFF(i), |
| 960 | mvchip->edge_mask_regs[i]); |
| 961 | regmap_write(mvchip->regs, |
| 962 | GPIO_LEVEL_MASK_MV78200_OFF(i), |
| 963 | mvchip->level_mask_regs[i]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 964 | } |
| 965 | break; |
| 966 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
| 967 | for (i = 0; i < 4; i++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 968 | regmap_write(mvchip->regs, |
| 969 | GPIO_EDGE_MASK_ARMADAXP_OFF(i), |
| 970 | mvchip->edge_mask_regs[i]); |
| 971 | regmap_write(mvchip->regs, |
| 972 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i), |
| 973 | mvchip->level_mask_regs[i]); |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 974 | } |
| 975 | break; |
| 976 | default: |
| 977 | BUG(); |
| 978 | } |
| 979 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 980 | if (IS_ENABLED(CONFIG_PWM)) |
| 981 | mvebu_pwm_resume(mvchip); |
| 982 | |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 983 | return 0; |
| 984 | } |
| 985 | |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 986 | static const struct regmap_config mvebu_gpio_regmap_config = { |
| 987 | .reg_bits = 32, |
| 988 | .reg_stride = 4, |
| 989 | .val_bits = 32, |
| 990 | .fast_io = true, |
| 991 | }; |
| 992 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 993 | static int mvebu_gpio_probe(struct platform_device *pdev) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 994 | { |
| 995 | struct mvebu_gpio_chip *mvchip; |
| 996 | const struct of_device_id *match; |
| 997 | struct device_node *np = pdev->dev.of_node; |
| 998 | struct resource *res; |
| 999 | struct irq_chip_generic *gc; |
| 1000 | struct irq_chip_type *ct; |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1001 | void __iomem *base; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1002 | unsigned int ngpios; |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1003 | bool have_irqs; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1004 | int soc_variant; |
| 1005 | int i, cpu, id; |
Andrew Lunn | f1d2d08 | 2015-01-10 00:34:48 +0100 | [diff] [blame] | 1006 | int err; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1007 | |
| 1008 | match = of_match_device(mvebu_gpio_of_match, &pdev->dev); |
| 1009 | if (match) |
Russell King | f0d5046 | 2017-01-10 22:53:28 +0000 | [diff] [blame] | 1010 | soc_variant = (unsigned long) match->data; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1011 | else |
| 1012 | soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; |
| 1013 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1014 | /* Some gpio controllers do not provide irq support */ |
| 1015 | have_irqs = of_irq_count(np) != 0; |
| 1016 | |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 1017 | mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), |
| 1018 | GFP_KERNEL); |
Jingoo Han | 6c8365f | 2014-04-29 17:38:21 +0900 | [diff] [blame] | 1019 | if (!mvchip) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1020 | return -ENOMEM; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1021 | |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 1022 | platform_set_drvdata(pdev, mvchip); |
| 1023 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1024 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { |
| 1025 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); |
| 1026 | return -ENODEV; |
| 1027 | } |
| 1028 | |
| 1029 | id = of_alias_get_id(pdev->dev.of_node, "gpio"); |
| 1030 | if (id < 0) { |
| 1031 | dev_err(&pdev->dev, "Couldn't get OF id\n"); |
| 1032 | return id; |
| 1033 | } |
| 1034 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 1035 | mvchip->clk = devm_clk_get(&pdev->dev, NULL); |
Andrew Lunn | de88747 | 2013-02-03 11:34:26 +0100 | [diff] [blame] | 1036 | /* Not all SoCs require a clock.*/ |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 1037 | if (!IS_ERR(mvchip->clk)) |
| 1038 | clk_prepare_enable(mvchip->clk); |
Andrew Lunn | de88747 | 2013-02-03 11:34:26 +0100 | [diff] [blame] | 1039 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1040 | mvchip->soc_variant = soc_variant; |
| 1041 | mvchip->chip.label = dev_name(&pdev->dev); |
Linus Walleij | 58383c78 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 1042 | mvchip->chip.parent = &pdev->dev; |
Jonas Gorski | 203f0da | 2015-10-11 17:34:16 +0200 | [diff] [blame] | 1043 | mvchip->chip.request = gpiochip_generic_request; |
| 1044 | mvchip->chip.free = gpiochip_generic_free; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1045 | mvchip->chip.direction_input = mvebu_gpio_direction_input; |
| 1046 | mvchip->chip.get = mvebu_gpio_get; |
| 1047 | mvchip->chip.direction_output = mvebu_gpio_direction_output; |
| 1048 | mvchip->chip.set = mvebu_gpio_set; |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1049 | if (have_irqs) |
| 1050 | mvchip->chip.to_irq = mvebu_gpio_to_irq; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1051 | mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; |
| 1052 | mvchip->chip.ngpio = ngpios; |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 1053 | mvchip->chip.can_sleep = false; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1054 | mvchip->chip.of_node = np; |
Simon Guinot | a4ba5e1 | 2013-03-24 15:45:29 +0100 | [diff] [blame] | 1055 | mvchip->chip.dbg_show = mvebu_gpio_dbg_show; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1056 | |
Julia Lawall | 08a67a5 | 2013-08-14 11:11:07 +0200 | [diff] [blame] | 1057 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1058 | base = devm_ioremap_resource(&pdev->dev, res); |
| 1059 | if (IS_ERR(base)) |
| 1060 | return PTR_ERR(base); |
| 1061 | |
| 1062 | mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, |
| 1063 | &mvebu_gpio_regmap_config); |
| 1064 | if (IS_ERR(mvchip->regs)) |
| 1065 | return PTR_ERR(mvchip->regs); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1066 | |
Ralph Sennhauser | 7077f4c | 2017-03-16 07:33:56 +0100 | [diff] [blame] | 1067 | /* |
| 1068 | * The Armada XP has a second range of registers for the |
| 1069 | * per-CPU registers |
| 1070 | */ |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1071 | if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { |
| 1072 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1073 | base = devm_ioremap_resource(&pdev->dev, res); |
| 1074 | if (IS_ERR(base)) |
| 1075 | return PTR_ERR(base); |
| 1076 | |
| 1077 | mvchip->percpu_regs = |
| 1078 | devm_regmap_init_mmio(&pdev->dev, base, |
| 1079 | &mvebu_gpio_regmap_config); |
| 1080 | if (IS_ERR(mvchip->percpu_regs)) |
| 1081 | return PTR_ERR(mvchip->percpu_regs); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1082 | } |
| 1083 | |
| 1084 | /* |
| 1085 | * Mask and clear GPIO interrupts. |
| 1086 | */ |
Laurent Navet | f4dcd2d9 | 2013-03-20 13:15:56 +0100 | [diff] [blame] | 1087 | switch (soc_variant) { |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1088 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1089 | regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); |
| 1090 | regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); |
| 1091 | regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1092 | break; |
| 1093 | case MVEBU_GPIO_SOC_VARIANT_MV78200: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1094 | regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1095 | for (cpu = 0; cpu < 2; cpu++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1096 | regmap_write(mvchip->regs, |
| 1097 | GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); |
| 1098 | regmap_write(mvchip->regs, |
| 1099 | GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1100 | } |
| 1101 | break; |
| 1102 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1103 | regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); |
| 1104 | regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); |
| 1105 | regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1106 | for (cpu = 0; cpu < 4; cpu++) { |
Thomas Petazzoni | 2233bf7 | 2017-05-19 18:09:21 +0200 | [diff] [blame^] | 1107 | regmap_write(mvchip->percpu_regs, |
| 1108 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); |
| 1109 | regmap_write(mvchip->percpu_regs, |
| 1110 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); |
| 1111 | regmap_write(mvchip->percpu_regs, |
| 1112 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1113 | } |
| 1114 | break; |
| 1115 | default: |
| 1116 | BUG(); |
| 1117 | } |
| 1118 | |
Laxman Dewangan | 00b9ab4 | 2016-02-22 17:43:28 +0530 | [diff] [blame] | 1119 | devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1120 | |
| 1121 | /* Some gpio controllers do not provide irq support */ |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1122 | if (!have_irqs) |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1123 | return 0; |
| 1124 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1125 | mvchip->domain = |
| 1126 | irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); |
| 1127 | if (!mvchip->domain) { |
| 1128 | dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", |
| 1129 | mvchip->chip.label); |
| 1130 | return -ENODEV; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1131 | } |
| 1132 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1133 | err = irq_alloc_domain_generic_chips( |
| 1134 | mvchip->domain, ngpios, 2, np->name, handle_level_irq, |
| 1135 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); |
| 1136 | if (err) { |
| 1137 | dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", |
| 1138 | mvchip->chip.label); |
| 1139 | goto err_domain; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1140 | } |
| 1141 | |
Ralph Sennhauser | 899c37e | 2017-03-16 07:33:57 +0100 | [diff] [blame] | 1142 | /* |
| 1143 | * NOTE: The common accessors cannot be used because of the percpu |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1144 | * access to the mask registers |
| 1145 | */ |
| 1146 | gc = irq_get_domain_generic_chip(mvchip->domain, 0); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1147 | gc->private = mvchip; |
| 1148 | ct = &gc->chip_types[0]; |
| 1149 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; |
| 1150 | ct->chip.irq_mask = mvebu_gpio_level_irq_mask; |
| 1151 | ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; |
| 1152 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; |
| 1153 | ct->chip.name = mvchip->chip.label; |
| 1154 | |
| 1155 | ct = &gc->chip_types[1]; |
| 1156 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 1157 | ct->chip.irq_ack = mvebu_gpio_irq_ack; |
| 1158 | ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; |
| 1159 | ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; |
| 1160 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; |
| 1161 | ct->handler = handle_edge_irq; |
| 1162 | ct->chip.name = mvchip->chip.label; |
| 1163 | |
Ralph Sennhauser | 899c37e | 2017-03-16 07:33:57 +0100 | [diff] [blame] | 1164 | /* |
| 1165 | * Setup the interrupt handlers. Each chip can have up to 4 |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1166 | * interrupt handlers, with each handler dealing with 8 GPIO |
| 1167 | * pins. |
| 1168 | */ |
| 1169 | for (i = 0; i < 4; i++) { |
| 1170 | int irq = platform_get_irq(pdev, i); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1171 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1172 | if (irq < 0) |
| 1173 | continue; |
| 1174 | irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, |
| 1175 | mvchip); |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1176 | } |
| 1177 | |
Andrew Lunn | 757642f | 2017-04-14 17:40:52 +0200 | [diff] [blame] | 1178 | /* Armada 370/XP has simple PWM support for GPIO lines */ |
| 1179 | if (IS_ENABLED(CONFIG_PWM)) |
| 1180 | return mvebu_pwm_probe(pdev, mvchip, id); |
| 1181 | |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1182 | return 0; |
Andrew Lunn | f1d2d08 | 2015-01-10 00:34:48 +0100 | [diff] [blame] | 1183 | |
Jason Gunthorpe | 812d478 | 2016-10-19 15:03:41 -0600 | [diff] [blame] | 1184 | err_domain: |
| 1185 | irq_domain_remove(mvchip->domain); |
Andrew Lunn | f1d2d08 | 2015-01-10 00:34:48 +0100 | [diff] [blame] | 1186 | |
Andrew Lunn | f1d2d08 | 2015-01-10 00:34:48 +0100 | [diff] [blame] | 1187 | return err; |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1188 | } |
| 1189 | |
| 1190 | static struct platform_driver mvebu_gpio_driver = { |
| 1191 | .driver = { |
Andrew Lunn | a4319a6 | 2015-01-10 00:34:47 +0100 | [diff] [blame] | 1192 | .name = "mvebu-gpio", |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1193 | .of_match_table = mvebu_gpio_of_match, |
| 1194 | }, |
| 1195 | .probe = mvebu_gpio_probe, |
Thomas Petazzoni | b5b7b48 | 2014-10-24 13:59:19 +0200 | [diff] [blame] | 1196 | .suspend = mvebu_gpio_suspend, |
| 1197 | .resume = mvebu_gpio_resume, |
Thomas Petazzoni | fefe7b0 | 2012-09-19 22:52:58 +0200 | [diff] [blame] | 1198 | }; |
Paul Gortmaker | ed329f3 | 2016-03-27 11:44:45 -0400 | [diff] [blame] | 1199 | builtin_platform_driver(mvebu_gpio_driver); |