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Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001/*
Heikki Krogerusb8014792012-10-18 17:34:08 +03002 * Core driver for the Synopsys DesignWare DMA Controller
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07003 *
4 * Copyright (C) 2007-2008 Atmel Corporation
Viresh Kumaraecb7b62011-05-24 14:04:09 +05305 * Copyright (C) 2010-2011 ST Microelectronics
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03006 * Copyright (C) 2013 Intel Corporation
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Heikki Krogerusb8014792012-10-18 17:34:08 +030012
Viresh Kumar327e6972012-02-01 16:12:26 +053013#include <linux/bitops.h>
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070014#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
Andy Shevchenkof8122a82013-01-16 15:48:50 +020017#include <linux/dmapool.h>
Thierry Reding73312052013-01-21 11:09:00 +010018#include <linux/err.h>
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070019#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/mm.h>
23#include <linux/module.h>
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070024#include <linux/slab.h>
Andy Shevchenkobb32baf2014-11-05 18:34:48 +020025#include <linux/pm_runtime.h>
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070026
Andy Shevchenko61a76492013-06-05 15:26:44 +030027#include "../dmaengine.h"
Andy Shevchenko9cade1a2013-06-05 15:26:45 +030028#include "internal.h"
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070029
30/*
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
35 *
Andy Shevchenkodd5720b2014-02-12 11:16:17 +020036 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070038 */
39
Viresh Kumar327e6972012-02-01 16:12:26 +053040#define DWC_DEFAULT_CTLLO(_chan) ({ \
Viresh Kumar327e6972012-02-01 16:12:26 +053041 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
Andy Shevchenko495aea42013-01-10 11:11:41 +020043 bool _is_slave = is_slave_direction(_dwc->direction); \
Andy Shevchenko495aea42013-01-10 11:11:41 +020044 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
Viresh Kumar327e6972012-02-01 16:12:26 +053045 DW_DMA_MSIZE_16; \
Andy Shevchenko495aea42013-01-10 11:11:41 +020046 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
Viresh Kumar327e6972012-02-01 16:12:26 +053047 DW_DMA_MSIZE_16; \
Jamie Ilesf301c062011-01-21 14:11:53 +000048 \
Viresh Kumar327e6972012-02-01 16:12:26 +053049 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
Jamie Ilesf301c062011-01-21 14:11:53 +000051 | DWC_CTLL_LLP_D_EN \
52 | DWC_CTLL_LLP_S_EN \
Arnd Bergmannf7760762013-03-26 16:53:57 +020053 | DWC_CTLL_DMS(_dwc->dst_master) \
54 | DWC_CTLL_SMS(_dwc->src_master)); \
Jamie Ilesf301c062011-01-21 14:11:53 +000055 })
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070056
57/*
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070058 * Number of descriptors to allocate for each channel. This should be
59 * made configurable somehow; preferably, the clients (at least the
60 * ones using slave transfers) should be able to give us a hint.
61 */
62#define NR_DESCS_PER_CHANNEL 64
63
Andy Shevchenko029a40e2015-01-02 16:17:24 +020064/* The set of bus widths supported by the DMA controller */
65#define DW_DMA_BUSWIDTHS \
66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
70
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070071/*----------------------------------------------------------------------*/
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070072
Dan Williams41d5e592009-01-06 11:38:21 -070073static struct device *chan2dev(struct dma_chan *chan)
74{
75 return &chan->dev->device;
76}
Dan Williams41d5e592009-01-06 11:38:21 -070077
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070078static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
79{
Andy Shevchenkoe63a47a2012-10-18 17:34:12 +030080 return to_dw_desc(dwc->active_list.next);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070081}
82
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070083static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
84{
85 struct dw_desc *desc, *_desc;
86 struct dw_desc *ret = NULL;
87 unsigned int i = 0;
Viresh Kumar69cea5a2011-04-15 16:03:35 +053088 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070089
Viresh Kumar69cea5a2011-04-15 16:03:35 +053090 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070091 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
Andy Shevchenko2ab37272012-06-19 13:34:04 +030092 i++;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070093 if (async_tx_test_ack(&desc->txd)) {
94 list_del(&desc->desc_node);
95 ret = desc;
96 break;
97 }
Dan Williams41d5e592009-01-06 11:38:21 -070098 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070099 }
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530100 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700101
Dan Williams41d5e592009-01-06 11:38:21 -0700102 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700103
104 return ret;
105}
106
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700107/*
108 * Move a descriptor, including any children, to the free list.
109 * `desc' must not be on any lists.
110 */
111static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
112{
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530113 unsigned long flags;
114
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700115 if (desc) {
116 struct dw_desc *child;
117
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530118 spin_lock_irqsave(&dwc->lock, flags);
Dan Williamse0bd0f82009-09-08 17:53:02 -0700119 list_for_each_entry(child, &desc->tx_list, desc_node)
Dan Williams41d5e592009-01-06 11:38:21 -0700120 dev_vdbg(chan2dev(&dwc->chan),
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700121 "moving child desc %p to freelist\n",
122 child);
Dan Williamse0bd0f82009-09-08 17:53:02 -0700123 list_splice_init(&desc->tx_list, &dwc->free_list);
Dan Williams41d5e592009-01-06 11:38:21 -0700124 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700125 list_add(&desc->desc_node, &dwc->free_list);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530126 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700127 }
128}
129
Viresh Kumar61e183f2011-11-17 16:01:29 +0530130static void dwc_initialize(struct dw_dma_chan *dwc)
131{
132 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
133 struct dw_dma_slave *dws = dwc->chan.private;
134 u32 cfghi = DWC_CFGH_FIFO_MODE;
135 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
136
137 if (dwc->initialized == true)
138 return;
139
Arnd Bergmannf7760762013-03-26 16:53:57 +0200140 if (dws) {
Viresh Kumar61e183f2011-11-17 16:01:29 +0530141 /*
142 * We need controller-specific data to set up slave
143 * transfers.
144 */
145 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
146
Andy Shevchenko7e1e2f22014-08-19 20:29:14 +0300147 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
148 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
Andy Shevchenko8fccc5b2012-09-03 13:46:19 +0300149 } else {
Andy Shevchenko89500522014-08-19 20:29:15 +0300150 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
151 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
Viresh Kumar61e183f2011-11-17 16:01:29 +0530152 }
153
154 channel_writel(dwc, CFG_LO, cfglo);
155 channel_writel(dwc, CFG_HI, cfghi);
156
157 /* Enable interrupts */
158 channel_set_bit(dw, MASK.XFER, dwc->mask);
Viresh Kumar61e183f2011-11-17 16:01:29 +0530159 channel_set_bit(dw, MASK.ERROR, dwc->mask);
160
161 dwc->initialized = true;
162}
163
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700164/*----------------------------------------------------------------------*/
165
Andy Shevchenko39416672015-09-28 18:57:04 +0300166static inline unsigned int dwc_fast_ffs(unsigned long long v)
Andy Shevchenko4c2d56c2012-06-19 13:34:08 +0300167{
168 /*
169 * We can be a lot more clever here, but this should take care
170 * of the most common optimization.
171 */
172 if (!(v & 7))
173 return 3;
174 else if (!(v & 3))
175 return 2;
176 else if (!(v & 1))
177 return 1;
178 return 0;
179}
180
Andy Shevchenkof52b36d2012-09-21 15:05:44 +0300181static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
Andy Shevchenko1d455432012-06-19 13:34:03 +0300182{
183 dev_err(chan2dev(&dwc->chan),
184 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
185 channel_readl(dwc, SAR),
186 channel_readl(dwc, DAR),
187 channel_readl(dwc, LLP),
188 channel_readl(dwc, CTL_HI),
189 channel_readl(dwc, CTL_LO));
190}
191
Andy Shevchenko3f9362072012-06-19 13:46:32 +0300192static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
193{
194 channel_clear_bit(dw, CH_EN, dwc->mask);
195 while (dma_readl(dw, CH_EN) & dwc->mask)
196 cpu_relax();
197}
198
Andy Shevchenko1d455432012-06-19 13:34:03 +0300199/*----------------------------------------------------------------------*/
200
Andy Shevchenkofed25742012-09-21 15:05:49 +0300201/* Perform single block transfer */
202static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
203 struct dw_desc *desc)
204{
205 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
206 u32 ctllo;
207
Andy Shevchenko1d566f12014-01-13 14:04:48 +0200208 /*
209 * Software emulation of LLP mode relies on interrupts to continue
210 * multi block transfer.
211 */
Andy Shevchenkofed25742012-09-21 15:05:49 +0300212 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
213
214 channel_writel(dwc, SAR, desc->lli.sar);
215 channel_writel(dwc, DAR, desc->lli.dar);
216 channel_writel(dwc, CTL_LO, ctllo);
217 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
218 channel_set_bit(dw, CH_EN, dwc->mask);
Andy Shevchenkof5c6a7d2013-01-09 10:17:13 +0200219
220 /* Move pointer to next descriptor */
221 dwc->tx_node_active = dwc->tx_node_active->next;
Andy Shevchenkofed25742012-09-21 15:05:49 +0300222}
223
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700224/* Called with dwc->lock held and bh disabled */
225static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
226{
227 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
Andy Shevchenkofed25742012-09-21 15:05:49 +0300228 unsigned long was_soft_llp;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700229
230 /* ASSERT: channel is idle */
231 if (dma_readl(dw, CH_EN) & dwc->mask) {
Dan Williams41d5e592009-01-06 11:38:21 -0700232 dev_err(chan2dev(&dwc->chan),
Jarkko Nikula550da642015-03-10 11:37:23 +0200233 "%s: BUG: Attempted to start non-idle channel\n",
234 __func__);
Andy Shevchenko1d455432012-06-19 13:34:03 +0300235 dwc_dump_chan_regs(dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700236
237 /* The tasklet will hopefully advance the queue... */
238 return;
239 }
240
Andy Shevchenkofed25742012-09-21 15:05:49 +0300241 if (dwc->nollp) {
242 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
243 &dwc->flags);
244 if (was_soft_llp) {
245 dev_err(chan2dev(&dwc->chan),
Andy Shevchenkofc61f6b2014-01-13 14:04:49 +0200246 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
Andy Shevchenkofed25742012-09-21 15:05:49 +0300247 return;
248 }
249
250 dwc_initialize(dwc);
251
Andy Shevchenko4702d522013-01-25 11:48:03 +0200252 dwc->residue = first->total_len;
Andy Shevchenkof5c6a7d2013-01-09 10:17:13 +0200253 dwc->tx_node_active = &first->tx_list;
Andy Shevchenkofed25742012-09-21 15:05:49 +0300254
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200255 /* Submit first block */
Andy Shevchenkofed25742012-09-21 15:05:49 +0300256 dwc_do_single_block(dwc, first);
257
258 return;
259 }
260
Viresh Kumar61e183f2011-11-17 16:01:29 +0530261 dwc_initialize(dwc);
262
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700263 channel_writel(dwc, LLP, first->txd.phys);
264 channel_writel(dwc, CTL_LO,
265 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
266 channel_writel(dwc, CTL_HI, 0);
267 channel_set_bit(dw, CH_EN, dwc->mask);
268}
269
Andy Shevchenkoe7637c62014-06-18 12:15:36 +0300270static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
271{
Andy Shevchenkocba15612014-06-18 12:15:37 +0300272 struct dw_desc *desc;
273
Andy Shevchenkoe7637c62014-06-18 12:15:36 +0300274 if (list_empty(&dwc->queue))
275 return;
276
277 list_move(dwc->queue.next, &dwc->active_list);
Andy Shevchenkocba15612014-06-18 12:15:37 +0300278 desc = dwc_first_active(dwc);
279 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
280 dwc_dostart(dwc, desc);
Andy Shevchenkoe7637c62014-06-18 12:15:36 +0300281}
282
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700283/*----------------------------------------------------------------------*/
284
285static void
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530286dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
287 bool callback_required)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700288{
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530289 dma_async_tx_callback callback = NULL;
290 void *param = NULL;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700291 struct dma_async_tx_descriptor *txd = &desc->txd;
Viresh Kumare5180762011-03-03 15:47:20 +0530292 struct dw_desc *child;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530293 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700294
Dan Williams41d5e592009-01-06 11:38:21 -0700295 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700296
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530297 spin_lock_irqsave(&dwc->lock, flags);
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +0000298 dma_cookie_complete(txd);
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530299 if (callback_required) {
300 callback = txd->callback;
301 param = txd->callback_param;
302 }
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700303
Viresh Kumare5180762011-03-03 15:47:20 +0530304 /* async_tx_ack */
305 list_for_each_entry(child, &desc->tx_list, desc_node)
306 async_tx_ack(&child->txd);
307 async_tx_ack(&desc->txd);
308
Dan Williamse0bd0f82009-09-08 17:53:02 -0700309 list_splice_init(&desc->tx_list, &dwc->free_list);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700310 list_move(&desc->desc_node, &dwc->free_list);
311
Dan Williamsd38a8c62013-10-18 19:35:23 +0200312 dma_descriptor_unmap(txd);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530313 spin_unlock_irqrestore(&dwc->lock, flags);
314
Andy Shevchenko21e93c12013-01-09 10:17:12 +0200315 if (callback)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700316 callback(param);
317}
318
319static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
320{
321 struct dw_desc *desc, *_desc;
322 LIST_HEAD(list);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530323 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700324
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530325 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700326 if (dma_readl(dw, CH_EN) & dwc->mask) {
Dan Williams41d5e592009-01-06 11:38:21 -0700327 dev_err(chan2dev(&dwc->chan),
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700328 "BUG: XFER bit set, but channel not idle!\n");
329
330 /* Try to continue after resetting the channel... */
Andy Shevchenko3f9362072012-06-19 13:46:32 +0300331 dwc_chan_disable(dw, dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700332 }
333
334 /*
335 * Submit queued descriptors ASAP, i.e. before we go through
336 * the completed ones.
337 */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700338 list_splice_init(&dwc->active_list, &list);
Andy Shevchenkoe7637c62014-06-18 12:15:36 +0300339 dwc_dostart_first_queued(dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700340
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530341 spin_unlock_irqrestore(&dwc->lock, flags);
342
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700343 list_for_each_entry_safe(desc, _desc, &list, desc_node)
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530344 dwc_descriptor_complete(dwc, desc, true);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700345}
346
Andy Shevchenko4702d522013-01-25 11:48:03 +0200347/* Returns how many bytes were already received from source */
348static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
349{
350 u32 ctlhi = channel_readl(dwc, CTL_HI);
351 u32 ctllo = channel_readl(dwc, CTL_LO);
352
353 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
354}
355
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700356static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
357{
358 dma_addr_t llp;
359 struct dw_desc *desc, *_desc;
360 struct dw_desc *child;
361 u32 status_xfer;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530362 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700363
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530364 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700365 llp = channel_readl(dwc, LLP);
366 status_xfer = dma_readl(dw, RAW.XFER);
367
368 if (status_xfer & dwc->mask) {
369 /* Everything we've submitted is done */
370 dma_writel(dw, CLEAR.XFER, dwc->mask);
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200371
372 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200373 struct list_head *head, *active = dwc->tx_node_active;
374
375 /*
376 * We are inside first active descriptor.
377 * Otherwise something is really wrong.
378 */
379 desc = dwc_first_active(dwc);
380
381 head = &desc->tx_list;
382 if (active != head) {
Andy Shevchenko4702d522013-01-25 11:48:03 +0200383 /* Update desc to reflect last sent one */
384 if (active != head->next)
385 desc = to_dw_desc(active->prev);
386
387 dwc->residue -= desc->len;
388
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200389 child = to_dw_desc(active);
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200390
391 /* Submit next block */
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200392 dwc_do_single_block(dwc, child);
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200393
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200394 spin_unlock_irqrestore(&dwc->lock, flags);
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200395 return;
396 }
Andy Shevchenkofdf475f2013-01-25 11:48:00 +0200397
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200398 /* We are done here */
399 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
400 }
Andy Shevchenko4702d522013-01-25 11:48:03 +0200401
402 dwc->residue = 0;
403
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530404 spin_unlock_irqrestore(&dwc->lock, flags);
405
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700406 dwc_complete_all(dw, dwc);
407 return;
408 }
409
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530410 if (list_empty(&dwc->active_list)) {
Andy Shevchenko4702d522013-01-25 11:48:03 +0200411 dwc->residue = 0;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530412 spin_unlock_irqrestore(&dwc->lock, flags);
Jamie Iles087809f2011-01-21 14:11:52 +0000413 return;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530414 }
Jamie Iles087809f2011-01-21 14:11:52 +0000415
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200416 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
417 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700418 spin_unlock_irqrestore(&dwc->lock, flags);
Dan Williams41d5e592009-01-06 11:38:21 -0700419 return;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700420 }
421
Andy Shevchenko5a87f0e2014-01-13 14:04:50 +0200422 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700423
424 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
Andy Shevchenko75c61222013-03-26 16:53:54 +0200425 /* Initial residue value */
Andy Shevchenko4702d522013-01-25 11:48:03 +0200426 dwc->residue = desc->total_len;
427
Andy Shevchenko75c61222013-03-26 16:53:54 +0200428 /* Check first descriptors addr */
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530429 if (desc->txd.phys == llp) {
430 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700431 return;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530432 }
Viresh Kumar84adccf2011-03-24 11:32:15 +0530433
Andy Shevchenko75c61222013-03-26 16:53:54 +0200434 /* Check first descriptors llp */
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530435 if (desc->lli.llp == llp) {
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700436 /* This one is currently in progress */
Andy Shevchenko4702d522013-01-25 11:48:03 +0200437 dwc->residue -= dwc_get_sent(dwc);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530438 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700439 return;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530440 }
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700441
Andy Shevchenko4702d522013-01-25 11:48:03 +0200442 dwc->residue -= desc->len;
443 list_for_each_entry(child, &desc->tx_list, desc_node) {
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530444 if (child->lli.llp == llp) {
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700445 /* Currently in progress */
Andy Shevchenko4702d522013-01-25 11:48:03 +0200446 dwc->residue -= dwc_get_sent(dwc);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530447 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700448 return;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530449 }
Andy Shevchenko4702d522013-01-25 11:48:03 +0200450 dwc->residue -= child->len;
451 }
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700452
453 /*
454 * No descriptors so far seem to be in progress, i.e.
455 * this one must be done.
456 */
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530457 spin_unlock_irqrestore(&dwc->lock, flags);
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530458 dwc_descriptor_complete(dwc, desc, true);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530459 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700460 }
461
Dan Williams41d5e592009-01-06 11:38:21 -0700462 dev_err(chan2dev(&dwc->chan),
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700463 "BUG: All descriptors done, but channel not idle!\n");
464
465 /* Try to continue after resetting the channel... */
Andy Shevchenko3f9362072012-06-19 13:46:32 +0300466 dwc_chan_disable(dw, dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700467
Andy Shevchenkoe7637c62014-06-18 12:15:36 +0300468 dwc_dostart_first_queued(dwc);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530469 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700470}
471
Andy Shevchenko93aad1b2012-07-13 11:09:32 +0300472static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700473{
Andy Shevchenko21d43f42012-10-18 17:34:09 +0300474 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
475 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700476}
477
478static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
479{
480 struct dw_desc *bad_desc;
481 struct dw_desc *child;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530482 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700483
484 dwc_scan_descriptors(dw, dwc);
485
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530486 spin_lock_irqsave(&dwc->lock, flags);
487
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700488 /*
489 * The descriptor currently at the head of the active list is
490 * borked. Since we don't have any way to report errors, we'll
491 * just have to scream loudly and try to carry on.
492 */
493 bad_desc = dwc_first_active(dwc);
494 list_del_init(&bad_desc->desc_node);
Viresh Kumarf336e422011-03-03 15:47:16 +0530495 list_move(dwc->queue.next, dwc->active_list.prev);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700496
497 /* Clear the error flag and try to restart the controller */
498 dma_writel(dw, CLEAR.ERROR, dwc->mask);
499 if (!list_empty(&dwc->active_list))
500 dwc_dostart(dwc, dwc_first_active(dwc));
501
502 /*
Andy Shevchenkoba84bd72012-10-18 17:34:11 +0300503 * WARN may seem harsh, but since this only happens
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700504 * when someone submits a bad physical address in a
505 * descriptor, we should consider ourselves lucky that the
506 * controller flagged an error instead of scribbling over
507 * random memory locations.
508 */
Andy Shevchenkoba84bd72012-10-18 17:34:11 +0300509 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
510 " cookie: %d\n", bad_desc->txd.cookie);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700511 dwc_dump_lli(dwc, &bad_desc->lli);
Dan Williamse0bd0f82009-09-08 17:53:02 -0700512 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700513 dwc_dump_lli(dwc, &child->lli);
514
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530515 spin_unlock_irqrestore(&dwc->lock, flags);
516
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700517 /* Pretend the descriptor completed successfully */
Viresh Kumar5fedefb2011-04-15 16:03:35 +0530518 dwc_descriptor_complete(dwc, bad_desc, true);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700519}
520
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200521/* --------------------- Cyclic DMA API extensions -------------------- */
522
Denis Efremov8004cbb2013-05-09 13:19:40 +0400523dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200524{
525 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
526 return channel_readl(dwc, SAR);
527}
528EXPORT_SYMBOL(dw_dma_get_src_addr);
529
Denis Efremov8004cbb2013-05-09 13:19:40 +0400530dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200531{
532 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
533 return channel_readl(dwc, DAR);
534}
535EXPORT_SYMBOL(dw_dma_get_dst_addr);
536
Andy Shevchenko75c61222013-03-26 16:53:54 +0200537/* Called with dwc->lock held and all DMAC interrupts disabled */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200538static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
Viresh Kumarff7b05f2012-02-01 16:12:23 +0530539 u32 status_err, u32 status_xfer)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200540{
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530541 unsigned long flags;
542
Viresh Kumarff7b05f2012-02-01 16:12:23 +0530543 if (dwc->mask) {
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200544 void (*callback)(void *param);
545 void *callback_param;
546
547 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
548 channel_readl(dwc, LLP));
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200549
550 callback = dwc->cdesc->period_callback;
551 callback_param = dwc->cdesc->period_callback_param;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530552
553 if (callback)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200554 callback(callback_param);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200555 }
556
557 /*
558 * Error and transfer complete are highly unlikely, and will most
559 * likely be due to a configuration error by the user.
560 */
561 if (unlikely(status_err & dwc->mask) ||
562 unlikely(status_xfer & dwc->mask)) {
563 int i;
564
Andy Shevchenkofc61f6b2014-01-13 14:04:49 +0200565 dev_err(chan2dev(&dwc->chan),
566 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
567 status_xfer ? "xfer" : "error");
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530568
569 spin_lock_irqsave(&dwc->lock, flags);
570
Andy Shevchenko1d455432012-06-19 13:34:03 +0300571 dwc_dump_chan_regs(dwc);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200572
Andy Shevchenko3f9362072012-06-19 13:46:32 +0300573 dwc_chan_disable(dw, dwc);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200574
Andy Shevchenko75c61222013-03-26 16:53:54 +0200575 /* Make sure DMA does not restart by loading a new list */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200576 channel_writel(dwc, LLP, 0);
577 channel_writel(dwc, CTL_LO, 0);
578 channel_writel(dwc, CTL_HI, 0);
579
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200580 dma_writel(dw, CLEAR.ERROR, dwc->mask);
581 dma_writel(dw, CLEAR.XFER, dwc->mask);
582
583 for (i = 0; i < dwc->cdesc->periods; i++)
584 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530585
586 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200587 }
588}
589
590/* ------------------------------------------------------------------------- */
591
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700592static void dw_dma_tasklet(unsigned long data)
593{
594 struct dw_dma *dw = (struct dw_dma *)data;
595 struct dw_dma_chan *dwc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700596 u32 status_xfer;
597 u32 status_err;
598 int i;
599
Haavard Skinnemoen7fe7b2f2008-10-03 15:23:46 -0700600 status_xfer = dma_readl(dw, RAW.XFER);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700601 status_err = dma_readl(dw, RAW.ERROR);
602
Andy Shevchenko2e4c3642012-06-19 13:34:05 +0300603 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700604
605 for (i = 0; i < dw->dma.chancnt; i++) {
606 dwc = &dw->chan[i];
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200607 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
Viresh Kumarff7b05f2012-02-01 16:12:23 +0530608 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200609 else if (status_err & (1 << i))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700610 dwc_handle_error(dw, dwc);
Andy Shevchenko77bcc4972013-01-18 14:14:15 +0200611 else if (status_xfer & (1 << i))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700612 dwc_scan_descriptors(dw, dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700613 }
614
615 /*
Viresh Kumarff7b05f2012-02-01 16:12:23 +0530616 * Re-enable interrupts.
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700617 */
618 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700619 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
620}
621
622static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
623{
624 struct dw_dma *dw = dev_id;
Andy Shevchenko3783cef2013-07-15 15:04:39 +0300625 u32 status = dma_readl(dw, STATUS_INT);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700626
Andy Shevchenko3783cef2013-07-15 15:04:39 +0300627 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
628
629 /* Check if we have any interrupt from the DMAC */
Jie Yang94b3eed2015-03-05 14:08:08 +0800630 if (!status || !dw->in_use)
Andy Shevchenko3783cef2013-07-15 15:04:39 +0300631 return IRQ_NONE;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700632
633 /*
634 * Just disable the interrupts. We'll turn them back on in the
635 * softirq handler.
636 */
637 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700638 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
639
640 status = dma_readl(dw, STATUS_INT);
641 if (status) {
642 dev_err(dw->dma.dev,
643 "BUG: Unexpected interrupts pending: 0x%x\n",
644 status);
645
646 /* Try to recover */
647 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700648 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
649 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
650 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
651 }
652
653 tasklet_schedule(&dw->tasklet);
654
655 return IRQ_HANDLED;
656}
657
658/*----------------------------------------------------------------------*/
659
660static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
661{
662 struct dw_desc *desc = txd_to_dw_desc(tx);
663 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
664 dma_cookie_t cookie;
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530665 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700666
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530667 spin_lock_irqsave(&dwc->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000668 cookie = dma_cookie_assign(tx);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700669
670 /*
671 * REVISIT: We should attempt to chain as many descriptors as
672 * possible, perhaps even appending to those already submitted
673 * for DMA. But this is hard to do in a race-free manner.
674 */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700675
Andy Shevchenkodd8ecfca2014-06-18 12:15:38 +0300676 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
677 list_add_tail(&desc->desc_node, &dwc->queue);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700678
Viresh Kumar69cea5a2011-04-15 16:03:35 +0530679 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700680
681 return cookie;
682}
683
684static struct dma_async_tx_descriptor *
685dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
686 size_t len, unsigned long flags)
687{
688 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
Arnd Bergmannf7760762013-03-26 16:53:57 +0200689 struct dw_dma *dw = to_dw_dma(chan->device);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700690 struct dw_desc *desc;
691 struct dw_desc *first;
692 struct dw_desc *prev;
693 size_t xfer_count;
694 size_t offset;
695 unsigned int src_width;
696 unsigned int dst_width;
Andy Shevchenko3d4f8602012-10-01 13:06:25 +0300697 unsigned int data_width;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700698 u32 ctllo;
699
Andy Shevchenko2f45d612012-06-19 13:34:02 +0300700 dev_vdbg(chan2dev(chan),
Andy Shevchenko5a87f0e2014-01-13 14:04:50 +0200701 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
702 &dest, &src, len, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700703
704 if (unlikely(!len)) {
Andy Shevchenko2e4c3642012-06-19 13:34:05 +0300705 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700706 return NULL;
707 }
708
Andy Shevchenko0fdb5672013-01-10 10:53:03 +0200709 dwc->direction = DMA_MEM_TO_MEM;
710
Arnd Bergmannf7760762013-03-26 16:53:57 +0200711 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
712 dw->data_width[dwc->dst_master]);
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300713
Andy Shevchenko3d4f8602012-10-01 13:06:25 +0300714 src_width = dst_width = min_t(unsigned int, data_width,
Andy Shevchenko39416672015-09-28 18:57:04 +0300715 dwc_fast_ffs(src | dest | len));
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700716
Viresh Kumar327e6972012-02-01 16:12:26 +0530717 ctllo = DWC_DEFAULT_CTLLO(chan)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700718 | DWC_CTLL_DST_WIDTH(dst_width)
719 | DWC_CTLL_SRC_WIDTH(src_width)
720 | DWC_CTLL_DST_INC
721 | DWC_CTLL_SRC_INC
722 | DWC_CTLL_FC_M2M;
723 prev = first = NULL;
724
725 for (offset = 0; offset < len; offset += xfer_count << src_width) {
726 xfer_count = min_t(size_t, (len - offset) >> src_width,
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +0300727 dwc->block_size);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700728
729 desc = dwc_desc_get(dwc);
730 if (!desc)
731 goto err_desc_get;
732
733 desc->lli.sar = src + offset;
734 desc->lli.dar = dest + offset;
735 desc->lli.ctllo = ctllo;
736 desc->lli.ctlhi = xfer_count;
Andy Shevchenko176dcec2013-01-25 11:48:02 +0200737 desc->len = xfer_count << src_width;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700738
739 if (!first) {
740 first = desc;
741 } else {
742 prev->lli.llp = desc->txd.phys;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700743 list_add_tail(&desc->desc_node,
Dan Williamse0bd0f82009-09-08 17:53:02 -0700744 &first->tx_list);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700745 }
746 prev = desc;
747 }
748
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700749 if (flags & DMA_PREP_INTERRUPT)
750 /* Trigger interrupt after last block */
751 prev->lli.ctllo |= DWC_CTLL_INT_EN;
752
753 prev->lli.llp = 0;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700754 first->txd.flags = flags;
Andy Shevchenko30d38a32013-01-25 11:48:01 +0200755 first->total_len = len;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700756
757 return &first->txd;
758
759err_desc_get:
760 dwc_desc_put(dwc, first);
761 return NULL;
762}
763
764static struct dma_async_tx_descriptor *
765dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530766 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500767 unsigned long flags, void *context)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700768{
769 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
Arnd Bergmannf7760762013-03-26 16:53:57 +0200770 struct dw_dma *dw = to_dw_dma(chan->device);
Viresh Kumar327e6972012-02-01 16:12:26 +0530771 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700772 struct dw_desc *prev;
773 struct dw_desc *first;
774 u32 ctllo;
775 dma_addr_t reg;
776 unsigned int reg_width;
777 unsigned int mem_width;
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300778 unsigned int data_width;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700779 unsigned int i;
780 struct scatterlist *sg;
781 size_t total_len = 0;
782
Andy Shevchenko2e4c3642012-06-19 13:34:05 +0300783 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700784
Andy Shevchenko495aea42013-01-10 11:11:41 +0200785 if (unlikely(!is_slave_direction(direction) || !sg_len))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700786 return NULL;
787
Andy Shevchenko0fdb5672013-01-10 10:53:03 +0200788 dwc->direction = direction;
789
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700790 prev = first = NULL;
791
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700792 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +0530793 case DMA_MEM_TO_DEV:
Andy Shevchenko39416672015-09-28 18:57:04 +0300794 reg_width = __ffs(sconfig->dst_addr_width);
Viresh Kumar327e6972012-02-01 16:12:26 +0530795 reg = sconfig->dst_addr;
796 ctllo = (DWC_DEFAULT_CTLLO(chan)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700797 | DWC_CTLL_DST_WIDTH(reg_width)
798 | DWC_CTLL_DST_FIX
Viresh Kumar327e6972012-02-01 16:12:26 +0530799 | DWC_CTLL_SRC_INC);
800
801 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
802 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
803
Arnd Bergmannf7760762013-03-26 16:53:57 +0200804 data_width = dw->data_width[dwc->src_master];
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300805
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700806 for_each_sg(sgl, sg, sg_len, i) {
807 struct dw_desc *desc;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530808 u32 len, dlen, mem;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700809
Lars-Peter Clausencbb796c2012-04-25 20:50:51 +0200810 mem = sg_dma_address(sg);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700811 len = sg_dma_len(sg);
Viresh Kumar6bc711f2012-02-01 16:12:25 +0530812
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300813 mem_width = min_t(unsigned int,
Andy Shevchenko39416672015-09-28 18:57:04 +0300814 data_width, dwc_fast_ffs(mem | len));
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700815
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530816slave_sg_todev_fill_desc:
817 desc = dwc_desc_get(dwc);
Jarkko Nikulab2607222015-03-10 11:37:24 +0200818 if (!desc)
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530819 goto err_desc_get;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530820
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700821 desc->lli.sar = mem;
822 desc->lli.dar = reg;
823 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +0300824 if ((len >> mem_width) > dwc->block_size) {
825 dlen = dwc->block_size << mem_width;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530826 mem += dlen;
827 len -= dlen;
828 } else {
829 dlen = len;
830 len = 0;
831 }
832
833 desc->lli.ctlhi = dlen >> mem_width;
Andy Shevchenko176dcec2013-01-25 11:48:02 +0200834 desc->len = dlen;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700835
836 if (!first) {
837 first = desc;
838 } else {
839 prev->lli.llp = desc->txd.phys;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700840 list_add_tail(&desc->desc_node,
Dan Williamse0bd0f82009-09-08 17:53:02 -0700841 &first->tx_list);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700842 }
843 prev = desc;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530844 total_len += dlen;
845
846 if (len)
847 goto slave_sg_todev_fill_desc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700848 }
849 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530850 case DMA_DEV_TO_MEM:
Andy Shevchenko39416672015-09-28 18:57:04 +0300851 reg_width = __ffs(sconfig->src_addr_width);
Viresh Kumar327e6972012-02-01 16:12:26 +0530852 reg = sconfig->src_addr;
853 ctllo = (DWC_DEFAULT_CTLLO(chan)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700854 | DWC_CTLL_SRC_WIDTH(reg_width)
855 | DWC_CTLL_DST_INC
Viresh Kumar327e6972012-02-01 16:12:26 +0530856 | DWC_CTLL_SRC_FIX);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700857
Viresh Kumar327e6972012-02-01 16:12:26 +0530858 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
859 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
860
Arnd Bergmannf7760762013-03-26 16:53:57 +0200861 data_width = dw->data_width[dwc->dst_master];
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300862
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700863 for_each_sg(sgl, sg, sg_len, i) {
864 struct dw_desc *desc;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530865 u32 len, dlen, mem;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700866
Lars-Peter Clausencbb796c2012-04-25 20:50:51 +0200867 mem = sg_dma_address(sg);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700868 len = sg_dma_len(sg);
Viresh Kumar6bc711f2012-02-01 16:12:25 +0530869
Andy Shevchenkoa0982002012-09-21 15:05:48 +0300870 mem_width = min_t(unsigned int,
Andy Shevchenko39416672015-09-28 18:57:04 +0300871 data_width, dwc_fast_ffs(mem | len));
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700872
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530873slave_sg_fromdev_fill_desc:
874 desc = dwc_desc_get(dwc);
Jarkko Nikulab2607222015-03-10 11:37:24 +0200875 if (!desc)
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530876 goto err_desc_get;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530877
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700878 desc->lli.sar = reg;
879 desc->lli.dar = mem;
880 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +0300881 if ((len >> reg_width) > dwc->block_size) {
882 dlen = dwc->block_size << reg_width;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530883 mem += dlen;
884 len -= dlen;
885 } else {
886 dlen = len;
887 len = 0;
888 }
889 desc->lli.ctlhi = dlen >> reg_width;
Andy Shevchenko176dcec2013-01-25 11:48:02 +0200890 desc->len = dlen;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700891
892 if (!first) {
893 first = desc;
894 } else {
895 prev->lli.llp = desc->txd.phys;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700896 list_add_tail(&desc->desc_node,
Dan Williamse0bd0f82009-09-08 17:53:02 -0700897 &first->tx_list);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700898 }
899 prev = desc;
Viresh Kumar69dc14b2011-04-18 14:54:56 +0530900 total_len += dlen;
901
902 if (len)
903 goto slave_sg_fromdev_fill_desc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700904 }
905 break;
906 default:
907 return NULL;
908 }
909
910 if (flags & DMA_PREP_INTERRUPT)
911 /* Trigger interrupt after last block */
912 prev->lli.ctllo |= DWC_CTLL_INT_EN;
913
914 prev->lli.llp = 0;
Andy Shevchenko30d38a32013-01-25 11:48:01 +0200915 first->total_len = total_len;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700916
917 return &first->txd;
918
919err_desc_get:
Jarkko Nikulab2607222015-03-10 11:37:24 +0200920 dev_err(chan2dev(chan),
921 "not enough descriptors available. Direction %d\n", direction);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700922 dwc_desc_put(dwc, first);
923 return NULL;
924}
925
Andy Shevchenko4d130de2014-08-19 20:29:16 +0300926bool dw_dma_filter(struct dma_chan *chan, void *param)
927{
928 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
929 struct dw_dma_slave *dws = param;
930
931 if (!dws || dws->dma_dev != chan->device->dev)
932 return false;
933
934 /* We have to copy data since dws can be temporary storage */
935
936 dwc->src_id = dws->src_id;
937 dwc->dst_id = dws->dst_id;
938
939 dwc->src_master = dws->src_master;
940 dwc->dst_master = dws->dst_master;
941
942 return true;
943}
944EXPORT_SYMBOL_GPL(dw_dma_filter);
945
Viresh Kumar327e6972012-02-01 16:12:26 +0530946/*
947 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
948 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
949 *
950 * NOTE: burst size 2 is not supported by controller.
951 *
952 * This can be done by finding least significant bit set: n & (n - 1)
953 */
954static inline void convert_burst(u32 *maxburst)
955{
956 if (*maxburst > 1)
957 *maxburst = fls(*maxburst) - 2;
958 else
959 *maxburst = 0;
960}
961
Maxime Riparda4b0d342014-11-17 14:42:12 +0100962static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
Viresh Kumar327e6972012-02-01 16:12:26 +0530963{
964 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
965
Andy Shevchenko495aea42013-01-10 11:11:41 +0200966 /* Check if chan will be configured for slave transfers */
967 if (!is_slave_direction(sconfig->direction))
Viresh Kumar327e6972012-02-01 16:12:26 +0530968 return -EINVAL;
969
970 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
Andy Shevchenko0fdb5672013-01-10 10:53:03 +0200971 dwc->direction = sconfig->direction;
Viresh Kumar327e6972012-02-01 16:12:26 +0530972
973 convert_burst(&dwc->dma_sconfig.src_maxburst);
974 convert_burst(&dwc->dma_sconfig.dst_maxburst);
975
976 return 0;
977}
978
Maxime Riparda4b0d342014-11-17 14:42:12 +0100979static int dwc_pause(struct dma_chan *chan)
Andy Shevchenko21fe3c52013-01-09 10:17:14 +0200980{
Maxime Riparda4b0d342014-11-17 14:42:12 +0100981 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
982 unsigned long flags;
983 unsigned int count = 20; /* timeout iterations */
984 u32 cfglo;
Andy Shevchenko21fe3c52013-01-09 10:17:14 +0200985
Maxime Riparda4b0d342014-11-17 14:42:12 +0100986 spin_lock_irqsave(&dwc->lock, flags);
987
988 cfglo = channel_readl(dwc, CFG_LO);
Andy Shevchenko21fe3c52013-01-09 10:17:14 +0200989 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
Andy Shevchenko123b69a2013-03-21 11:49:17 +0200990 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
991 udelay(2);
Andy Shevchenko21fe3c52013-01-09 10:17:14 +0200992
993 dwc->paused = true;
Maxime Riparda4b0d342014-11-17 14:42:12 +0100994
995 spin_unlock_irqrestore(&dwc->lock, flags);
996
997 return 0;
Andy Shevchenko21fe3c52013-01-09 10:17:14 +0200998}
999
1000static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1001{
1002 u32 cfglo = channel_readl(dwc, CFG_LO);
1003
1004 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1005
1006 dwc->paused = false;
1007}
1008
Maxime Riparda4b0d342014-11-17 14:42:12 +01001009static int dwc_resume(struct dma_chan *chan)
1010{
1011 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1012 unsigned long flags;
1013
1014 if (!dwc->paused)
1015 return 0;
1016
1017 spin_lock_irqsave(&dwc->lock, flags);
1018
1019 dwc_chan_resume(dwc);
1020
1021 spin_unlock_irqrestore(&dwc->lock, flags);
1022
1023 return 0;
1024}
1025
1026static int dwc_terminate_all(struct dma_chan *chan)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001027{
1028 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1029 struct dw_dma *dw = to_dw_dma(chan->device);
1030 struct dw_desc *desc, *_desc;
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301031 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001032 LIST_HEAD(list);
1033
Maxime Riparda4b0d342014-11-17 14:42:12 +01001034 spin_lock_irqsave(&dwc->lock, flags);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001035
Maxime Riparda4b0d342014-11-17 14:42:12 +01001036 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001037
Maxime Riparda4b0d342014-11-17 14:42:12 +01001038 dwc_chan_disable(dw, dwc);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001039
Maxime Riparda4b0d342014-11-17 14:42:12 +01001040 dwc_chan_resume(dwc);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001041
Maxime Riparda4b0d342014-11-17 14:42:12 +01001042 /* active_list entries will end up before queued entries */
1043 list_splice_init(&dwc->queue, &list);
1044 list_splice_init(&dwc->active_list, &list);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001045
Maxime Riparda4b0d342014-11-17 14:42:12 +01001046 spin_unlock_irqrestore(&dwc->lock, flags);
Linus Walleija7c57cf2011-04-19 08:31:32 +08001047
Maxime Riparda4b0d342014-11-17 14:42:12 +01001048 /* Flush all pending and queued descriptors */
1049 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1050 dwc_descriptor_complete(dwc, desc, false);
Linus Walleijc3635c72010-03-26 16:44:01 -07001051
Linus Walleijc3635c72010-03-26 16:44:01 -07001052 return 0;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001053}
1054
Andy Shevchenko4702d522013-01-25 11:48:03 +02001055static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1056{
1057 unsigned long flags;
1058 u32 residue;
1059
1060 spin_lock_irqsave(&dwc->lock, flags);
1061
1062 residue = dwc->residue;
1063 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1064 residue -= dwc_get_sent(dwc);
1065
1066 spin_unlock_irqrestore(&dwc->lock, flags);
1067 return residue;
1068}
1069
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001070static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -07001071dwc_tx_status(struct dma_chan *chan,
1072 dma_cookie_t cookie,
1073 struct dma_tx_state *txstate)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001074{
1075 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00001076 enum dma_status ret;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001077
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00001078 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul2c404102013-10-16 13:41:15 +05301079 if (ret == DMA_COMPLETE)
Andy Shevchenko12381dc2013-07-15 15:04:40 +03001080 return ret;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001081
Andy Shevchenko12381dc2013-07-15 15:04:40 +03001082 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001083
Andy Shevchenko12381dc2013-07-15 15:04:40 +03001084 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul2c404102013-10-16 13:41:15 +05301085 if (ret != DMA_COMPLETE)
Andy Shevchenko4702d522013-01-25 11:48:03 +02001086 dma_set_residue(txstate, dwc_get_residue(dwc));
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001087
Andy Shevchenkoeffd5cf2013-07-15 15:04:41 +03001088 if (dwc->paused && ret == DMA_IN_PROGRESS)
Linus Walleija7c57cf2011-04-19 08:31:32 +08001089 return DMA_PAUSED;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001090
1091 return ret;
1092}
1093
1094static void dwc_issue_pending(struct dma_chan *chan)
1095{
1096 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
Andy Shevchenkodd8ecfca2014-06-18 12:15:38 +03001097 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001098
Andy Shevchenkodd8ecfca2014-06-18 12:15:38 +03001099 spin_lock_irqsave(&dwc->lock, flags);
1100 if (list_empty(&dwc->active_list))
1101 dwc_dostart_first_queued(dwc);
1102 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001103}
1104
Andy Shevchenko99d9bf42014-09-23 17:18:14 +03001105/*----------------------------------------------------------------------*/
1106
1107static void dw_dma_off(struct dw_dma *dw)
1108{
1109 int i;
1110
1111 dma_writel(dw, CFG, 0);
1112
1113 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1114 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1115 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1116 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1117
1118 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1119 cpu_relax();
1120
1121 for (i = 0; i < dw->dma.chancnt; i++)
1122 dw->chan[i].initialized = false;
1123}
1124
1125static void dw_dma_on(struct dw_dma *dw)
1126{
1127 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1128}
1129
Dan Williamsaa1e6f12009-01-06 11:38:17 -07001130static int dwc_alloc_chan_resources(struct dma_chan *chan)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001131{
1132 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1133 struct dw_dma *dw = to_dw_dma(chan->device);
1134 struct dw_desc *desc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001135 int i;
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301136 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001137
Andy Shevchenko2e4c3642012-06-19 13:34:05 +03001138 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001139
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001140 /* ASSERT: channel is idle */
1141 if (dma_readl(dw, CH_EN) & dwc->mask) {
Dan Williams41d5e592009-01-06 11:38:21 -07001142 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001143 return -EIO;
1144 }
1145
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001146 dma_cookie_init(chan);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001147
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001148 /*
1149 * NOTE: some controllers may have additional features that we
1150 * need to initialize here, like "scatter-gather" (which
1151 * doesn't mean what you think it means), and status writeback.
1152 */
1153
Andy Shevchenko99d9bf42014-09-23 17:18:14 +03001154 /* Enable controller here if needed */
1155 if (!dw->in_use)
1156 dw_dma_on(dw);
1157 dw->in_use |= dwc->mask;
1158
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301159 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001160 i = dwc->descs_allocated;
1161 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001162 dma_addr_t phys;
1163
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301164 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001165
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001166 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
Andy Shevchenkocbd65312013-01-09 10:17:11 +02001167 if (!desc)
1168 goto err_desc_alloc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001169
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001170 memset(desc, 0, sizeof(struct dw_desc));
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001171
Dan Williamse0bd0f82009-09-08 17:53:02 -07001172 INIT_LIST_HEAD(&desc->tx_list);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001173 dma_async_tx_descriptor_init(&desc->txd, chan);
1174 desc->txd.tx_submit = dwc_tx_submit;
1175 desc->txd.flags = DMA_CTRL_ACK;
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001176 desc->txd.phys = phys;
Andy Shevchenkocbd65312013-01-09 10:17:11 +02001177
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001178 dwc_desc_put(dwc, desc);
1179
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301180 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001181 i = ++dwc->descs_allocated;
1182 }
1183
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301184 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001185
Andy Shevchenko2e4c3642012-06-19 13:34:05 +03001186 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001187
1188 return i;
Andy Shevchenkocbd65312013-01-09 10:17:11 +02001189
1190err_desc_alloc:
Andy Shevchenkocbd65312013-01-09 10:17:11 +02001191 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1192
1193 return i;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001194}
1195
1196static void dwc_free_chan_resources(struct dma_chan *chan)
1197{
1198 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1199 struct dw_dma *dw = to_dw_dma(chan->device);
1200 struct dw_desc *desc, *_desc;
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301201 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001202 LIST_HEAD(list);
1203
Andy Shevchenko2e4c3642012-06-19 13:34:05 +03001204 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001205 dwc->descs_allocated);
1206
1207 /* ASSERT: channel is idle */
1208 BUG_ON(!list_empty(&dwc->active_list));
1209 BUG_ON(!list_empty(&dwc->queue));
1210 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1211
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301212 spin_lock_irqsave(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001213 list_splice_init(&dwc->free_list, &list);
1214 dwc->descs_allocated = 0;
Viresh Kumar61e183f2011-11-17 16:01:29 +05301215 dwc->initialized = false;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001216
1217 /* Disable interrupts */
1218 channel_clear_bit(dw, MASK.XFER, dwc->mask);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001219 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1220
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301221 spin_unlock_irqrestore(&dwc->lock, flags);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001222
Andy Shevchenko99d9bf42014-09-23 17:18:14 +03001223 /* Disable controller in case it was a last user */
1224 dw->in_use &= ~dwc->mask;
1225 if (!dw->in_use)
1226 dw_dma_off(dw);
1227
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001228 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
Dan Williams41d5e592009-01-06 11:38:21 -07001229 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001230 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001231 }
1232
Andy Shevchenko2e4c3642012-06-19 13:34:05 +03001233 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001234}
1235
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001236/* --------------------- Cyclic DMA API extensions -------------------- */
1237
1238/**
1239 * dw_dma_cyclic_start - start the cyclic DMA transfer
1240 * @chan: the DMA channel to start
1241 *
1242 * Must be called with soft interrupts disabled. Returns zero on success or
1243 * -errno on failure.
1244 */
1245int dw_dma_cyclic_start(struct dma_chan *chan)
1246{
1247 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1248 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301249 unsigned long flags;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001250
1251 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1252 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1253 return -ENODEV;
1254 }
1255
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301256 spin_lock_irqsave(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001257
Andy Shevchenko75c61222013-03-26 16:53:54 +02001258 /* Assert channel is idle */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001259 if (dma_readl(dw, CH_EN) & dwc->mask) {
1260 dev_err(chan2dev(&dwc->chan),
Jarkko Nikula550da642015-03-10 11:37:23 +02001261 "%s: BUG: Attempted to start non-idle channel\n",
1262 __func__);
Andy Shevchenko1d455432012-06-19 13:34:03 +03001263 dwc_dump_chan_regs(dwc);
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301264 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001265 return -EBUSY;
1266 }
1267
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001268 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1269 dma_writel(dw, CLEAR.XFER, dwc->mask);
1270
Andy Shevchenko75c61222013-03-26 16:53:54 +02001271 /* Setup DMAC channel registers */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001272 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1273 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1274 channel_writel(dwc, CTL_HI, 0);
1275
1276 channel_set_bit(dw, CH_EN, dwc->mask);
1277
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301278 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001279
1280 return 0;
1281}
1282EXPORT_SYMBOL(dw_dma_cyclic_start);
1283
1284/**
1285 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1286 * @chan: the DMA channel to stop
1287 *
1288 * Must be called with soft interrupts disabled.
1289 */
1290void dw_dma_cyclic_stop(struct dma_chan *chan)
1291{
1292 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1293 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301294 unsigned long flags;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001295
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301296 spin_lock_irqsave(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001297
Andy Shevchenko3f9362072012-06-19 13:46:32 +03001298 dwc_chan_disable(dw, dwc);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001299
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301300 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001301}
1302EXPORT_SYMBOL(dw_dma_cyclic_stop);
1303
1304/**
1305 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1306 * @chan: the DMA channel to prepare
1307 * @buf_addr: physical DMA address where the buffer starts
1308 * @buf_len: total number of bytes for the entire buffer
1309 * @period_len: number of bytes for each period
1310 * @direction: transfer direction, to or from device
1311 *
1312 * Must be called before trying to start the transfer. Returns a valid struct
1313 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1314 */
1315struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1316 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301317 enum dma_transfer_direction direction)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001318{
1319 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
Viresh Kumar327e6972012-02-01 16:12:26 +05301320 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001321 struct dw_cyclic_desc *cdesc;
1322 struct dw_cyclic_desc *retval = NULL;
1323 struct dw_desc *desc;
1324 struct dw_desc *last = NULL;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001325 unsigned long was_cyclic;
1326 unsigned int reg_width;
1327 unsigned int periods;
1328 unsigned int i;
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301329 unsigned long flags;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001330
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301331 spin_lock_irqsave(&dwc->lock, flags);
Andy Shevchenkofed25742012-09-21 15:05:49 +03001332 if (dwc->nollp) {
1333 spin_unlock_irqrestore(&dwc->lock, flags);
1334 dev_dbg(chan2dev(&dwc->chan),
1335 "channel doesn't support LLP transfers\n");
1336 return ERR_PTR(-EINVAL);
1337 }
1338
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001339 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301340 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001341 dev_dbg(chan2dev(&dwc->chan),
1342 "queue and/or active list are not empty\n");
1343 return ERR_PTR(-EBUSY);
1344 }
1345
1346 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301347 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001348 if (was_cyclic) {
1349 dev_dbg(chan2dev(&dwc->chan),
1350 "channel already prepared for cyclic DMA\n");
1351 return ERR_PTR(-EBUSY);
1352 }
1353
1354 retval = ERR_PTR(-EINVAL);
Viresh Kumar327e6972012-02-01 16:12:26 +05301355
Andy Shevchenkof44b92f2013-01-10 10:52:58 +02001356 if (unlikely(!is_slave_direction(direction)))
1357 goto out_err;
1358
Andy Shevchenko0fdb5672013-01-10 10:53:03 +02001359 dwc->direction = direction;
1360
Viresh Kumar327e6972012-02-01 16:12:26 +05301361 if (direction == DMA_MEM_TO_DEV)
1362 reg_width = __ffs(sconfig->dst_addr_width);
1363 else
1364 reg_width = __ffs(sconfig->src_addr_width);
1365
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001366 periods = buf_len / period_len;
1367
1368 /* Check for too big/unaligned periods and unaligned DMA buffer. */
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001369 if (period_len > (dwc->block_size << reg_width))
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001370 goto out_err;
1371 if (unlikely(period_len & ((1 << reg_width) - 1)))
1372 goto out_err;
1373 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1374 goto out_err;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001375
1376 retval = ERR_PTR(-ENOMEM);
1377
1378 if (periods > NR_DESCS_PER_CHANNEL)
1379 goto out_err;
1380
1381 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1382 if (!cdesc)
1383 goto out_err;
1384
1385 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1386 if (!cdesc->desc)
1387 goto out_err_alloc;
1388
1389 for (i = 0; i < periods; i++) {
1390 desc = dwc_desc_get(dwc);
1391 if (!desc)
1392 goto out_err_desc_get;
1393
1394 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05301395 case DMA_MEM_TO_DEV:
Viresh Kumar327e6972012-02-01 16:12:26 +05301396 desc->lli.dar = sconfig->dst_addr;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001397 desc->lli.sar = buf_addr + (period_len * i);
Viresh Kumar327e6972012-02-01 16:12:26 +05301398 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001399 | DWC_CTLL_DST_WIDTH(reg_width)
1400 | DWC_CTLL_SRC_WIDTH(reg_width)
1401 | DWC_CTLL_DST_FIX
1402 | DWC_CTLL_SRC_INC
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001403 | DWC_CTLL_INT_EN);
Viresh Kumar327e6972012-02-01 16:12:26 +05301404
1405 desc->lli.ctllo |= sconfig->device_fc ?
1406 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1407 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1408
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001409 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +05301410 case DMA_DEV_TO_MEM:
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001411 desc->lli.dar = buf_addr + (period_len * i);
Viresh Kumar327e6972012-02-01 16:12:26 +05301412 desc->lli.sar = sconfig->src_addr;
1413 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001414 | DWC_CTLL_SRC_WIDTH(reg_width)
1415 | DWC_CTLL_DST_WIDTH(reg_width)
1416 | DWC_CTLL_DST_INC
1417 | DWC_CTLL_SRC_FIX
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001418 | DWC_CTLL_INT_EN);
Viresh Kumar327e6972012-02-01 16:12:26 +05301419
1420 desc->lli.ctllo |= sconfig->device_fc ?
1421 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1422 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1423
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001424 break;
1425 default:
1426 break;
1427 }
1428
1429 desc->lli.ctlhi = (period_len >> reg_width);
1430 cdesc->desc[i] = desc;
1431
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001432 if (last)
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001433 last->lli.llp = desc->txd.phys;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001434
1435 last = desc;
1436 }
1437
Andy Shevchenko75c61222013-03-26 16:53:54 +02001438 /* Let's make a cyclic list */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001439 last->lli.llp = cdesc->desc[0]->txd.phys;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001440
Andy Shevchenko5a87f0e2014-01-13 14:04:50 +02001441 dev_dbg(chan2dev(&dwc->chan),
1442 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1443 &buf_addr, buf_len, period_len, periods);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001444
1445 cdesc->periods = periods;
1446 dwc->cdesc = cdesc;
1447
1448 return cdesc;
1449
1450out_err_desc_get:
1451 while (i--)
1452 dwc_desc_put(dwc, cdesc->desc[i]);
1453out_err_alloc:
1454 kfree(cdesc);
1455out_err:
1456 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1457 return (struct dw_cyclic_desc *)retval;
1458}
1459EXPORT_SYMBOL(dw_dma_cyclic_prep);
1460
1461/**
1462 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1463 * @chan: the DMA channel to free
1464 */
1465void dw_dma_cyclic_free(struct dma_chan *chan)
1466{
1467 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1468 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1469 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1470 int i;
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301471 unsigned long flags;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001472
Andy Shevchenko2e4c3642012-06-19 13:34:05 +03001473 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001474
1475 if (!cdesc)
1476 return;
1477
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301478 spin_lock_irqsave(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001479
Andy Shevchenko3f9362072012-06-19 13:46:32 +03001480 dwc_chan_disable(dw, dwc);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001481
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001482 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1483 dma_writel(dw, CLEAR.XFER, dwc->mask);
1484
Viresh Kumar69cea5a2011-04-15 16:03:35 +05301485 spin_unlock_irqrestore(&dwc->lock, flags);
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +02001486
1487 for (i = 0; i < cdesc->periods; i++)
1488 dwc_desc_put(dwc, cdesc->desc[i]);
1489
1490 kfree(cdesc->desc);
1491 kfree(cdesc);
1492
1493 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1494}
1495EXPORT_SYMBOL(dw_dma_cyclic_free);
1496
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001497/*----------------------------------------------------------------------*/
1498
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001499int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
Viresh Kumara9ddb572012-10-16 09:49:17 +05301500{
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001501 struct dw_dma *dw;
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001502 bool autocfg = false;
Andy Shevchenko482c67e2012-09-21 15:05:46 +03001503 unsigned int dw_params;
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001504 unsigned int max_blk_size = 0;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001505 int err;
1506 int i;
1507
Andy Shevchenko000871c2014-03-05 15:48:12 +02001508 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1509 if (!dw)
1510 return -ENOMEM;
1511
1512 dw->regs = chip->regs;
1513 chip->dw = dw;
1514
Andy Shevchenkobb32baf2014-11-05 18:34:48 +02001515 pm_runtime_get_sync(chip->dev);
1516
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001517 if (!pdata) {
1518 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1519 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
Andy Shevchenko482c67e2012-09-21 15:05:46 +03001520
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001521 autocfg = dw_params >> DW_PARAMS_EN & 1;
1522 if (!autocfg) {
1523 err = -EINVAL;
1524 goto err_pdata;
1525 }
Andy Shevchenko123de542013-01-09 10:17:01 +02001526
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001527 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001528 if (!pdata) {
1529 err = -ENOMEM;
1530 goto err_pdata;
1531 }
Andy Shevchenko123de542013-01-09 10:17:01 +02001532
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001533 /* Get hardware configuration parameters */
1534 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1535 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1536 for (i = 0; i < pdata->nr_masters; i++) {
1537 pdata->data_width[i] =
1538 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1539 }
1540 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1541
Andy Shevchenko123de542013-01-09 10:17:01 +02001542 /* Fill platform data with the default values */
1543 pdata->is_private = true;
Andy Shevchenkodf5c7382015-10-13 20:09:19 +03001544 pdata->is_memcpy = true;
Andy Shevchenko123de542013-01-09 10:17:01 +02001545 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1546 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001547 } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001548 err = -EINVAL;
1549 goto err_pdata;
1550 }
Andy Shevchenko123de542013-01-09 10:17:01 +02001551
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001552 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
Andy Shevchenko000871c2014-03-05 15:48:12 +02001553 GFP_KERNEL);
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001554 if (!dw->chan) {
1555 err = -ENOMEM;
1556 goto err_pdata;
1557 }
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001558
Andy Shevchenko75c61222013-03-26 16:53:54 +02001559 /* Get hardware configuration parameters */
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001560 dw->nr_masters = pdata->nr_masters;
1561 for (i = 0; i < dw->nr_masters; i++)
1562 dw->data_width[i] = pdata->data_width[i];
Andy Shevchenkoa0982002012-09-21 15:05:48 +03001563
Andy Shevchenko11f932e2012-06-19 13:34:06 +03001564 /* Calculate all channel mask before DMA setup */
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001565 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
Andy Shevchenko11f932e2012-06-19 13:34:06 +03001566
Andy Shevchenko75c61222013-03-26 16:53:54 +02001567 /* Force dma off, just in case */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001568 dw_dma_off(dw);
1569
Andy Shevchenko75c61222013-03-26 16:53:54 +02001570 /* Disable BLOCK interrupts as well */
Andy Shevchenko236b1062012-06-19 13:34:07 +03001571 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1572
Andy Shevchenko75c61222013-03-26 16:53:54 +02001573 /* Create a pool of consistent memory blocks for hardware descriptors */
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001574 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001575 sizeof(struct dw_desc), 4, 0);
1576 if (!dw->desc_pool) {
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001577 dev_err(chip->dev, "No memory for descriptors dma pool\n");
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001578 err = -ENOMEM;
1579 goto err_pdata;
Andy Shevchenkof8122a82013-01-16 15:48:50 +02001580 }
1581
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001582 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1583
Andy Shevchenko97977f72014-05-07 10:56:24 +03001584 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1585 "dw_dmac", dw);
1586 if (err)
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001587 goto err_pdata;
Andy Shevchenko97977f72014-05-07 10:56:24 +03001588
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001589 INIT_LIST_HEAD(&dw->dma.channels);
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001590 for (i = 0; i < pdata->nr_channels; i++) {
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001591 struct dw_dma_chan *dwc = &dw->chan[i];
1592
1593 dwc->chan.device = &dw->dma;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001594 dma_cookie_init(&dwc->chan);
Viresh Kumarb0c31302011-03-03 15:47:21 +05301595 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1596 list_add_tail(&dwc->chan.device_node,
1597 &dw->dma.channels);
1598 else
1599 list_add(&dwc->chan.device_node, &dw->dma.channels);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001600
Viresh Kumar93317e82011-03-03 15:47:22 +05301601 /* 7 is highest priority & 0 is lowest. */
1602 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001603 dwc->priority = pdata->nr_channels - i - 1;
Viresh Kumar93317e82011-03-03 15:47:22 +05301604 else
1605 dwc->priority = i;
1606
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001607 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1608 spin_lock_init(&dwc->lock);
1609 dwc->mask = 1 << i;
1610
1611 INIT_LIST_HEAD(&dwc->active_list);
1612 INIT_LIST_HEAD(&dwc->queue);
1613 INIT_LIST_HEAD(&dwc->free_list);
1614
1615 channel_clear_bit(dw, CH_EN, dwc->mask);
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001616
Andy Shevchenko0fdb5672013-01-10 10:53:03 +02001617 dwc->direction = DMA_TRANS_NONE;
Andy Shevchenkoa0982002012-09-21 15:05:48 +03001618
Andy Shevchenko75c61222013-03-26 16:53:54 +02001619 /* Hardware configuration */
Andy Shevchenkofed25742012-09-21 15:05:49 +03001620 if (autocfg) {
1621 unsigned int dwc_params;
Andy Shevchenko6bea0f62015-09-28 18:57:03 +03001622 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001623 void __iomem *addr = chip->regs + r * sizeof(u32);
Andy Shevchenkofed25742012-09-21 15:05:49 +03001624
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001625 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
Andy Shevchenkofed25742012-09-21 15:05:49 +03001626
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001627 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1628 dwc_params);
Andy Shevchenko985a6c72013-01-18 17:10:59 +02001629
Andy Shevchenko1d566f12014-01-13 14:04:48 +02001630 /*
1631 * Decode maximum block size for given channel. The
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001632 * stored 4 bit value represents blocks from 0x00 for 3
Andy Shevchenko1d566f12014-01-13 14:04:48 +02001633 * up to 0x0a for 4095.
1634 */
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001635 dwc->block_size =
1636 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
Andy Shevchenkofed25742012-09-21 15:05:49 +03001637 dwc->nollp =
1638 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1639 } else {
Andy Shevchenko4a63a8b2012-09-21 15:05:47 +03001640 dwc->block_size = pdata->block_size;
Andy Shevchenkofed25742012-09-21 15:05:49 +03001641
1642 /* Check if channel supports multi block transfer */
1643 channel_writel(dwc, LLP, 0xfffffffc);
1644 dwc->nollp =
1645 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1646 channel_writel(dwc, LLP, 0);
1647 }
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001648 }
1649
Andy Shevchenko11f932e2012-06-19 13:34:06 +03001650 /* Clear all interrupts on all channels. */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001651 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
Andy Shevchenko236b1062012-06-19 13:34:07 +03001652 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001653 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1654 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1655 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1656
Andy Shevchenkodf5c7382015-10-13 20:09:19 +03001657 /* Set capabilities */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001658 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
Jamie Iles95ea7592011-01-21 14:11:54 +00001659 if (pdata->is_private)
1660 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
Andy Shevchenkodf5c7382015-10-13 20:09:19 +03001661 if (pdata->is_memcpy)
1662 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1663
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001664 dw->dma.dev = chip->dev;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001665 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1666 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1667
1668 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001669 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
Andy Shevchenko029a40e2015-01-02 16:17:24 +02001670
Maxime Riparda4b0d342014-11-17 14:42:12 +01001671 dw->dma.device_config = dwc_config;
1672 dw->dma.device_pause = dwc_pause;
1673 dw->dma.device_resume = dwc_resume;
1674 dw->dma.device_terminate_all = dwc_terminate_all;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001675
Linus Walleij07934482010-03-26 16:50:49 -07001676 dw->dma.device_tx_status = dwc_tx_status;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001677 dw->dma.device_issue_pending = dwc_issue_pending;
1678
Andy Shevchenko029a40e2015-01-02 16:17:24 +02001679 /* DMA capabilities */
1680 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1681 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1682 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1683 BIT(DMA_MEM_TO_MEM);
1684 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1685
Andy Shevchenko12229342014-05-08 12:01:50 +03001686 err = dma_async_device_register(&dw->dma);
1687 if (err)
1688 goto err_dma_register;
1689
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001690 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
Andy Shevchenko30cb2632015-10-13 20:09:17 +03001691 pdata->nr_channels);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001692
Andy Shevchenkobb32baf2014-11-05 18:34:48 +02001693 pm_runtime_put_sync_suspend(chip->dev);
1694
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001695 return 0;
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001696
Andy Shevchenko12229342014-05-08 12:01:50 +03001697err_dma_register:
1698 free_irq(chip->irq, dw);
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001699err_pdata:
Andy Shevchenkobb32baf2014-11-05 18:34:48 +02001700 pm_runtime_put_sync_suspend(chip->dev);
Andy Shevchenko8be4f522014-05-08 12:01:49 +03001701 return err;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001702}
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001703EXPORT_SYMBOL_GPL(dw_dma_probe);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001704
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001705int dw_dma_remove(struct dw_dma_chip *chip)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001706{
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001707 struct dw_dma *dw = chip->dw;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001708 struct dw_dma_chan *dwc, *_dwc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001709
Andy Shevchenkobb32baf2014-11-05 18:34:48 +02001710 pm_runtime_get_sync(chip->dev);
1711
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001712 dw_dma_off(dw);
1713 dma_async_device_unregister(&dw->dma);
1714
Andy Shevchenko97977f72014-05-07 10:56:24 +03001715 free_irq(chip->irq, dw);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001716 tasklet_kill(&dw->tasklet);
1717
1718 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1719 chan.device_node) {
1720 list_del(&dwc->chan.device_node);
1721 channel_clear_bit(dw, CH_EN, dwc->mask);
1722 }
1723
Andy Shevchenkobb32baf2014-11-05 18:34:48 +02001724 pm_runtime_put_sync_suspend(chip->dev);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001725 return 0;
1726}
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001727EXPORT_SYMBOL_GPL(dw_dma_remove);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001728
Andy Shevchenko2540f742014-09-23 17:18:13 +03001729int dw_dma_disable(struct dw_dma_chip *chip)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001730{
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001731 struct dw_dma *dw = chip->dw;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001732
Andy Shevchenko6168d562012-10-18 17:34:10 +03001733 dw_dma_off(dw);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001734 return 0;
1735}
Andy Shevchenko2540f742014-09-23 17:18:13 +03001736EXPORT_SYMBOL_GPL(dw_dma_disable);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001737
Andy Shevchenko2540f742014-09-23 17:18:13 +03001738int dw_dma_enable(struct dw_dma_chip *chip)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001739{
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001740 struct dw_dma *dw = chip->dw;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001741
Andy Shevchenko7a83c042014-09-23 17:18:12 +03001742 dw_dma_on(dw);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001743 return 0;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001744}
Andy Shevchenko2540f742014-09-23 17:18:13 +03001745EXPORT_SYMBOL_GPL(dw_dma_enable);
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001746
1747MODULE_LICENSE("GPL v2");
Andy Shevchenko9cade1a2013-06-05 15:26:45 +03001748MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
Jean Delvaree05503e2011-05-18 16:49:24 +02001749MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Viresh Kumarda899472015-07-17 16:23:50 -07001750MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");