Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1 | /* |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007-2008 Atmel Corporation |
Viresh Kumar | aecb7b6 | 2011-05-24 14:04:09 +0530 | [diff] [blame] | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 6 | * Copyright (C) 2013 Intel Corporation |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 12 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 13 | #include <linux/bitops.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 14 | #include <linux/delay.h> |
| 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/dma-mapping.h> |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 17 | #include <linux/dmapool.h> |
Thierry Reding | 7331205 | 2013-01-21 11:09:00 +0100 | [diff] [blame] | 18 | #include <linux/err.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 19 | #include <linux/init.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/mm.h> |
| 23 | #include <linux/module.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 25 | #include <linux/pm_runtime.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 26 | |
Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 27 | #include "../dmaengine.h" |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 28 | #include "internal.h" |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", |
| 32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all |
| 33 | * of which use ARM any more). See the "Databook" from Synopsys for |
| 34 | * information beyond what licensees probably provide. |
| 35 | * |
Andy Shevchenko | dd5720b | 2014-02-12 11:16:17 +0200 | [diff] [blame] | 36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
| 37 | * support descriptor writeback. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 38 | */ |
| 39 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
| 42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 45 | DW_DMA_MSIZE_16; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 47 | DW_DMA_MSIZE_16; \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 48 | \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 49 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
| 50 | | DWC_CTLL_SRC_MSIZE(_smsize) \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 51 | | DWC_CTLL_LLP_D_EN \ |
| 52 | | DWC_CTLL_LLP_S_EN \ |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 53 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
| 54 | | DWC_CTLL_SMS(_dwc->src_master)); \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 55 | }) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 56 | |
| 57 | /* |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 58 | * Number of descriptors to allocate for each channel. This should be |
| 59 | * made configurable somehow; preferably, the clients (at least the |
| 60 | * ones using slave transfers) should be able to give us a hint. |
| 61 | */ |
| 62 | #define NR_DESCS_PER_CHANNEL 64 |
| 63 | |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 64 | /* The set of bus widths supported by the DMA controller */ |
| 65 | #define DW_DMA_BUSWIDTHS \ |
| 66 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ |
| 67 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
| 68 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
| 69 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
| 70 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 71 | /*----------------------------------------------------------------------*/ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 72 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 73 | static struct device *chan2dev(struct dma_chan *chan) |
| 74 | { |
| 75 | return &chan->dev->device; |
| 76 | } |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 77 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 78 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
| 79 | { |
Andy Shevchenko | e63a47a | 2012-10-18 17:34:12 +0300 | [diff] [blame] | 80 | return to_dw_desc(dwc->active_list.next); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 81 | } |
| 82 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 83 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
| 84 | { |
| 85 | struct dw_desc *desc, *_desc; |
| 86 | struct dw_desc *ret = NULL; |
| 87 | unsigned int i = 0; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 88 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 89 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 90 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 91 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
Andy Shevchenko | 2ab3727 | 2012-06-19 13:34:04 +0300 | [diff] [blame] | 92 | i++; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 93 | if (async_tx_test_ack(&desc->txd)) { |
| 94 | list_del(&desc->desc_node); |
| 95 | ret = desc; |
| 96 | break; |
| 97 | } |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 98 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 99 | } |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 100 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 101 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 102 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 103 | |
| 104 | return ret; |
| 105 | } |
| 106 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 107 | /* |
| 108 | * Move a descriptor, including any children, to the free list. |
| 109 | * `desc' must not be on any lists. |
| 110 | */ |
| 111 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
| 112 | { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 113 | unsigned long flags; |
| 114 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 115 | if (desc) { |
| 116 | struct dw_desc *child; |
| 117 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 118 | spin_lock_irqsave(&dwc->lock, flags); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 119 | list_for_each_entry(child, &desc->tx_list, desc_node) |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 120 | dev_vdbg(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 121 | "moving child desc %p to freelist\n", |
| 122 | child); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 123 | list_splice_init(&desc->tx_list, &dwc->free_list); |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 124 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 125 | list_add(&desc->desc_node, &dwc->free_list); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 126 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 127 | } |
| 128 | } |
| 129 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 130 | static void dwc_initialize(struct dw_dma_chan *dwc) |
| 131 | { |
| 132 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 133 | struct dw_dma_slave *dws = dwc->chan.private; |
| 134 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
| 135 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); |
| 136 | |
| 137 | if (dwc->initialized == true) |
| 138 | return; |
| 139 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 140 | if (dws) { |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 141 | /* |
| 142 | * We need controller-specific data to set up slave |
| 143 | * transfers. |
| 144 | */ |
| 145 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
| 146 | |
Andy Shevchenko | 7e1e2f2 | 2014-08-19 20:29:14 +0300 | [diff] [blame] | 147 | cfghi |= DWC_CFGH_DST_PER(dws->dst_id); |
| 148 | cfghi |= DWC_CFGH_SRC_PER(dws->src_id); |
Andy Shevchenko | 8fccc5b | 2012-09-03 13:46:19 +0300 | [diff] [blame] | 149 | } else { |
Andy Shevchenko | 8950052 | 2014-08-19 20:29:15 +0300 | [diff] [blame] | 150 | cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); |
| 151 | cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | channel_writel(dwc, CFG_LO, cfglo); |
| 155 | channel_writel(dwc, CFG_HI, cfghi); |
| 156 | |
| 157 | /* Enable interrupts */ |
| 158 | channel_set_bit(dw, MASK.XFER, dwc->mask); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 159 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
| 160 | |
| 161 | dwc->initialized = true; |
| 162 | } |
| 163 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 164 | /*----------------------------------------------------------------------*/ |
| 165 | |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 166 | static inline unsigned int dwc_fast_ffs(unsigned long long v) |
Andy Shevchenko | 4c2d56c | 2012-06-19 13:34:08 +0300 | [diff] [blame] | 167 | { |
| 168 | /* |
| 169 | * We can be a lot more clever here, but this should take care |
| 170 | * of the most common optimization. |
| 171 | */ |
| 172 | if (!(v & 7)) |
| 173 | return 3; |
| 174 | else if (!(v & 3)) |
| 175 | return 2; |
| 176 | else if (!(v & 1)) |
| 177 | return 1; |
| 178 | return 0; |
| 179 | } |
| 180 | |
Andy Shevchenko | f52b36d | 2012-09-21 15:05:44 +0300 | [diff] [blame] | 181 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 182 | { |
| 183 | dev_err(chan2dev(&dwc->chan), |
| 184 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
| 185 | channel_readl(dwc, SAR), |
| 186 | channel_readl(dwc, DAR), |
| 187 | channel_readl(dwc, LLP), |
| 188 | channel_readl(dwc, CTL_HI), |
| 189 | channel_readl(dwc, CTL_LO)); |
| 190 | } |
| 191 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 192 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 193 | { |
| 194 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 195 | while (dma_readl(dw, CH_EN) & dwc->mask) |
| 196 | cpu_relax(); |
| 197 | } |
| 198 | |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 199 | /*----------------------------------------------------------------------*/ |
| 200 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 201 | /* Perform single block transfer */ |
| 202 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, |
| 203 | struct dw_desc *desc) |
| 204 | { |
| 205 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 206 | u32 ctllo; |
| 207 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 208 | /* |
| 209 | * Software emulation of LLP mode relies on interrupts to continue |
| 210 | * multi block transfer. |
| 211 | */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 212 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
| 213 | |
| 214 | channel_writel(dwc, SAR, desc->lli.sar); |
| 215 | channel_writel(dwc, DAR, desc->lli.dar); |
| 216 | channel_writel(dwc, CTL_LO, ctllo); |
| 217 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); |
| 218 | channel_set_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 219 | |
| 220 | /* Move pointer to next descriptor */ |
| 221 | dwc->tx_node_active = dwc->tx_node_active->next; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 222 | } |
| 223 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 224 | /* Called with dwc->lock held and bh disabled */ |
| 225 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) |
| 226 | { |
| 227 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 228 | unsigned long was_soft_llp; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 229 | |
| 230 | /* ASSERT: channel is idle */ |
| 231 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 232 | dev_err(chan2dev(&dwc->chan), |
Jarkko Nikula | 550da64 | 2015-03-10 11:37:23 +0200 | [diff] [blame] | 233 | "%s: BUG: Attempted to start non-idle channel\n", |
| 234 | __func__); |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 235 | dwc_dump_chan_regs(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 236 | |
| 237 | /* The tasklet will hopefully advance the queue... */ |
| 238 | return; |
| 239 | } |
| 240 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 241 | if (dwc->nollp) { |
| 242 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, |
| 243 | &dwc->flags); |
| 244 | if (was_soft_llp) { |
| 245 | dev_err(chan2dev(&dwc->chan), |
Andy Shevchenko | fc61f6b | 2014-01-13 14:04:49 +0200 | [diff] [blame] | 246 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 247 | return; |
| 248 | } |
| 249 | |
| 250 | dwc_initialize(dwc); |
| 251 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 252 | dwc->residue = first->total_len; |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 253 | dwc->tx_node_active = &first->tx_list; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 254 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 255 | /* Submit first block */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 256 | dwc_do_single_block(dwc, first); |
| 257 | |
| 258 | return; |
| 259 | } |
| 260 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 261 | dwc_initialize(dwc); |
| 262 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 263 | channel_writel(dwc, LLP, first->txd.phys); |
| 264 | channel_writel(dwc, CTL_LO, |
| 265 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
| 266 | channel_writel(dwc, CTL_HI, 0); |
| 267 | channel_set_bit(dw, CH_EN, dwc->mask); |
| 268 | } |
| 269 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 270 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
| 271 | { |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 272 | struct dw_desc *desc; |
| 273 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 274 | if (list_empty(&dwc->queue)) |
| 275 | return; |
| 276 | |
| 277 | list_move(dwc->queue.next, &dwc->active_list); |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 278 | desc = dwc_first_active(dwc); |
| 279 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); |
| 280 | dwc_dostart(dwc, desc); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 281 | } |
| 282 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 283 | /*----------------------------------------------------------------------*/ |
| 284 | |
| 285 | static void |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 286 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
| 287 | bool callback_required) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 288 | { |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 289 | dma_async_tx_callback callback = NULL; |
| 290 | void *param = NULL; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 291 | struct dma_async_tx_descriptor *txd = &desc->txd; |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 292 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 293 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 294 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 295 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 296 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 297 | spin_lock_irqsave(&dwc->lock, flags); |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 298 | dma_cookie_complete(txd); |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 299 | if (callback_required) { |
| 300 | callback = txd->callback; |
| 301 | param = txd->callback_param; |
| 302 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 303 | |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 304 | /* async_tx_ack */ |
| 305 | list_for_each_entry(child, &desc->tx_list, desc_node) |
| 306 | async_tx_ack(&child->txd); |
| 307 | async_tx_ack(&desc->txd); |
| 308 | |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 309 | list_splice_init(&desc->tx_list, &dwc->free_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 310 | list_move(&desc->desc_node, &dwc->free_list); |
| 311 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 312 | dma_descriptor_unmap(txd); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 313 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 314 | |
Andy Shevchenko | 21e93c1 | 2013-01-09 10:17:12 +0200 | [diff] [blame] | 315 | if (callback) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 316 | callback(param); |
| 317 | } |
| 318 | |
| 319 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 320 | { |
| 321 | struct dw_desc *desc, *_desc; |
| 322 | LIST_HEAD(list); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 323 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 324 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 325 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 326 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 327 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 328 | "BUG: XFER bit set, but channel not idle!\n"); |
| 329 | |
| 330 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 331 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | /* |
| 335 | * Submit queued descriptors ASAP, i.e. before we go through |
| 336 | * the completed ones. |
| 337 | */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 338 | list_splice_init(&dwc->active_list, &list); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 339 | dwc_dostart_first_queued(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 340 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 341 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 342 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 343 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 344 | dwc_descriptor_complete(dwc, desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 345 | } |
| 346 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 347 | /* Returns how many bytes were already received from source */ |
| 348 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) |
| 349 | { |
| 350 | u32 ctlhi = channel_readl(dwc, CTL_HI); |
| 351 | u32 ctllo = channel_readl(dwc, CTL_LO); |
| 352 | |
| 353 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); |
| 354 | } |
| 355 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 356 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 357 | { |
| 358 | dma_addr_t llp; |
| 359 | struct dw_desc *desc, *_desc; |
| 360 | struct dw_desc *child; |
| 361 | u32 status_xfer; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 362 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 363 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 364 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 365 | llp = channel_readl(dwc, LLP); |
| 366 | status_xfer = dma_readl(dw, RAW.XFER); |
| 367 | |
| 368 | if (status_xfer & dwc->mask) { |
| 369 | /* Everything we've submitted is done */ |
| 370 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 371 | |
| 372 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 373 | struct list_head *head, *active = dwc->tx_node_active; |
| 374 | |
| 375 | /* |
| 376 | * We are inside first active descriptor. |
| 377 | * Otherwise something is really wrong. |
| 378 | */ |
| 379 | desc = dwc_first_active(dwc); |
| 380 | |
| 381 | head = &desc->tx_list; |
| 382 | if (active != head) { |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 383 | /* Update desc to reflect last sent one */ |
| 384 | if (active != head->next) |
| 385 | desc = to_dw_desc(active->prev); |
| 386 | |
| 387 | dwc->residue -= desc->len; |
| 388 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 389 | child = to_dw_desc(active); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 390 | |
| 391 | /* Submit next block */ |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 392 | dwc_do_single_block(dwc, child); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 393 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 394 | spin_unlock_irqrestore(&dwc->lock, flags); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 395 | return; |
| 396 | } |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 397 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 398 | /* We are done here */ |
| 399 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
| 400 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 401 | |
| 402 | dwc->residue = 0; |
| 403 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 404 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 405 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 406 | dwc_complete_all(dw, dwc); |
| 407 | return; |
| 408 | } |
| 409 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 410 | if (list_empty(&dwc->active_list)) { |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 411 | dwc->residue = 0; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 412 | spin_unlock_irqrestore(&dwc->lock, flags); |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 413 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 414 | } |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 415 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 416 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
| 417 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 418 | spin_unlock_irqrestore(&dwc->lock, flags); |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 419 | return; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 420 | } |
| 421 | |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 422 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 423 | |
| 424 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 425 | /* Initial residue value */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 426 | dwc->residue = desc->total_len; |
| 427 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 428 | /* Check first descriptors addr */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 429 | if (desc->txd.phys == llp) { |
| 430 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 431 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 432 | } |
Viresh Kumar | 84adccf | 2011-03-24 11:32:15 +0530 | [diff] [blame] | 433 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 434 | /* Check first descriptors llp */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 435 | if (desc->lli.llp == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 436 | /* This one is currently in progress */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 437 | dwc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 438 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 439 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 440 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 441 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 442 | dwc->residue -= desc->len; |
| 443 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 444 | if (child->lli.llp == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 445 | /* Currently in progress */ |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 446 | dwc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 447 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 448 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 449 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 450 | dwc->residue -= child->len; |
| 451 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 452 | |
| 453 | /* |
| 454 | * No descriptors so far seem to be in progress, i.e. |
| 455 | * this one must be done. |
| 456 | */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 458 | dwc_descriptor_complete(dwc, desc, true); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 459 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 460 | } |
| 461 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 462 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 463 | "BUG: All descriptors done, but channel not idle!\n"); |
| 464 | |
| 465 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 466 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 467 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 468 | dwc_dostart_first_queued(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 469 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 470 | } |
| 471 | |
Andy Shevchenko | 93aad1b | 2012-07-13 11:09:32 +0300 | [diff] [blame] | 472 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 473 | { |
Andy Shevchenko | 21d43f4 | 2012-10-18 17:34:09 +0300 | [diff] [blame] | 474 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
| 475 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 479 | { |
| 480 | struct dw_desc *bad_desc; |
| 481 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 482 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 483 | |
| 484 | dwc_scan_descriptors(dw, dwc); |
| 485 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 486 | spin_lock_irqsave(&dwc->lock, flags); |
| 487 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 488 | /* |
| 489 | * The descriptor currently at the head of the active list is |
| 490 | * borked. Since we don't have any way to report errors, we'll |
| 491 | * just have to scream loudly and try to carry on. |
| 492 | */ |
| 493 | bad_desc = dwc_first_active(dwc); |
| 494 | list_del_init(&bad_desc->desc_node); |
Viresh Kumar | f336e42 | 2011-03-03 15:47:16 +0530 | [diff] [blame] | 495 | list_move(dwc->queue.next, dwc->active_list.prev); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 496 | |
| 497 | /* Clear the error flag and try to restart the controller */ |
| 498 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 499 | if (!list_empty(&dwc->active_list)) |
| 500 | dwc_dostart(dwc, dwc_first_active(dwc)); |
| 501 | |
| 502 | /* |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 503 | * WARN may seem harsh, but since this only happens |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 504 | * when someone submits a bad physical address in a |
| 505 | * descriptor, we should consider ourselves lucky that the |
| 506 | * controller flagged an error instead of scribbling over |
| 507 | * random memory locations. |
| 508 | */ |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 509 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
| 510 | " cookie: %d\n", bad_desc->txd.cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 511 | dwc_dump_lli(dwc, &bad_desc->lli); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 512 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 513 | dwc_dump_lli(dwc, &child->lli); |
| 514 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 515 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 516 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 517 | /* Pretend the descriptor completed successfully */ |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 518 | dwc_descriptor_complete(dwc, bad_desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 519 | } |
| 520 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 521 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
| 522 | |
Denis Efremov | 8004cbb | 2013-05-09 13:19:40 +0400 | [diff] [blame] | 523 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 524 | { |
| 525 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 526 | return channel_readl(dwc, SAR); |
| 527 | } |
| 528 | EXPORT_SYMBOL(dw_dma_get_src_addr); |
| 529 | |
Denis Efremov | 8004cbb | 2013-05-09 13:19:40 +0400 | [diff] [blame] | 530 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 531 | { |
| 532 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 533 | return channel_readl(dwc, DAR); |
| 534 | } |
| 535 | EXPORT_SYMBOL(dw_dma_get_dst_addr); |
| 536 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 537 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 538 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 539 | u32 status_err, u32 status_xfer) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 540 | { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 541 | unsigned long flags; |
| 542 | |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 543 | if (dwc->mask) { |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 544 | void (*callback)(void *param); |
| 545 | void *callback_param; |
| 546 | |
| 547 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", |
| 548 | channel_readl(dwc, LLP)); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 549 | |
| 550 | callback = dwc->cdesc->period_callback; |
| 551 | callback_param = dwc->cdesc->period_callback_param; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 552 | |
| 553 | if (callback) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 554 | callback(callback_param); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 555 | } |
| 556 | |
| 557 | /* |
| 558 | * Error and transfer complete are highly unlikely, and will most |
| 559 | * likely be due to a configuration error by the user. |
| 560 | */ |
| 561 | if (unlikely(status_err & dwc->mask) || |
| 562 | unlikely(status_xfer & dwc->mask)) { |
| 563 | int i; |
| 564 | |
Andy Shevchenko | fc61f6b | 2014-01-13 14:04:49 +0200 | [diff] [blame] | 565 | dev_err(chan2dev(&dwc->chan), |
| 566 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", |
| 567 | status_xfer ? "xfer" : "error"); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 568 | |
| 569 | spin_lock_irqsave(&dwc->lock, flags); |
| 570 | |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 571 | dwc_dump_chan_regs(dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 572 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 573 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 574 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 575 | /* Make sure DMA does not restart by loading a new list */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 576 | channel_writel(dwc, LLP, 0); |
| 577 | channel_writel(dwc, CTL_LO, 0); |
| 578 | channel_writel(dwc, CTL_HI, 0); |
| 579 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 580 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 581 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 582 | |
| 583 | for (i = 0; i < dwc->cdesc->periods; i++) |
| 584 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 585 | |
| 586 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 587 | } |
| 588 | } |
| 589 | |
| 590 | /* ------------------------------------------------------------------------- */ |
| 591 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 592 | static void dw_dma_tasklet(unsigned long data) |
| 593 | { |
| 594 | struct dw_dma *dw = (struct dw_dma *)data; |
| 595 | struct dw_dma_chan *dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 596 | u32 status_xfer; |
| 597 | u32 status_err; |
| 598 | int i; |
| 599 | |
Haavard Skinnemoen | 7fe7b2f | 2008-10-03 15:23:46 -0700 | [diff] [blame] | 600 | status_xfer = dma_readl(dw, RAW.XFER); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 601 | status_err = dma_readl(dw, RAW.ERROR); |
| 602 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 603 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 604 | |
| 605 | for (i = 0; i < dw->dma.chancnt; i++) { |
| 606 | dwc = &dw->chan[i]; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 607 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 608 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 609 | else if (status_err & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 610 | dwc_handle_error(dw, dwc); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 611 | else if (status_xfer & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 612 | dwc_scan_descriptors(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | /* |
Viresh Kumar | ff7b05f | 2012-02-01 16:12:23 +0530 | [diff] [blame] | 616 | * Re-enable interrupts. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 617 | */ |
| 618 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 619 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 620 | } |
| 621 | |
| 622 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) |
| 623 | { |
| 624 | struct dw_dma *dw = dev_id; |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 625 | u32 status = dma_readl(dw, STATUS_INT); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 626 | |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 627 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
| 628 | |
| 629 | /* Check if we have any interrupt from the DMAC */ |
Jie Yang | 94b3eed | 2015-03-05 14:08:08 +0800 | [diff] [blame] | 630 | if (!status || !dw->in_use) |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 631 | return IRQ_NONE; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 632 | |
| 633 | /* |
| 634 | * Just disable the interrupts. We'll turn them back on in the |
| 635 | * softirq handler. |
| 636 | */ |
| 637 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 638 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 639 | |
| 640 | status = dma_readl(dw, STATUS_INT); |
| 641 | if (status) { |
| 642 | dev_err(dw->dma.dev, |
| 643 | "BUG: Unexpected interrupts pending: 0x%x\n", |
| 644 | status); |
| 645 | |
| 646 | /* Try to recover */ |
| 647 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 648 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
| 649 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); |
| 650 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); |
| 651 | } |
| 652 | |
| 653 | tasklet_schedule(&dw->tasklet); |
| 654 | |
| 655 | return IRQ_HANDLED; |
| 656 | } |
| 657 | |
| 658 | /*----------------------------------------------------------------------*/ |
| 659 | |
| 660 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
| 661 | { |
| 662 | struct dw_desc *desc = txd_to_dw_desc(tx); |
| 663 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); |
| 664 | dma_cookie_t cookie; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 665 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 666 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 667 | spin_lock_irqsave(&dwc->lock, flags); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 668 | cookie = dma_cookie_assign(tx); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 669 | |
| 670 | /* |
| 671 | * REVISIT: We should attempt to chain as many descriptors as |
| 672 | * possible, perhaps even appending to those already submitted |
| 673 | * for DMA. But this is hard to do in a race-free manner. |
| 674 | */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 675 | |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 676 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
| 677 | list_add_tail(&desc->desc_node, &dwc->queue); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 678 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 679 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 680 | |
| 681 | return cookie; |
| 682 | } |
| 683 | |
| 684 | static struct dma_async_tx_descriptor * |
| 685 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 686 | size_t len, unsigned long flags) |
| 687 | { |
| 688 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 689 | struct dw_dma *dw = to_dw_dma(chan->device); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 690 | struct dw_desc *desc; |
| 691 | struct dw_desc *first; |
| 692 | struct dw_desc *prev; |
| 693 | size_t xfer_count; |
| 694 | size_t offset; |
| 695 | unsigned int src_width; |
| 696 | unsigned int dst_width; |
Andy Shevchenko | 3d4f860 | 2012-10-01 13:06:25 +0300 | [diff] [blame] | 697 | unsigned int data_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 698 | u32 ctllo; |
| 699 | |
Andy Shevchenko | 2f45d61 | 2012-06-19 13:34:02 +0300 | [diff] [blame] | 700 | dev_vdbg(chan2dev(chan), |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 701 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
| 702 | &dest, &src, len, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 703 | |
| 704 | if (unlikely(!len)) { |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 705 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 706 | return NULL; |
| 707 | } |
| 708 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 709 | dwc->direction = DMA_MEM_TO_MEM; |
| 710 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 711 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
| 712 | dw->data_width[dwc->dst_master]); |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 713 | |
Andy Shevchenko | 3d4f860 | 2012-10-01 13:06:25 +0300 | [diff] [blame] | 714 | src_width = dst_width = min_t(unsigned int, data_width, |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 715 | dwc_fast_ffs(src | dest | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 716 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 717 | ctllo = DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 718 | | DWC_CTLL_DST_WIDTH(dst_width) |
| 719 | | DWC_CTLL_SRC_WIDTH(src_width) |
| 720 | | DWC_CTLL_DST_INC |
| 721 | | DWC_CTLL_SRC_INC |
| 722 | | DWC_CTLL_FC_M2M; |
| 723 | prev = first = NULL; |
| 724 | |
| 725 | for (offset = 0; offset < len; offset += xfer_count << src_width) { |
| 726 | xfer_count = min_t(size_t, (len - offset) >> src_width, |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 727 | dwc->block_size); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 728 | |
| 729 | desc = dwc_desc_get(dwc); |
| 730 | if (!desc) |
| 731 | goto err_desc_get; |
| 732 | |
| 733 | desc->lli.sar = src + offset; |
| 734 | desc->lli.dar = dest + offset; |
| 735 | desc->lli.ctllo = ctllo; |
| 736 | desc->lli.ctlhi = xfer_count; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 737 | desc->len = xfer_count << src_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 738 | |
| 739 | if (!first) { |
| 740 | first = desc; |
| 741 | } else { |
| 742 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 743 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 744 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 745 | } |
| 746 | prev = desc; |
| 747 | } |
| 748 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 749 | if (flags & DMA_PREP_INTERRUPT) |
| 750 | /* Trigger interrupt after last block */ |
| 751 | prev->lli.ctllo |= DWC_CTLL_INT_EN; |
| 752 | |
| 753 | prev->lli.llp = 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 754 | first->txd.flags = flags; |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 755 | first->total_len = len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 756 | |
| 757 | return &first->txd; |
| 758 | |
| 759 | err_desc_get: |
| 760 | dwc_desc_put(dwc, first); |
| 761 | return NULL; |
| 762 | } |
| 763 | |
| 764 | static struct dma_async_tx_descriptor * |
| 765 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 766 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 767 | unsigned long flags, void *context) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 768 | { |
| 769 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 770 | struct dw_dma *dw = to_dw_dma(chan->device); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 771 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 772 | struct dw_desc *prev; |
| 773 | struct dw_desc *first; |
| 774 | u32 ctllo; |
| 775 | dma_addr_t reg; |
| 776 | unsigned int reg_width; |
| 777 | unsigned int mem_width; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 778 | unsigned int data_width; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 779 | unsigned int i; |
| 780 | struct scatterlist *sg; |
| 781 | size_t total_len = 0; |
| 782 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 783 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 784 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 785 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 786 | return NULL; |
| 787 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 788 | dwc->direction = direction; |
| 789 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 790 | prev = first = NULL; |
| 791 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 792 | switch (direction) { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 793 | case DMA_MEM_TO_DEV: |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 794 | reg_width = __ffs(sconfig->dst_addr_width); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 795 | reg = sconfig->dst_addr; |
| 796 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 797 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 798 | | DWC_CTLL_DST_FIX |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 799 | | DWC_CTLL_SRC_INC); |
| 800 | |
| 801 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
| 802 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
| 803 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 804 | data_width = dw->data_width[dwc->src_master]; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 805 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 806 | for_each_sg(sgl, sg, sg_len, i) { |
| 807 | struct dw_desc *desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 808 | u32 len, dlen, mem; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 809 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 810 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 811 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 812 | |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 813 | mem_width = min_t(unsigned int, |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 814 | data_width, dwc_fast_ffs(mem | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 815 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 816 | slave_sg_todev_fill_desc: |
| 817 | desc = dwc_desc_get(dwc); |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 818 | if (!desc) |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 819 | goto err_desc_get; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 820 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 821 | desc->lli.sar = mem; |
| 822 | desc->lli.dar = reg; |
| 823 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 824 | if ((len >> mem_width) > dwc->block_size) { |
| 825 | dlen = dwc->block_size << mem_width; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 826 | mem += dlen; |
| 827 | len -= dlen; |
| 828 | } else { |
| 829 | dlen = len; |
| 830 | len = 0; |
| 831 | } |
| 832 | |
| 833 | desc->lli.ctlhi = dlen >> mem_width; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 834 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 835 | |
| 836 | if (!first) { |
| 837 | first = desc; |
| 838 | } else { |
| 839 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 840 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 841 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 842 | } |
| 843 | prev = desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 844 | total_len += dlen; |
| 845 | |
| 846 | if (len) |
| 847 | goto slave_sg_todev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 848 | } |
| 849 | break; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 850 | case DMA_DEV_TO_MEM: |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 851 | reg_width = __ffs(sconfig->src_addr_width); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 852 | reg = sconfig->src_addr; |
| 853 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 854 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 855 | | DWC_CTLL_DST_INC |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 856 | | DWC_CTLL_SRC_FIX); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 857 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 858 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
| 859 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
| 860 | |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 861 | data_width = dw->data_width[dwc->dst_master]; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 862 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 863 | for_each_sg(sgl, sg, sg_len, i) { |
| 864 | struct dw_desc *desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 865 | u32 len, dlen, mem; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 866 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 867 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 868 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 869 | |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 870 | mem_width = min_t(unsigned int, |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 871 | data_width, dwc_fast_ffs(mem | len)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 872 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 873 | slave_sg_fromdev_fill_desc: |
| 874 | desc = dwc_desc_get(dwc); |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 875 | if (!desc) |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 876 | goto err_desc_get; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 877 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 878 | desc->lli.sar = reg; |
| 879 | desc->lli.dar = mem; |
| 880 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 881 | if ((len >> reg_width) > dwc->block_size) { |
| 882 | dlen = dwc->block_size << reg_width; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 883 | mem += dlen; |
| 884 | len -= dlen; |
| 885 | } else { |
| 886 | dlen = len; |
| 887 | len = 0; |
| 888 | } |
| 889 | desc->lli.ctlhi = dlen >> reg_width; |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 890 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 891 | |
| 892 | if (!first) { |
| 893 | first = desc; |
| 894 | } else { |
| 895 | prev->lli.llp = desc->txd.phys; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 896 | list_add_tail(&desc->desc_node, |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 897 | &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 898 | } |
| 899 | prev = desc; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 900 | total_len += dlen; |
| 901 | |
| 902 | if (len) |
| 903 | goto slave_sg_fromdev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 904 | } |
| 905 | break; |
| 906 | default: |
| 907 | return NULL; |
| 908 | } |
| 909 | |
| 910 | if (flags & DMA_PREP_INTERRUPT) |
| 911 | /* Trigger interrupt after last block */ |
| 912 | prev->lli.ctllo |= DWC_CTLL_INT_EN; |
| 913 | |
| 914 | prev->lli.llp = 0; |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 915 | first->total_len = total_len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 916 | |
| 917 | return &first->txd; |
| 918 | |
| 919 | err_desc_get: |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 920 | dev_err(chan2dev(chan), |
| 921 | "not enough descriptors available. Direction %d\n", direction); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 922 | dwc_desc_put(dwc, first); |
| 923 | return NULL; |
| 924 | } |
| 925 | |
Andy Shevchenko | 4d130de | 2014-08-19 20:29:16 +0300 | [diff] [blame] | 926 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
| 927 | { |
| 928 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 929 | struct dw_dma_slave *dws = param; |
| 930 | |
| 931 | if (!dws || dws->dma_dev != chan->device->dev) |
| 932 | return false; |
| 933 | |
| 934 | /* We have to copy data since dws can be temporary storage */ |
| 935 | |
| 936 | dwc->src_id = dws->src_id; |
| 937 | dwc->dst_id = dws->dst_id; |
| 938 | |
| 939 | dwc->src_master = dws->src_master; |
| 940 | dwc->dst_master = dws->dst_master; |
| 941 | |
| 942 | return true; |
| 943 | } |
| 944 | EXPORT_SYMBOL_GPL(dw_dma_filter); |
| 945 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 946 | /* |
| 947 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: |
| 948 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. |
| 949 | * |
| 950 | * NOTE: burst size 2 is not supported by controller. |
| 951 | * |
| 952 | * This can be done by finding least significant bit set: n & (n - 1) |
| 953 | */ |
| 954 | static inline void convert_burst(u32 *maxburst) |
| 955 | { |
| 956 | if (*maxburst > 1) |
| 957 | *maxburst = fls(*maxburst) - 2; |
| 958 | else |
| 959 | *maxburst = 0; |
| 960 | } |
| 961 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 962 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 963 | { |
| 964 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 965 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 966 | /* Check if chan will be configured for slave transfers */ |
| 967 | if (!is_slave_direction(sconfig->direction)) |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 968 | return -EINVAL; |
| 969 | |
| 970 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 971 | dwc->direction = sconfig->direction; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 972 | |
| 973 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
| 974 | convert_burst(&dwc->dma_sconfig.dst_maxburst); |
| 975 | |
| 976 | return 0; |
| 977 | } |
| 978 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 979 | static int dwc_pause(struct dma_chan *chan) |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 980 | { |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 981 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 982 | unsigned long flags; |
| 983 | unsigned int count = 20; /* timeout iterations */ |
| 984 | u32 cfglo; |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 985 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 986 | spin_lock_irqsave(&dwc->lock, flags); |
| 987 | |
| 988 | cfglo = channel_readl(dwc, CFG_LO); |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 989 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
Andy Shevchenko | 123b69a | 2013-03-21 11:49:17 +0200 | [diff] [blame] | 990 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
| 991 | udelay(2); |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 992 | |
| 993 | dwc->paused = true; |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 994 | |
| 995 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 996 | |
| 997 | return 0; |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 998 | } |
| 999 | |
| 1000 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) |
| 1001 | { |
| 1002 | u32 cfglo = channel_readl(dwc, CFG_LO); |
| 1003 | |
| 1004 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); |
| 1005 | |
| 1006 | dwc->paused = false; |
| 1007 | } |
| 1008 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1009 | static int dwc_resume(struct dma_chan *chan) |
| 1010 | { |
| 1011 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1012 | unsigned long flags; |
| 1013 | |
| 1014 | if (!dwc->paused) |
| 1015 | return 0; |
| 1016 | |
| 1017 | spin_lock_irqsave(&dwc->lock, flags); |
| 1018 | |
| 1019 | dwc_chan_resume(dwc); |
| 1020 | |
| 1021 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1022 | |
| 1023 | return 0; |
| 1024 | } |
| 1025 | |
| 1026 | static int dwc_terminate_all(struct dma_chan *chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1027 | { |
| 1028 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1029 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1030 | struct dw_desc *desc, *_desc; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1031 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1032 | LIST_HEAD(list); |
| 1033 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1034 | spin_lock_irqsave(&dwc->lock, flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1035 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1036 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1037 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1038 | dwc_chan_disable(dw, dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1039 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1040 | dwc_chan_resume(dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1041 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1042 | /* active_list entries will end up before queued entries */ |
| 1043 | list_splice_init(&dwc->queue, &list); |
| 1044 | list_splice_init(&dwc->active_list, &list); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1045 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1046 | spin_unlock_irqrestore(&dwc->lock, flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1047 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1048 | /* Flush all pending and queued descriptors */ |
| 1049 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
| 1050 | dwc_descriptor_complete(dwc, desc, false); |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1051 | |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 1052 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1053 | } |
| 1054 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1055 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
| 1056 | { |
| 1057 | unsigned long flags; |
| 1058 | u32 residue; |
| 1059 | |
| 1060 | spin_lock_irqsave(&dwc->lock, flags); |
| 1061 | |
| 1062 | residue = dwc->residue; |
| 1063 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) |
| 1064 | residue -= dwc_get_sent(dwc); |
| 1065 | |
| 1066 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1067 | return residue; |
| 1068 | } |
| 1069 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1070 | static enum dma_status |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1071 | dwc_tx_status(struct dma_chan *chan, |
| 1072 | dma_cookie_t cookie, |
| 1073 | struct dma_tx_state *txstate) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1074 | { |
| 1075 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1076 | enum dma_status ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1077 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1078 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 2c40410 | 2013-10-16 13:41:15 +0530 | [diff] [blame] | 1079 | if (ret == DMA_COMPLETE) |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1080 | return ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1081 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1082 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1083 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1084 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 2c40410 | 2013-10-16 13:41:15 +0530 | [diff] [blame] | 1085 | if (ret != DMA_COMPLETE) |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1086 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1087 | |
Andy Shevchenko | effd5cf | 2013-07-15 15:04:41 +0300 | [diff] [blame] | 1088 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1089 | return DMA_PAUSED; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1090 | |
| 1091 | return ret; |
| 1092 | } |
| 1093 | |
| 1094 | static void dwc_issue_pending(struct dma_chan *chan) |
| 1095 | { |
| 1096 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1097 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1098 | |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1099 | spin_lock_irqsave(&dwc->lock, flags); |
| 1100 | if (list_empty(&dwc->active_list)) |
| 1101 | dwc_dostart_first_queued(dwc); |
| 1102 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1105 | /*----------------------------------------------------------------------*/ |
| 1106 | |
| 1107 | static void dw_dma_off(struct dw_dma *dw) |
| 1108 | { |
| 1109 | int i; |
| 1110 | |
| 1111 | dma_writel(dw, CFG, 0); |
| 1112 | |
| 1113 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
| 1114 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
| 1115 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); |
| 1116 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 1117 | |
| 1118 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) |
| 1119 | cpu_relax(); |
| 1120 | |
| 1121 | for (i = 0; i < dw->dma.chancnt; i++) |
| 1122 | dw->chan[i].initialized = false; |
| 1123 | } |
| 1124 | |
| 1125 | static void dw_dma_on(struct dw_dma *dw) |
| 1126 | { |
| 1127 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
| 1128 | } |
| 1129 | |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 1130 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1131 | { |
| 1132 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1133 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1134 | struct dw_desc *desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1135 | int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1136 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1137 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1138 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1139 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1140 | /* ASSERT: channel is idle */ |
| 1141 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 1142 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1143 | return -EIO; |
| 1144 | } |
| 1145 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1146 | dma_cookie_init(chan); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1147 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1148 | /* |
| 1149 | * NOTE: some controllers may have additional features that we |
| 1150 | * need to initialize here, like "scatter-gather" (which |
| 1151 | * doesn't mean what you think it means), and status writeback. |
| 1152 | */ |
| 1153 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1154 | /* Enable controller here if needed */ |
| 1155 | if (!dw->in_use) |
| 1156 | dw_dma_on(dw); |
| 1157 | dw->in_use |= dwc->mask; |
| 1158 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1159 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1160 | i = dwc->descs_allocated; |
| 1161 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1162 | dma_addr_t phys; |
| 1163 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1164 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1165 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1166 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1167 | if (!desc) |
| 1168 | goto err_desc_alloc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1169 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1170 | memset(desc, 0, sizeof(struct dw_desc)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1171 | |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 1172 | INIT_LIST_HEAD(&desc->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1173 | dma_async_tx_descriptor_init(&desc->txd, chan); |
| 1174 | desc->txd.tx_submit = dwc_tx_submit; |
| 1175 | desc->txd.flags = DMA_CTRL_ACK; |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1176 | desc->txd.phys = phys; |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1177 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1178 | dwc_desc_put(dwc, desc); |
| 1179 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1180 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1181 | i = ++dwc->descs_allocated; |
| 1182 | } |
| 1183 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1184 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1185 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1186 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1187 | |
| 1188 | return i; |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1189 | |
| 1190 | err_desc_alloc: |
Andy Shevchenko | cbd6531 | 2013-01-09 10:17:11 +0200 | [diff] [blame] | 1191 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
| 1192 | |
| 1193 | return i; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1194 | } |
| 1195 | |
| 1196 | static void dwc_free_chan_resources(struct dma_chan *chan) |
| 1197 | { |
| 1198 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1199 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 1200 | struct dw_desc *desc, *_desc; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1201 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1202 | LIST_HEAD(list); |
| 1203 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1204 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1205 | dwc->descs_allocated); |
| 1206 | |
| 1207 | /* ASSERT: channel is idle */ |
| 1208 | BUG_ON(!list_empty(&dwc->active_list)); |
| 1209 | BUG_ON(!list_empty(&dwc->queue)); |
| 1210 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); |
| 1211 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1212 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1213 | list_splice_init(&dwc->free_list, &list); |
| 1214 | dwc->descs_allocated = 0; |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 1215 | dwc->initialized = false; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1216 | |
| 1217 | /* Disable interrupts */ |
| 1218 | channel_clear_bit(dw, MASK.XFER, dwc->mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1219 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
| 1220 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1221 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1222 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1223 | /* Disable controller in case it was a last user */ |
| 1224 | dw->in_use &= ~dwc->mask; |
| 1225 | if (!dw->in_use) |
| 1226 | dw_dma_off(dw); |
| 1227 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1228 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 1229 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1230 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1231 | } |
| 1232 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1233 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1234 | } |
| 1235 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1236 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
| 1237 | |
| 1238 | /** |
| 1239 | * dw_dma_cyclic_start - start the cyclic DMA transfer |
| 1240 | * @chan: the DMA channel to start |
| 1241 | * |
| 1242 | * Must be called with soft interrupts disabled. Returns zero on success or |
| 1243 | * -errno on failure. |
| 1244 | */ |
| 1245 | int dw_dma_cyclic_start(struct dma_chan *chan) |
| 1246 | { |
| 1247 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1248 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1249 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1250 | |
| 1251 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { |
| 1252 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); |
| 1253 | return -ENODEV; |
| 1254 | } |
| 1255 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1256 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1257 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1258 | /* Assert channel is idle */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1259 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
| 1260 | dev_err(chan2dev(&dwc->chan), |
Jarkko Nikula | 550da64 | 2015-03-10 11:37:23 +0200 | [diff] [blame] | 1261 | "%s: BUG: Attempted to start non-idle channel\n", |
| 1262 | __func__); |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 1263 | dwc_dump_chan_regs(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1264 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1265 | return -EBUSY; |
| 1266 | } |
| 1267 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1268 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 1269 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 1270 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1271 | /* Setup DMAC channel registers */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1272 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
| 1273 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
| 1274 | channel_writel(dwc, CTL_HI, 0); |
| 1275 | |
| 1276 | channel_set_bit(dw, CH_EN, dwc->mask); |
| 1277 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1278 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | EXPORT_SYMBOL(dw_dma_cyclic_start); |
| 1283 | |
| 1284 | /** |
| 1285 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer |
| 1286 | * @chan: the DMA channel to stop |
| 1287 | * |
| 1288 | * Must be called with soft interrupts disabled. |
| 1289 | */ |
| 1290 | void dw_dma_cyclic_stop(struct dma_chan *chan) |
| 1291 | { |
| 1292 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1293 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1294 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1295 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1296 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1297 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 1298 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1299 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1300 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1301 | } |
| 1302 | EXPORT_SYMBOL(dw_dma_cyclic_stop); |
| 1303 | |
| 1304 | /** |
| 1305 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer |
| 1306 | * @chan: the DMA channel to prepare |
| 1307 | * @buf_addr: physical DMA address where the buffer starts |
| 1308 | * @buf_len: total number of bytes for the entire buffer |
| 1309 | * @period_len: number of bytes for each period |
| 1310 | * @direction: transfer direction, to or from device |
| 1311 | * |
| 1312 | * Must be called before trying to start the transfer. Returns a valid struct |
| 1313 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. |
| 1314 | */ |
| 1315 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, |
| 1316 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1317 | enum dma_transfer_direction direction) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1318 | { |
| 1319 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1320 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1321 | struct dw_cyclic_desc *cdesc; |
| 1322 | struct dw_cyclic_desc *retval = NULL; |
| 1323 | struct dw_desc *desc; |
| 1324 | struct dw_desc *last = NULL; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1325 | unsigned long was_cyclic; |
| 1326 | unsigned int reg_width; |
| 1327 | unsigned int periods; |
| 1328 | unsigned int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1329 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1330 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1331 | spin_lock_irqsave(&dwc->lock, flags); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1332 | if (dwc->nollp) { |
| 1333 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1334 | dev_dbg(chan2dev(&dwc->chan), |
| 1335 | "channel doesn't support LLP transfers\n"); |
| 1336 | return ERR_PTR(-EINVAL); |
| 1337 | } |
| 1338 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1339 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1340 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1341 | dev_dbg(chan2dev(&dwc->chan), |
| 1342 | "queue and/or active list are not empty\n"); |
| 1343 | return ERR_PTR(-EBUSY); |
| 1344 | } |
| 1345 | |
| 1346 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1347 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1348 | if (was_cyclic) { |
| 1349 | dev_dbg(chan2dev(&dwc->chan), |
| 1350 | "channel already prepared for cyclic DMA\n"); |
| 1351 | return ERR_PTR(-EBUSY); |
| 1352 | } |
| 1353 | |
| 1354 | retval = ERR_PTR(-EINVAL); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1355 | |
Andy Shevchenko | f44b92f | 2013-01-10 10:52:58 +0200 | [diff] [blame] | 1356 | if (unlikely(!is_slave_direction(direction))) |
| 1357 | goto out_err; |
| 1358 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 1359 | dwc->direction = direction; |
| 1360 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1361 | if (direction == DMA_MEM_TO_DEV) |
| 1362 | reg_width = __ffs(sconfig->dst_addr_width); |
| 1363 | else |
| 1364 | reg_width = __ffs(sconfig->src_addr_width); |
| 1365 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1366 | periods = buf_len / period_len; |
| 1367 | |
| 1368 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1369 | if (period_len > (dwc->block_size << reg_width)) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1370 | goto out_err; |
| 1371 | if (unlikely(period_len & ((1 << reg_width) - 1))) |
| 1372 | goto out_err; |
| 1373 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) |
| 1374 | goto out_err; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1375 | |
| 1376 | retval = ERR_PTR(-ENOMEM); |
| 1377 | |
| 1378 | if (periods > NR_DESCS_PER_CHANNEL) |
| 1379 | goto out_err; |
| 1380 | |
| 1381 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); |
| 1382 | if (!cdesc) |
| 1383 | goto out_err; |
| 1384 | |
| 1385 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); |
| 1386 | if (!cdesc->desc) |
| 1387 | goto out_err_alloc; |
| 1388 | |
| 1389 | for (i = 0; i < periods; i++) { |
| 1390 | desc = dwc_desc_get(dwc); |
| 1391 | if (!desc) |
| 1392 | goto out_err_desc_get; |
| 1393 | |
| 1394 | switch (direction) { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1395 | case DMA_MEM_TO_DEV: |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1396 | desc->lli.dar = sconfig->dst_addr; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1397 | desc->lli.sar = buf_addr + (period_len * i); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1398 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1399 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 1400 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 1401 | | DWC_CTLL_DST_FIX |
| 1402 | | DWC_CTLL_SRC_INC |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1403 | | DWC_CTLL_INT_EN); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1404 | |
| 1405 | desc->lli.ctllo |= sconfig->device_fc ? |
| 1406 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
| 1407 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
| 1408 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1409 | break; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 1410 | case DMA_DEV_TO_MEM: |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1411 | desc->lli.dar = buf_addr + (period_len * i); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1412 | desc->lli.sar = sconfig->src_addr; |
| 1413 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1414 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 1415 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 1416 | | DWC_CTLL_DST_INC |
| 1417 | | DWC_CTLL_SRC_FIX |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1418 | | DWC_CTLL_INT_EN); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 1419 | |
| 1420 | desc->lli.ctllo |= sconfig->device_fc ? |
| 1421 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
| 1422 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
| 1423 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1424 | break; |
| 1425 | default: |
| 1426 | break; |
| 1427 | } |
| 1428 | |
| 1429 | desc->lli.ctlhi = (period_len >> reg_width); |
| 1430 | cdesc->desc[i] = desc; |
| 1431 | |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1432 | if (last) |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1433 | last->lli.llp = desc->txd.phys; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1434 | |
| 1435 | last = desc; |
| 1436 | } |
| 1437 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1438 | /* Let's make a cyclic list */ |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1439 | last->lli.llp = cdesc->desc[0]->txd.phys; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1440 | |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 1441 | dev_dbg(chan2dev(&dwc->chan), |
| 1442 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", |
| 1443 | &buf_addr, buf_len, period_len, periods); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1444 | |
| 1445 | cdesc->periods = periods; |
| 1446 | dwc->cdesc = cdesc; |
| 1447 | |
| 1448 | return cdesc; |
| 1449 | |
| 1450 | out_err_desc_get: |
| 1451 | while (i--) |
| 1452 | dwc_desc_put(dwc, cdesc->desc[i]); |
| 1453 | out_err_alloc: |
| 1454 | kfree(cdesc); |
| 1455 | out_err: |
| 1456 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
| 1457 | return (struct dw_cyclic_desc *)retval; |
| 1458 | } |
| 1459 | EXPORT_SYMBOL(dw_dma_cyclic_prep); |
| 1460 | |
| 1461 | /** |
| 1462 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer |
| 1463 | * @chan: the DMA channel to free |
| 1464 | */ |
| 1465 | void dw_dma_cyclic_free(struct dma_chan *chan) |
| 1466 | { |
| 1467 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1468 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 1469 | struct dw_cyclic_desc *cdesc = dwc->cdesc; |
| 1470 | int i; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1471 | unsigned long flags; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1472 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1473 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1474 | |
| 1475 | if (!cdesc) |
| 1476 | return; |
| 1477 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1478 | spin_lock_irqsave(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1479 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 1480 | dwc_chan_disable(dw, dwc); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1481 | |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1482 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 1483 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
| 1484 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1485 | spin_unlock_irqrestore(&dwc->lock, flags); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 1486 | |
| 1487 | for (i = 0; i < cdesc->periods; i++) |
| 1488 | dwc_desc_put(dwc, cdesc->desc[i]); |
| 1489 | |
| 1490 | kfree(cdesc->desc); |
| 1491 | kfree(cdesc); |
| 1492 | |
| 1493 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
| 1494 | } |
| 1495 | EXPORT_SYMBOL(dw_dma_cyclic_free); |
| 1496 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1497 | /*----------------------------------------------------------------------*/ |
| 1498 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1499 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
Viresh Kumar | a9ddb57 | 2012-10-16 09:49:17 +0530 | [diff] [blame] | 1500 | { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1501 | struct dw_dma *dw; |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1502 | bool autocfg = false; |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1503 | unsigned int dw_params; |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1504 | unsigned int max_blk_size = 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1505 | int err; |
| 1506 | int i; |
| 1507 | |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1508 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
| 1509 | if (!dw) |
| 1510 | return -ENOMEM; |
| 1511 | |
| 1512 | dw->regs = chip->regs; |
| 1513 | chip->dw = dw; |
| 1514 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1515 | pm_runtime_get_sync(chip->dev); |
| 1516 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1517 | if (!pdata) { |
| 1518 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
| 1519 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1520 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1521 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
| 1522 | if (!autocfg) { |
| 1523 | err = -EINVAL; |
| 1524 | goto err_pdata; |
| 1525 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1526 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1527 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1528 | if (!pdata) { |
| 1529 | err = -ENOMEM; |
| 1530 | goto err_pdata; |
| 1531 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1532 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1533 | /* Get hardware configuration parameters */ |
| 1534 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; |
| 1535 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
| 1536 | for (i = 0; i < pdata->nr_masters; i++) { |
| 1537 | pdata->data_width[i] = |
| 1538 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; |
| 1539 | } |
| 1540 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
| 1541 | |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1542 | /* Fill platform data with the default values */ |
| 1543 | pdata->is_private = true; |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1544 | pdata->is_memcpy = true; |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1545 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
| 1546 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1547 | } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1548 | err = -EINVAL; |
| 1549 | goto err_pdata; |
| 1550 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1551 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1552 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1553 | GFP_KERNEL); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1554 | if (!dw->chan) { |
| 1555 | err = -ENOMEM; |
| 1556 | goto err_pdata; |
| 1557 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1558 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1559 | /* Get hardware configuration parameters */ |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1560 | dw->nr_masters = pdata->nr_masters; |
| 1561 | for (i = 0; i < dw->nr_masters; i++) |
| 1562 | dw->data_width[i] = pdata->data_width[i]; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1563 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1564 | /* Calculate all channel mask before DMA setup */ |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1565 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1566 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1567 | /* Force dma off, just in case */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1568 | dw_dma_off(dw); |
| 1569 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1570 | /* Disable BLOCK interrupts as well */ |
Andy Shevchenko | 236b106 | 2012-06-19 13:34:07 +0300 | [diff] [blame] | 1571 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
| 1572 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1573 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1574 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1575 | sizeof(struct dw_desc), 4, 0); |
| 1576 | if (!dw->desc_pool) { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1577 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1578 | err = -ENOMEM; |
| 1579 | goto err_pdata; |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1580 | } |
| 1581 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1582 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
| 1583 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1584 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
| 1585 | "dw_dmac", dw); |
| 1586 | if (err) |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1587 | goto err_pdata; |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1588 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1589 | INIT_LIST_HEAD(&dw->dma.channels); |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1590 | for (i = 0; i < pdata->nr_channels; i++) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1591 | struct dw_dma_chan *dwc = &dw->chan[i]; |
| 1592 | |
| 1593 | dwc->chan.device = &dw->dma; |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1594 | dma_cookie_init(&dwc->chan); |
Viresh Kumar | b0c3130 | 2011-03-03 15:47:21 +0530 | [diff] [blame] | 1595 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
| 1596 | list_add_tail(&dwc->chan.device_node, |
| 1597 | &dw->dma.channels); |
| 1598 | else |
| 1599 | list_add(&dwc->chan.device_node, &dw->dma.channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1600 | |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1601 | /* 7 is highest priority & 0 is lowest. */ |
| 1602 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1603 | dwc->priority = pdata->nr_channels - i - 1; |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1604 | else |
| 1605 | dwc->priority = i; |
| 1606 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1607 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
| 1608 | spin_lock_init(&dwc->lock); |
| 1609 | dwc->mask = 1 << i; |
| 1610 | |
| 1611 | INIT_LIST_HEAD(&dwc->active_list); |
| 1612 | INIT_LIST_HEAD(&dwc->queue); |
| 1613 | INIT_LIST_HEAD(&dwc->free_list); |
| 1614 | |
| 1615 | channel_clear_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1616 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 1617 | dwc->direction = DMA_TRANS_NONE; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1618 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1619 | /* Hardware configuration */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1620 | if (autocfg) { |
| 1621 | unsigned int dwc_params; |
Andy Shevchenko | 6bea0f6 | 2015-09-28 18:57:03 +0300 | [diff] [blame] | 1622 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1623 | void __iomem *addr = chip->regs + r * sizeof(u32); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1624 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1625 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1626 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1627 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
| 1628 | dwc_params); |
Andy Shevchenko | 985a6c7 | 2013-01-18 17:10:59 +0200 | [diff] [blame] | 1629 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1630 | /* |
| 1631 | * Decode maximum block size for given channel. The |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1632 | * stored 4 bit value represents blocks from 0x00 for 3 |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1633 | * up to 0x0a for 4095. |
| 1634 | */ |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1635 | dwc->block_size = |
| 1636 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1637 | dwc->nollp = |
| 1638 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; |
| 1639 | } else { |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1640 | dwc->block_size = pdata->block_size; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1641 | |
| 1642 | /* Check if channel supports multi block transfer */ |
| 1643 | channel_writel(dwc, LLP, 0xfffffffc); |
| 1644 | dwc->nollp = |
| 1645 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; |
| 1646 | channel_writel(dwc, LLP, 0); |
| 1647 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1648 | } |
| 1649 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1650 | /* Clear all interrupts on all channels. */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1651 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
Andy Shevchenko | 236b106 | 2012-06-19 13:34:07 +0300 | [diff] [blame] | 1652 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1653 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
| 1654 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); |
| 1655 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); |
| 1656 | |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1657 | /* Set capabilities */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1658 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 1659 | if (pdata->is_private) |
| 1660 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1661 | if (pdata->is_memcpy) |
| 1662 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
| 1663 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1664 | dw->dma.dev = chip->dev; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1665 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
| 1666 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; |
| 1667 | |
| 1668 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1669 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 1670 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1671 | dw->dma.device_config = dwc_config; |
| 1672 | dw->dma.device_pause = dwc_pause; |
| 1673 | dw->dma.device_resume = dwc_resume; |
| 1674 | dw->dma.device_terminate_all = dwc_terminate_all; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1675 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1676 | dw->dma.device_tx_status = dwc_tx_status; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1677 | dw->dma.device_issue_pending = dwc_issue_pending; |
| 1678 | |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 1679 | /* DMA capabilities */ |
| 1680 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; |
| 1681 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; |
| 1682 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | |
| 1683 | BIT(DMA_MEM_TO_MEM); |
| 1684 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
| 1685 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1686 | err = dma_async_device_register(&dw->dma); |
| 1687 | if (err) |
| 1688 | goto err_dma_register; |
| 1689 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1690 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1691 | pdata->nr_channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1692 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1693 | pm_runtime_put_sync_suspend(chip->dev); |
| 1694 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1695 | return 0; |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1696 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1697 | err_dma_register: |
| 1698 | free_irq(chip->irq, dw); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1699 | err_pdata: |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1700 | pm_runtime_put_sync_suspend(chip->dev); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1701 | return err; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1702 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1703 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1704 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1705 | int dw_dma_remove(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1706 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1707 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1708 | struct dw_dma_chan *dwc, *_dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1709 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1710 | pm_runtime_get_sync(chip->dev); |
| 1711 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1712 | dw_dma_off(dw); |
| 1713 | dma_async_device_unregister(&dw->dma); |
| 1714 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1715 | free_irq(chip->irq, dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1716 | tasklet_kill(&dw->tasklet); |
| 1717 | |
| 1718 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, |
| 1719 | chan.device_node) { |
| 1720 | list_del(&dwc->chan.device_node); |
| 1721 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 1722 | } |
| 1723 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1724 | pm_runtime_put_sync_suspend(chip->dev); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1725 | return 0; |
| 1726 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1727 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1728 | |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1729 | int dw_dma_disable(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1730 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1731 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1732 | |
Andy Shevchenko | 6168d56 | 2012-10-18 17:34:10 +0300 | [diff] [blame] | 1733 | dw_dma_off(dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1734 | return 0; |
| 1735 | } |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1736 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1737 | |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1738 | int dw_dma_enable(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1739 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1740 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1741 | |
Andy Shevchenko | 7a83c04 | 2014-09-23 17:18:12 +0300 | [diff] [blame] | 1742 | dw_dma_on(dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1743 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1744 | } |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1745 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1746 | |
| 1747 | MODULE_LICENSE("GPL v2"); |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1748 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
Jean Delvare | e05503e | 2011-05-18 16:49:24 +0200 | [diff] [blame] | 1749 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
Viresh Kumar | da89947 | 2015-07-17 16:23:50 -0700 | [diff] [blame] | 1750 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |