Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1 | /* |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007-2008 Atmel Corporation |
Viresh Kumar | aecb7b6 | 2011-05-24 14:04:09 +0530 | [diff] [blame] | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 6 | * Copyright (C) 2013 Intel Corporation |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
Heikki Krogerus | b801479 | 2012-10-18 17:34:08 +0300 | [diff] [blame] | 12 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 13 | #include <linux/bitops.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 14 | #include <linux/delay.h> |
| 15 | #include <linux/dmaengine.h> |
| 16 | #include <linux/dma-mapping.h> |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 17 | #include <linux/dmapool.h> |
Thierry Reding | 7331205 | 2013-01-21 11:09:00 +0100 | [diff] [blame] | 18 | #include <linux/err.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 19 | #include <linux/init.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/mm.h> |
| 23 | #include <linux/module.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 25 | #include <linux/pm_runtime.h> |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 26 | |
Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 27 | #include "../dmaengine.h" |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 28 | #include "internal.h" |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", |
| 32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all |
| 33 | * of which use ARM any more). See the "Databook" from Synopsys for |
| 34 | * information beyond what licensees probably provide. |
| 35 | * |
Andy Shevchenko | dd5720b | 2014-02-12 11:16:17 +0200 | [diff] [blame] | 36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
| 37 | * support descriptor writeback. |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 38 | */ |
| 39 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
| 42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 45 | DW_DMA_MSIZE_16; \ |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 47 | DW_DMA_MSIZE_16; \ |
Mans Rullgard | bb3450a | 2016-03-18 16:24:42 +0200 | [diff] [blame] | 48 | u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 49 | _dwc->dws.p_master : _dwc->dws.m_master; \ |
Mans Rullgard | bb3450a | 2016-03-18 16:24:42 +0200 | [diff] [blame] | 50 | u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 51 | _dwc->dws.p_master : _dwc->dws.m_master; \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 52 | \ |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 53 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
| 54 | | DWC_CTLL_SRC_MSIZE(_smsize) \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 55 | | DWC_CTLL_LLP_D_EN \ |
| 56 | | DWC_CTLL_LLP_S_EN \ |
Mans Rullgard | bb3450a | 2016-03-18 16:24:42 +0200 | [diff] [blame] | 57 | | DWC_CTLL_DMS(_dms) \ |
| 58 | | DWC_CTLL_SMS(_sms)); \ |
Jamie Iles | f301c06 | 2011-01-21 14:11:53 +0000 | [diff] [blame] | 59 | }) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 60 | |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 61 | /* The set of bus widths supported by the DMA controller */ |
| 62 | #define DW_DMA_BUSWIDTHS \ |
| 63 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ |
| 64 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
| 65 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
| 66 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
| 67 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 68 | /*----------------------------------------------------------------------*/ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 69 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 70 | static struct device *chan2dev(struct dma_chan *chan) |
| 71 | { |
| 72 | return &chan->dev->device; |
| 73 | } |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 74 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 75 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
| 76 | { |
Andy Shevchenko | e63a47a | 2012-10-18 17:34:12 +0300 | [diff] [blame] | 77 | return to_dw_desc(dwc->active_list.next); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 78 | } |
| 79 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 80 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 81 | { |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 82 | struct dw_desc *desc = txd_to_dw_desc(tx); |
| 83 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); |
| 84 | dma_cookie_t cookie; |
| 85 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 86 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 87 | spin_lock_irqsave(&dwc->lock, flags); |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 88 | cookie = dma_cookie_assign(tx); |
| 89 | |
| 90 | /* |
| 91 | * REVISIT: We should attempt to chain as many descriptors as |
| 92 | * possible, perhaps even appending to those already submitted |
| 93 | * for DMA. But this is hard to do in a race-free manner. |
| 94 | */ |
| 95 | |
| 96 | list_add_tail(&desc->desc_node, &dwc->queue); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 97 | spin_unlock_irqrestore(&dwc->lock, flags); |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 98 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", |
| 99 | __func__, desc->txd.cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 100 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 101 | return cookie; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 102 | } |
| 103 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 104 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
| 105 | { |
| 106 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 107 | struct dw_desc *desc; |
| 108 | dma_addr_t phys; |
| 109 | |
| 110 | desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); |
| 111 | if (!desc) |
| 112 | return NULL; |
| 113 | |
| 114 | dwc->descs_allocated++; |
| 115 | INIT_LIST_HEAD(&desc->tx_list); |
| 116 | dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); |
| 117 | desc->txd.tx_submit = dwc_tx_submit; |
| 118 | desc->txd.flags = DMA_CTRL_ACK; |
| 119 | desc->txd.phys = phys; |
| 120 | return desc; |
| 121 | } |
| 122 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 123 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
| 124 | { |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 125 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 126 | struct dw_desc *child, *_next; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 127 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 128 | if (unlikely(!desc)) |
| 129 | return; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 130 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 131 | list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { |
| 132 | list_del(&child->desc_node); |
| 133 | dma_pool_free(dw->desc_pool, child, child->txd.phys); |
| 134 | dwc->descs_allocated--; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 135 | } |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 136 | |
| 137 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
| 138 | dwc->descs_allocated--; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 141 | static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc) |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 142 | { |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 143 | u32 cfghi = 0; |
| 144 | u32 cfglo = 0; |
| 145 | |
| 146 | /* Set default burst alignment */ |
| 147 | cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN; |
| 148 | |
| 149 | /* Low 4 bits of the request lines */ |
| 150 | cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); |
| 151 | cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); |
| 152 | |
| 153 | /* Request line extension (2 bits) */ |
| 154 | cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); |
| 155 | cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); |
| 156 | |
| 157 | channel_writel(dwc, CFG_LO, cfglo); |
| 158 | channel_writel(dwc, CFG_HI, cfghi); |
| 159 | } |
| 160 | |
| 161 | static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc) |
| 162 | { |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 163 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
| 164 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); |
Andy Shevchenko | c072e11 | 2016-08-17 19:20:21 +0300 | [diff] [blame] | 165 | bool hs_polarity = dwc->dws.hs_polarity; |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 166 | |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 167 | cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); |
| 168 | cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 169 | |
Andy Shevchenko | c072e11 | 2016-08-17 19:20:21 +0300 | [diff] [blame] | 170 | /* Set polarity of handshake interface */ |
| 171 | cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; |
| 172 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 173 | channel_writel(dwc, CFG_LO, cfglo); |
| 174 | channel_writel(dwc, CFG_HI, cfghi); |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static void dwc_initialize(struct dw_dma_chan *dwc) |
| 178 | { |
| 179 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 180 | |
| 181 | if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) |
| 182 | return; |
| 183 | |
| 184 | if (dw->pdata->is_idma32) |
| 185 | dwc_initialize_chan_idma32(dwc); |
| 186 | else |
| 187 | dwc_initialize_chan_dw(dwc); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 188 | |
| 189 | /* Enable interrupts */ |
| 190 | channel_set_bit(dw, MASK.XFER, dwc->mask); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 191 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
| 192 | |
Andy Shevchenko | 423f9cb | 2016-03-18 16:24:52 +0200 | [diff] [blame] | 193 | set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 194 | } |
| 195 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 196 | /*----------------------------------------------------------------------*/ |
| 197 | |
Andy Shevchenko | f52b36d | 2012-09-21 15:05:44 +0300 | [diff] [blame] | 198 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 199 | { |
| 200 | dev_err(chan2dev(&dwc->chan), |
| 201 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
| 202 | channel_readl(dwc, SAR), |
| 203 | channel_readl(dwc, DAR), |
| 204 | channel_readl(dwc, LLP), |
| 205 | channel_readl(dwc, CTL_HI), |
| 206 | channel_readl(dwc, CTL_LO)); |
| 207 | } |
| 208 | |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 209 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 210 | { |
| 211 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 212 | while (dma_readl(dw, CH_EN) & dwc->mask) |
| 213 | cpu_relax(); |
| 214 | } |
| 215 | |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 216 | static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes, |
| 217 | unsigned int width, size_t *len) |
| 218 | { |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 219 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 220 | u32 block; |
| 221 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 222 | /* Always in bytes for iDMA 32-bit */ |
| 223 | if (dw->pdata->is_idma32) |
| 224 | width = 0; |
| 225 | |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 226 | if ((bytes >> width) > dwc->block_size) { |
| 227 | block = dwc->block_size; |
| 228 | *len = block << width; |
| 229 | } else { |
| 230 | block = bytes >> width; |
| 231 | *len = bytes; |
| 232 | } |
| 233 | |
| 234 | return block; |
| 235 | } |
| 236 | |
| 237 | static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) |
| 238 | { |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 239 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 240 | |
| 241 | if (dw->pdata->is_idma32) |
| 242 | return IDMA32C_CTLH_BLOCK_TS(block); |
| 243 | |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 244 | return DWC_CTLH_BLOCK_TS(block) << width; |
| 245 | } |
| 246 | |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 247 | /*----------------------------------------------------------------------*/ |
| 248 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 249 | /* Perform single block transfer */ |
| 250 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, |
| 251 | struct dw_desc *desc) |
| 252 | { |
| 253 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
| 254 | u32 ctllo; |
| 255 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 256 | /* |
| 257 | * Software emulation of LLP mode relies on interrupts to continue |
| 258 | * multi block transfer. |
| 259 | */ |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 260 | ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 261 | |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 262 | channel_writel(dwc, SAR, lli_read(desc, sar)); |
| 263 | channel_writel(dwc, DAR, lli_read(desc, dar)); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 264 | channel_writel(dwc, CTL_LO, ctllo); |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 265 | channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 266 | channel_set_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 267 | |
| 268 | /* Move pointer to next descriptor */ |
| 269 | dwc->tx_node_active = dwc->tx_node_active->next; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 270 | } |
| 271 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 272 | /* Called with dwc->lock held and bh disabled */ |
| 273 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) |
| 274 | { |
| 275 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 276 | u8 lms = DWC_LLP_LMS(dwc->dws.m_master); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 277 | unsigned long was_soft_llp; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 278 | |
| 279 | /* ASSERT: channel is idle */ |
| 280 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 281 | dev_err(chan2dev(&dwc->chan), |
Jarkko Nikula | 550da64 | 2015-03-10 11:37:23 +0200 | [diff] [blame] | 282 | "%s: BUG: Attempted to start non-idle channel\n", |
| 283 | __func__); |
Andy Shevchenko | 1d45543 | 2012-06-19 13:34:03 +0300 | [diff] [blame] | 284 | dwc_dump_chan_regs(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 285 | |
| 286 | /* The tasklet will hopefully advance the queue... */ |
| 287 | return; |
| 288 | } |
| 289 | |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 290 | if (dwc->nollp) { |
| 291 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, |
| 292 | &dwc->flags); |
| 293 | if (was_soft_llp) { |
| 294 | dev_err(chan2dev(&dwc->chan), |
Andy Shevchenko | fc61f6b | 2014-01-13 14:04:49 +0200 | [diff] [blame] | 295 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 296 | return; |
| 297 | } |
| 298 | |
| 299 | dwc_initialize(dwc); |
| 300 | |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 301 | first->residue = first->total_len; |
Andy Shevchenko | f5c6a7d | 2013-01-09 10:17:13 +0200 | [diff] [blame] | 302 | dwc->tx_node_active = &first->tx_list; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 303 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 304 | /* Submit first block */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 305 | dwc_do_single_block(dwc, first); |
| 306 | |
| 307 | return; |
| 308 | } |
| 309 | |
Viresh Kumar | 61e183f | 2011-11-17 16:01:29 +0530 | [diff] [blame] | 310 | dwc_initialize(dwc); |
| 311 | |
Mans Rullgard | 2a0fae0 | 2016-03-18 16:24:44 +0200 | [diff] [blame] | 312 | channel_writel(dwc, LLP, first->txd.phys | lms); |
| 313 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 314 | channel_writel(dwc, CTL_HI, 0); |
| 315 | channel_set_bit(dw, CH_EN, dwc->mask); |
| 316 | } |
| 317 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 318 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
| 319 | { |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 320 | struct dw_desc *desc; |
| 321 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 322 | if (list_empty(&dwc->queue)) |
| 323 | return; |
| 324 | |
| 325 | list_move(dwc->queue.next, &dwc->active_list); |
Andy Shevchenko | cba1561 | 2014-06-18 12:15:37 +0300 | [diff] [blame] | 326 | desc = dwc_first_active(dwc); |
| 327 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); |
| 328 | dwc_dostart(dwc, desc); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 329 | } |
| 330 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 331 | /*----------------------------------------------------------------------*/ |
| 332 | |
| 333 | static void |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 334 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
| 335 | bool callback_required) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 336 | { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 337 | struct dma_async_tx_descriptor *txd = &desc->txd; |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 338 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 339 | unsigned long flags; |
Dave Jiang | 577ef92 | 2016-07-20 13:11:00 -0700 | [diff] [blame] | 340 | struct dmaengine_desc_callback cb; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 341 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 342 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 343 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 344 | spin_lock_irqsave(&dwc->lock, flags); |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 345 | dma_cookie_complete(txd); |
Dave Jiang | 577ef92 | 2016-07-20 13:11:00 -0700 | [diff] [blame] | 346 | if (callback_required) |
| 347 | dmaengine_desc_get_callback(txd, &cb); |
| 348 | else |
| 349 | memset(&cb, 0, sizeof(cb)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 350 | |
Viresh Kumar | e518076 | 2011-03-03 15:47:20 +0530 | [diff] [blame] | 351 | /* async_tx_ack */ |
| 352 | list_for_each_entry(child, &desc->tx_list, desc_node) |
| 353 | async_tx_ack(&child->txd); |
| 354 | async_tx_ack(&desc->txd); |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 355 | dwc_desc_put(dwc, desc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 356 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 357 | |
Dave Jiang | 577ef92 | 2016-07-20 13:11:00 -0700 | [diff] [blame] | 358 | dmaengine_desc_callback_invoke(&cb, NULL); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 362 | { |
| 363 | struct dw_desc *desc, *_desc; |
| 364 | LIST_HEAD(list); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 365 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 366 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 367 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 368 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 369 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 370 | "BUG: XFER bit set, but channel not idle!\n"); |
| 371 | |
| 372 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 373 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 374 | } |
| 375 | |
| 376 | /* |
| 377 | * Submit queued descriptors ASAP, i.e. before we go through |
| 378 | * the completed ones. |
| 379 | */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 380 | list_splice_init(&dwc->active_list, &list); |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 381 | dwc_dostart_first_queued(dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 382 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 383 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 384 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 385 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 386 | dwc_descriptor_complete(dwc, desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 387 | } |
| 388 | |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 389 | /* Returns how many bytes were already received from source */ |
| 390 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) |
| 391 | { |
| 392 | u32 ctlhi = channel_readl(dwc, CTL_HI); |
| 393 | u32 ctllo = channel_readl(dwc, CTL_LO); |
| 394 | |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 395 | return block2bytes(dwc, ctlhi, ctllo >> 4 & 7); |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 396 | } |
| 397 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 398 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 399 | { |
| 400 | dma_addr_t llp; |
| 401 | struct dw_desc *desc, *_desc; |
| 402 | struct dw_desc *child; |
| 403 | u32 status_xfer; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 404 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 405 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 406 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 407 | llp = channel_readl(dwc, LLP); |
| 408 | status_xfer = dma_readl(dw, RAW.XFER); |
| 409 | |
| 410 | if (status_xfer & dwc->mask) { |
| 411 | /* Everything we've submitted is done */ |
| 412 | dma_writel(dw, CLEAR.XFER, dwc->mask); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 413 | |
| 414 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 415 | struct list_head *head, *active = dwc->tx_node_active; |
| 416 | |
| 417 | /* |
| 418 | * We are inside first active descriptor. |
| 419 | * Otherwise something is really wrong. |
| 420 | */ |
| 421 | desc = dwc_first_active(dwc); |
| 422 | |
| 423 | head = &desc->tx_list; |
| 424 | if (active != head) { |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 425 | /* Update residue to reflect last sent descriptor */ |
| 426 | if (active == head->next) |
| 427 | desc->residue -= desc->len; |
| 428 | else |
| 429 | desc->residue -= to_dw_desc(active->prev)->len; |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 430 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 431 | child = to_dw_desc(active); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 432 | |
| 433 | /* Submit next block */ |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 434 | dwc_do_single_block(dwc, child); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 435 | |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 436 | spin_unlock_irqrestore(&dwc->lock, flags); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 437 | return; |
| 438 | } |
Andy Shevchenko | fdf475f | 2013-01-25 11:48:00 +0200 | [diff] [blame] | 439 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 440 | /* We are done here */ |
| 441 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
| 442 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 443 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 444 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 445 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 446 | dwc_complete_all(dw, dwc); |
| 447 | return; |
| 448 | } |
| 449 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 450 | if (list_empty(&dwc->active_list)) { |
| 451 | spin_unlock_irqrestore(&dwc->lock, flags); |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 452 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 453 | } |
Jamie Iles | 087809f | 2011-01-21 14:11:52 +0000 | [diff] [blame] | 454 | |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 455 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
| 456 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 458 | return; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 459 | } |
| 460 | |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 461 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 462 | |
| 463 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 464 | /* Initial residue value */ |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 465 | desc->residue = desc->total_len; |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 466 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 467 | /* Check first descriptors addr */ |
Mans Rullgard | 2a0fae0 | 2016-03-18 16:24:44 +0200 | [diff] [blame] | 468 | if (desc->txd.phys == DWC_LLP_LOC(llp)) { |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 469 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 470 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 471 | } |
Viresh Kumar | 84adccf | 2011-03-24 11:32:15 +0530 | [diff] [blame] | 472 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 473 | /* Check first descriptors llp */ |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 474 | if (lli_read(desc, llp) == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 475 | /* This one is currently in progress */ |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 476 | desc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 477 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 478 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 479 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 480 | |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 481 | desc->residue -= desc->len; |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 482 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 483 | if (lli_read(child, llp) == llp) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 484 | /* Currently in progress */ |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 485 | desc->residue -= dwc_get_sent(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 486 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 487 | return; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 488 | } |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 489 | desc->residue -= child->len; |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 490 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 491 | |
| 492 | /* |
| 493 | * No descriptors so far seem to be in progress, i.e. |
| 494 | * this one must be done. |
| 495 | */ |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 496 | spin_unlock_irqrestore(&dwc->lock, flags); |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 497 | dwc_descriptor_complete(dwc, desc, true); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 498 | spin_lock_irqsave(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 499 | } |
| 500 | |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 501 | dev_err(chan2dev(&dwc->chan), |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 502 | "BUG: All descriptors done, but channel not idle!\n"); |
| 503 | |
| 504 | /* Try to continue after resetting the channel... */ |
Andy Shevchenko | 3f936207 | 2012-06-19 13:46:32 +0300 | [diff] [blame] | 505 | dwc_chan_disable(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 506 | |
Andy Shevchenko | e7637c6 | 2014-06-18 12:15:36 +0300 | [diff] [blame] | 507 | dwc_dostart_first_queued(dwc); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 508 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 509 | } |
| 510 | |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 511 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 512 | { |
Andy Shevchenko | 21d43f4 | 2012-10-18 17:34:09 +0300 | [diff] [blame] | 513 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 514 | lli_read(desc, sar), |
| 515 | lli_read(desc, dar), |
| 516 | lli_read(desc, llp), |
| 517 | lli_read(desc, ctlhi), |
| 518 | lli_read(desc, ctllo)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) |
| 522 | { |
| 523 | struct dw_desc *bad_desc; |
| 524 | struct dw_desc *child; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 525 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 526 | |
| 527 | dwc_scan_descriptors(dw, dwc); |
| 528 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 529 | spin_lock_irqsave(&dwc->lock, flags); |
| 530 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 531 | /* |
| 532 | * The descriptor currently at the head of the active list is |
| 533 | * borked. Since we don't have any way to report errors, we'll |
| 534 | * just have to scream loudly and try to carry on. |
| 535 | */ |
| 536 | bad_desc = dwc_first_active(dwc); |
| 537 | list_del_init(&bad_desc->desc_node); |
Viresh Kumar | f336e42 | 2011-03-03 15:47:16 +0530 | [diff] [blame] | 538 | list_move(dwc->queue.next, dwc->active_list.prev); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 539 | |
| 540 | /* Clear the error flag and try to restart the controller */ |
| 541 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
| 542 | if (!list_empty(&dwc->active_list)) |
| 543 | dwc_dostart(dwc, dwc_first_active(dwc)); |
| 544 | |
| 545 | /* |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 546 | * WARN may seem harsh, but since this only happens |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 547 | * when someone submits a bad physical address in a |
| 548 | * descriptor, we should consider ourselves lucky that the |
| 549 | * controller flagged an error instead of scribbling over |
| 550 | * random memory locations. |
| 551 | */ |
Andy Shevchenko | ba84bd7 | 2012-10-18 17:34:11 +0300 | [diff] [blame] | 552 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
| 553 | " cookie: %d\n", bad_desc->txd.cookie); |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 554 | dwc_dump_lli(dwc, bad_desc); |
Dan Williams | e0bd0f8 | 2009-09-08 17:53:02 -0700 | [diff] [blame] | 555 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 556 | dwc_dump_lli(dwc, child); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 557 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 558 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 559 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 560 | /* Pretend the descriptor completed successfully */ |
Viresh Kumar | 5fedefb | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 561 | dwc_descriptor_complete(dwc, bad_desc, true); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | static void dw_dma_tasklet(unsigned long data) |
| 565 | { |
| 566 | struct dw_dma *dw = (struct dw_dma *)data; |
| 567 | struct dw_dma_chan *dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 568 | u32 status_xfer; |
| 569 | u32 status_err; |
Andy Shevchenko | 7794e5b | 2016-03-18 16:24:48 +0200 | [diff] [blame] | 570 | unsigned int i; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 571 | |
Haavard Skinnemoen | 7fe7b2f | 2008-10-03 15:23:46 -0700 | [diff] [blame] | 572 | status_xfer = dma_readl(dw, RAW.XFER); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 573 | status_err = dma_readl(dw, RAW.ERROR); |
| 574 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 575 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 576 | |
| 577 | for (i = 0; i < dw->dma.chancnt; i++) { |
| 578 | dwc = &dw->chan[i]; |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 579 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
Andy Shevchenko | 14bebd0 | 2017-05-09 19:18:37 +0300 | [diff] [blame] | 580 | dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); |
Hans-Christian Egtvedt | d9de451 | 2009-04-01 15:47:02 +0200 | [diff] [blame] | 581 | else if (status_err & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 582 | dwc_handle_error(dw, dwc); |
Andy Shevchenko | 77bcc497 | 2013-01-18 14:14:15 +0200 | [diff] [blame] | 583 | else if (status_xfer & (1 << i)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 584 | dwc_scan_descriptors(dw, dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 585 | } |
| 586 | |
Andy Shevchenko | ee1cdcd | 2016-02-10 15:59:42 +0200 | [diff] [blame] | 587 | /* Re-enable interrupts */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 588 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 589 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 590 | } |
| 591 | |
| 592 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) |
| 593 | { |
| 594 | struct dw_dma *dw = dev_id; |
Andy Shevchenko | 02a21b7 | 2015-12-04 23:49:24 +0200 | [diff] [blame] | 595 | u32 status; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 596 | |
Andy Shevchenko | 02a21b7 | 2015-12-04 23:49:24 +0200 | [diff] [blame] | 597 | /* Check if we have any interrupt from the DMAC which is not in use */ |
| 598 | if (!dw->in_use) |
| 599 | return IRQ_NONE; |
| 600 | |
| 601 | status = dma_readl(dw, STATUS_INT); |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 602 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
| 603 | |
| 604 | /* Check if we have any interrupt from the DMAC */ |
Andy Shevchenko | 02a21b7 | 2015-12-04 23:49:24 +0200 | [diff] [blame] | 605 | if (!status) |
Andy Shevchenko | 3783cef | 2013-07-15 15:04:39 +0300 | [diff] [blame] | 606 | return IRQ_NONE; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 607 | |
| 608 | /* |
| 609 | * Just disable the interrupts. We'll turn them back on in the |
| 610 | * softirq handler. |
| 611 | */ |
| 612 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
Mans Rullgard | 2895b2c | 2016-01-11 13:04:29 +0000 | [diff] [blame] | 613 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 614 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 615 | |
| 616 | status = dma_readl(dw, STATUS_INT); |
| 617 | if (status) { |
| 618 | dev_err(dw->dma.dev, |
| 619 | "BUG: Unexpected interrupts pending: 0x%x\n", |
| 620 | status); |
| 621 | |
| 622 | /* Try to recover */ |
| 623 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); |
Mans Rullgard | 2895b2c | 2016-01-11 13:04:29 +0000 | [diff] [blame] | 624 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 625 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
| 626 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); |
| 627 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); |
| 628 | } |
| 629 | |
| 630 | tasklet_schedule(&dw->tasklet); |
| 631 | |
| 632 | return IRQ_HANDLED; |
| 633 | } |
| 634 | |
| 635 | /*----------------------------------------------------------------------*/ |
| 636 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 637 | static struct dma_async_tx_descriptor * |
| 638 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 639 | size_t len, unsigned long flags) |
| 640 | { |
| 641 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 642 | struct dw_dma *dw = to_dw_dma(chan->device); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 643 | struct dw_desc *desc; |
| 644 | struct dw_desc *first; |
| 645 | struct dw_desc *prev; |
| 646 | size_t xfer_count; |
| 647 | size_t offset; |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 648 | u8 m_master = dwc->dws.m_master; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 649 | unsigned int src_width; |
| 650 | unsigned int dst_width; |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 651 | unsigned int data_width = dw->pdata->data_width[m_master]; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 652 | u32 ctllo; |
Andy Shevchenko | 2e65060 | 2016-04-27 14:15:38 +0300 | [diff] [blame] | 653 | u8 lms = DWC_LLP_LMS(m_master); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 654 | |
Andy Shevchenko | 2f45d61 | 2012-06-19 13:34:02 +0300 | [diff] [blame] | 655 | dev_vdbg(chan2dev(chan), |
Andy Shevchenko | 5a87f0e | 2014-01-13 14:04:50 +0200 | [diff] [blame] | 656 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
| 657 | &dest, &src, len, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 658 | |
| 659 | if (unlikely(!len)) { |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 660 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 661 | return NULL; |
| 662 | } |
| 663 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 664 | dwc->direction = DMA_MEM_TO_MEM; |
| 665 | |
Andy Shevchenko | 2e65060 | 2016-04-27 14:15:38 +0300 | [diff] [blame] | 666 | src_width = dst_width = __ffs(data_width | src | dest | len); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 667 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 668 | ctllo = DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 669 | | DWC_CTLL_DST_WIDTH(dst_width) |
| 670 | | DWC_CTLL_SRC_WIDTH(src_width) |
| 671 | | DWC_CTLL_DST_INC |
| 672 | | DWC_CTLL_SRC_INC |
| 673 | | DWC_CTLL_FC_M2M; |
| 674 | prev = first = NULL; |
| 675 | |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 676 | for (offset = 0; offset < len; offset += xfer_count) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 677 | desc = dwc_desc_get(dwc); |
| 678 | if (!desc) |
| 679 | goto err_desc_get; |
| 680 | |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 681 | lli_write(desc, sar, src + offset); |
| 682 | lli_write(desc, dar, dest + offset); |
| 683 | lli_write(desc, ctllo, ctllo); |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 684 | lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count)); |
| 685 | desc->len = xfer_count; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 686 | |
| 687 | if (!first) { |
| 688 | first = desc; |
| 689 | } else { |
Mans Rullgard | 2a0fae0 | 2016-03-18 16:24:44 +0200 | [diff] [blame] | 690 | lli_write(prev, llp, desc->txd.phys | lms); |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 691 | list_add_tail(&desc->desc_node, &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 692 | } |
| 693 | prev = desc; |
| 694 | } |
| 695 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 696 | if (flags & DMA_PREP_INTERRUPT) |
| 697 | /* Trigger interrupt after last block */ |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 698 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 699 | |
| 700 | prev->lli.llp = 0; |
Mans Rullgard | a3e5579 | 2016-03-18 16:24:45 +0200 | [diff] [blame] | 701 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 702 | first->txd.flags = flags; |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 703 | first->total_len = len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 704 | |
| 705 | return &first->txd; |
| 706 | |
| 707 | err_desc_get: |
| 708 | dwc_desc_put(dwc, first); |
| 709 | return NULL; |
| 710 | } |
| 711 | |
| 712 | static struct dma_async_tx_descriptor * |
| 713 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 714 | unsigned int sg_len, enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 715 | unsigned long flags, void *context) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 716 | { |
| 717 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Arnd Bergmann | f776076 | 2013-03-26 16:53:57 +0200 | [diff] [blame] | 718 | struct dw_dma *dw = to_dw_dma(chan->device); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 719 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 720 | struct dw_desc *prev; |
| 721 | struct dw_desc *first; |
| 722 | u32 ctllo; |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 723 | u8 m_master = dwc->dws.m_master; |
Andy Shevchenko | 2e65060 | 2016-04-27 14:15:38 +0300 | [diff] [blame] | 724 | u8 lms = DWC_LLP_LMS(m_master); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 725 | dma_addr_t reg; |
| 726 | unsigned int reg_width; |
| 727 | unsigned int mem_width; |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 728 | unsigned int data_width = dw->pdata->data_width[m_master]; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 729 | unsigned int i; |
| 730 | struct scatterlist *sg; |
| 731 | size_t total_len = 0; |
| 732 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 733 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 734 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 735 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 736 | return NULL; |
| 737 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 738 | dwc->direction = direction; |
| 739 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 740 | prev = first = NULL; |
| 741 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 742 | switch (direction) { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 743 | case DMA_MEM_TO_DEV: |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 744 | reg_width = __ffs(sconfig->dst_addr_width); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 745 | reg = sconfig->dst_addr; |
| 746 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 747 | | DWC_CTLL_DST_WIDTH(reg_width) |
| 748 | | DWC_CTLL_DST_FIX |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 749 | | DWC_CTLL_SRC_INC); |
| 750 | |
| 751 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
| 752 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
| 753 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 754 | for_each_sg(sgl, sg, sg_len, i) { |
| 755 | struct dw_desc *desc; |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 756 | u32 len, mem; |
| 757 | size_t dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 758 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 759 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 760 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 761 | |
Andy Shevchenko | 2e65060 | 2016-04-27 14:15:38 +0300 | [diff] [blame] | 762 | mem_width = __ffs(data_width | mem | len); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 763 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 764 | slave_sg_todev_fill_desc: |
| 765 | desc = dwc_desc_get(dwc); |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 766 | if (!desc) |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 767 | goto err_desc_get; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 768 | |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 769 | lli_write(desc, sar, mem); |
| 770 | lli_write(desc, dar, reg); |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 771 | lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen)); |
Jarkko Nikula | a46a763 | 2017-01-17 13:57:25 +0200 | [diff] [blame] | 772 | lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 773 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 774 | |
| 775 | if (!first) { |
| 776 | first = desc; |
| 777 | } else { |
Mans Rullgard | 2a0fae0 | 2016-03-18 16:24:44 +0200 | [diff] [blame] | 778 | lli_write(prev, llp, desc->txd.phys | lms); |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 779 | list_add_tail(&desc->desc_node, &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 780 | } |
| 781 | prev = desc; |
Jarkko Nikula | a46a763 | 2017-01-17 13:57:25 +0200 | [diff] [blame] | 782 | |
| 783 | mem += dlen; |
| 784 | len -= dlen; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 785 | total_len += dlen; |
| 786 | |
| 787 | if (len) |
| 788 | goto slave_sg_todev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 789 | } |
| 790 | break; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 791 | case DMA_DEV_TO_MEM: |
Andy Shevchenko | 3941667 | 2015-09-28 18:57:04 +0300 | [diff] [blame] | 792 | reg_width = __ffs(sconfig->src_addr_width); |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 793 | reg = sconfig->src_addr; |
| 794 | ctllo = (DWC_DEFAULT_CTLLO(chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 795 | | DWC_CTLL_SRC_WIDTH(reg_width) |
| 796 | | DWC_CTLL_DST_INC |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 797 | | DWC_CTLL_SRC_FIX); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 798 | |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 799 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
| 800 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
| 801 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 802 | for_each_sg(sgl, sg, sg_len, i) { |
| 803 | struct dw_desc *desc; |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 804 | u32 len, mem; |
| 805 | size_t dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 806 | |
Lars-Peter Clausen | cbb796c | 2012-04-25 20:50:51 +0200 | [diff] [blame] | 807 | mem = sg_dma_address(sg); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 808 | len = sg_dma_len(sg); |
Viresh Kumar | 6bc711f | 2012-02-01 16:12:25 +0530 | [diff] [blame] | 809 | |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 810 | slave_sg_fromdev_fill_desc: |
| 811 | desc = dwc_desc_get(dwc); |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 812 | if (!desc) |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 813 | goto err_desc_get; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 814 | |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 815 | lli_write(desc, sar, reg); |
| 816 | lli_write(desc, dar, mem); |
Andy Shevchenko | 2d24881 | 2017-01-17 13:57:29 +0200 | [diff] [blame] | 817 | lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen)); |
Jarkko Nikula | a46a763 | 2017-01-17 13:57:25 +0200 | [diff] [blame] | 818 | mem_width = __ffs(data_width | mem | dlen); |
| 819 | lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); |
Andy Shevchenko | 176dcec | 2013-01-25 11:48:02 +0200 | [diff] [blame] | 820 | desc->len = dlen; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 821 | |
| 822 | if (!first) { |
| 823 | first = desc; |
| 824 | } else { |
Mans Rullgard | 2a0fae0 | 2016-03-18 16:24:44 +0200 | [diff] [blame] | 825 | lli_write(prev, llp, desc->txd.phys | lms); |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 826 | list_add_tail(&desc->desc_node, &first->tx_list); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 827 | } |
| 828 | prev = desc; |
Jarkko Nikula | a46a763 | 2017-01-17 13:57:25 +0200 | [diff] [blame] | 829 | |
| 830 | mem += dlen; |
| 831 | len -= dlen; |
Viresh Kumar | 69dc14b | 2011-04-18 14:54:56 +0530 | [diff] [blame] | 832 | total_len += dlen; |
| 833 | |
| 834 | if (len) |
| 835 | goto slave_sg_fromdev_fill_desc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 836 | } |
| 837 | break; |
| 838 | default: |
| 839 | return NULL; |
| 840 | } |
| 841 | |
| 842 | if (flags & DMA_PREP_INTERRUPT) |
| 843 | /* Trigger interrupt after last block */ |
Mans Rullgard | df1f3a2 | 2016-03-18 16:24:43 +0200 | [diff] [blame] | 844 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 845 | |
| 846 | prev->lli.llp = 0; |
Mans Rullgard | a3e5579 | 2016-03-18 16:24:45 +0200 | [diff] [blame] | 847 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
Andy Shevchenko | 30d38a3 | 2013-01-25 11:48:01 +0200 | [diff] [blame] | 848 | first->total_len = total_len; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 849 | |
| 850 | return &first->txd; |
| 851 | |
| 852 | err_desc_get: |
Jarkko Nikula | b260722 | 2015-03-10 11:37:24 +0200 | [diff] [blame] | 853 | dev_err(chan2dev(chan), |
| 854 | "not enough descriptors available. Direction %d\n", direction); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 855 | dwc_desc_put(dwc, first); |
| 856 | return NULL; |
| 857 | } |
| 858 | |
Andy Shevchenko | 4d130de | 2014-08-19 20:29:16 +0300 | [diff] [blame] | 859 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
| 860 | { |
| 861 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 862 | struct dw_dma_slave *dws = param; |
| 863 | |
Andy Shevchenko | 3fe6409 | 2016-04-08 16:22:17 +0300 | [diff] [blame] | 864 | if (dws->dma_dev != chan->device->dev) |
Andy Shevchenko | 4d130de | 2014-08-19 20:29:16 +0300 | [diff] [blame] | 865 | return false; |
| 866 | |
| 867 | /* We have to copy data since dws can be temporary storage */ |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 868 | memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); |
Andy Shevchenko | 4d130de | 2014-08-19 20:29:16 +0300 | [diff] [blame] | 869 | |
| 870 | return true; |
| 871 | } |
| 872 | EXPORT_SYMBOL_GPL(dw_dma_filter); |
| 873 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 874 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 875 | { |
| 876 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Andy Shevchenko | be242f4 | 2017-01-17 13:57:27 +0200 | [diff] [blame] | 877 | struct dma_slave_config *sc = &dwc->dma_sconfig; |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 878 | struct dw_dma *dw = to_dw_dma(chan->device); |
Andy Shevchenko | be242f4 | 2017-01-17 13:57:27 +0200 | [diff] [blame] | 879 | /* |
| 880 | * Fix sconfig's burst size according to dw_dmac. We need to convert |
| 881 | * them as: |
| 882 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. |
| 883 | * |
| 884 | * NOTE: burst size 2 is not supported by DesignWare controller. |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 885 | * iDMA 32-bit supports it. |
Andy Shevchenko | be242f4 | 2017-01-17 13:57:27 +0200 | [diff] [blame] | 886 | */ |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 887 | u32 s = dw->pdata->is_idma32 ? 1 : 2; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 888 | |
Andy Shevchenko | 495aea4 | 2013-01-10 11:11:41 +0200 | [diff] [blame] | 889 | /* Check if chan will be configured for slave transfers */ |
| 890 | if (!is_slave_direction(sconfig->direction)) |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 891 | return -EINVAL; |
| 892 | |
| 893 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 894 | dwc->direction = sconfig->direction; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 895 | |
Andy Shevchenko | be242f4 | 2017-01-17 13:57:27 +0200 | [diff] [blame] | 896 | sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0; |
| 897 | sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0; |
Viresh Kumar | 327e697 | 2012-02-01 16:12:26 +0530 | [diff] [blame] | 898 | |
| 899 | return 0; |
| 900 | } |
| 901 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 902 | static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 903 | { |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 904 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 905 | unsigned int count = 20; /* timeout iterations */ |
| 906 | u32 cfglo; |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 907 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 908 | cfglo = channel_readl(dwc, CFG_LO); |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 909 | if (dw->pdata->is_idma32) { |
| 910 | if (drain) |
| 911 | cfglo |= IDMA32C_CFGL_CH_DRAIN; |
| 912 | else |
| 913 | cfglo &= ~IDMA32C_CFGL_CH_DRAIN; |
| 914 | } |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 915 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
Andy Shevchenko | 123b69a | 2013-03-21 11:49:17 +0200 | [diff] [blame] | 916 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
| 917 | udelay(2); |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 918 | |
Andy Shevchenko | 5e09f98 | 2016-03-18 16:24:51 +0200 | [diff] [blame] | 919 | set_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
Andy Shevchenko | f4aa318 | 2017-01-17 13:57:28 +0200 | [diff] [blame] | 920 | } |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 921 | |
Andy Shevchenko | f4aa318 | 2017-01-17 13:57:28 +0200 | [diff] [blame] | 922 | static int dwc_pause(struct dma_chan *chan) |
| 923 | { |
| 924 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 925 | unsigned long flags; |
| 926 | |
| 927 | spin_lock_irqsave(&dwc->lock, flags); |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 928 | dwc_chan_pause(dwc, false); |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 929 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 930 | |
| 931 | return 0; |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) |
| 935 | { |
| 936 | u32 cfglo = channel_readl(dwc, CFG_LO); |
| 937 | |
| 938 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); |
| 939 | |
Andy Shevchenko | 5e09f98 | 2016-03-18 16:24:51 +0200 | [diff] [blame] | 940 | clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
Andy Shevchenko | 21fe3c5 | 2013-01-09 10:17:14 +0200 | [diff] [blame] | 941 | } |
| 942 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 943 | static int dwc_resume(struct dma_chan *chan) |
| 944 | { |
| 945 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 946 | unsigned long flags; |
| 947 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 948 | spin_lock_irqsave(&dwc->lock, flags); |
| 949 | |
Andy Shevchenko | 5e09f98 | 2016-03-18 16:24:51 +0200 | [diff] [blame] | 950 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) |
| 951 | dwc_chan_resume(dwc); |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 952 | |
| 953 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 954 | |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | static int dwc_terminate_all(struct dma_chan *chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 959 | { |
| 960 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 961 | struct dw_dma *dw = to_dw_dma(chan->device); |
| 962 | struct dw_desc *desc, *_desc; |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 963 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 964 | LIST_HEAD(list); |
| 965 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 966 | spin_lock_irqsave(&dwc->lock, flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 967 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 968 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 969 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 970 | dwc_chan_pause(dwc, true); |
| 971 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 972 | dwc_chan_disable(dw, dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 973 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 974 | dwc_chan_resume(dwc); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 975 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 976 | /* active_list entries will end up before queued entries */ |
| 977 | list_splice_init(&dwc->queue, &list); |
| 978 | list_splice_init(&dwc->active_list, &list); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 979 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 980 | spin_unlock_irqrestore(&dwc->lock, flags); |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 981 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 982 | /* Flush all pending and queued descriptors */ |
| 983 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
| 984 | dwc_descriptor_complete(dwc, desc, false); |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 985 | |
Linus Walleij | c3635c7 | 2010-03-26 16:44:01 -0700 | [diff] [blame] | 986 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 987 | } |
| 988 | |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 989 | static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 990 | { |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 991 | struct dw_desc *desc; |
| 992 | |
| 993 | list_for_each_entry(desc, &dwc->active_list, desc_node) |
| 994 | if (desc->txd.cookie == c) |
| 995 | return desc; |
| 996 | |
| 997 | return NULL; |
| 998 | } |
| 999 | |
| 1000 | static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) |
| 1001 | { |
| 1002 | struct dw_desc *desc; |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1003 | unsigned long flags; |
| 1004 | u32 residue; |
| 1005 | |
| 1006 | spin_lock_irqsave(&dwc->lock, flags); |
| 1007 | |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 1008 | desc = dwc_find_desc(dwc, cookie); |
| 1009 | if (desc) { |
| 1010 | if (desc == dwc_first_active(dwc)) { |
| 1011 | residue = desc->residue; |
| 1012 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) |
| 1013 | residue -= dwc_get_sent(dwc); |
| 1014 | } else { |
| 1015 | residue = desc->total_len; |
| 1016 | } |
| 1017 | } else { |
| 1018 | residue = 0; |
| 1019 | } |
Andy Shevchenko | 4702d52 | 2013-01-25 11:48:03 +0200 | [diff] [blame] | 1020 | |
| 1021 | spin_unlock_irqrestore(&dwc->lock, flags); |
| 1022 | return residue; |
| 1023 | } |
| 1024 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1025 | static enum dma_status |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1026 | dwc_tx_status(struct dma_chan *chan, |
| 1027 | dma_cookie_t cookie, |
| 1028 | struct dma_tx_state *txstate) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1029 | { |
| 1030 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1031 | enum dma_status ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1032 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 1033 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 2c40410 | 2013-10-16 13:41:15 +0530 | [diff] [blame] | 1034 | if (ret == DMA_COMPLETE) |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1035 | return ret; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1036 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1037 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1038 | |
Andy Shevchenko | 12381dc | 2013-07-15 15:04:40 +0300 | [diff] [blame] | 1039 | ret = dma_cookie_status(chan, cookie, txstate); |
Andy Shevchenko | b68fd09 | 2016-03-18 16:24:53 +0200 | [diff] [blame] | 1040 | if (ret == DMA_COMPLETE) |
| 1041 | return ret; |
| 1042 | |
| 1043 | dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1044 | |
Andy Shevchenko | 5e09f98 | 2016-03-18 16:24:51 +0200 | [diff] [blame] | 1045 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) |
Linus Walleij | a7c57cf | 2011-04-19 08:31:32 +0800 | [diff] [blame] | 1046 | return DMA_PAUSED; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1047 | |
| 1048 | return ret; |
| 1049 | } |
| 1050 | |
| 1051 | static void dwc_issue_pending(struct dma_chan *chan) |
| 1052 | { |
| 1053 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1054 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1055 | |
Andy Shevchenko | dd8ecfca | 2014-06-18 12:15:38 +0300 | [diff] [blame] | 1056 | spin_lock_irqsave(&dwc->lock, flags); |
| 1057 | if (list_empty(&dwc->active_list)) |
| 1058 | dwc_dostart_first_queued(dwc); |
| 1059 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1060 | } |
| 1061 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1062 | /*----------------------------------------------------------------------*/ |
| 1063 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 1064 | /* |
| 1065 | * Program FIFO size of channels. |
| 1066 | * |
| 1067 | * By default full FIFO (1024 bytes) is assigned to channel 0. Here we |
| 1068 | * slice FIFO on equal parts between channels. |
| 1069 | */ |
| 1070 | static void idma32_fifo_partition(struct dw_dma *dw) |
| 1071 | { |
| 1072 | u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) | |
| 1073 | IDMA32C_FP_UPDATE; |
| 1074 | u64 fifo_partition = 0; |
| 1075 | |
| 1076 | if (!dw->pdata->is_idma32) |
| 1077 | return; |
| 1078 | |
| 1079 | /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */ |
| 1080 | fifo_partition |= value << 0; |
| 1081 | |
| 1082 | /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */ |
| 1083 | fifo_partition |= value << 32; |
| 1084 | |
| 1085 | /* Program FIFO Partition registers - 128 bytes for each channel */ |
| 1086 | idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); |
| 1087 | idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); |
| 1088 | } |
| 1089 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1090 | static void dw_dma_off(struct dw_dma *dw) |
| 1091 | { |
Andy Shevchenko | 7794e5b | 2016-03-18 16:24:48 +0200 | [diff] [blame] | 1092 | unsigned int i; |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1093 | |
| 1094 | dma_writel(dw, CFG, 0); |
| 1095 | |
| 1096 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
Mans Rullgard | 2895b2c | 2016-01-11 13:04:29 +0000 | [diff] [blame] | 1097 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1098 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
| 1099 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); |
| 1100 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
| 1101 | |
| 1102 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) |
| 1103 | cpu_relax(); |
| 1104 | |
| 1105 | for (i = 0; i < dw->dma.chancnt; i++) |
Andy Shevchenko | 423f9cb | 2016-03-18 16:24:52 +0200 | [diff] [blame] | 1106 | clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1107 | } |
| 1108 | |
| 1109 | static void dw_dma_on(struct dw_dma *dw) |
| 1110 | { |
| 1111 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
| 1112 | } |
| 1113 | |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 1114 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1115 | { |
| 1116 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1117 | struct dw_dma *dw = to_dw_dma(chan->device); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1118 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1119 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1120 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1121 | /* ASSERT: channel is idle */ |
| 1122 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
Dan Williams | 41d5e59 | 2009-01-06 11:38:21 -0700 | [diff] [blame] | 1123 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1124 | return -EIO; |
| 1125 | } |
| 1126 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1127 | dma_cookie_init(chan); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1128 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1129 | /* |
| 1130 | * NOTE: some controllers may have additional features that we |
| 1131 | * need to initialize here, like "scatter-gather" (which |
| 1132 | * doesn't mean what you think it means), and status writeback. |
| 1133 | */ |
| 1134 | |
Andy Shevchenko | 3fe6409 | 2016-04-08 16:22:17 +0300 | [diff] [blame] | 1135 | /* |
| 1136 | * We need controller-specific data to set up slave transfers. |
| 1137 | */ |
| 1138 | if (chan->private && !dw_dma_filter(chan, chan->private)) { |
| 1139 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); |
| 1140 | return -EINVAL; |
| 1141 | } |
| 1142 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1143 | /* Enable controller here if needed */ |
| 1144 | if (!dw->in_use) |
| 1145 | dw_dma_on(dw); |
| 1146 | dw->in_use |= dwc->mask; |
| 1147 | |
Christian Lamparter | ab703f8 | 2016-04-14 18:11:01 +0200 | [diff] [blame] | 1148 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1149 | } |
| 1150 | |
| 1151 | static void dwc_free_chan_resources(struct dma_chan *chan) |
| 1152 | { |
| 1153 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
| 1154 | struct dw_dma *dw = to_dw_dma(chan->device); |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1155 | unsigned long flags; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1156 | LIST_HEAD(list); |
| 1157 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1158 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1159 | dwc->descs_allocated); |
| 1160 | |
| 1161 | /* ASSERT: channel is idle */ |
| 1162 | BUG_ON(!list_empty(&dwc->active_list)); |
| 1163 | BUG_ON(!list_empty(&dwc->queue)); |
| 1164 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); |
| 1165 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1166 | spin_lock_irqsave(&dwc->lock, flags); |
Andy Shevchenko | 3fe6409 | 2016-04-08 16:22:17 +0300 | [diff] [blame] | 1167 | |
| 1168 | /* Clear custom channel configuration */ |
Andy Shevchenko | 9217a5b | 2016-08-17 19:20:20 +0300 | [diff] [blame] | 1169 | memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); |
Andy Shevchenko | 3fe6409 | 2016-04-08 16:22:17 +0300 | [diff] [blame] | 1170 | |
Andy Shevchenko | 423f9cb | 2016-03-18 16:24:52 +0200 | [diff] [blame] | 1171 | clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1172 | |
| 1173 | /* Disable interrupts */ |
| 1174 | channel_clear_bit(dw, MASK.XFER, dwc->mask); |
Mans Rullgard | 2895b2c | 2016-01-11 13:04:29 +0000 | [diff] [blame] | 1175 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1176 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
| 1177 | |
Viresh Kumar | 69cea5a | 2011-04-15 16:03:35 +0530 | [diff] [blame] | 1178 | spin_unlock_irqrestore(&dwc->lock, flags); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1179 | |
Andy Shevchenko | 99d9bf4 | 2014-09-23 17:18:14 +0300 | [diff] [blame] | 1180 | /* Disable controller in case it was a last user */ |
| 1181 | dw->in_use &= ~dwc->mask; |
| 1182 | if (!dw->in_use) |
| 1183 | dw_dma_off(dw); |
| 1184 | |
Andy Shevchenko | 2e4c364 | 2012-06-19 13:34:05 +0300 | [diff] [blame] | 1185 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1186 | } |
| 1187 | |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 1188 | int dw_dma_probe(struct dw_dma_chip *chip) |
Viresh Kumar | a9ddb57 | 2012-10-16 09:49:17 +0530 | [diff] [blame] | 1189 | { |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 1190 | struct dw_dma_platform_data *pdata; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1191 | struct dw_dma *dw; |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1192 | bool autocfg = false; |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1193 | unsigned int dw_params; |
Andy Shevchenko | 7794e5b | 2016-03-18 16:24:48 +0200 | [diff] [blame] | 1194 | unsigned int i; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1195 | int err; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1196 | |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1197 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
| 1198 | if (!dw) |
| 1199 | return -ENOMEM; |
| 1200 | |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1201 | dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); |
| 1202 | if (!dw->pdata) |
| 1203 | return -ENOMEM; |
| 1204 | |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1205 | dw->regs = chip->regs; |
| 1206 | chip->dw = dw; |
| 1207 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1208 | pm_runtime_get_sync(chip->dev); |
| 1209 | |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 1210 | if (!chip->pdata) { |
Andy Shevchenko | 897e40d | 2016-03-18 16:24:46 +0200 | [diff] [blame] | 1211 | dw_params = dma_readl(dw, DW_PARAMS); |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1212 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
Andy Shevchenko | 482c67e | 2012-09-21 15:05:46 +0300 | [diff] [blame] | 1213 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1214 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
| 1215 | if (!autocfg) { |
| 1216 | err = -EINVAL; |
| 1217 | goto err_pdata; |
| 1218 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1219 | |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1220 | /* Reassign the platform data pointer */ |
| 1221 | pdata = dw->pdata; |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1222 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1223 | /* Get hardware configuration parameters */ |
| 1224 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; |
| 1225 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
| 1226 | for (i = 0; i < pdata->nr_masters; i++) { |
| 1227 | pdata->data_width[i] = |
Andy Shevchenko | 2e65060 | 2016-04-27 14:15:38 +0300 | [diff] [blame] | 1228 | 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1229 | } |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1230 | pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1231 | |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1232 | /* Fill platform data with the default values */ |
| 1233 | pdata->is_private = true; |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1234 | pdata->is_memcpy = true; |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1235 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
| 1236 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 1237 | } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1238 | err = -EINVAL; |
| 1239 | goto err_pdata; |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1240 | } else { |
Andy Shevchenko | 3a14c66 | 2016-04-27 14:15:40 +0300 | [diff] [blame] | 1241 | memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1242 | |
| 1243 | /* Reassign the platform data pointer */ |
| 1244 | pdata = dw->pdata; |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1245 | } |
Andy Shevchenko | 123de54 | 2013-01-09 10:17:01 +0200 | [diff] [blame] | 1246 | |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1247 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
Andy Shevchenko | 000871c | 2014-03-05 15:48:12 +0200 | [diff] [blame] | 1248 | GFP_KERNEL); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1249 | if (!dw->chan) { |
| 1250 | err = -ENOMEM; |
| 1251 | goto err_pdata; |
| 1252 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1253 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1254 | /* Calculate all channel mask before DMA setup */ |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1255 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1256 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1257 | /* Force dma off, just in case */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1258 | dw_dma_off(dw); |
| 1259 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 1260 | idma32_fifo_partition(dw); |
| 1261 | |
Andy Shevchenko | 08d62f5 | 2017-01-17 13:57:26 +0200 | [diff] [blame] | 1262 | /* Device and instance ID for IRQ and DMA pool */ |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 1263 | if (pdata->is_idma32) |
| 1264 | snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id); |
| 1265 | else |
| 1266 | snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id); |
Andy Shevchenko | 08d62f5 | 2017-01-17 13:57:26 +0200 | [diff] [blame] | 1267 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1268 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
Andy Shevchenko | 08d62f5 | 2017-01-17 13:57:26 +0200 | [diff] [blame] | 1269 | dw->desc_pool = dmam_pool_create(dw->name, chip->dev, |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1270 | sizeof(struct dw_desc), 4, 0); |
| 1271 | if (!dw->desc_pool) { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1272 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1273 | err = -ENOMEM; |
| 1274 | goto err_pdata; |
Andy Shevchenko | f8122a8 | 2013-01-16 15:48:50 +0200 | [diff] [blame] | 1275 | } |
| 1276 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1277 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
| 1278 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1279 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
Andy Shevchenko | 08d62f5 | 2017-01-17 13:57:26 +0200 | [diff] [blame] | 1280 | dw->name, dw); |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1281 | if (err) |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1282 | goto err_pdata; |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1283 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1284 | INIT_LIST_HEAD(&dw->dma.channels); |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1285 | for (i = 0; i < pdata->nr_channels; i++) { |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1286 | struct dw_dma_chan *dwc = &dw->chan[i]; |
| 1287 | |
| 1288 | dwc->chan.device = &dw->dma; |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 1289 | dma_cookie_init(&dwc->chan); |
Viresh Kumar | b0c3130 | 2011-03-03 15:47:21 +0530 | [diff] [blame] | 1290 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
| 1291 | list_add_tail(&dwc->chan.device_node, |
| 1292 | &dw->dma.channels); |
| 1293 | else |
| 1294 | list_add(&dwc->chan.device_node, &dw->dma.channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1295 | |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1296 | /* 7 is highest priority & 0 is lowest. */ |
| 1297 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1298 | dwc->priority = pdata->nr_channels - i - 1; |
Viresh Kumar | 93317e8 | 2011-03-03 15:47:22 +0530 | [diff] [blame] | 1299 | else |
| 1300 | dwc->priority = i; |
| 1301 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1302 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
| 1303 | spin_lock_init(&dwc->lock); |
| 1304 | dwc->mask = 1 << i; |
| 1305 | |
| 1306 | INIT_LIST_HEAD(&dwc->active_list); |
| 1307 | INIT_LIST_HEAD(&dwc->queue); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1308 | |
| 1309 | channel_clear_bit(dw, CH_EN, dwc->mask); |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1310 | |
Andy Shevchenko | 0fdb567 | 2013-01-10 10:53:03 +0200 | [diff] [blame] | 1311 | dwc->direction = DMA_TRANS_NONE; |
Andy Shevchenko | a098200 | 2012-09-21 15:05:48 +0300 | [diff] [blame] | 1312 | |
Andy Shevchenko | 75c6122 | 2013-03-26 16:53:54 +0200 | [diff] [blame] | 1313 | /* Hardware configuration */ |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1314 | if (autocfg) { |
Andy Shevchenko | 6bea0f6 | 2015-09-28 18:57:03 +0300 | [diff] [blame] | 1315 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
Andy Shevchenko | 897e40d | 2016-03-18 16:24:46 +0200 | [diff] [blame] | 1316 | void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; |
Andy Shevchenko | 14bebd0 | 2017-05-09 19:18:37 +0300 | [diff] [blame] | 1317 | unsigned int dwc_params = readl(addr); |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1318 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1319 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
| 1320 | dwc_params); |
Andy Shevchenko | 985a6c7 | 2013-01-18 17:10:59 +0200 | [diff] [blame] | 1321 | |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1322 | /* |
| 1323 | * Decode maximum block size for given channel. The |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1324 | * stored 4 bit value represents blocks from 0x00 for 3 |
Andy Shevchenko | 1d566f1 | 2014-01-13 14:04:48 +0200 | [diff] [blame] | 1325 | * up to 0x0a for 4095. |
| 1326 | */ |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1327 | dwc->block_size = |
Andy Shevchenko | 161c3d0 | 2016-04-27 14:15:39 +0300 | [diff] [blame] | 1328 | (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1329 | dwc->nollp = |
| 1330 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; |
| 1331 | } else { |
Andy Shevchenko | 4a63a8b | 2012-09-21 15:05:47 +0300 | [diff] [blame] | 1332 | dwc->block_size = pdata->block_size; |
Eugeniy Paltsev | bd2c663 | 2016-11-25 17:59:07 +0300 | [diff] [blame] | 1333 | dwc->nollp = !pdata->multi_block[i]; |
Andy Shevchenko | fed2574 | 2012-09-21 15:05:49 +0300 | [diff] [blame] | 1334 | } |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1335 | } |
| 1336 | |
Andy Shevchenko | 11f932e | 2012-06-19 13:34:06 +0300 | [diff] [blame] | 1337 | /* Clear all interrupts on all channels. */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1338 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
Andy Shevchenko | 236b106 | 2012-06-19 13:34:07 +0300 | [diff] [blame] | 1339 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1340 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
| 1341 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); |
| 1342 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); |
| 1343 | |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1344 | /* Set capabilities */ |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1345 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
Jamie Iles | 95ea759 | 2011-01-21 14:11:54 +0000 | [diff] [blame] | 1346 | if (pdata->is_private) |
| 1347 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); |
Andy Shevchenko | df5c738 | 2015-10-13 20:09:19 +0300 | [diff] [blame] | 1348 | if (pdata->is_memcpy) |
| 1349 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
| 1350 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1351 | dw->dma.dev = chip->dev; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1352 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
| 1353 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; |
| 1354 | |
| 1355 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1356 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 1357 | |
Maxime Ripard | a4b0d34 | 2014-11-17 14:42:12 +0100 | [diff] [blame] | 1358 | dw->dma.device_config = dwc_config; |
| 1359 | dw->dma.device_pause = dwc_pause; |
| 1360 | dw->dma.device_resume = dwc_resume; |
| 1361 | dw->dma.device_terminate_all = dwc_terminate_all; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1362 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1363 | dw->dma.device_tx_status = dwc_tx_status; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1364 | dw->dma.device_issue_pending = dwc_issue_pending; |
| 1365 | |
Andy Shevchenko | 029a40e | 2015-01-02 16:17:24 +0200 | [diff] [blame] | 1366 | /* DMA capabilities */ |
| 1367 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; |
| 1368 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; |
| 1369 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | |
| 1370 | BIT(DMA_MEM_TO_MEM); |
| 1371 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
| 1372 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1373 | err = dma_async_device_register(&dw->dma); |
| 1374 | if (err) |
| 1375 | goto err_dma_register; |
| 1376 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1377 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
Andy Shevchenko | 30cb263 | 2015-10-13 20:09:17 +0300 | [diff] [blame] | 1378 | pdata->nr_channels); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1379 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1380 | pm_runtime_put_sync_suspend(chip->dev); |
| 1381 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1382 | return 0; |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1383 | |
Andy Shevchenko | 1222934 | 2014-05-08 12:01:50 +0300 | [diff] [blame] | 1384 | err_dma_register: |
| 1385 | free_irq(chip->irq, dw); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1386 | err_pdata: |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1387 | pm_runtime_put_sync_suspend(chip->dev); |
Andy Shevchenko | 8be4f52 | 2014-05-08 12:01:49 +0300 | [diff] [blame] | 1388 | return err; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1389 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1390 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1391 | |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1392 | int dw_dma_remove(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1393 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1394 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1395 | struct dw_dma_chan *dwc, *_dwc; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1396 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1397 | pm_runtime_get_sync(chip->dev); |
| 1398 | |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1399 | dw_dma_off(dw); |
| 1400 | dma_async_device_unregister(&dw->dma); |
| 1401 | |
Andy Shevchenko | 97977f7 | 2014-05-07 10:56:24 +0300 | [diff] [blame] | 1402 | free_irq(chip->irq, dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1403 | tasklet_kill(&dw->tasklet); |
| 1404 | |
| 1405 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, |
| 1406 | chan.device_node) { |
| 1407 | list_del(&dwc->chan.device_node); |
| 1408 | channel_clear_bit(dw, CH_EN, dwc->mask); |
| 1409 | } |
| 1410 | |
Andy Shevchenko | bb32baf | 2014-11-05 18:34:48 +0200 | [diff] [blame] | 1411 | pm_runtime_put_sync_suspend(chip->dev); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1412 | return 0; |
| 1413 | } |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1414 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1415 | |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1416 | int dw_dma_disable(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1417 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1418 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1419 | |
Andy Shevchenko | 6168d56 | 2012-10-18 17:34:10 +0300 | [diff] [blame] | 1420 | dw_dma_off(dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1421 | return 0; |
| 1422 | } |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1423 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1424 | |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1425 | int dw_dma_enable(struct dw_dma_chip *chip) |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1426 | { |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1427 | struct dw_dma *dw = chip->dw; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1428 | |
Andy Shevchenko | 199244d | 2017-01-17 13:57:31 +0200 | [diff] [blame] | 1429 | idma32_fifo_partition(dw); |
| 1430 | |
Andy Shevchenko | 7a83c04 | 2014-09-23 17:18:12 +0300 | [diff] [blame] | 1431 | dw_dma_on(dw); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1432 | return 0; |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1433 | } |
Andy Shevchenko | 2540f74 | 2014-09-23 17:18:13 +0300 | [diff] [blame] | 1434 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame] | 1435 | |
| 1436 | MODULE_LICENSE("GPL v2"); |
Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 1437 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
Jean Delvare | e05503e | 2011-05-18 16:49:24 +0200 | [diff] [blame] | 1438 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
Viresh Kumar | da89947 | 2015-07-17 16:23:50 -0700 | [diff] [blame] | 1439 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |