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Florian Fainelli246d7f72014-08-27 17:04:56 -07001/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
Florian Fainelli8b7c94e2015-10-23 12:11:08 -070024#include <linux/of_net.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070025#include <net/dsa.h>
Florian Fainelli96e65d72014-09-18 17:31:25 -070026#include <linux/ethtool.h>
Florian Fainelli12f460f2015-02-24 13:15:34 -080027#include <linux/if_bridge.h>
Florian Fainelliaafc66f2015-06-10 18:08:01 -070028#include <linux/brcmphy.h>
Florian Fainelli680060d2015-10-23 11:38:07 -070029#include <linux/etherdevice.h>
30#include <net/switchdev.h>
Florian Fainelli246d7f72014-08-27 17:04:56 -070031
32#include "bcm_sf2.h"
33#include "bcm_sf2_regs.h"
34
35/* String, offset, and register size in bytes if different from 4 bytes */
36static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
37 { "TxOctets", 0x000, 8 },
38 { "TxDropPkts", 0x020 },
39 { "TxQPKTQ0", 0x030 },
40 { "TxBroadcastPkts", 0x040 },
41 { "TxMulticastPkts", 0x050 },
42 { "TxUnicastPKts", 0x060 },
43 { "TxCollisions", 0x070 },
44 { "TxSingleCollision", 0x080 },
45 { "TxMultipleCollision", 0x090 },
46 { "TxDeferredCollision", 0x0a0 },
47 { "TxLateCollision", 0x0b0 },
48 { "TxExcessiveCollision", 0x0c0 },
49 { "TxFrameInDisc", 0x0d0 },
50 { "TxPausePkts", 0x0e0 },
51 { "TxQPKTQ1", 0x0f0 },
52 { "TxQPKTQ2", 0x100 },
53 { "TxQPKTQ3", 0x110 },
54 { "TxQPKTQ4", 0x120 },
55 { "TxQPKTQ5", 0x130 },
56 { "RxOctets", 0x140, 8 },
57 { "RxUndersizePkts", 0x160 },
58 { "RxPausePkts", 0x170 },
59 { "RxPkts64Octets", 0x180 },
60 { "RxPkts65to127Octets", 0x190 },
61 { "RxPkts128to255Octets", 0x1a0 },
62 { "RxPkts256to511Octets", 0x1b0 },
63 { "RxPkts512to1023Octets", 0x1c0 },
64 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
65 { "RxOversizePkts", 0x1e0 },
66 { "RxJabbers", 0x1f0 },
67 { "RxAlignmentErrors", 0x200 },
68 { "RxFCSErrors", 0x210 },
69 { "RxGoodOctets", 0x220, 8 },
70 { "RxDropPkts", 0x240 },
71 { "RxUnicastPkts", 0x250 },
72 { "RxMulticastPkts", 0x260 },
73 { "RxBroadcastPkts", 0x270 },
74 { "RxSAChanges", 0x280 },
75 { "RxFragments", 0x290 },
76 { "RxJumboPkt", 0x2a0 },
77 { "RxSymblErr", 0x2b0 },
78 { "InRangeErrCount", 0x2c0 },
79 { "OutRangeErrCount", 0x2d0 },
80 { "EEELpiEvent", 0x2e0 },
81 { "EEELpiDuration", 0x2f0 },
82 { "RxDiscard", 0x300, 8 },
83 { "TxQPKTQ6", 0x320 },
84 { "TxQPKTQ7", 0x330 },
85 { "TxPkts64Octets", 0x340 },
86 { "TxPkts65to127Octets", 0x350 },
87 { "TxPkts128to255Octets", 0x360 },
88 { "TxPkts256to511Ocets", 0x370 },
89 { "TxPkts512to1023Ocets", 0x380 },
90 { "TxPkts1024toMaxPktOcets", 0x390 },
91};
92
93#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
94
95static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
96 int port, uint8_t *data)
97{
98 unsigned int i;
99
100 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
101 memcpy(data + i * ETH_GSTRING_LEN,
102 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
103}
104
105static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
106 int port, uint64_t *data)
107{
108 struct bcm_sf2_priv *priv = ds_to_priv(ds);
109 const struct bcm_sf2_hw_stats *s;
110 unsigned int i;
111 u64 val = 0;
112 u32 offset;
113
114 mutex_lock(&priv->stats_mutex);
115
116 /* Now fetch the per-port counters */
117 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
118 s = &bcm_sf2_mib[i];
119
120 /* Do a latched 64-bit read if needed */
121 offset = s->reg + CORE_P_MIB_OFFSET(port);
122 if (s->sizeof_stat == 8)
123 val = core_readq(priv, offset);
124 else
125 val = core_readl(priv, offset);
126
127 data[i] = (u64)val;
128 }
129
130 mutex_unlock(&priv->stats_mutex);
131}
132
133static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
134{
135 return BCM_SF2_STATS_SIZE;
136}
137
Alexander Duyckb4d23942014-09-15 13:00:27 -0400138static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700139{
140 return "Broadcom Starfighter 2";
141}
142
Florian Fainellib6d045d2014-09-24 17:05:20 -0700143static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700144{
145 struct bcm_sf2_priv *priv = ds_to_priv(ds);
146 unsigned int i;
Florian Fainellib6d045d2014-09-24 17:05:20 -0700147 u32 reg;
148
149 /* Enable the IMP Port to be in the same VLAN as the other ports
150 * on a per-port basis such that we only have Port i and IMP in
151 * the same VLAN.
152 */
153 for (i = 0; i < priv->hw_params.num_ports; i++) {
154 if (!((1 << i) & ds->phys_port_mask))
155 continue;
156
157 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
158 reg |= (1 << cpu_port);
159 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
160 }
161}
162
163static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
164{
165 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700166 u32 reg, val;
167
168 /* Enable the port memories */
169 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
170 reg &= ~P_TXQ_PSM_VDD(port);
171 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
172
173 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
174 reg = core_readl(priv, CORE_IMP_CTL);
175 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
176 reg &= ~(RX_DIS | TX_DIS);
177 core_writel(priv, reg, CORE_IMP_CTL);
178
179 /* Enable forwarding */
180 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
181
182 /* Enable IMP port in dumb mode */
183 reg = core_readl(priv, CORE_SWITCH_CTRL);
184 reg |= MII_DUMB_FWDG_EN;
185 core_writel(priv, reg, CORE_SWITCH_CTRL);
186
187 /* Resolve which bit controls the Broadcom tag */
188 switch (port) {
189 case 8:
190 val = BRCM_HDR_EN_P8;
191 break;
192 case 7:
193 val = BRCM_HDR_EN_P7;
194 break;
195 case 5:
196 val = BRCM_HDR_EN_P5;
197 break;
198 default:
199 val = 0;
200 break;
201 }
202
203 /* Enable Broadcom tags for IMP port */
204 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
205 reg |= val;
206 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
207
208 /* Enable reception Broadcom tag for CPU TX (switch RX) to
209 * allow us to tag outgoing frames
210 */
211 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
212 reg &= ~(1 << port);
213 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
214
215 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
216 * allow delivering frames to the per-port net_devices
217 */
218 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
219 reg &= ~(1 << port);
220 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
221
222 /* Force link status for IMP port */
223 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
224 reg |= (MII_SW_OR | LINK_STS);
225 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700226}
227
Florian Fainelli450b05c2014-09-24 17:05:22 -0700228static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
229{
230 struct bcm_sf2_priv *priv = ds_to_priv(ds);
231 u32 reg;
232
233 reg = core_readl(priv, CORE_EEE_EN_CTRL);
234 if (enable)
235 reg |= 1 << port;
236 else
237 reg &= ~(1 << port);
238 core_writel(priv, reg, CORE_EEE_EN_CTRL);
239}
240
Florian Fainellib0836682015-02-05 11:40:41 -0800241static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
242{
243 struct bcm_sf2_priv *priv = ds_to_priv(ds);
244 u32 reg;
245
Florian Fainelli9af197a2015-02-05 11:40:42 -0800246 reg = reg_readl(priv, REG_SPHY_CNTRL);
247 if (enable) {
248 reg |= PHY_RESET;
249 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
250 reg_writel(priv, reg, REG_SPHY_CNTRL);
251 udelay(21);
252 reg = reg_readl(priv, REG_SPHY_CNTRL);
253 reg &= ~PHY_RESET;
254 } else {
255 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
256 reg_writel(priv, reg, REG_SPHY_CNTRL);
257 mdelay(1);
258 reg |= CK25_DIS;
259 }
260 reg_writel(priv, reg, REG_SPHY_CNTRL);
Florian Fainellib0836682015-02-05 11:40:41 -0800261
Florian Fainelli9af197a2015-02-05 11:40:42 -0800262 /* Use PHY-driven LED signaling */
263 if (!enable) {
264 reg = reg_readl(priv, REG_LED_CNTRL(0));
265 reg |= SPDLNK_SRC_SEL;
266 reg_writel(priv, reg, REG_LED_CNTRL(0));
267 }
Florian Fainellib0836682015-02-05 11:40:41 -0800268}
269
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700270static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
271 int port)
272{
273 unsigned int off;
274
275 switch (port) {
276 case 7:
277 off = P7_IRQ_OFF;
278 break;
279 case 0:
280 /* Port 0 interrupts are located on the first bank */
281 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
282 return;
283 default:
284 off = P_IRQ_OFF(port);
285 break;
286 }
287
288 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
289}
290
291static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
292 int port)
293{
294 unsigned int off;
295
296 switch (port) {
297 case 7:
298 off = P7_IRQ_OFF;
299 break;
300 case 0:
301 /* Port 0 interrupts are located on the first bank */
302 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
303 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
304 return;
305 default:
306 off = P_IRQ_OFF(port);
307 break;
308 }
309
310 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
311 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
312}
313
Florian Fainellib6d045d2014-09-24 17:05:20 -0700314static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
315 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700316{
317 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700318 s8 cpu_port = ds->dst[ds->index].cpu_port;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700319 u32 reg;
320
321 /* Clear the memory power down */
322 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
323 reg &= ~P_TXQ_PSM_VDD(port);
324 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
325
326 /* Clear the Rx and Tx disable bits and set to no spanning tree */
327 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
328
Florian Fainelli9af197a2015-02-05 11:40:42 -0800329 /* Re-enable the GPHY and re-apply workarounds */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700330 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
Florian Fainelli9af197a2015-02-05 11:40:42 -0800331 bcm_sf2_gphy_enable_set(ds, true);
332 if (phy) {
333 /* if phy_stop() has been called before, phy
334 * will be in halted state, and phy_start()
335 * will call resume.
336 *
337 * the resume path does not configure back
338 * autoneg settings, and since we hard reset
339 * the phy manually here, we need to reset the
340 * state machine also.
341 */
342 phy->state = PHY_READY;
343 phy_init_hw(phy);
344 }
345 }
346
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700347 /* Enable MoCA port interrupts to get notified */
348 if (port == priv->moca_port)
349 bcm_sf2_port_intr_enable(priv, port);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700350
Florian Fainelli12f460f2015-02-24 13:15:34 -0800351 /* Set this port, and only this one to be in the default VLAN,
352 * if member of a bridge, restore its membership prior to
353 * bringing down this port.
354 */
Florian Fainelli246d7f72014-08-27 17:04:56 -0700355 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
356 reg &= ~PORT_VLAN_CTRL_MASK;
357 reg |= (1 << port);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800358 reg |= priv->port_sts[port].vlan_ctl_mask;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700359 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
Florian Fainellib6d045d2014-09-24 17:05:20 -0700360
361 bcm_sf2_imp_vlan_setup(ds, cpu_port);
362
Florian Fainelli450b05c2014-09-24 17:05:22 -0700363 /* If EEE was enabled, restore it */
364 if (priv->port_sts[port].eee.eee_enabled)
365 bcm_sf2_eee_enable_set(ds, port, true);
366
Florian Fainellib6d045d2014-09-24 17:05:20 -0700367 return 0;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700368}
369
Florian Fainellib6d045d2014-09-24 17:05:20 -0700370static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
371 struct phy_device *phy)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700372{
373 struct bcm_sf2_priv *priv = ds_to_priv(ds);
374 u32 off, reg;
375
Florian Fainelli96e65d72014-09-18 17:31:25 -0700376 if (priv->wol_ports_mask & (1 << port))
377 return;
378
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700379 if (port == priv->moca_port)
380 bcm_sf2_port_intr_disable(priv, port);
Florian Fainellib6d045d2014-09-24 17:05:20 -0700381
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700382 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
Florian Fainelli9af197a2015-02-05 11:40:42 -0800383 bcm_sf2_gphy_enable_set(ds, false);
384
Florian Fainelli246d7f72014-08-27 17:04:56 -0700385 if (dsa_is_cpu_port(ds, port))
386 off = CORE_IMP_CTL;
387 else
388 off = CORE_G_PCTL_PORT(port);
389
390 reg = core_readl(priv, off);
391 reg |= RX_DIS | TX_DIS;
392 core_writel(priv, reg, off);
393
394 /* Power down the port memory */
395 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
396 reg |= P_TXQ_PSM_VDD(port);
397 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
398}
399
Florian Fainelli450b05c2014-09-24 17:05:22 -0700400/* Returns 0 if EEE was not enabled, or 1 otherwise
401 */
402static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
403 struct phy_device *phy)
404{
405 struct bcm_sf2_priv *priv = ds_to_priv(ds);
406 struct ethtool_eee *p = &priv->port_sts[port].eee;
407 int ret;
408
409 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
410
411 ret = phy_init_eee(phy, 0);
412 if (ret)
413 return 0;
414
415 bcm_sf2_eee_enable_set(ds, port, true);
416
417 return 1;
418}
419
420static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
421 struct ethtool_eee *e)
422{
423 struct bcm_sf2_priv *priv = ds_to_priv(ds);
424 struct ethtool_eee *p = &priv->port_sts[port].eee;
425 u32 reg;
426
427 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
428 e->eee_enabled = p->eee_enabled;
429 e->eee_active = !!(reg & (1 << port));
430
431 return 0;
432}
433
434static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
435 struct phy_device *phydev,
436 struct ethtool_eee *e)
437{
438 struct bcm_sf2_priv *priv = ds_to_priv(ds);
439 struct ethtool_eee *p = &priv->port_sts[port].eee;
440
441 p->eee_enabled = e->eee_enabled;
442
443 if (!p->eee_enabled) {
444 bcm_sf2_eee_enable_set(ds, port, false);
445 } else {
446 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
447 if (!p->eee_enabled)
448 return -EOPNOTSUPP;
449 }
450
451 return 0;
452}
453
Florian Fainelli12f460f2015-02-24 13:15:34 -0800454/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
455 * flush for that port.
456 */
457static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
458{
459 struct bcm_sf2_priv *priv = ds_to_priv(ds);
460 unsigned int timeout = 1000;
461 u32 reg;
462
463 core_writel(priv, port, CORE_FAST_AGE_PORT);
464
465 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
Florian Fainelli39797a22015-09-05 13:07:27 -0700466 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800467 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
468
469 do {
470 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
471 if (!(reg & FAST_AGE_STR_DONE))
472 break;
473
474 cpu_relax();
475 } while (timeout--);
476
477 if (!timeout)
478 return -ETIMEDOUT;
479
Florian Fainelli39797a22015-09-05 13:07:27 -0700480 core_writel(priv, 0, CORE_FAST_AGE_CTRL);
481
Florian Fainelli12f460f2015-02-24 13:15:34 -0800482 return 0;
483}
484
485static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
Vivien Didelota6692752016-02-12 12:09:39 -0500486 struct net_device *bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800487{
488 struct bcm_sf2_priv *priv = ds_to_priv(ds);
489 unsigned int i;
490 u32 reg, p_ctl;
491
Vivien Didelota6692752016-02-12 12:09:39 -0500492 priv->port_sts[port].bridge_dev = bridge;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800493 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
494
495 for (i = 0; i < priv->hw_params.num_ports; i++) {
Vivien Didelota6692752016-02-12 12:09:39 -0500496 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800497 continue;
498
499 /* Add this local port to the remote port VLAN control
500 * membership and update the remote port bitmask
501 */
502 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
503 reg |= 1 << port;
504 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
505 priv->port_sts[i].vlan_ctl_mask = reg;
506
507 p_ctl |= 1 << i;
508 }
509
510 /* Configure the local port VLAN control membership to include
511 * remote ports and update the local port bitmask
512 */
513 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
514 priv->port_sts[port].vlan_ctl_mask = p_ctl;
515
516 return 0;
517}
518
Vivien Didelot16bfa702016-03-13 16:21:33 -0400519static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800520{
521 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Vivien Didelota6692752016-02-12 12:09:39 -0500522 struct net_device *bridge = priv->port_sts[port].bridge_dev;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800523 unsigned int i;
524 u32 reg, p_ctl;
525
526 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
527
528 for (i = 0; i < priv->hw_params.num_ports; i++) {
529 /* Don't touch the remaining ports */
Vivien Didelota6692752016-02-12 12:09:39 -0500530 if (priv->port_sts[i].bridge_dev != bridge)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800531 continue;
532
533 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
534 reg &= ~(1 << port);
535 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
536 priv->port_sts[port].vlan_ctl_mask = reg;
537
538 /* Prevent self removal to preserve isolation */
539 if (port != i)
540 p_ctl &= ~(1 << i);
541 }
542
543 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
544 priv->port_sts[port].vlan_ctl_mask = p_ctl;
Vivien Didelota6692752016-02-12 12:09:39 -0500545 priv->port_sts[port].bridge_dev = NULL;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800546}
547
Vivien Didelot43c44a92016-04-06 11:55:03 -0400548static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
549 u8 state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800550{
551 struct bcm_sf2_priv *priv = ds_to_priv(ds);
552 u8 hw_state, cur_hw_state;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800553 u32 reg;
554
555 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
Florian Fainelli39797a22015-09-05 13:07:27 -0700556 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
Florian Fainelli12f460f2015-02-24 13:15:34 -0800557
558 switch (state) {
559 case BR_STATE_DISABLED:
560 hw_state = G_MISTP_DIS_STATE;
561 break;
562 case BR_STATE_LISTENING:
563 hw_state = G_MISTP_LISTEN_STATE;
564 break;
565 case BR_STATE_LEARNING:
566 hw_state = G_MISTP_LEARN_STATE;
567 break;
568 case BR_STATE_FORWARDING:
569 hw_state = G_MISTP_FWD_STATE;
570 break;
571 case BR_STATE_BLOCKING:
572 hw_state = G_MISTP_BLOCK_STATE;
573 break;
574 default:
575 pr_err("%s: invalid STP state: %d\n", __func__, state);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400576 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800577 }
578
579 /* Fast-age ARL entries if we are moving a port from Learning or
Florian Fainelli39797a22015-09-05 13:07:27 -0700580 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
581 * state (hw_state)
Florian Fainelli12f460f2015-02-24 13:15:34 -0800582 */
583 if (cur_hw_state != hw_state) {
Florian Fainelli39797a22015-09-05 13:07:27 -0700584 if (cur_hw_state >= G_MISTP_LEARN_STATE &&
585 hw_state <= G_MISTP_LISTEN_STATE) {
Vivien Didelot43c44a92016-04-06 11:55:03 -0400586 if (bcm_sf2_sw_fast_age_port(ds, port)) {
Florian Fainelli12f460f2015-02-24 13:15:34 -0800587 pr_err("%s: fast-ageing failed\n", __func__);
Vivien Didelot43c44a92016-04-06 11:55:03 -0400588 return;
Florian Fainelli12f460f2015-02-24 13:15:34 -0800589 }
590 }
591 }
592
593 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
594 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
595 reg |= hw_state;
596 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
Florian Fainelli12f460f2015-02-24 13:15:34 -0800597}
598
Florian Fainelli680060d2015-10-23 11:38:07 -0700599/* Address Resolution Logic routines */
600static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv)
601{
602 unsigned int timeout = 10;
603 u32 reg;
604
605 do {
606 reg = core_readl(priv, CORE_ARLA_RWCTL);
607 if (!(reg & ARL_STRTDN))
608 return 0;
609
610 usleep_range(1000, 2000);
611 } while (timeout--);
612
613 return -ETIMEDOUT;
614}
615
616static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op)
617{
618 u32 cmd;
619
620 if (op > ARL_RW)
621 return -EINVAL;
622
623 cmd = core_readl(priv, CORE_ARLA_RWCTL);
624 cmd &= ~IVL_SVL_SELECT;
625 cmd |= ARL_STRTDN;
626 if (op)
627 cmd |= ARL_RW;
628 else
629 cmd &= ~ARL_RW;
630 core_writel(priv, cmd, CORE_ARLA_RWCTL);
631
632 return bcm_sf2_arl_op_wait(priv);
633}
634
635static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac,
636 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx,
637 bool is_valid)
638{
639 unsigned int i;
640 int ret;
641
642 ret = bcm_sf2_arl_op_wait(priv);
643 if (ret)
644 return ret;
645
646 /* Read the 4 bins */
647 for (i = 0; i < 4; i++) {
648 u64 mac_vid;
649 u32 fwd_entry;
650
651 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i));
652 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i));
653 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
654
655 if (ent->is_valid && is_valid) {
656 *idx = i;
657 return 0;
658 }
659
660 /* This is the MAC we just deleted */
661 if (!is_valid && (mac_vid & mac))
662 return 0;
663 }
664
665 return -ENOENT;
666}
667
668static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port,
669 const unsigned char *addr, u16 vid, bool is_valid)
670{
671 struct bcm_sf2_arl_entry ent;
672 u32 fwd_entry;
673 u64 mac, mac_vid = 0;
674 u8 idx = 0;
675 int ret;
676
677 /* Convert the array into a 64-bit MAC */
678 mac = bcm_sf2_mac_to_u64(addr);
679
680 /* Perform a read for the given MAC and VID */
681 core_writeq(priv, mac, CORE_ARLA_MAC);
682 core_writel(priv, vid, CORE_ARLA_VID);
683
684 /* Issue a read operation for this MAC */
685 ret = bcm_sf2_arl_rw_op(priv, 1);
686 if (ret)
687 return ret;
688
689 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
690 /* If this is a read, just finish now */
691 if (op)
692 return ret;
693
694 /* We could not find a matching MAC, so reset to a new entry */
695 if (ret) {
696 fwd_entry = 0;
697 idx = 0;
698 }
699
700 memset(&ent, 0, sizeof(ent));
701 ent.port = port;
702 ent.is_valid = is_valid;
703 ent.vid = vid;
704 ent.is_static = true;
705 memcpy(ent.mac, addr, ETH_ALEN);
706 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent);
707
708 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx));
709 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx));
710
711 ret = bcm_sf2_arl_rw_op(priv, 0);
712 if (ret)
713 return ret;
714
715 /* Re-read the entry to check */
716 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
717}
718
719static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port,
720 const struct switchdev_obj_port_fdb *fdb,
721 struct switchdev_trans *trans)
722{
723 /* We do not need to do anything specific here yet */
724 return 0;
725}
726
727static int bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port,
728 const struct switchdev_obj_port_fdb *fdb,
729 struct switchdev_trans *trans)
730{
731 struct bcm_sf2_priv *priv = ds_to_priv(ds);
732
733 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true);
734}
735
736static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port,
737 const struct switchdev_obj_port_fdb *fdb)
738{
739 struct bcm_sf2_priv *priv = ds_to_priv(ds);
740
741 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
742}
743
744static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv)
745{
746 unsigned timeout = 1000;
747 u32 reg;
748
749 do {
750 reg = core_readl(priv, CORE_ARLA_SRCH_CTL);
751 if (!(reg & ARLA_SRCH_STDN))
752 return 0;
753
754 if (reg & ARLA_SRCH_VLID)
755 return 0;
756
757 usleep_range(1000, 2000);
758 } while (timeout--);
759
760 return -ETIMEDOUT;
761}
762
763static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx,
764 struct bcm_sf2_arl_entry *ent)
765{
766 u64 mac_vid;
767 u32 fwd_entry;
768
769 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx));
770 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx));
771 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
772}
773
774static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port,
775 const struct bcm_sf2_arl_entry *ent,
776 struct switchdev_obj_port_fdb *fdb,
777 int (*cb)(struct switchdev_obj *obj))
778{
779 if (!ent->is_valid)
780 return 0;
781
782 if (port != ent->port)
783 return 0;
784
785 ether_addr_copy(fdb->addr, ent->mac);
786 fdb->vid = ent->vid;
787 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
788
789 return cb(&fdb->obj);
790}
791
792static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
793 struct switchdev_obj_port_fdb *fdb,
794 int (*cb)(struct switchdev_obj *obj))
795{
796 struct bcm_sf2_priv *priv = ds_to_priv(ds);
797 struct net_device *dev = ds->ports[port];
798 struct bcm_sf2_arl_entry results[2];
799 unsigned int count = 0;
800 int ret;
801
802 /* Start search operation */
803 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL);
804
805 do {
806 ret = bcm_sf2_arl_search_wait(priv);
807 if (ret)
808 return ret;
809
810 /* Read both entries, then return their values back */
811 bcm_sf2_arl_search_rd(priv, 0, &results[0]);
812 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb);
813 if (ret)
814 return ret;
815
816 bcm_sf2_arl_search_rd(priv, 1, &results[1]);
817 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb);
818 if (ret)
819 return ret;
820
821 if (!results[0].is_valid && !results[1].is_valid)
822 break;
823
824 } while (count++ < CORE_ARLA_NUM_ENTRIES);
825
826 return 0;
827}
828
Florian Fainelli246d7f72014-08-27 17:04:56 -0700829static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
830{
831 struct bcm_sf2_priv *priv = dev_id;
832
833 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
834 ~priv->irq0_mask;
835 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
836
837 return IRQ_HANDLED;
838}
839
840static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
841{
842 struct bcm_sf2_priv *priv = dev_id;
843
844 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
845 ~priv->irq1_mask;
846 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
847
848 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
849 priv->port_sts[7].link = 1;
850 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
851 priv->port_sts[7].link = 0;
852
853 return IRQ_HANDLED;
854}
855
Florian Fainelli33f84612014-11-25 18:08:49 -0800856static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
857{
858 unsigned int timeout = 1000;
859 u32 reg;
860
861 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
862 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
863 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
864
865 do {
866 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
867 if (!(reg & SOFTWARE_RESET))
868 break;
869
870 usleep_range(1000, 2000);
871 } while (timeout-- > 0);
872
873 if (timeout == 0)
874 return -ETIMEDOUT;
875
876 return 0;
877}
878
Florian Fainelli691c9a82015-01-20 16:42:00 -0800879static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
880{
881 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
882 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
883 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
884 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
885 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
886 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
887}
888
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700889static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
890 struct device_node *dn)
891{
892 struct device_node *port;
893 const char *phy_mode_str;
894 int mode;
895 unsigned int port_num;
896 int ret;
897
898 priv->moca_port = -1;
899
900 for_each_available_child_of_node(dn, port) {
901 if (of_property_read_u32(port, "reg", &port_num))
902 continue;
903
904 /* Internal PHYs get assigned a specific 'phy-mode' property
905 * value: "internal" to help flag them before MDIO probing
906 * has completed, since they might be turned off at that
907 * time
908 */
909 mode = of_get_phy_mode(port);
910 if (mode < 0) {
911 ret = of_property_read_string(port, "phy-mode",
912 &phy_mode_str);
913 if (ret < 0)
914 continue;
915
916 if (!strcasecmp(phy_mode_str, "internal"))
917 priv->int_phy_mask |= 1 << port_num;
918 }
919
920 if (mode == PHY_INTERFACE_MODE_MOCA)
921 priv->moca_port = port_num;
922 }
923}
924
Florian Fainelli246d7f72014-08-27 17:04:56 -0700925static int bcm_sf2_sw_setup(struct dsa_switch *ds)
926{
927 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
928 struct bcm_sf2_priv *priv = ds_to_priv(ds);
929 struct device_node *dn;
930 void __iomem **base;
931 unsigned int port;
932 unsigned int i;
933 u32 reg, rev;
934 int ret;
935
936 spin_lock_init(&priv->indir_lock);
937 mutex_init(&priv->stats_mutex);
938
939 /* All the interesting properties are at the parent device_node
940 * level
941 */
942 dn = ds->pd->of_node->parent;
Florian Fainelli8b7c94e2015-10-23 12:11:08 -0700943 bcm_sf2_identify_ports(priv, ds->pd->of_node);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700944
945 priv->irq0 = irq_of_parse_and_map(dn, 0);
946 priv->irq1 = irq_of_parse_and_map(dn, 1);
947
948 base = &priv->core;
949 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
950 *base = of_iomap(dn, i);
951 if (*base == NULL) {
952 pr_err("unable to find register: %s\n", reg_names[i]);
Florian Fainellia5660592014-11-25 18:08:48 -0800953 ret = -ENOMEM;
954 goto out_unmap;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700955 }
956 base++;
957 }
958
Florian Fainelli33f84612014-11-25 18:08:49 -0800959 ret = bcm_sf2_sw_rst(priv);
960 if (ret) {
961 pr_err("unable to software reset switch: %d\n", ret);
962 goto out_unmap;
963 }
964
Florian Fainelli246d7f72014-08-27 17:04:56 -0700965 /* Disable all interrupts and request them */
Florian Fainelli691c9a82015-01-20 16:42:00 -0800966 bcm_sf2_intr_disable(priv);
Florian Fainelli246d7f72014-08-27 17:04:56 -0700967
968 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
969 "switch_0", priv);
970 if (ret < 0) {
971 pr_err("failed to request switch_0 IRQ\n");
972 goto out_unmap;
973 }
974
975 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
976 "switch_1", priv);
977 if (ret < 0) {
978 pr_err("failed to request switch_1 IRQ\n");
979 goto out_free_irq0;
980 }
981
982 /* Reset the MIB counters */
983 reg = core_readl(priv, CORE_GMNCFGCFG);
984 reg |= RST_MIB_CNT;
985 core_writel(priv, reg, CORE_GMNCFGCFG);
986 reg &= ~RST_MIB_CNT;
987 core_writel(priv, reg, CORE_GMNCFGCFG);
988
989 /* Get the maximum number of ports for this switch */
990 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
991 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
992 priv->hw_params.num_ports = DSA_MAX_PORTS;
993
994 /* Assume a single GPHY setup if we can't read that property */
995 if (of_property_read_u32(dn, "brcm,num-gphy",
996 &priv->hw_params.num_gphy))
997 priv->hw_params.num_gphy = 1;
998
999 /* Enable all valid ports and disable those unused */
1000 for (port = 0; port < priv->hw_params.num_ports; port++) {
1001 /* IMP port receives special treatment */
1002 if ((1 << port) & ds->phys_port_mask)
Florian Fainellib6d045d2014-09-24 17:05:20 -07001003 bcm_sf2_port_setup(ds, port, NULL);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001004 else if (dsa_is_cpu_port(ds, port))
1005 bcm_sf2_imp_setup(ds, port);
1006 else
Florian Fainellib6d045d2014-09-24 17:05:20 -07001007 bcm_sf2_port_disable(ds, port, NULL);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001008 }
1009
1010 /* Include the pseudo-PHY address and the broadcast PHY address to
Florian Fainellib8c6cd12015-07-15 16:09:32 -07001011 * divert reads towards our workaround. This is only required for
1012 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
1013 * that we can use the regular SWITCH_MDIO master controller instead.
1014 *
1015 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
1016 * to have a 1:1 mapping between Port address and PHY address in order
1017 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
1018 * not what we want here, so we initialize phys_mii_mask 0 to always
1019 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
Florian Fainelli246d7f72014-08-27 17:04:56 -07001020 */
Florian Fainellib8c6cd12015-07-15 16:09:32 -07001021 if (of_machine_is_compatible("brcm,bcm7445d0"))
1022 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
1023 else
1024 ds->phys_mii_mask = 0;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001025
1026 rev = reg_readl(priv, REG_SWITCH_REVISION);
1027 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1028 SWITCH_TOP_REV_MASK;
1029 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1030
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001031 rev = reg_readl(priv, REG_PHY_REVISION);
1032 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1033
Florian Fainelli246d7f72014-08-27 17:04:56 -07001034 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1035 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1036 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1037 priv->core, priv->irq0, priv->irq1);
1038
1039 return 0;
1040
1041out_free_irq0:
1042 free_irq(priv->irq0, priv);
1043out_unmap:
1044 base = &priv->core;
1045 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
Florian Fainellia5660592014-11-25 18:08:48 -08001046 if (*base)
1047 iounmap(*base);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001048 base++;
1049 }
1050 return ret;
1051}
1052
1053static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
1054{
1055 return 0;
1056}
1057
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001058static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
1059{
1060 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1061
1062 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1063 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1064 * the REG_PHY_REVISION register layout is.
1065 */
1066
1067 return priv->hw_params.gphy_rev;
1068}
1069
Florian Fainelli246d7f72014-08-27 17:04:56 -07001070static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
1071 int regnum, u16 val)
1072{
1073 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1074 int ret = 0;
1075 u32 reg;
1076
1077 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1078 reg |= MDIO_MASTER_SEL;
1079 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1080
1081 /* Page << 8 | offset */
1082 reg = 0x70;
1083 reg <<= 2;
1084 core_writel(priv, addr, reg);
1085
1086 /* Page << 8 | offset */
1087 reg = 0x80 << 8 | regnum << 1;
1088 reg <<= 2;
1089
1090 if (op)
1091 ret = core_readl(priv, reg);
1092 else
1093 core_writel(priv, val, reg);
1094
1095 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1096 reg &= ~MDIO_MASTER_SEL;
1097 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1098
1099 return ret & 0xffff;
1100}
1101
1102static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
1103{
1104 /* Intercept reads from the MDIO broadcast address or Broadcom
1105 * pseudo-PHY address
1106 */
1107 switch (addr) {
1108 case 0:
Florian Fainelliaafc66f2015-06-10 18:08:01 -07001109 case BRCM_PSEUDO_PHY_ADDR:
Florian Fainelli246d7f72014-08-27 17:04:56 -07001110 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
1111 default:
1112 return 0xffff;
1113 }
1114}
1115
1116static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
1117 u16 val)
1118{
1119 /* Intercept writes to the MDIO broadcast address or Broadcom
1120 * pseudo-PHY address
1121 */
1122 switch (addr) {
1123 case 0:
Florian Fainelliaafc66f2015-06-10 18:08:01 -07001124 case BRCM_PSEUDO_PHY_ADDR:
Florian Fainelli246d7f72014-08-27 17:04:56 -07001125 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
1126 break;
1127 }
1128
1129 return 0;
1130}
1131
1132static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
1133 struct phy_device *phydev)
1134{
1135 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1136 u32 id_mode_dis = 0, port_mode;
1137 const char *str = NULL;
1138 u32 reg;
1139
1140 switch (phydev->interface) {
1141 case PHY_INTERFACE_MODE_RGMII:
1142 str = "RGMII (no delay)";
1143 id_mode_dis = 1;
1144 case PHY_INTERFACE_MODE_RGMII_TXID:
1145 if (!str)
1146 str = "RGMII (TX delay)";
1147 port_mode = EXT_GPHY;
1148 break;
1149 case PHY_INTERFACE_MODE_MII:
1150 str = "MII";
1151 port_mode = EXT_EPHY;
1152 break;
1153 case PHY_INTERFACE_MODE_REVMII:
1154 str = "Reverse MII";
1155 port_mode = EXT_REVMII;
1156 break;
1157 default:
Florian Fainelli7de15572014-09-24 17:05:19 -07001158 /* All other PHYs: internal and MoCA */
1159 goto force_link;
1160 }
1161
1162 /* If the link is down, just disable the interface to conserve power */
1163 if (!phydev->link) {
1164 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1165 reg &= ~RGMII_MODE_EN;
1166 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
Florian Fainelli246d7f72014-08-27 17:04:56 -07001167 goto force_link;
1168 }
1169
1170 /* Clear id_mode_dis bit, and the existing port mode, but
1171 * make sure we enable the RGMII block for data to pass
1172 */
1173 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1174 reg &= ~ID_MODE_DIS;
1175 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
1176 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1177
1178 reg |= port_mode | RGMII_MODE_EN;
1179 if (id_mode_dis)
1180 reg |= ID_MODE_DIS;
1181
1182 if (phydev->pause) {
1183 if (phydev->asym_pause)
1184 reg |= TX_PAUSE_EN;
1185 reg |= RX_PAUSE_EN;
1186 }
1187
1188 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1189
1190 pr_info("Port %d configured for %s\n", port, str);
1191
1192force_link:
1193 /* Force link settings detected from the PHY */
1194 reg = SW_OVERRIDE;
1195 switch (phydev->speed) {
1196 case SPEED_1000:
1197 reg |= SPDSTS_1000 << SPEED_SHIFT;
1198 break;
1199 case SPEED_100:
1200 reg |= SPDSTS_100 << SPEED_SHIFT;
1201 break;
1202 }
1203
1204 if (phydev->link)
1205 reg |= LINK_STS;
1206 if (phydev->duplex == DUPLEX_FULL)
1207 reg |= DUPLX_MODE;
1208
1209 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1210}
1211
1212static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
1213 struct fixed_phy_status *status)
1214{
1215 struct bcm_sf2_priv *priv = ds_to_priv(ds);
Florian Fainellid2eac982015-07-20 17:49:55 -07001216 u32 duplex, pause;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001217 u32 reg;
1218
Florian Fainelli246d7f72014-08-27 17:04:56 -07001219 duplex = core_readl(priv, CORE_DUPSTS);
1220 pause = core_readl(priv, CORE_PAUSESTS);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001221
1222 status->link = 0;
1223
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001224 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001225 * which means that we need to force the link at the port override
1226 * level to get the data to flow. We do use what the interrupt handler
1227 * did determine before.
Florian Fainelli7855f672014-12-11 18:12:42 -08001228 *
1229 * For the other ports, we just force the link status, since this is
1230 * a fixed PHY device.
Florian Fainelli246d7f72014-08-27 17:04:56 -07001231 */
Florian Fainelli8b7c94e2015-10-23 12:11:08 -07001232 if (port == priv->moca_port) {
Florian Fainelli246d7f72014-08-27 17:04:56 -07001233 status->link = priv->port_sts[port].link;
Florian Fainelli4ab7f912015-05-15 12:38:01 -07001234 /* For MoCA interfaces, also force a link down notification
1235 * since some version of the user-space daemon (mocad) use
1236 * cmd->autoneg to force the link, which messes up the PHY
1237 * state machine and make it go in PHY_FORCING state instead.
1238 */
1239 if (!status->link)
1240 netif_carrier_off(ds->ports[port]);
Florian Fainelli246d7f72014-08-27 17:04:56 -07001241 status->duplex = 1;
1242 } else {
Florian Fainelli7855f672014-12-11 18:12:42 -08001243 status->link = 1;
Florian Fainelli246d7f72014-08-27 17:04:56 -07001244 status->duplex = !!(duplex & (1 << port));
1245 }
1246
Florian Fainelli7855f672014-12-11 18:12:42 -08001247 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1248 reg |= SW_OVERRIDE;
1249 if (status->link)
1250 reg |= LINK_STS;
1251 else
1252 reg &= ~LINK_STS;
1253 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1254
Florian Fainelli246d7f72014-08-27 17:04:56 -07001255 if ((pause & (1 << port)) &&
1256 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
1257 status->asym_pause = 1;
1258 status->pause = 1;
1259 }
1260
1261 if (pause & (1 << port))
1262 status->pause = 1;
1263}
1264
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001265static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
1266{
1267 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1268 unsigned int port;
1269
Florian Fainelli691c9a82015-01-20 16:42:00 -08001270 bcm_sf2_intr_disable(priv);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001271
1272 /* Disable all ports physically present including the IMP
1273 * port, the other ones have already been disabled during
1274 * bcm_sf2_sw_setup
1275 */
1276 for (port = 0; port < DSA_MAX_PORTS; port++) {
1277 if ((1 << port) & ds->phys_port_mask ||
1278 dsa_is_cpu_port(ds, port))
Florian Fainellib6d045d2014-09-24 17:05:20 -07001279 bcm_sf2_port_disable(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001280 }
1281
1282 return 0;
1283}
1284
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001285static int bcm_sf2_sw_resume(struct dsa_switch *ds)
1286{
1287 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1288 unsigned int port;
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001289 int ret;
1290
1291 ret = bcm_sf2_sw_rst(priv);
1292 if (ret) {
1293 pr_err("%s: failed to software reset switch\n", __func__);
1294 return ret;
1295 }
1296
Florian Fainellib0836682015-02-05 11:40:41 -08001297 if (priv->hw_params.num_gphy == 1)
1298 bcm_sf2_gphy_enable_set(ds, true);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001299
1300 for (port = 0; port < DSA_MAX_PORTS; port++) {
1301 if ((1 << port) & ds->phys_port_mask)
Florian Fainellib6d045d2014-09-24 17:05:20 -07001302 bcm_sf2_port_setup(ds, port, NULL);
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001303 else if (dsa_is_cpu_port(ds, port))
1304 bcm_sf2_imp_setup(ds, port);
1305 }
1306
1307 return 0;
1308}
1309
Florian Fainelli96e65d72014-09-18 17:31:25 -07001310static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1311 struct ethtool_wolinfo *wol)
1312{
1313 struct net_device *p = ds->dst[ds->index].master_netdev;
1314 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1315 struct ethtool_wolinfo pwol;
1316
1317 /* Get the parent device WoL settings */
1318 p->ethtool_ops->get_wol(p, &pwol);
1319
1320 /* Advertise the parent device supported settings */
1321 wol->supported = pwol.supported;
1322 memset(&wol->sopass, 0, sizeof(wol->sopass));
1323
1324 if (pwol.wolopts & WAKE_MAGICSECURE)
1325 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1326
1327 if (priv->wol_ports_mask & (1 << port))
1328 wol->wolopts = pwol.wolopts;
1329 else
1330 wol->wolopts = 0;
1331}
1332
1333static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1334 struct ethtool_wolinfo *wol)
1335{
1336 struct net_device *p = ds->dst[ds->index].master_netdev;
1337 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1338 s8 cpu_port = ds->dst[ds->index].cpu_port;
1339 struct ethtool_wolinfo pwol;
1340
1341 p->ethtool_ops->get_wol(p, &pwol);
1342 if (wol->wolopts & ~pwol.supported)
1343 return -EINVAL;
1344
1345 if (wol->wolopts)
1346 priv->wol_ports_mask |= (1 << port);
1347 else
1348 priv->wol_ports_mask &= ~(1 << port);
1349
1350 /* If we have at least one port enabled, make sure the CPU port
1351 * is also enabled. If the CPU port is the last one enabled, we disable
1352 * it since this configuration does not make sense.
1353 */
1354 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1355 priv->wol_ports_mask |= (1 << cpu_port);
1356 else
1357 priv->wol_ports_mask &= ~(1 << cpu_port);
1358
1359 return p->ethtool_ops->set_wol(p, wol);
1360}
1361
Florian Fainelli246d7f72014-08-27 17:04:56 -07001362static struct dsa_switch_driver bcm_sf2_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -07001363 .tag_protocol = DSA_TAG_PROTO_BRCM,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001364 .priv_size = sizeof(struct bcm_sf2_priv),
1365 .probe = bcm_sf2_sw_probe,
1366 .setup = bcm_sf2_sw_setup,
1367 .set_addr = bcm_sf2_sw_set_addr,
Florian Fainelliaa9aef72014-09-19 13:07:55 -07001368 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001369 .phy_read = bcm_sf2_sw_phy_read,
1370 .phy_write = bcm_sf2_sw_phy_write,
1371 .get_strings = bcm_sf2_sw_get_strings,
1372 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1373 .get_sset_count = bcm_sf2_sw_get_sset_count,
1374 .adjust_link = bcm_sf2_sw_adjust_link,
1375 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
Florian Fainelli8cfa9492014-09-18 17:31:23 -07001376 .suspend = bcm_sf2_sw_suspend,
1377 .resume = bcm_sf2_sw_resume,
Florian Fainelli96e65d72014-09-18 17:31:25 -07001378 .get_wol = bcm_sf2_sw_get_wol,
1379 .set_wol = bcm_sf2_sw_set_wol,
Florian Fainellib6d045d2014-09-24 17:05:20 -07001380 .port_enable = bcm_sf2_port_setup,
1381 .port_disable = bcm_sf2_port_disable,
Florian Fainelli450b05c2014-09-24 17:05:22 -07001382 .get_eee = bcm_sf2_sw_get_eee,
1383 .set_eee = bcm_sf2_sw_set_eee,
Vivien Didelot71327a42016-03-13 16:21:32 -04001384 .port_bridge_join = bcm_sf2_sw_br_join,
1385 .port_bridge_leave = bcm_sf2_sw_br_leave,
Vivien Didelot43c44a92016-04-06 11:55:03 -04001386 .port_stp_state_set = bcm_sf2_sw_br_set_stp_state,
Florian Fainelli680060d2015-10-23 11:38:07 -07001387 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare,
1388 .port_fdb_add = bcm_sf2_sw_fdb_add,
1389 .port_fdb_del = bcm_sf2_sw_fdb_del,
1390 .port_fdb_dump = bcm_sf2_sw_fdb_dump,
Florian Fainelli246d7f72014-08-27 17:04:56 -07001391};
1392
1393static int __init bcm_sf2_init(void)
1394{
1395 register_switch_driver(&bcm_sf2_switch_driver);
1396
1397 return 0;
1398}
1399module_init(bcm_sf2_init);
1400
1401static void __exit bcm_sf2_exit(void)
1402{
1403 unregister_switch_driver(&bcm_sf2_switch_driver);
1404}
1405module_exit(bcm_sf2_exit);
1406
1407MODULE_AUTHOR("Broadcom Corporation");
1408MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1409MODULE_LICENSE("GPL");
1410MODULE_ALIAS("platform:brcm-sf2");