blob: de76a231c8a56747c1f6143f0f27fefb7fc04fd3 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010033#include <linux/circ_buf.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drmP.h>
35#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010037#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Daniel Vetterfca52a52014-09-30 10:56:45 +020040/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +030048static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50};
51
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +030052static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54};
55
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +030056static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58};
59
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020060static const u32 hpd_ibx[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050061 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66};
67
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020068static const u32 hpd_cpt[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050069 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010070 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050071 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74};
75
Xiong Zhang26951ca2015-08-17 15:55:50 +080076static const u32 hpd_spt[HPD_NUM_PINS] = {
Ville Syrjälä74c0b392015-08-27 23:56:07 +030077 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
Xiong Zhang26951ca2015-08-17 15:55:50 +080078 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82};
83
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020084static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050085 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91};
92
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020093static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050094 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100};
101
Ville Syrjälä4bca26d2015-05-11 20:49:10 +0300102static const u32 hpd_status_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -0500103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109};
110
Shashank Sharmae0a20ad2015-03-27 14:54:14 +0200111/* BXT hpd list */
112static const u32 hpd_bxt[HPD_NUM_PINS] = {
Sonika Jindal7f3561b2015-08-10 10:35:35 +0530113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
Shashank Sharmae0a20ad2015-03-27 14:54:14 +0200114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116};
117
Paulo Zanoni5c502442014-04-01 15:37:11 -0300118/* IIR can theoretically queue up two events. Be paranoid. */
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300119#define GEN8_IRQ_RESET_NDX(type, which) do { \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127} while (0)
128
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300129#define GEN5_IRQ_RESET(type) do { \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300130 I915_WRITE(type##IMR, 0xffffffff); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300131 POSTING_READ(type##IMR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300132 I915_WRITE(type##IER, 0); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300137} while (0)
138
Paulo Zanoni337ba012014-04-01 15:37:16 -0300139/*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300142static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
143{
144 u32 val = I915_READ(reg);
145
146 if (val == 0)
147 return;
148
149 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
150 reg, val);
151 I915_WRITE(reg, 0xffffffff);
152 POSTING_READ(reg);
153 I915_WRITE(reg, 0xffffffff);
154 POSTING_READ(reg);
155}
Paulo Zanoni337ba012014-04-01 15:37:16 -0300156
Paulo Zanoni35079892014-04-01 15:37:15 -0300157#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300158 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300159 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200160 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
161 POSTING_READ(GEN8_##type##_IMR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300162} while (0)
163
164#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
Ville Syrjäläb51a2842015-09-18 20:03:41 +0300165 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300166 I915_WRITE(type##IER, (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200167 I915_WRITE(type##IMR, (imr_val)); \
168 POSTING_READ(type##IMR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300169} while (0)
170
Imre Deakc9a9a262014-11-05 20:48:37 +0200171static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
172
Egbert Eich0706f172015-09-23 16:15:27 +0200173/* For display hotplug interrupt */
174static inline void
175i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
176 uint32_t mask,
177 uint32_t bits)
178{
179 uint32_t val;
180
181 assert_spin_locked(&dev_priv->irq_lock);
182 WARN_ON(bits & ~mask);
183
184 val = I915_READ(PORT_HOTPLUG_EN);
185 val &= ~mask;
186 val |= bits;
187 I915_WRITE(PORT_HOTPLUG_EN, val);
188}
189
190/**
191 * i915_hotplug_interrupt_update - update hotplug interrupt enable
192 * @dev_priv: driver private
193 * @mask: bits to update
194 * @bits: bits to enable
195 * NOTE: the HPD enable bits are modified both inside and outside
196 * of an interrupt context. To avoid that read-modify-write cycles
197 * interfer, these bits are protected by a spinlock. Since this
198 * function is usually not called from a context where the lock is
199 * held already, this function acquires the lock itself. A non-locking
200 * version is also available.
201 */
202void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
203 uint32_t mask,
204 uint32_t bits)
205{
206 spin_lock_irq(&dev_priv->irq_lock);
207 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
208 spin_unlock_irq(&dev_priv->irq_lock);
209}
210
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300211/**
212 * ilk_update_display_irq - update DEIMR
213 * @dev_priv: driver private
214 * @interrupt_mask: mask of interrupt bits to update
215 * @enabled_irq_mask: mask of interrupt bits to enable
216 */
217static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
218 uint32_t interrupt_mask,
219 uint32_t enabled_irq_mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800220{
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300221 uint32_t new_val;
222
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200223 assert_spin_locked(&dev_priv->irq_lock);
224
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300225 WARN_ON(enabled_irq_mask & ~interrupt_mask);
226
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700227 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300228 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300229
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300230 new_val = dev_priv->irq_mask;
231 new_val &= ~interrupt_mask;
232 new_val |= (~enabled_irq_mask & interrupt_mask);
233
234 if (new_val != dev_priv->irq_mask) {
235 dev_priv->irq_mask = new_val;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000236 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000237 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800238 }
239}
240
Daniel Vetter47339cd2014-09-30 10:56:46 +0200241void
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300242ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
243{
244 ilk_update_display_irq(dev_priv, mask, mask);
245}
246
247void
Jani Nikula2d1013d2014-03-31 14:27:17 +0300248ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800249{
Ville Syrjäläd9dc34f12015-08-27 23:55:58 +0300250 ilk_update_display_irq(dev_priv, mask, 0);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800251}
252
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300253/**
254 * ilk_update_gt_irq - update GTIMR
255 * @dev_priv: driver private
256 * @interrupt_mask: mask of interrupt bits to update
257 * @enabled_irq_mask: mask of interrupt bits to enable
258 */
259static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
260 uint32_t interrupt_mask,
261 uint32_t enabled_irq_mask)
262{
263 assert_spin_locked(&dev_priv->irq_lock);
264
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100265 WARN_ON(enabled_irq_mask & ~interrupt_mask);
266
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700267 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300268 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300269
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300270 dev_priv->gt_irq_mask &= ~interrupt_mask;
271 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
272 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
273 POSTING_READ(GTIMR);
274}
275
Daniel Vetter480c8032014-07-16 09:49:40 +0200276void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300277{
278 ilk_update_gt_irq(dev_priv, mask, mask);
279}
280
Daniel Vetter480c8032014-07-16 09:49:40 +0200281void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300282{
283 ilk_update_gt_irq(dev_priv, mask, 0);
284}
285
Imre Deakb900b942014-11-05 20:48:48 +0200286static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
287{
288 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
289}
290
Imre Deaka72fbc32014-11-05 20:48:31 +0200291static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
292{
293 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
294}
295
Imre Deakb900b942014-11-05 20:48:48 +0200296static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
297{
298 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
299}
300
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300301/**
302 * snb_update_pm_irq - update GEN6_PMIMR
303 * @dev_priv: driver private
304 * @interrupt_mask: mask of interrupt bits to update
305 * @enabled_irq_mask: mask of interrupt bits to enable
306 */
307static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
308 uint32_t interrupt_mask,
309 uint32_t enabled_irq_mask)
310{
Paulo Zanoni605cd252013-08-06 18:57:15 -0300311 uint32_t new_val;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300312
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100313 WARN_ON(enabled_irq_mask & ~interrupt_mask);
314
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300315 assert_spin_locked(&dev_priv->irq_lock);
316
Paulo Zanoni605cd252013-08-06 18:57:15 -0300317 new_val = dev_priv->pm_irq_mask;
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300318 new_val &= ~interrupt_mask;
319 new_val |= (~enabled_irq_mask & interrupt_mask);
320
Paulo Zanoni605cd252013-08-06 18:57:15 -0300321 if (new_val != dev_priv->pm_irq_mask) {
322 dev_priv->pm_irq_mask = new_val;
Imre Deaka72fbc32014-11-05 20:48:31 +0200323 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
324 POSTING_READ(gen6_pm_imr(dev_priv));
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300325 }
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300326}
327
Daniel Vetter480c8032014-07-16 09:49:40 +0200328void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300329{
Imre Deak9939fba2014-11-20 23:01:47 +0200330 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
331 return;
332
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300333 snb_update_pm_irq(dev_priv, mask, mask);
334}
335
Imre Deak9939fba2014-11-20 23:01:47 +0200336static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
337 uint32_t mask)
338{
339 snb_update_pm_irq(dev_priv, mask, 0);
340}
341
Daniel Vetter480c8032014-07-16 09:49:40 +0200342void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300343{
Imre Deak9939fba2014-11-20 23:01:47 +0200344 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
345 return;
346
347 __gen6_disable_pm_irq(dev_priv, mask);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300348}
349
Imre Deak3cc134e2014-11-19 15:30:03 +0200350void gen6_reset_rps_interrupts(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353 uint32_t reg = gen6_pm_iir(dev_priv);
354
355 spin_lock_irq(&dev_priv->irq_lock);
356 I915_WRITE(reg, dev_priv->pm_rps_events);
357 I915_WRITE(reg, dev_priv->pm_rps_events);
358 POSTING_READ(reg);
Imre Deak096fad92015-03-23 19:11:35 +0200359 dev_priv->rps.pm_iir = 0;
Imre Deak3cc134e2014-11-19 15:30:03 +0200360 spin_unlock_irq(&dev_priv->irq_lock);
361}
362
Imre Deakb900b942014-11-05 20:48:48 +0200363void gen6_enable_rps_interrupts(struct drm_device *dev)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366
367 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak78e68d32014-12-15 18:59:27 +0200368
Imre Deakb900b942014-11-05 20:48:48 +0200369 WARN_ON(dev_priv->rps.pm_iir);
Imre Deak3cc134e2014-11-19 15:30:03 +0200370 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +0200371 dev_priv->rps.interrupts_enabled = true;
Imre Deak78e68d32014-12-15 18:59:27 +0200372 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
373 dev_priv->pm_rps_events);
Imre Deakb900b942014-11-05 20:48:48 +0200374 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deak78e68d32014-12-15 18:59:27 +0200375
Imre Deakb900b942014-11-05 20:48:48 +0200376 spin_unlock_irq(&dev_priv->irq_lock);
377}
378
Imre Deak59d02a12014-12-19 19:33:26 +0200379u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
380{
381 /*
Imre Deakf24eeb12014-12-19 19:33:27 +0200382 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
Imre Deak59d02a12014-12-19 19:33:26 +0200383 * if GEN6_PM_UP_EI_EXPIRED is masked.
Imre Deakf24eeb12014-12-19 19:33:27 +0200384 *
385 * TODO: verify if this can be reproduced on VLV,CHV.
Imre Deak59d02a12014-12-19 19:33:26 +0200386 */
387 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
388 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
389
390 if (INTEL_INFO(dev_priv)->gen >= 8)
391 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
392
393 return mask;
394}
395
Imre Deakb900b942014-11-05 20:48:48 +0200396void gen6_disable_rps_interrupts(struct drm_device *dev)
397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399
Imre Deakd4d70aa2014-11-19 15:30:04 +0200400 spin_lock_irq(&dev_priv->irq_lock);
401 dev_priv->rps.interrupts_enabled = false;
402 spin_unlock_irq(&dev_priv->irq_lock);
403
404 cancel_work_sync(&dev_priv->rps.work);
405
Imre Deak9939fba2014-11-20 23:01:47 +0200406 spin_lock_irq(&dev_priv->irq_lock);
407
Imre Deak59d02a12014-12-19 19:33:26 +0200408 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
Imre Deak9939fba2014-11-20 23:01:47 +0200409
410 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deakb900b942014-11-05 20:48:48 +0200411 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
412 ~dev_priv->pm_rps_events);
Imre Deak58072cc2015-03-23 19:11:34 +0200413
414 spin_unlock_irq(&dev_priv->irq_lock);
415
416 synchronize_irq(dev->irq);
Imre Deakb900b942014-11-05 20:48:48 +0200417}
418
Ben Widawsky09610212014-05-15 20:58:08 +0300419/**
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +0300420 * bdw_update_port_irq - update DE port interrupt
421 * @dev_priv: driver private
422 * @interrupt_mask: mask of interrupt bits to update
423 * @enabled_irq_mask: mask of interrupt bits to enable
424 */
425static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
426 uint32_t interrupt_mask,
427 uint32_t enabled_irq_mask)
428{
429 uint32_t new_val;
430 uint32_t old_val;
431
432 assert_spin_locked(&dev_priv->irq_lock);
433
434 WARN_ON(enabled_irq_mask & ~interrupt_mask);
435
436 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
437 return;
438
439 old_val = I915_READ(GEN8_DE_PORT_IMR);
440
441 new_val = old_val;
442 new_val &= ~interrupt_mask;
443 new_val |= (~enabled_irq_mask & interrupt_mask);
444
445 if (new_val != old_val) {
446 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
447 POSTING_READ(GEN8_DE_PORT_IMR);
448 }
449}
450
451/**
Daniel Vetterfee884e2013-07-04 23:35:21 +0200452 * ibx_display_interrupt_update - update SDEIMR
453 * @dev_priv: driver private
454 * @interrupt_mask: mask of interrupt bits to update
455 * @enabled_irq_mask: mask of interrupt bits to enable
456 */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200457void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
458 uint32_t interrupt_mask,
459 uint32_t enabled_irq_mask)
Daniel Vetterfee884e2013-07-04 23:35:21 +0200460{
461 uint32_t sdeimr = I915_READ(SDEIMR);
462 sdeimr &= ~interrupt_mask;
463 sdeimr |= (~enabled_irq_mask & interrupt_mask);
464
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100465 WARN_ON(enabled_irq_mask & ~interrupt_mask);
466
Daniel Vetterfee884e2013-07-04 23:35:21 +0200467 assert_spin_locked(&dev_priv->irq_lock);
468
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700469 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300470 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300471
Daniel Vetterfee884e2013-07-04 23:35:21 +0200472 I915_WRITE(SDEIMR, sdeimr);
473 POSTING_READ(SDEIMR);
474}
Paulo Zanoni86642812013-04-12 17:57:57 -0300475
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100476static void
Imre Deak755e9012014-02-10 18:42:47 +0200477__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
478 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800479{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200480 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200481 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800482
Daniel Vetterb79480b2013-06-27 17:52:10 +0200483 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200484 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200485
Ville Syrjälä04feced2014-04-03 13:28:33 +0300486 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
487 status_mask & ~PIPESTAT_INT_STATUS_MASK,
488 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
489 pipe_name(pipe), enable_mask, status_mask))
Imre Deak755e9012014-02-10 18:42:47 +0200490 return;
491
492 if ((pipestat & enable_mask) == enable_mask)
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200493 return;
494
Imre Deak91d181d2014-02-10 18:42:49 +0200495 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
496
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200497 /* Enable the interrupt, clear any pending status */
Imre Deak755e9012014-02-10 18:42:47 +0200498 pipestat |= enable_mask | status_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200499 I915_WRITE(reg, pipestat);
500 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800501}
502
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100503static void
Imre Deak755e9012014-02-10 18:42:47 +0200504__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
505 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800506{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200507 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200508 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800509
Daniel Vetterb79480b2013-06-27 17:52:10 +0200510 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200511 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200512
Ville Syrjälä04feced2014-04-03 13:28:33 +0300513 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
514 status_mask & ~PIPESTAT_INT_STATUS_MASK,
515 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
516 pipe_name(pipe), enable_mask, status_mask))
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200517 return;
518
Imre Deak755e9012014-02-10 18:42:47 +0200519 if ((pipestat & enable_mask) == 0)
520 return;
521
Imre Deak91d181d2014-02-10 18:42:49 +0200522 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
523
Imre Deak755e9012014-02-10 18:42:47 +0200524 pipestat &= ~enable_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200525 I915_WRITE(reg, pipestat);
526 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800527}
528
Imre Deak10c59c52014-02-10 18:42:48 +0200529static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
530{
531 u32 enable_mask = status_mask << 16;
532
533 /*
Ville Syrjälä724a6902014-04-09 13:28:48 +0300534 * On pipe A we don't support the PSR interrupt yet,
535 * on pipe B and C the same bit MBZ.
Imre Deak10c59c52014-02-10 18:42:48 +0200536 */
537 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
538 return 0;
Ville Syrjälä724a6902014-04-09 13:28:48 +0300539 /*
540 * On pipe B and C we don't support the PSR interrupt yet, on pipe
541 * A the same bit is for perf counters which we don't use either.
542 */
543 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
544 return 0;
Imre Deak10c59c52014-02-10 18:42:48 +0200545
546 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
547 SPRITE0_FLIP_DONE_INT_EN_VLV |
548 SPRITE1_FLIP_DONE_INT_EN_VLV);
549 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
550 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
551 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
552 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
553
554 return enable_mask;
555}
556
Imre Deak755e9012014-02-10 18:42:47 +0200557void
558i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
559 u32 status_mask)
560{
561 u32 enable_mask;
562
Imre Deak10c59c52014-02-10 18:42:48 +0200563 if (IS_VALLEYVIEW(dev_priv->dev))
564 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
565 status_mask);
566 else
567 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200568 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
569}
570
571void
572i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
573 u32 status_mask)
574{
575 u32 enable_mask;
576
Imre Deak10c59c52014-02-10 18:42:48 +0200577 if (IS_VALLEYVIEW(dev_priv->dev))
578 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
579 status_mask);
580 else
581 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200582 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
583}
584
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000585/**
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300586 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
Javier Martinez Canillas468f9d22015-10-08 09:54:44 +0200587 * @dev: drm device
Zhao Yakui01c66882009-10-28 05:10:00 +0000588 */
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300589static void i915_enable_asle_pipestat(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000590{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300591 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000592
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300593 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
594 return;
595
Daniel Vetter13321782014-09-15 14:55:29 +0200596 spin_lock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000597
Imre Deak755e9012014-02-10 18:42:47 +0200598 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
Jani Nikulaf8987802013-04-29 13:02:53 +0300599 if (INTEL_INFO(dev)->gen >= 4)
Daniel Vetter3b6c42e2013-10-21 18:04:35 +0200600 i915_enable_pipestat(dev_priv, PIPE_A,
Imre Deak755e9012014-02-10 18:42:47 +0200601 PIPE_LEGACY_BLC_EVENT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000602
Daniel Vetter13321782014-09-15 14:55:29 +0200603 spin_unlock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000604}
605
Ville Syrjäläf75f3742014-05-15 20:20:36 +0300606/*
607 * This timing diagram depicts the video signal in and
608 * around the vertical blanking period.
609 *
610 * Assumptions about the fictitious mode used in this example:
611 * vblank_start >= 3
612 * vsync_start = vblank_start + 1
613 * vsync_end = vblank_start + 2
614 * vtotal = vblank_start + 3
615 *
616 * start of vblank:
617 * latch double buffered registers
618 * increment frame counter (ctg+)
619 * generate start of vblank interrupt (gen4+)
620 * |
621 * | frame start:
622 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
623 * | may be shifted forward 1-3 extra lines via PIPECONF
624 * | |
625 * | | start of vsync:
626 * | | generate vsync interrupt
627 * | | |
628 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
629 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
630 * ----va---> <-----------------vb--------------------> <--------va-------------
631 * | | <----vs-----> |
632 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
633 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
634 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
635 * | | |
636 * last visible pixel first visible pixel
637 * | increment frame counter (gen3/4)
638 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
639 *
640 * x = horizontal active
641 * _ = horizontal blanking
642 * hs = horizontal sync
643 * va = vertical active
644 * vb = vertical blanking
645 * vs = vertical sync
646 * vbs = vblank_start (number)
647 *
648 * Summary:
649 * - most events happen at the start of horizontal sync
650 * - frame start happens at the start of horizontal blank, 1-4 lines
651 * (depending on PIPECONF settings) after the start of vblank
652 * - gen3/4 pixel and frame counter are synchronized with the start
653 * of horizontal active on the first line of vertical active
654 */
655
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +0300656static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
657{
658 /* Gen2 doesn't have a hardware frame counter */
659 return 0;
660}
661
Keith Packard42f52ef2008-10-18 19:39:29 -0700662/* Called from drm generic code, passed a 'crtc', which
663 * we use as a pipe index
664 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700665static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700666{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300667 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700668 unsigned long high_frame;
669 unsigned long low_frame;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300670 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +0100671 struct intel_crtc *intel_crtc =
672 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200673 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700674
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +0100675 htotal = mode->crtc_htotal;
676 hsync_start = mode->crtc_hsync_start;
677 vbl_start = mode->crtc_vblank_start;
678 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
679 vbl_start = DIV_ROUND_UP(vbl_start, 2);
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300680
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300681 /* Convert to pixel count */
682 vbl_start *= htotal;
683
684 /* Start of vblank event occurs at start of hsync */
685 vbl_start -= htotal - hsync_start;
686
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800687 high_frame = PIPEFRAME(pipe);
688 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100689
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700690 /*
691 * High & low register fields aren't synchronized, so make sure
692 * we get a low value that's stable across two reads of the high
693 * register.
694 */
695 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100696 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300697 low = I915_READ(low_frame);
Chris Wilson5eddb702010-09-11 13:48:45 +0100698 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700699 } while (high1 != high2);
700
Chris Wilson5eddb702010-09-11 13:48:45 +0100701 high1 >>= PIPE_FRAME_HIGH_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300702 pixel = low & PIPE_PIXEL_MASK;
Chris Wilson5eddb702010-09-11 13:48:45 +0100703 low >>= PIPE_FRAME_LOW_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300704
705 /*
706 * The frame counter increments at beginning of active.
707 * Cook up a vblank counter by also checking the pixel
708 * counter against vblank start.
709 */
Ville Syrjäläedc08d02013-11-06 13:56:27 -0200710 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700711}
712
Ville Syrjäläfd8f5072015-09-18 20:03:42 +0300713static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800714{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300715 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800716
Ville Syrjälä649636e2015-09-22 19:50:01 +0300717 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800718}
719
Mario Kleinerad3543e2013-10-30 05:13:08 +0100720/* raw reads, only for fast reads of display block, no need for forcewake etc. */
721#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
Mario Kleinerad3543e2013-10-30 05:13:08 +0100722
Ville Syrjäläa225f072014-04-29 13:35:45 +0300723static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
724{
725 struct drm_device *dev = crtc->base.dev;
726 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200727 const struct drm_display_mode *mode = &crtc->base.hwmode;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300728 enum pipe pipe = crtc->pipe;
Ville Syrjälä80715b22014-05-15 20:23:23 +0300729 int position, vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300730
Ville Syrjälä80715b22014-05-15 20:23:23 +0300731 vtotal = mode->crtc_vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300732 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
733 vtotal /= 2;
734
735 if (IS_GEN2(dev))
736 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
737 else
738 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
739
740 /*
Jesse Barnes41b578f2015-09-22 12:15:54 -0700741 * On HSW, the DSL reg (0x70000) appears to return 0 if we
742 * read it just before the start of vblank. So try it again
743 * so we don't accidentally end up spanning a vblank frame
744 * increment, causing the pipe_update_end() code to squak at us.
745 *
746 * The nature of this problem means we can't simply check the ISR
747 * bit and return the vblank start value; nor can we use the scanline
748 * debug register in the transcoder as it appears to have the same
749 * problem. We may need to extend this to include other platforms,
750 * but so far testing only shows the problem on HSW.
751 */
752 if (IS_HASWELL(dev) && !position) {
753 int i, temp;
754
755 for (i = 0; i < 100; i++) {
756 udelay(1);
757 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
758 DSL_LINEMASK_GEN3;
759 if (temp != position) {
760 position = temp;
761 break;
762 }
763 }
764 }
765
766 /*
Ville Syrjälä80715b22014-05-15 20:23:23 +0300767 * See update_scanline_offset() for the details on the
768 * scanline_offset adjustment.
Ville Syrjäläa225f072014-04-29 13:35:45 +0300769 */
Ville Syrjälä80715b22014-05-15 20:23:23 +0300770 return (position + crtc->scanline_offset) % vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300771}
772
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700773static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Ville Syrjäläabca9e42013-10-28 20:50:48 +0200774 unsigned int flags, int *vpos, int *hpos,
Ville Syrjälä3bb403b2015-09-14 22:43:44 +0300775 ktime_t *stime, ktime_t *etime,
776 const struct drm_display_mode *mode)
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100777{
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300778 struct drm_i915_private *dev_priv = dev->dev_private;
779 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300781 int position;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300782 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100783 bool in_vbl = true;
784 int ret = 0;
Mario Kleinerad3543e2013-10-30 05:13:08 +0100785 unsigned long irqflags;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100786
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200787 if (WARN_ON(!mode->crtc_clock)) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100788 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800789 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100790 return 0;
791 }
792
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300793 htotal = mode->crtc_htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300794 hsync_start = mode->crtc_hsync_start;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300795 vtotal = mode->crtc_vtotal;
796 vbl_start = mode->crtc_vblank_start;
797 vbl_end = mode->crtc_vblank_end;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100798
Ville Syrjäläd31faf62013-10-28 16:31:41 +0200799 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
800 vbl_start = DIV_ROUND_UP(vbl_start, 2);
801 vbl_end /= 2;
802 vtotal /= 2;
803 }
804
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300805 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
806
Mario Kleinerad3543e2013-10-30 05:13:08 +0100807 /*
808 * Lock uncore.lock, as we will do multiple timing critical raw
809 * register reads, potentially with preemption disabled, so the
810 * following code must not block on uncore.lock.
811 */
812 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300813
Mario Kleinerad3543e2013-10-30 05:13:08 +0100814 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815
816 /* Get optional system timestamp before query. */
817 if (stime)
818 *stime = ktime_get();
819
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300820 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100821 /* No obvious pixelcount register. Only query vertical
822 * scanout position from Display scan line register.
823 */
Ville Syrjäläa225f072014-04-29 13:35:45 +0300824 position = __intel_get_crtc_scanline(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100825 } else {
826 /* Have access to pixelcount since start of frame.
827 * We can split this into vertical and horizontal
828 * scanout position.
829 */
Mario Kleinerad3543e2013-10-30 05:13:08 +0100830 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100831
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300832 /* convert to pixel counts */
833 vbl_start *= htotal;
834 vbl_end *= htotal;
835 vtotal *= htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300836
837 /*
Ville Syrjälä7e78f1cb2014-04-29 13:35:49 +0300838 * In interlaced modes, the pixel counter counts all pixels,
839 * so one field will have htotal more pixels. In order to avoid
840 * the reported position from jumping backwards when the pixel
841 * counter is beyond the length of the shorter field, just
842 * clamp the position the length of the shorter field. This
843 * matches how the scanline counter based position works since
844 * the scanline counter doesn't count the two half lines.
845 */
846 if (position >= vtotal)
847 position = vtotal - 1;
848
849 /*
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300850 * Start of vblank interrupt is triggered at start of hsync,
851 * just prior to the first active line of vblank. However we
852 * consider lines to start at the leading edge of horizontal
853 * active. So, should we get here before we've crossed into
854 * the horizontal active of the first line in vblank, we would
855 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
856 * always add htotal-hsync_start to the current pixel position.
857 */
858 position = (position + htotal - hsync_start) % vtotal;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300859 }
860
Mario Kleinerad3543e2013-10-30 05:13:08 +0100861 /* Get optional system timestamp after query. */
862 if (etime)
863 *etime = ktime_get();
864
865 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
866
867 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
868
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300869 in_vbl = position >= vbl_start && position < vbl_end;
870
871 /*
872 * While in vblank, position will be negative
873 * counting up towards 0 at vbl_end. And outside
874 * vblank, position will be positive counting
875 * up since vbl_end.
876 */
877 if (position >= vbl_start)
878 position -= vbl_end;
879 else
880 position += vtotal - vbl_end;
881
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300882 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300883 *vpos = position;
884 *hpos = 0;
885 } else {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100886 *vpos = position / htotal;
887 *hpos = position - (*vpos * htotal);
888 }
889
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100890 /* In vblank? */
891 if (in_vbl)
Daniel Vetter3d3cbd82014-09-10 17:36:11 +0200892 ret |= DRM_SCANOUTPOS_IN_VBLANK;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100893
894 return ret;
895}
896
Ville Syrjäläa225f072014-04-29 13:35:45 +0300897int intel_get_crtc_scanline(struct intel_crtc *crtc)
898{
899 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
900 unsigned long irqflags;
901 int position;
902
903 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
904 position = __intel_get_crtc_scanline(crtc);
905 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
906
907 return position;
908}
909
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700910static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100911 int *max_error,
912 struct timeval *vblank_time,
913 unsigned flags)
914{
Chris Wilson4041b852011-01-22 10:07:56 +0000915 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100916
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700917 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000918 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100919 return -EINVAL;
920 }
921
922 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000923 crtc = intel_get_crtc_for_pipe(dev, pipe);
924 if (crtc == NULL) {
925 DRM_ERROR("Invalid crtc %d\n", pipe);
926 return -EINVAL;
927 }
928
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200929 if (!crtc->hwmode.crtc_clock) {
Chris Wilson4041b852011-01-22 10:07:56 +0000930 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
931 return -EBUSY;
932 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100933
934 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000935 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
936 vblank_time, flags,
Maarten Lankhorstfc467a222015-06-01 12:50:07 +0200937 &crtc->hwmode);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100938}
939
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200940static void ironlake_rps_change_irq_handler(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800941{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300942 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000943 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200944 u8 new_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200945
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200946 spin_lock(&mchdev_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800947
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200948 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
949
Daniel Vetter20e4d402012-08-08 23:35:39 +0200950 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200951
Jesse Barnes7648fa92010-05-20 14:28:11 -0700952 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000953 busy_up = I915_READ(RCPREVBSYTUPAVG);
954 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800955 max_avg = I915_READ(RCBMAXAVG);
956 min_avg = I915_READ(RCBMINAVG);
957
958 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000959 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200960 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.cur_delay - 1;
962 if (new_delay < dev_priv->ips.max_delay)
963 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000964 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200965 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.cur_delay + 1;
967 if (new_delay > dev_priv->ips.min_delay)
968 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800969 }
970
Jesse Barnes7648fa92010-05-20 14:28:11 -0700971 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200972 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800973
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200974 spin_unlock(&mchdev_lock);
Daniel Vetter92703882012-08-09 16:46:01 +0200975
Jesse Barnesf97108d2010-01-29 11:27:07 -0800976 return;
977}
978
Chris Wilson74cdb332015-04-07 16:21:05 +0100979static void notify_ring(struct intel_engine_cs *ring)
Chris Wilson549f7362010-10-19 11:19:32 +0100980{
Oscar Mateo93b0a4e2014-05-22 14:13:36 +0100981 if (!intel_ring_initialized(ring))
Chris Wilson475553d2011-01-20 09:52:56 +0000982 return;
983
John Harrisonbcfcc8b2014-12-05 13:49:36 +0000984 trace_i915_gem_request_notify(ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000985
Chris Wilson549f7362010-10-19 11:19:32 +0100986 wake_up_all(&ring->irq_queue);
Chris Wilson549f7362010-10-19 11:19:32 +0100987}
988
Chris Wilson43cf3bf2015-03-18 09:48:22 +0000989static void vlv_c0_read(struct drm_i915_private *dev_priv,
990 struct intel_rps_ei *ei)
Deepak S31685c22014-07-03 17:33:01 -0400991{
Chris Wilson43cf3bf2015-03-18 09:48:22 +0000992 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
993 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
994 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
Deepak S31685c22014-07-03 17:33:01 -0400995}
996
Chris Wilson43cf3bf2015-03-18 09:48:22 +0000997static bool vlv_c0_above(struct drm_i915_private *dev_priv,
998 const struct intel_rps_ei *old,
999 const struct intel_rps_ei *now,
1000 int threshold)
Deepak S31685c22014-07-03 17:33:01 -04001001{
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001002 u64 time, c0;
Ville Syrjälä7bad74d2015-09-24 23:29:20 +03001003 unsigned int mul = 100;
Deepak S31685c22014-07-03 17:33:01 -04001004
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001005 if (old->cz_clock == 0)
1006 return false;
Deepak S31685c22014-07-03 17:33:01 -04001007
Ville Syrjälä7bad74d2015-09-24 23:29:20 +03001008 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1009 mul <<= 8;
1010
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001011 time = now->cz_clock - old->cz_clock;
Ville Syrjälä7bad74d2015-09-24 23:29:20 +03001012 time *= threshold * dev_priv->czclk_freq;
Deepak S31685c22014-07-03 17:33:01 -04001013
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001014 /* Workload can be split between render + media, e.g. SwapBuffers
1015 * being blitted in X after being rendered in mesa. To account for
1016 * this we need to combine both engines into our activity counter.
1017 */
1018 c0 = now->render_c0 - old->render_c0;
1019 c0 += now->media_c0 - old->media_c0;
Ville Syrjälä7bad74d2015-09-24 23:29:20 +03001020 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
Deepak S31685c22014-07-03 17:33:01 -04001021
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001022 return c0 >= time;
1023}
Deepak S31685c22014-07-03 17:33:01 -04001024
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001025void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1026{
1027 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1028 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001029}
1030
1031static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1032{
1033 struct intel_rps_ei now;
1034 u32 events = 0;
1035
Chris Wilson6f4b12f82015-03-18 09:48:23 +00001036 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001037 return 0;
1038
1039 vlv_c0_read(dev_priv, &now);
1040 if (now.cz_clock == 0)
1041 return 0;
Deepak S31685c22014-07-03 17:33:01 -04001042
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001043 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1044 if (!vlv_c0_above(dev_priv,
1045 &dev_priv->rps.down_ei, &now,
Chris Wilson8fb55192015-04-07 16:20:28 +01001046 dev_priv->rps.down_threshold))
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001047 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1048 dev_priv->rps.down_ei = now;
Deepak S31685c22014-07-03 17:33:01 -04001049 }
1050
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001051 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1052 if (vlv_c0_above(dev_priv,
1053 &dev_priv->rps.up_ei, &now,
Chris Wilson8fb55192015-04-07 16:20:28 +01001054 dev_priv->rps.up_threshold))
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001055 events |= GEN6_PM_RP_UP_THRESHOLD;
1056 dev_priv->rps.up_ei = now;
1057 }
1058
1059 return events;
Deepak S31685c22014-07-03 17:33:01 -04001060}
1061
Chris Wilsonf5a4c672015-04-27 13:41:23 +01001062static bool any_waiters(struct drm_i915_private *dev_priv)
1063{
1064 struct intel_engine_cs *ring;
1065 int i;
1066
1067 for_each_ring(ring, dev_priv, i)
1068 if (ring->irq_refcount)
1069 return true;
1070
1071 return false;
1072}
1073
Ben Widawsky4912d042011-04-25 11:25:20 -07001074static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001075{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001076 struct drm_i915_private *dev_priv =
1077 container_of(work, struct drm_i915_private, rps.work);
Chris Wilson8d3afd72015-05-21 21:01:47 +01001078 bool client_boost;
1079 int new_delay, adj, min, max;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -03001080 u32 pm_iir;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001081
Daniel Vetter59cdb632013-07-04 23:35:28 +02001082 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001083 /* Speed up work cancelation during disabling rps interrupts. */
1084 if (!dev_priv->rps.interrupts_enabled) {
1085 spin_unlock_irq(&dev_priv->irq_lock);
1086 return;
1087 }
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001088 pm_iir = dev_priv->rps.pm_iir;
1089 dev_priv->rps.pm_iir = 0;
Imre Deaka72fbc32014-11-05 20:48:31 +02001090 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1091 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Chris Wilson8d3afd72015-05-21 21:01:47 +01001092 client_boost = dev_priv->rps.client_boost;
1093 dev_priv->rps.client_boost = false;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001094 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawsky4912d042011-04-25 11:25:20 -07001095
Paulo Zanoni60611c12013-08-15 11:50:01 -03001096 /* Make sure we didn't queue anything we're not going to process. */
Deepak Sa6706b42014-03-15 20:23:22 +05301097 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001098
Chris Wilson8d3afd72015-05-21 21:01:47 +01001099 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001100 return;
1101
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001102 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01001103
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001104 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1105
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001106 adj = dev_priv->rps.last_adj;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001107 new_delay = dev_priv->rps.cur_freq;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001108 min = dev_priv->rps.min_freq_softlimit;
1109 max = dev_priv->rps.max_freq_softlimit;
1110
1111 if (client_boost) {
1112 new_delay = dev_priv->rps.max_freq_softlimit;
1113 adj = 0;
1114 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001115 if (adj > 0)
1116 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001117 else /* CHV needs even encode values */
1118 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
Ville Syrjälä74250342013-06-25 21:38:11 +03001119 /*
1120 * For better performance, jump directly
1121 * to RPe if we're below it.
1122 */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001123 if (new_delay < dev_priv->rps.efficient_freq - adj) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001124 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001125 adj = 0;
1126 }
Chris Wilsonf5a4c672015-04-27 13:41:23 +01001127 } else if (any_waiters(dev_priv)) {
1128 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001129 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001130 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1131 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001132 else
Ben Widawskyb39fb292014-03-19 18:31:11 -07001133 new_delay = dev_priv->rps.min_freq_softlimit;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001134 adj = 0;
1135 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1136 if (adj < 0)
1137 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001138 else /* CHV needs even encode values */
1139 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001140 } else { /* unknown event */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001141 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001142 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001143
Chris Wilsonedcf2842015-04-07 16:20:29 +01001144 dev_priv->rps.last_adj = adj;
1145
Ben Widawsky79249632012-09-07 19:43:42 -07001146 /* sysfs frequency interfaces may have snuck in while servicing the
1147 * interrupt
1148 */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001149 new_delay += adj;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001150 new_delay = clamp_t(int, new_delay, min, max);
Deepak S27544362014-01-27 21:35:05 +05301151
Ville Syrjäläffe02b42015-02-02 19:09:50 +02001152 intel_set_rps(dev_priv->dev, new_delay);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001153
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001154 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001155}
1156
Ben Widawskye3689192012-05-25 16:56:22 -07001157
1158/**
1159 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1160 * occurred.
1161 * @work: workqueue struct
1162 *
1163 * Doesn't actually do anything except notify userspace. As a consequence of
1164 * this event, userspace should try to remap the bad rows since statistically
1165 * it is likely the same row is more likely to go bad again.
1166 */
1167static void ivybridge_parity_work(struct work_struct *work)
1168{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001169 struct drm_i915_private *dev_priv =
1170 container_of(work, struct drm_i915_private, l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001171 u32 error_status, row, bank, subbank;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001172 char *parity_event[6];
Ben Widawskye3689192012-05-25 16:56:22 -07001173 uint32_t misccpctl;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001174 uint8_t slice = 0;
Ben Widawskye3689192012-05-25 16:56:22 -07001175
1176 /* We must turn off DOP level clock gating to access the L3 registers.
1177 * In order to prevent a get/put style interface, acquire struct mutex
1178 * any time we access those registers.
1179 */
1180 mutex_lock(&dev_priv->dev->struct_mutex);
1181
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001182 /* If we've screwed up tracking, just let the interrupt fire again */
1183 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1184 goto out;
1185
Ben Widawskye3689192012-05-25 16:56:22 -07001186 misccpctl = I915_READ(GEN7_MISCCPCTL);
1187 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1188 POSTING_READ(GEN7_MISCCPCTL);
1189
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001190 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1191 u32 reg;
Ben Widawskye3689192012-05-25 16:56:22 -07001192
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001193 slice--;
1194 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1195 break;
1196
1197 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1198
1199 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1200
1201 error_status = I915_READ(reg);
1202 row = GEN7_PARITY_ERROR_ROW(error_status);
1203 bank = GEN7_PARITY_ERROR_BANK(error_status);
1204 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1205
1206 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1207 POSTING_READ(reg);
1208
1209 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1210 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1211 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1212 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1213 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1214 parity_event[5] = NULL;
1215
Dave Airlie5bdebb12013-10-11 14:07:25 +10001216 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001217 KOBJ_CHANGE, parity_event);
1218
1219 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1220 slice, row, bank, subbank);
1221
1222 kfree(parity_event[4]);
1223 kfree(parity_event[3]);
1224 kfree(parity_event[2]);
1225 kfree(parity_event[1]);
1226 }
Ben Widawskye3689192012-05-25 16:56:22 -07001227
1228 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1229
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001230out:
1231 WARN_ON(dev_priv->l3_parity.which_slice);
Daniel Vetter4cb21832014-09-15 14:55:26 +02001232 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001233 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
Daniel Vetter4cb21832014-09-15 14:55:26 +02001234 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001235
1236 mutex_unlock(&dev_priv->dev->struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001237}
1238
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001239static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
Ben Widawskye3689192012-05-25 16:56:22 -07001240{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001241 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3689192012-05-25 16:56:22 -07001242
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001243 if (!HAS_L3_DPF(dev))
Ben Widawskye3689192012-05-25 16:56:22 -07001244 return;
1245
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001246 spin_lock(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001247 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001248 spin_unlock(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001249
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001250 iir &= GT_PARITY_ERROR(dev);
1251 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1252 dev_priv->l3_parity.which_slice |= 1 << 1;
1253
1254 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1255 dev_priv->l3_parity.which_slice |= 1 << 0;
1256
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001257 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001258}
1259
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001260static void ilk_gt_irq_handler(struct drm_device *dev,
1261 struct drm_i915_private *dev_priv,
1262 u32 gt_iir)
1263{
1264 if (gt_iir &
1265 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001266 notify_ring(&dev_priv->ring[RCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001267 if (gt_iir & ILK_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001268 notify_ring(&dev_priv->ring[VCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001269}
1270
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001271static void snb_gt_irq_handler(struct drm_device *dev,
1272 struct drm_i915_private *dev_priv,
1273 u32 gt_iir)
1274{
1275
Ben Widawskycc609d52013-05-28 19:22:29 -07001276 if (gt_iir &
1277 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001278 notify_ring(&dev_priv->ring[RCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001279 if (gt_iir & GT_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001280 notify_ring(&dev_priv->ring[VCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001281 if (gt_iir & GT_BLT_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001282 notify_ring(&dev_priv->ring[BCS]);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001283
Ben Widawskycc609d52013-05-28 19:22:29 -07001284 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1285 GT_BSD_CS_ERROR_INTERRUPT |
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001286 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1287 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
Ben Widawskye3689192012-05-25 16:56:22 -07001288
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001289 if (gt_iir & GT_PARITY_ERROR(dev))
1290 ivybridge_parity_error_irq_handler(dev, gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001291}
1292
Chris Wilson74cdb332015-04-07 16:21:05 +01001293static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
Ben Widawskyabd58f02013-11-02 21:07:09 -07001294 u32 master_ctl)
1295{
Ben Widawskyabd58f02013-11-02 21:07:09 -07001296 irqreturn_t ret = IRQ_NONE;
1297
1298 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
Nick Hoath5dd280b2015-10-20 10:23:51 +01001299 u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
1300 if (iir) {
1301 I915_WRITE_FW(GEN8_GT_IIR(0), iir);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001302 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001303
Nick Hoath5dd280b2015-10-20 10:23:51 +01001304 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001305 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
Nick Hoath5dd280b2015-10-20 10:23:51 +01001306 if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001307 notify_ring(&dev_priv->ring[RCS]);
Thomas Daniele981e7b2014-07-24 17:04:39 +01001308
Nick Hoath5dd280b2015-10-20 10:23:51 +01001309 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001310 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
Nick Hoath5dd280b2015-10-20 10:23:51 +01001311 if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001312 notify_ring(&dev_priv->ring[BCS]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001313 } else
1314 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1315 }
1316
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001317 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
Nick Hoath5dd280b2015-10-20 10:23:51 +01001318 u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
1319 if (iir) {
1320 I915_WRITE_FW(GEN8_GT_IIR(1), iir);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001321 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001322
Nick Hoath5dd280b2015-10-20 10:23:51 +01001323 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001324 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
Nick Hoath5dd280b2015-10-20 10:23:51 +01001325 if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001326 notify_ring(&dev_priv->ring[VCS]);
Thomas Daniele981e7b2014-07-24 17:04:39 +01001327
Nick Hoath5dd280b2015-10-20 10:23:51 +01001328 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001329 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
Nick Hoath5dd280b2015-10-20 10:23:51 +01001330 if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001331 notify_ring(&dev_priv->ring[VCS2]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001332 } else
1333 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1334 }
1335
Chris Wilson74cdb332015-04-07 16:21:05 +01001336 if (master_ctl & GEN8_GT_VECS_IRQ) {
Nick Hoath5dd280b2015-10-20 10:23:51 +01001337 u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
1338 if (iir) {
1339 I915_WRITE_FW(GEN8_GT_IIR(3), iir);
Chris Wilson74cdb332015-04-07 16:21:05 +01001340 ret = IRQ_HANDLED;
1341
Nick Hoath5dd280b2015-10-20 10:23:51 +01001342 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001343 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
Nick Hoath5dd280b2015-10-20 10:23:51 +01001344 if (iir & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001345 notify_ring(&dev_priv->ring[VECS]);
1346 } else
1347 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1348 }
1349
Ben Widawsky09610212014-05-15 20:58:08 +03001350 if (master_ctl & GEN8_GT_PM_IRQ) {
Nick Hoath5dd280b2015-10-20 10:23:51 +01001351 u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
1352 if (iir & dev_priv->pm_rps_events) {
Chris Wilsoncb0d2052015-04-07 16:21:04 +01001353 I915_WRITE_FW(GEN8_GT_IIR(2),
Nick Hoath5dd280b2015-10-20 10:23:51 +01001354 iir & dev_priv->pm_rps_events);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001355 ret = IRQ_HANDLED;
Nick Hoath5dd280b2015-10-20 10:23:51 +01001356 gen6_rps_irq_handler(dev_priv, iir);
Ben Widawsky09610212014-05-15 20:58:08 +03001357 } else
1358 DRM_ERROR("The master control interrupt lied (PM)!\n");
1359 }
1360
Ben Widawskyabd58f02013-11-02 21:07:09 -07001361 return ret;
1362}
1363
Imre Deak63c88d22015-07-20 14:43:39 -07001364static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1365{
1366 switch (port) {
1367 case PORT_A:
Ville Syrjälä195baa02015-08-27 23:56:00 +03001368 return val & PORTA_HOTPLUG_LONG_DETECT;
Imre Deak63c88d22015-07-20 14:43:39 -07001369 case PORT_B:
1370 return val & PORTB_HOTPLUG_LONG_DETECT;
1371 case PORT_C:
1372 return val & PORTC_HOTPLUG_LONG_DETECT;
Imre Deak63c88d22015-07-20 14:43:39 -07001373 default:
1374 return false;
1375 }
1376}
1377
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03001378static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1379{
1380 switch (port) {
1381 case PORT_E:
1382 return val & PORTE_HOTPLUG_LONG_DETECT;
1383 default:
1384 return false;
1385 }
1386}
1387
Ville Syrjälä74c0b392015-08-27 23:56:07 +03001388static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1389{
1390 switch (port) {
1391 case PORT_A:
1392 return val & PORTA_HOTPLUG_LONG_DETECT;
1393 case PORT_B:
1394 return val & PORTB_HOTPLUG_LONG_DETECT;
1395 case PORT_C:
1396 return val & PORTC_HOTPLUG_LONG_DETECT;
1397 case PORT_D:
1398 return val & PORTD_HOTPLUG_LONG_DETECT;
1399 default:
1400 return false;
1401 }
1402}
1403
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03001404static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1405{
1406 switch (port) {
1407 case PORT_A:
1408 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1409 default:
1410 return false;
1411 }
1412}
1413
Jani Nikula676574d2015-05-28 15:43:53 +03001414static bool pch_port_hotplug_long_detect(enum port port, u32 val)
Dave Airlie13cf5502014-06-18 11:29:35 +10001415{
1416 switch (port) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001417 case PORT_B:
Jani Nikula676574d2015-05-28 15:43:53 +03001418 return val & PORTB_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001419 case PORT_C:
Jani Nikula676574d2015-05-28 15:43:53 +03001420 return val & PORTC_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001421 case PORT_D:
Jani Nikula676574d2015-05-28 15:43:53 +03001422 return val & PORTD_HOTPLUG_LONG_DETECT;
1423 default:
1424 return false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001425 }
1426}
1427
Jani Nikula676574d2015-05-28 15:43:53 +03001428static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
Dave Airlie13cf5502014-06-18 11:29:35 +10001429{
1430 switch (port) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001431 case PORT_B:
Jani Nikula676574d2015-05-28 15:43:53 +03001432 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
Dave Airlie13cf5502014-06-18 11:29:35 +10001433 case PORT_C:
Jani Nikula676574d2015-05-28 15:43:53 +03001434 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
Dave Airlie13cf5502014-06-18 11:29:35 +10001435 case PORT_D:
Jani Nikula676574d2015-05-28 15:43:53 +03001436 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1437 default:
1438 return false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001439 }
1440}
1441
Ville Syrjälä42db67d2015-08-28 21:26:27 +03001442/*
1443 * Get a bit mask of pins that have triggered, and which ones may be long.
1444 * This can be called multiple times with the same masks to accumulate
1445 * hotplug detection results from several registers.
1446 *
1447 * Note that the caller is expected to zero out the masks initially.
1448 */
Imre Deakfd63e2a2015-07-21 15:32:44 -07001449static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
Jani Nikula8c841e52015-06-18 13:06:17 +03001450 u32 hotplug_trigger, u32 dig_hotplug_reg,
Imre Deakfd63e2a2015-07-21 15:32:44 -07001451 const u32 hpd[HPD_NUM_PINS],
1452 bool long_pulse_detect(enum port port, u32 val))
Jani Nikula676574d2015-05-28 15:43:53 +03001453{
Jani Nikula8c841e52015-06-18 13:06:17 +03001454 enum port port;
Jani Nikula676574d2015-05-28 15:43:53 +03001455 int i;
1456
Jani Nikula676574d2015-05-28 15:43:53 +03001457 for_each_hpd_pin(i) {
Jani Nikula8c841e52015-06-18 13:06:17 +03001458 if ((hpd[i] & hotplug_trigger) == 0)
1459 continue;
Jani Nikula676574d2015-05-28 15:43:53 +03001460
Jani Nikula8c841e52015-06-18 13:06:17 +03001461 *pin_mask |= BIT(i);
1462
Imre Deakcc24fcd2015-07-21 15:32:45 -07001463 if (!intel_hpd_pin_to_port(i, &port))
1464 continue;
1465
Imre Deakfd63e2a2015-07-21 15:32:44 -07001466 if (long_pulse_detect(port, dig_hotplug_reg))
Jani Nikula8c841e52015-06-18 13:06:17 +03001467 *long_mask |= BIT(i);
Jani Nikula676574d2015-05-28 15:43:53 +03001468 }
1469
1470 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1471 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1472
1473}
1474
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001475static void gmbus_irq_handler(struct drm_device *dev)
1476{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001477 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter28c70f12012-12-01 13:53:45 +01001478
Daniel Vetter28c70f12012-12-01 13:53:45 +01001479 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001480}
1481
Daniel Vetterce99c252012-12-01 13:53:47 +01001482static void dp_aux_irq_handler(struct drm_device *dev)
1483{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001484 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001485
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001486 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +01001487}
1488
Shuang He8bf1e9f2013-10-15 18:55:27 +01001489#if defined(CONFIG_DEBUG_FS)
Daniel Vetter277de952013-10-18 16:37:07 +02001490static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1491 uint32_t crc0, uint32_t crc1,
1492 uint32_t crc2, uint32_t crc3,
1493 uint32_t crc4)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001494{
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1497 struct intel_pipe_crc_entry *entry;
Damien Lespiauac2300d2013-10-15 18:55:30 +01001498 int head, tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001499
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001500 spin_lock(&pipe_crc->lock);
1501
Damien Lespiau0c912c72013-10-15 18:55:37 +01001502 if (!pipe_crc->entries) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001503 spin_unlock(&pipe_crc->lock);
Daniel Vetter34273622014-11-26 16:29:04 +01001504 DRM_DEBUG_KMS("spurious interrupt\n");
Damien Lespiau0c912c72013-10-15 18:55:37 +01001505 return;
1506 }
1507
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001508 head = pipe_crc->head;
1509 tail = pipe_crc->tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001510
1511 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001512 spin_unlock(&pipe_crc->lock);
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001513 DRM_ERROR("CRC buffer overflowing\n");
1514 return;
1515 }
1516
1517 entry = &pipe_crc->entries[head];
Shuang He8bf1e9f2013-10-15 18:55:27 +01001518
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001519 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
Daniel Vettereba94eb2013-10-16 22:55:46 +02001520 entry->crc[0] = crc0;
1521 entry->crc[1] = crc1;
1522 entry->crc[2] = crc2;
1523 entry->crc[3] = crc3;
1524 entry->crc[4] = crc4;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001525
1526 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001527 pipe_crc->head = head;
1528
1529 spin_unlock(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01001530
1531 wake_up_interruptible(&pipe_crc->wq);
Shuang He8bf1e9f2013-10-15 18:55:27 +01001532}
Daniel Vetter277de952013-10-18 16:37:07 +02001533#else
1534static inline void
1535display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1536 uint32_t crc0, uint32_t crc1,
1537 uint32_t crc2, uint32_t crc3,
1538 uint32_t crc4) {}
1539#endif
Daniel Vettereba94eb2013-10-16 22:55:46 +02001540
Daniel Vetter277de952013-10-18 16:37:07 +02001541
1542static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001543{
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545
Daniel Vetter277de952013-10-18 16:37:07 +02001546 display_pipe_crc_irq_handler(dev, pipe,
1547 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1548 0, 0, 0, 0);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001549}
1550
Daniel Vetter277de952013-10-18 16:37:07 +02001551static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vettereba94eb2013-10-16 22:55:46 +02001552{
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554
Daniel Vetter277de952013-10-18 16:37:07 +02001555 display_pipe_crc_irq_handler(dev, pipe,
1556 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1557 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1558 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1559 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1560 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
Daniel Vettereba94eb2013-10-16 22:55:46 +02001561}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001562
Daniel Vetter277de952013-10-18 16:37:07 +02001563static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001564{
1565 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001566 uint32_t res1, res2;
1567
1568 if (INTEL_INFO(dev)->gen >= 3)
1569 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1570 else
1571 res1 = 0;
1572
1573 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1574 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1575 else
1576 res2 = 0;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001577
Daniel Vetter277de952013-10-18 16:37:07 +02001578 display_pipe_crc_irq_handler(dev, pipe,
1579 I915_READ(PIPE_CRC_RES_RED(pipe)),
1580 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1581 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1582 res1, res2);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001583}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001584
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001585/* The RPS events need forcewake, so we add them to a work queue and mask their
1586 * IMR bits until the work is done. Other interrupts can be processed without
1587 * the work queue. */
1588static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
Ben Widawskybaf02a12013-05-28 19:22:24 -07001589{
Deepak Sa6706b42014-03-15 20:23:22 +05301590 if (pm_iir & dev_priv->pm_rps_events) {
Daniel Vetter59cdb632013-07-04 23:35:28 +02001591 spin_lock(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001592 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001593 if (dev_priv->rps.interrupts_enabled) {
1594 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1595 queue_work(dev_priv->wq, &dev_priv->rps.work);
1596 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001597 spin_unlock(&dev_priv->irq_lock);
Ben Widawskybaf02a12013-05-28 19:22:24 -07001598 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001599
Imre Deakc9a9a262014-11-05 20:48:37 +02001600 if (INTEL_INFO(dev_priv)->gen >= 8)
1601 return;
1602
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001603 if (HAS_VEBOX(dev_priv->dev)) {
1604 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001605 notify_ring(&dev_priv->ring[VECS]);
Ben Widawsky12638c52013-05-28 19:22:31 -07001606
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001607 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1608 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
Ben Widawsky12638c52013-05-28 19:22:31 -07001609 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001610}
1611
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001612static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1613{
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001614 if (!drm_handle_vblank(dev, pipe))
1615 return false;
1616
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001617 return true;
1618}
1619
Imre Deakc1874ed2014-02-04 21:35:46 +02001620static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1621{
1622 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak91d181d2014-02-10 18:42:49 +02001623 u32 pipe_stats[I915_MAX_PIPES] = { };
Imre Deakc1874ed2014-02-04 21:35:46 +02001624 int pipe;
1625
Imre Deak58ead0d2014-02-04 21:35:47 +02001626 spin_lock(&dev_priv->irq_lock);
Damien Lespiau055e3932014-08-18 13:49:10 +01001627 for_each_pipe(dev_priv, pipe) {
Imre Deak91d181d2014-02-10 18:42:49 +02001628 int reg;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001629 u32 mask, iir_bit = 0;
Imre Deak91d181d2014-02-10 18:42:49 +02001630
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001631 /*
1632 * PIPESTAT bits get signalled even when the interrupt is
1633 * disabled with the mask bits, and some of the status bits do
1634 * not generate interrupts at all (like the underrun bit). Hence
1635 * we need to be careful that we only handle what we want to
1636 * handle.
1637 */
Daniel Vetter0f239f42014-09-30 10:56:49 +02001638
1639 /* fifo underruns are filterered in the underrun handler. */
1640 mask = PIPE_FIFO_UNDERRUN_STATUS;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001641
1642 switch (pipe) {
1643 case PIPE_A:
1644 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1645 break;
1646 case PIPE_B:
1647 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1648 break;
Ville Syrjälä3278f672014-04-09 13:28:49 +03001649 case PIPE_C:
1650 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1651 break;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001652 }
1653 if (iir & iir_bit)
1654 mask |= dev_priv->pipestat_irq_mask[pipe];
1655
1656 if (!mask)
Imre Deak91d181d2014-02-10 18:42:49 +02001657 continue;
1658
1659 reg = PIPESTAT(pipe);
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001660 mask |= PIPESTAT_INT_ENABLE_MASK;
1661 pipe_stats[pipe] = I915_READ(reg) & mask;
Imre Deakc1874ed2014-02-04 21:35:46 +02001662
1663 /*
1664 * Clear the PIPE*STAT regs before the IIR
1665 */
Imre Deak91d181d2014-02-10 18:42:49 +02001666 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1667 PIPESTAT_INT_STATUS_MASK))
Imre Deakc1874ed2014-02-04 21:35:46 +02001668 I915_WRITE(reg, pipe_stats[pipe]);
1669 }
Imre Deak58ead0d2014-02-04 21:35:47 +02001670 spin_unlock(&dev_priv->irq_lock);
Imre Deakc1874ed2014-02-04 21:35:46 +02001671
Damien Lespiau055e3932014-08-18 13:49:10 +01001672 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01001673 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1674 intel_pipe_handle_vblank(dev, pipe))
1675 intel_check_page_flip(dev, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001676
Imre Deak579a9b02014-02-04 21:35:48 +02001677 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
Imre Deakc1874ed2014-02-04 21:35:46 +02001678 intel_prepare_page_flip(dev, pipe);
1679 intel_finish_page_flip(dev, pipe);
1680 }
1681
1682 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1683 i9xx_pipe_crc_irq_handler(dev, pipe);
1684
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001685 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1686 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001687 }
1688
1689 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1690 gmbus_irq_handler(dev);
1691}
1692
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001693static void i9xx_hpd_irq_handler(struct drm_device *dev)
1694{
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Ville Syrjälä42db67d2015-08-28 21:26:27 +03001697 u32 pin_mask = 0, long_mask = 0;
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001698
Jani Nikula0d2e4292015-05-27 15:03:39 +03001699 if (!hotplug_status)
1700 return;
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001701
Jani Nikula0d2e4292015-05-27 15:03:39 +03001702 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1703 /*
1704 * Make sure hotplug status is cleared before we clear IIR, or else we
1705 * may miss hotplug events.
1706 */
1707 POSTING_READ(PORT_HOTPLUG_STAT);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001708
Jani Nikula0d2e4292015-05-27 15:03:39 +03001709 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1710 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001711
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001712 if (hotplug_trigger) {
1713 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1714 hotplug_trigger, hpd_status_g4x,
1715 i9xx_port_hotplug_long_detect);
1716
1717 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1718 }
Jani Nikula369712e2015-05-27 15:03:40 +03001719
1720 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1721 dp_aux_irq_handler(dev);
Jani Nikula0d2e4292015-05-27 15:03:39 +03001722 } else {
1723 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001724
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001725 if (hotplug_trigger) {
1726 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
Daniel Vetter44cc6c02015-09-30 08:47:41 +02001727 hotplug_trigger, hpd_status_i915,
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001728 i9xx_port_hotplug_long_detect);
Ville Syrjälä58f2cf22015-08-28 22:59:08 +03001729 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1730 }
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001731 }
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001732}
1733
Daniel Vetterff1f5252012-10-02 15:10:55 +02001734static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001735{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001736 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03001737 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001738 u32 iir, gt_iir, pm_iir;
1739 irqreturn_t ret = IRQ_NONE;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001740
Imre Deak2dd2a882015-02-24 11:14:30 +02001741 if (!intel_irqs_enabled(dev_priv))
1742 return IRQ_NONE;
1743
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001744 while (true) {
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001745 /* Find, clear, then process each source of interrupt */
1746
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001747 gt_iir = I915_READ(GTIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001748 if (gt_iir)
1749 I915_WRITE(GTIIR, gt_iir);
1750
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001751 pm_iir = I915_READ(GEN6_PMIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001752 if (pm_iir)
1753 I915_WRITE(GEN6_PMIIR, pm_iir);
1754
1755 iir = I915_READ(VLV_IIR);
1756 if (iir) {
1757 /* Consume port before clearing IIR or we'll miss events */
1758 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1759 i9xx_hpd_irq_handler(dev);
1760 I915_WRITE(VLV_IIR, iir);
1761 }
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001762
1763 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1764 goto out;
1765
1766 ret = IRQ_HANDLED;
1767
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001768 if (gt_iir)
1769 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001770 if (pm_iir)
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001771 gen6_rps_irq_handler(dev_priv, pm_iir);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001772 /* Call regardless, as some status bits might not be
1773 * signalled in iir */
1774 valleyview_pipestat_irq_handler(dev, iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001775 }
1776
1777out:
1778 return ret;
1779}
1780
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001781static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1782{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001783 struct drm_device *dev = arg;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 u32 master_ctl, iir;
1786 irqreturn_t ret = IRQ_NONE;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001787
Imre Deak2dd2a882015-02-24 11:14:30 +02001788 if (!intel_irqs_enabled(dev_priv))
1789 return IRQ_NONE;
1790
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001791 for (;;) {
1792 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1793 iir = I915_READ(VLV_IIR);
Ville Syrjälä3278f672014-04-09 13:28:49 +03001794
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001795 if (master_ctl == 0 && iir == 0)
1796 break;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001797
Oscar Mateo27b6c122014-06-16 16:11:00 +01001798 ret = IRQ_HANDLED;
1799
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001800 I915_WRITE(GEN8_MASTER_IRQ, 0);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001801
Oscar Mateo27b6c122014-06-16 16:11:00 +01001802 /* Find, clear, then process each source of interrupt */
1803
1804 if (iir) {
1805 /* Consume port before clearing IIR or we'll miss events */
1806 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1807 i9xx_hpd_irq_handler(dev);
1808 I915_WRITE(VLV_IIR, iir);
1809 }
1810
Chris Wilson74cdb332015-04-07 16:21:05 +01001811 gen8_gt_irq_handler(dev_priv, master_ctl);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001812
Oscar Mateo27b6c122014-06-16 16:11:00 +01001813 /* Call regardless, as some status bits might not be
1814 * signalled in iir */
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001815 valleyview_pipestat_irq_handler(dev, iir);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001816
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001817 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1818 POSTING_READ(GEN8_MASTER_IRQ);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001819 }
1820
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001821 return ret;
1822}
1823
Ville Syrjälä40e56412015-08-27 23:56:10 +03001824static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1825 const u32 hpd[HPD_NUM_PINS])
1826{
1827 struct drm_i915_private *dev_priv = to_i915(dev);
1828 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1829
1830 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1831 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1832
1833 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1834 dig_hotplug_reg, hpd,
1835 pch_port_hotplug_long_detect);
1836
1837 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1838}
1839
Adam Jackson23e81d62012-06-06 15:45:44 -04001840static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -08001841{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001842 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001843 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001844 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Jesse Barnes776ad802011-01-04 15:09:39 -08001845
Ville Syrjälä40e56412015-08-27 23:56:10 +03001846 if (hotplug_trigger)
1847 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001848
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001849 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1850 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1851 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -08001852 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001853 port_name(port));
1854 }
Jesse Barnes776ad802011-01-04 15:09:39 -08001855
Daniel Vetterce99c252012-12-01 13:53:47 +01001856 if (pch_iir & SDE_AUX_MASK)
1857 dp_aux_irq_handler(dev);
1858
Jesse Barnes776ad802011-01-04 15:09:39 -08001859 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001860 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -08001861
1862 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1863 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1864
1865 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1866 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1867
1868 if (pch_iir & SDE_POISON)
1869 DRM_ERROR("PCH poison interrupt\n");
1870
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001871 if (pch_iir & SDE_FDI_MASK)
Damien Lespiau055e3932014-08-18 13:49:10 +01001872 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001873 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1874 pipe_name(pipe),
1875 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08001876
1877 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1878 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1879
1880 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1881 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1882
Jesse Barnes776ad802011-01-04 15:09:39 -08001883 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001884 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03001885
1886 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001887 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03001888}
1889
1890static void ivb_err_int_handler(struct drm_device *dev)
1891{
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 u32 err_int = I915_READ(GEN7_ERR_INT);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001894 enum pipe pipe;
Paulo Zanoni86642812013-04-12 17:57:57 -03001895
Paulo Zanonide032bf2013-04-12 17:57:58 -03001896 if (err_int & ERR_INT_POISON)
1897 DRM_ERROR("Poison interrupt\n");
1898
Damien Lespiau055e3932014-08-18 13:49:10 +01001899 for_each_pipe(dev_priv, pipe) {
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001900 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1901 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanoni86642812013-04-12 17:57:57 -03001902
Daniel Vetter5a69b892013-10-16 22:55:52 +02001903 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1904 if (IS_IVYBRIDGE(dev))
Daniel Vetter277de952013-10-18 16:37:07 +02001905 ivb_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001906 else
Daniel Vetter277de952013-10-18 16:37:07 +02001907 hsw_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001908 }
1909 }
Shuang He8bf1e9f2013-10-15 18:55:27 +01001910
Paulo Zanoni86642812013-04-12 17:57:57 -03001911 I915_WRITE(GEN7_ERR_INT, err_int);
1912}
1913
1914static void cpt_serr_int_handler(struct drm_device *dev)
1915{
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 u32 serr_int = I915_READ(SERR_INT);
1918
Paulo Zanonide032bf2013-04-12 17:57:58 -03001919 if (serr_int & SERR_INT_POISON)
1920 DRM_ERROR("PCH poison interrupt\n");
1921
Paulo Zanoni86642812013-04-12 17:57:57 -03001922 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001923 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03001924
1925 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001926 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03001927
1928 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001929 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
Paulo Zanoni86642812013-04-12 17:57:57 -03001930
1931 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08001932}
1933
Adam Jackson23e81d62012-06-06 15:45:44 -04001934static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1935{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001936 struct drm_i915_private *dev_priv = dev->dev_private;
Adam Jackson23e81d62012-06-06 15:45:44 -04001937 int pipe;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03001938 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Adam Jackson23e81d62012-06-06 15:45:44 -04001939
Ville Syrjälä40e56412015-08-27 23:56:10 +03001940 if (hotplug_trigger)
1941 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001942
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001943 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1944 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1945 SDE_AUDIO_POWER_SHIFT_CPT);
1946 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1947 port_name(port));
1948 }
Adam Jackson23e81d62012-06-06 15:45:44 -04001949
1950 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +01001951 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001952
1953 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001954 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001955
1956 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1957 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1958
1959 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1960 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1961
1962 if (pch_iir & SDE_FDI_MASK_CPT)
Damien Lespiau055e3932014-08-18 13:49:10 +01001963 for_each_pipe(dev_priv, pipe)
Adam Jackson23e81d62012-06-06 15:45:44 -04001964 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1965 pipe_name(pipe),
1966 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03001967
1968 if (pch_iir & SDE_ERROR_CPT)
1969 cpt_serr_int_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001970}
1971
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03001972static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
1973{
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1976 ~SDE_PORTE_HOTPLUG_SPT;
1977 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1978 u32 pin_mask = 0, long_mask = 0;
1979
1980 if (hotplug_trigger) {
1981 u32 dig_hotplug_reg;
1982
1983 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1984 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1985
1986 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1987 dig_hotplug_reg, hpd_spt,
Ville Syrjälä74c0b392015-08-27 23:56:07 +03001988 spt_port_hotplug_long_detect);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03001989 }
1990
1991 if (hotplug2_trigger) {
1992 u32 dig_hotplug_reg;
1993
1994 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1995 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1996
1997 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
1998 dig_hotplug_reg, hpd_spt,
1999 spt_port_hotplug2_long_detect);
2000 }
2001
2002 if (pin_mask)
2003 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2004
2005 if (pch_iir & SDE_GMBUS_CPT)
2006 gmbus_irq_handler(dev);
2007}
2008
Ville Syrjälä40e56412015-08-27 23:56:10 +03002009static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2010 const u32 hpd[HPD_NUM_PINS])
2011{
2012 struct drm_i915_private *dev_priv = to_i915(dev);
2013 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2014
2015 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2016 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2017
2018 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2019 dig_hotplug_reg, hpd,
2020 ilk_port_hotplug_long_detect);
2021
2022 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2023}
2024
Paulo Zanonic008bc62013-07-12 16:35:10 -03002025static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter40da17c2013-10-21 18:04:36 +02002028 enum pipe pipe;
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03002029 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2030
Ville Syrjälä40e56412015-08-27 23:56:10 +03002031 if (hotplug_trigger)
2032 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002033
2034 if (de_iir & DE_AUX_CHANNEL_A)
2035 dp_aux_irq_handler(dev);
2036
2037 if (de_iir & DE_GSE)
2038 intel_opregion_asle_intr(dev);
2039
Paulo Zanonic008bc62013-07-12 16:35:10 -03002040 if (de_iir & DE_POISON)
2041 DRM_ERROR("Poison interrupt\n");
2042
Damien Lespiau055e3932014-08-18 13:49:10 +01002043 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002044 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2045 intel_pipe_handle_vblank(dev, pipe))
2046 intel_check_page_flip(dev, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002047
Daniel Vetter40da17c2013-10-21 18:04:36 +02002048 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002049 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002050
Daniel Vetter40da17c2013-10-21 18:04:36 +02002051 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2052 i9xx_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002053
Daniel Vetter40da17c2013-10-21 18:04:36 +02002054 /* plane/pipes map 1:1 on ilk+ */
2055 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2056 intel_prepare_page_flip(dev, pipe);
2057 intel_finish_page_flip_plane(dev, pipe);
2058 }
Paulo Zanonic008bc62013-07-12 16:35:10 -03002059 }
2060
2061 /* check event from PCH */
2062 if (de_iir & DE_PCH_EVENT) {
2063 u32 pch_iir = I915_READ(SDEIIR);
2064
2065 if (HAS_PCH_CPT(dev))
2066 cpt_irq_handler(dev, pch_iir);
2067 else
2068 ibx_irq_handler(dev, pch_iir);
2069
2070 /* should clear PCH hotplug event before clear CPU irq */
2071 I915_WRITE(SDEIIR, pch_iir);
2072 }
2073
2074 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2075 ironlake_rps_change_irq_handler(dev);
2076}
2077
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002078static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2079{
2080 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau07d27e22014-03-03 17:31:46 +00002081 enum pipe pipe;
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03002082 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2083
Ville Syrjälä40e56412015-08-27 23:56:10 +03002084 if (hotplug_trigger)
2085 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002086
2087 if (de_iir & DE_ERR_INT_IVB)
2088 ivb_err_int_handler(dev);
2089
2090 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2091 dp_aux_irq_handler(dev);
2092
2093 if (de_iir & DE_GSE_IVB)
2094 intel_opregion_asle_intr(dev);
2095
Damien Lespiau055e3932014-08-18 13:49:10 +01002096 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002097 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2098 intel_pipe_handle_vblank(dev, pipe))
2099 intel_check_page_flip(dev, pipe);
Daniel Vetter40da17c2013-10-21 18:04:36 +02002100
2101 /* plane/pipes map 1:1 on ilk+ */
Damien Lespiau07d27e22014-03-03 17:31:46 +00002102 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2103 intel_prepare_page_flip(dev, pipe);
2104 intel_finish_page_flip_plane(dev, pipe);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002105 }
2106 }
2107
2108 /* check event from PCH */
2109 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2110 u32 pch_iir = I915_READ(SDEIIR);
2111
2112 cpt_irq_handler(dev, pch_iir);
2113
2114 /* clear PCH hotplug event before clear CPU irq */
2115 I915_WRITE(SDEIIR, pch_iir);
2116 }
2117}
2118
Oscar Mateo72c90f62014-06-16 16:10:57 +01002119/*
2120 * To handle irqs with the minimum potential races with fresh interrupts, we:
2121 * 1 - Disable Master Interrupt Control.
2122 * 2 - Find the source(s) of the interrupt.
2123 * 3 - Clear the Interrupt Identity bits (IIR).
2124 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2125 * 5 - Re-enable Master Interrupt Control.
2126 */
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002127static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002128{
Daniel Vetter45a83f82014-05-12 19:17:55 +02002129 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03002130 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002131 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01002132 irqreturn_t ret = IRQ_NONE;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002133
Imre Deak2dd2a882015-02-24 11:14:30 +02002134 if (!intel_irqs_enabled(dev_priv))
2135 return IRQ_NONE;
2136
Paulo Zanoni86642812013-04-12 17:57:57 -03002137 /* We get interrupts on unclaimed registers, so check for this before we
2138 * do any I915_{READ,WRITE}. */
Chris Wilson907b28c2013-07-19 20:36:52 +01002139 intel_uncore_check_errors(dev);
Paulo Zanoni86642812013-04-12 17:57:57 -03002140
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002141 /* disable master interrupt before clearing iir */
2142 de_ier = I915_READ(DEIER);
2143 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Paulo Zanoni23a78512013-07-12 16:35:14 -03002144 POSTING_READ(DEIER);
Chris Wilson0e434062012-05-09 21:45:44 +01002145
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002146 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2147 * interrupts will will be stored on its back queue, and then we'll be
2148 * able to process them after we restore SDEIER (as soon as we restore
2149 * it, we'll get an interrupt if SDEIIR still has something to process
2150 * due to its back queue). */
Ben Widawskyab5c6082013-04-05 13:12:41 -07002151 if (!HAS_PCH_NOP(dev)) {
2152 sde_ier = I915_READ(SDEIER);
2153 I915_WRITE(SDEIER, 0);
2154 POSTING_READ(SDEIER);
2155 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002156
Oscar Mateo72c90f62014-06-16 16:10:57 +01002157 /* Find, clear, then process each source of interrupt */
2158
Chris Wilson0e434062012-05-09 21:45:44 +01002159 gt_iir = I915_READ(GTIIR);
2160 if (gt_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002161 I915_WRITE(GTIIR, gt_iir);
2162 ret = IRQ_HANDLED;
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002163 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002164 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002165 else
2166 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002167 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002168
2169 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01002170 if (de_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002171 I915_WRITE(DEIIR, de_iir);
2172 ret = IRQ_HANDLED;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002173 if (INTEL_INFO(dev)->gen >= 7)
2174 ivb_display_irq_handler(dev, de_iir);
2175 else
2176 ilk_display_irq_handler(dev, de_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002177 }
2178
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002179 if (INTEL_INFO(dev)->gen >= 6) {
2180 u32 pm_iir = I915_READ(GEN6_PMIIR);
2181 if (pm_iir) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002182 I915_WRITE(GEN6_PMIIR, pm_iir);
2183 ret = IRQ_HANDLED;
Oscar Mateo72c90f62014-06-16 16:10:57 +01002184 gen6_rps_irq_handler(dev_priv, pm_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002185 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002186 }
2187
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002188 I915_WRITE(DEIER, de_ier);
2189 POSTING_READ(DEIER);
Ben Widawskyab5c6082013-04-05 13:12:41 -07002190 if (!HAS_PCH_NOP(dev)) {
2191 I915_WRITE(SDEIER, sde_ier);
2192 POSTING_READ(SDEIER);
2193 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002194
2195 return ret;
2196}
2197
Ville Syrjälä40e56412015-08-27 23:56:10 +03002198static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2199 const u32 hpd[HPD_NUM_PINS])
Shashank Sharmad04a4922014-08-22 17:40:41 +05302200{
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002201 struct drm_i915_private *dev_priv = to_i915(dev);
2202 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
Shashank Sharmad04a4922014-08-22 17:40:41 +05302203
Ville Syrjäläa52bb152015-08-27 23:56:11 +03002204 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2205 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302206
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002207 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
Ville Syrjälä40e56412015-08-27 23:56:10 +03002208 dig_hotplug_reg, hpd,
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002209 bxt_port_hotplug_long_detect);
Ville Syrjälä40e56412015-08-27 23:56:10 +03002210
Jani Nikula475c2e32015-05-28 15:43:54 +03002211 intel_hpd_irq_handler(dev, pin_mask, long_mask);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302212}
2213
Ben Widawskyabd58f02013-11-02 21:07:09 -07002214static irqreturn_t gen8_irq_handler(int irq, void *arg)
2215{
2216 struct drm_device *dev = arg;
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 u32 master_ctl;
2219 irqreturn_t ret = IRQ_NONE;
2220 uint32_t tmp = 0;
Daniel Vetterc42664c2013-11-07 11:05:40 +01002221 enum pipe pipe;
Jesse Barnes88e04702014-11-13 17:51:48 +00002222 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2223
Imre Deak2dd2a882015-02-24 11:14:30 +02002224 if (!intel_irqs_enabled(dev_priv))
2225 return IRQ_NONE;
2226
Rodrigo Vivib4834a52015-09-02 15:19:24 -07002227 if (INTEL_INFO(dev_priv)->gen >= 9)
Jesse Barnes88e04702014-11-13 17:51:48 +00002228 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2229 GEN9_AUX_CHANNEL_D;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002230
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002231 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002232 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2233 if (!master_ctl)
2234 return IRQ_NONE;
2235
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002236 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002237
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002238 /* Find, clear, then process each source of interrupt */
2239
Chris Wilson74cdb332015-04-07 16:21:05 +01002240 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002241
2242 if (master_ctl & GEN8_DE_MISC_IRQ) {
2243 tmp = I915_READ(GEN8_DE_MISC_IIR);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002244 if (tmp) {
2245 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2246 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002247 if (tmp & GEN8_DE_MISC_GSE)
2248 intel_opregion_asle_intr(dev);
2249 else
2250 DRM_ERROR("Unexpected DE Misc interrupt\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002251 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002252 else
2253 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002254 }
2255
Daniel Vetter6d766f02013-11-07 14:49:55 +01002256 if (master_ctl & GEN8_DE_PORT_IRQ) {
2257 tmp = I915_READ(GEN8_DE_PORT_IIR);
Daniel Vetter6d766f02013-11-07 14:49:55 +01002258 if (tmp) {
Shashank Sharmad04a4922014-08-22 17:40:41 +05302259 bool found = false;
Ville Syrjäläcebd87a2015-08-27 23:56:09 +03002260 u32 hotplug_trigger = 0;
2261
2262 if (IS_BROXTON(dev_priv))
2263 hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
2264 else if (IS_BROADWELL(dev_priv))
2265 hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
Shashank Sharmad04a4922014-08-22 17:40:41 +05302266
Daniel Vetter6d766f02013-11-07 14:49:55 +01002267 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2268 ret = IRQ_HANDLED;
Jesse Barnes88e04702014-11-13 17:51:48 +00002269
Shashank Sharmad04a4922014-08-22 17:40:41 +05302270 if (tmp & aux_mask) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002271 dp_aux_irq_handler(dev);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302272 found = true;
2273 }
2274
Ville Syrjälä40e56412015-08-27 23:56:10 +03002275 if (hotplug_trigger) {
2276 if (IS_BROXTON(dev))
2277 bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
2278 else
2279 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302280 found = true;
2281 }
2282
Shashank Sharma9e637432014-08-22 17:40:43 +05302283 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2284 gmbus_irq_handler(dev);
2285 found = true;
2286 }
2287
Shashank Sharmad04a4922014-08-22 17:40:41 +05302288 if (!found)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002289 DRM_ERROR("Unexpected DE Port interrupt\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002290 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002291 else
2292 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002293 }
2294
Damien Lespiau055e3932014-08-18 13:49:10 +01002295 for_each_pipe(dev_priv, pipe) {
Damien Lespiau770de832014-03-20 20:45:01 +00002296 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002297
Daniel Vetterc42664c2013-11-07 11:05:40 +01002298 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2299 continue;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002300
Daniel Vetterc42664c2013-11-07 11:05:40 +01002301 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
Daniel Vetterc42664c2013-11-07 11:05:40 +01002302 if (pipe_iir) {
2303 ret = IRQ_HANDLED;
2304 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
Damien Lespiau770de832014-03-20 20:45:01 +00002305
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002306 if (pipe_iir & GEN8_PIPE_VBLANK &&
2307 intel_pipe_handle_vblank(dev, pipe))
2308 intel_check_page_flip(dev, pipe);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002309
Rodrigo Vivib4834a52015-09-02 15:19:24 -07002310 if (INTEL_INFO(dev_priv)->gen >= 9)
Damien Lespiau770de832014-03-20 20:45:01 +00002311 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2312 else
2313 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2314
2315 if (flip_done) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002316 intel_prepare_page_flip(dev, pipe);
2317 intel_finish_page_flip_plane(dev, pipe);
2318 }
2319
2320 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2321 hsw_pipe_crc_irq_handler(dev, pipe);
2322
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002323 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2324 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2325 pipe);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002326
Damien Lespiau770de832014-03-20 20:45:01 +00002327
Rodrigo Vivib4834a52015-09-02 15:19:24 -07002328 if (INTEL_INFO(dev_priv)->gen >= 9)
Damien Lespiau770de832014-03-20 20:45:01 +00002329 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2330 else
2331 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2332
2333 if (fault_errors)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002334 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2335 pipe_name(pipe),
2336 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
Daniel Vetterc42664c2013-11-07 11:05:40 +01002337 } else
Ben Widawskyabd58f02013-11-02 21:07:09 -07002338 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2339 }
2340
Shashank Sharma266ea3d2014-08-22 17:40:42 +05302341 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2342 master_ctl & GEN8_DE_PCH_IRQ) {
Daniel Vetter92d03a82013-11-07 11:05:43 +01002343 /*
2344 * FIXME(BDW): Assume for now that the new interrupt handling
2345 * scheme also closed the SDE interrupt handling race we've seen
2346 * on older pch-split platforms. But this needs testing.
2347 */
2348 u32 pch_iir = I915_READ(SDEIIR);
Daniel Vetter92d03a82013-11-07 11:05:43 +01002349 if (pch_iir) {
2350 I915_WRITE(SDEIIR, pch_iir);
2351 ret = IRQ_HANDLED;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03002352
2353 if (HAS_PCH_SPT(dev_priv))
2354 spt_irq_handler(dev, pch_iir);
2355 else
2356 cpt_irq_handler(dev, pch_iir);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002357 } else
2358 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2359
Daniel Vetter92d03a82013-11-07 11:05:43 +01002360 }
2361
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002362 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2363 POSTING_READ_FW(GEN8_MASTER_IRQ);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002364
2365 return ret;
2366}
2367
Daniel Vetter17e1df02013-09-08 21:57:13 +02002368static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2369 bool reset_completed)
2370{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002371 struct intel_engine_cs *ring;
Daniel Vetter17e1df02013-09-08 21:57:13 +02002372 int i;
2373
2374 /*
2375 * Notify all waiters for GPU completion events that reset state has
2376 * been changed, and that they need to restart their wait after
2377 * checking for potential errors (and bail out to drop locks if there is
2378 * a gpu reset pending so that i915_error_work_func can acquire them).
2379 */
2380
2381 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2382 for_each_ring(ring, dev_priv, i)
2383 wake_up_all(&ring->irq_queue);
2384
2385 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2386 wake_up_all(&dev_priv->pending_flip_queue);
2387
2388 /*
2389 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2390 * reset state is cleared.
2391 */
2392 if (reset_completed)
2393 wake_up_all(&dev_priv->gpu_error.reset_queue);
2394}
2395
Jesse Barnes8a905232009-07-11 16:48:03 -04002396/**
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002397 * i915_reset_and_wakeup - do process context error handling work
Javier Martinez Canillas468f9d22015-10-08 09:54:44 +02002398 * @dev: drm device
Jesse Barnes8a905232009-07-11 16:48:03 -04002399 *
2400 * Fire an error uevent so userspace can see that a hang or error
2401 * was detected.
2402 */
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002403static void i915_reset_and_wakeup(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04002404{
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002405 struct drm_i915_private *dev_priv = to_i915(dev);
2406 struct i915_gpu_error *error = &dev_priv->gpu_error;
Ben Widawskycce723e2013-07-19 09:16:42 -07002407 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2408 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2409 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
Daniel Vetter17e1df02013-09-08 21:57:13 +02002410 int ret;
Jesse Barnes8a905232009-07-11 16:48:03 -04002411
Dave Airlie5bdebb12013-10-11 14:07:25 +10002412 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04002413
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002414 /*
2415 * Note that there's only one work item which does gpu resets, so we
2416 * need not worry about concurrent gpu resets potentially incrementing
2417 * error->reset_counter twice. We only need to take care of another
2418 * racing irq/hangcheck declaring the gpu dead for a second time. A
2419 * quick check for that is good enough: schedule_work ensures the
2420 * correct ordering between hang detection and this work item, and since
2421 * the reset in-progress bit is only ever set by code outside of this
2422 * work we don't need to worry about any other races.
2423 */
2424 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +01002425 DRM_DEBUG_DRIVER("resetting chip\n");
Dave Airlie5bdebb12013-10-11 14:07:25 +10002426 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002427 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002428
Daniel Vetter17e1df02013-09-08 21:57:13 +02002429 /*
Imre Deakf454c692014-04-23 01:09:04 +03002430 * In most cases it's guaranteed that we get here with an RPM
2431 * reference held, for example because there is a pending GPU
2432 * request that won't finish until the reset is done. This
2433 * isn't the case at least when we get here by doing a
2434 * simulated reset via debugs, so get an RPM reference.
2435 */
2436 intel_runtime_pm_get(dev_priv);
Ville Syrjälä75147472014-11-24 18:28:11 +02002437
2438 intel_prepare_reset(dev);
2439
Imre Deakf454c692014-04-23 01:09:04 +03002440 /*
Daniel Vetter17e1df02013-09-08 21:57:13 +02002441 * All state reset _must_ be completed before we update the
2442 * reset counter, for otherwise waiters might miss the reset
2443 * pending state and not properly drop locks, resulting in
2444 * deadlocks with the reset work.
2445 */
Daniel Vetterf69061b2012-12-06 09:01:42 +01002446 ret = i915_reset(dev);
2447
Ville Syrjälä75147472014-11-24 18:28:11 +02002448 intel_finish_reset(dev);
Daniel Vetter17e1df02013-09-08 21:57:13 +02002449
Imre Deakf454c692014-04-23 01:09:04 +03002450 intel_runtime_pm_put(dev_priv);
2451
Daniel Vetterf69061b2012-12-06 09:01:42 +01002452 if (ret == 0) {
2453 /*
2454 * After all the gem state is reset, increment the reset
2455 * counter and wake up everyone waiting for the reset to
2456 * complete.
2457 *
2458 * Since unlock operations are a one-sided barrier only,
2459 * we need to insert a barrier here to order any seqno
2460 * updates before
2461 * the counter increment.
2462 */
Peter Zijlstra4e857c52014-03-17 18:06:10 +01002463 smp_mb__before_atomic();
Daniel Vetterf69061b2012-12-06 09:01:42 +01002464 atomic_inc(&dev_priv->gpu_error.reset_counter);
2465
Dave Airlie5bdebb12013-10-11 14:07:25 +10002466 kobject_uevent_env(&dev->primary->kdev->kobj,
Daniel Vetterf69061b2012-12-06 09:01:42 +01002467 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002468 } else {
Peter Zijlstra805de8f42015-04-24 01:12:32 +02002469 atomic_or(I915_WEDGED, &error->reset_counter);
Ben Gamarif316a422009-09-14 17:48:46 -04002470 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002471
Daniel Vetter17e1df02013-09-08 21:57:13 +02002472 /*
2473 * Note: The wake_up also serves as a memory barrier so that
2474 * waiters see the update value of the reset counter atomic_t.
2475 */
2476 i915_error_wake_up(dev_priv, true);
Ben Gamarif316a422009-09-14 17:48:46 -04002477 }
Jesse Barnes8a905232009-07-11 16:48:03 -04002478}
2479
Chris Wilson35aed2e2010-05-27 13:18:12 +01002480static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04002481{
2482 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07002483 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04002484 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07002485 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04002486
Chris Wilson35aed2e2010-05-27 13:18:12 +01002487 if (!eir)
2488 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04002489
Joe Perchesa70491c2012-03-18 13:00:11 -07002490 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04002491
Ben Widawskybd9854f2012-08-23 15:18:09 -07002492 i915_get_extra_instdone(dev, instdone);
2493
Jesse Barnes8a905232009-07-11 16:48:03 -04002494 if (IS_G4X(dev)) {
2495 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2496 u32 ipeir = I915_READ(IPEIR_I965);
2497
Joe Perchesa70491c2012-03-18 13:00:11 -07002498 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2499 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07002500 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2501 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07002502 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002503 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002504 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002505 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002506 }
2507 if (eir & GM45_ERROR_PAGE_TABLE) {
2508 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002509 pr_err("page table error\n");
2510 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002511 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002512 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002513 }
2514 }
2515
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002516 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002517 if (eir & I915_ERROR_PAGE_TABLE) {
2518 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002519 pr_err("page table error\n");
2520 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002521 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002522 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002523 }
2524 }
2525
2526 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002527 pr_err("memory refresh error:\n");
Damien Lespiau055e3932014-08-18 13:49:10 +01002528 for_each_pipe(dev_priv, pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07002529 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002530 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04002531 /* pipestat has already been acked */
2532 }
2533 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002534 pr_err("instruction error\n");
2535 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07002536 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2537 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002538 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002539 u32 ipeir = I915_READ(IPEIR);
2540
Joe Perchesa70491c2012-03-18 13:00:11 -07002541 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2542 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07002543 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04002544 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002545 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002546 } else {
2547 u32 ipeir = I915_READ(IPEIR_I965);
2548
Joe Perchesa70491c2012-03-18 13:00:11 -07002549 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2550 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07002551 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002552 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002553 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002554 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002555 }
2556 }
2557
2558 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002559 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002560 eir = I915_READ(EIR);
2561 if (eir) {
2562 /*
2563 * some errors might have become stuck,
2564 * mask them.
2565 */
2566 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2567 I915_WRITE(EMR, I915_READ(EMR) | eir);
2568 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2569 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01002570}
2571
2572/**
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002573 * i915_handle_error - handle a gpu error
Chris Wilson35aed2e2010-05-27 13:18:12 +01002574 * @dev: drm device
2575 *
Javier Martinez Canillasaafd8582015-10-08 09:57:49 +02002576 * Do some basic checking of register state at error time and
Chris Wilson35aed2e2010-05-27 13:18:12 +01002577 * dump it to the syslog. Also call i915_capture_error_state() to make
2578 * sure we get a record and make it available in debugfs. Fire a uevent
2579 * so userspace knows something bad happened (should trigger collection
2580 * of a ring dump etc.).
2581 */
Mika Kuoppala58174462014-02-25 17:11:26 +02002582void i915_handle_error(struct drm_device *dev, bool wedged,
2583 const char *fmt, ...)
Chris Wilson35aed2e2010-05-27 13:18:12 +01002584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala58174462014-02-25 17:11:26 +02002586 va_list args;
2587 char error_msg[80];
Chris Wilson35aed2e2010-05-27 13:18:12 +01002588
Mika Kuoppala58174462014-02-25 17:11:26 +02002589 va_start(args, fmt);
2590 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2591 va_end(args);
2592
2593 i915_capture_error_state(dev, wedged, error_msg);
Chris Wilson35aed2e2010-05-27 13:18:12 +01002594 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002595
Ben Gamariba1234d2009-09-14 17:48:47 -04002596 if (wedged) {
Peter Zijlstra805de8f42015-04-24 01:12:32 +02002597 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
Daniel Vetterf69061b2012-12-06 09:01:42 +01002598 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04002599
Ben Gamari11ed50e2009-09-14 17:48:45 -04002600 /*
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002601 * Wakeup waiting processes so that the reset function
2602 * i915_reset_and_wakeup doesn't deadlock trying to grab
2603 * various locks. By bumping the reset counter first, the woken
Daniel Vetter17e1df02013-09-08 21:57:13 +02002604 * processes will see a reset in progress and back off,
2605 * releasing their locks and then wait for the reset completion.
2606 * We must do this for _all_ gpu waiters that might hold locks
2607 * that the reset work needs to acquire.
2608 *
2609 * Note: The wake_up serves as the required memory barrier to
2610 * ensure that the waiters see the updated value of the reset
2611 * counter atomic_t.
Ben Gamari11ed50e2009-09-14 17:48:45 -04002612 */
Daniel Vetter17e1df02013-09-08 21:57:13 +02002613 i915_error_wake_up(dev_priv, false);
Ben Gamari11ed50e2009-09-14 17:48:45 -04002614 }
2615
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002616 i915_reset_and_wakeup(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002617}
2618
Keith Packard42f52ef2008-10-18 19:39:29 -07002619/* Called from drm generic code, passed 'crtc' which
2620 * we use as a pipe index
2621 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002622static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002623{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002624 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002625 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002626
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002627 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002628 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08002629 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002630 PIPE_START_VBLANK_INTERRUPT_STATUS);
Keith Packarde9d21d72008-10-16 11:31:38 -07002631 else
Keith Packard7c463582008-11-04 02:03:27 -08002632 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002633 PIPE_VBLANK_INTERRUPT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002634 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002635
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002636 return 0;
2637}
2638
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002639static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002640{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002641 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002642 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002643 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c2013-10-21 18:04:36 +02002644 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002645
Jesse Barnesf796cf82011-04-07 13:58:17 -07002646 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002647 ironlake_enable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002648 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2649
2650 return 0;
2651}
2652
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002653static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2654{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002655 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002656 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002657
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002658 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002659 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002660 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002661 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2662
2663 return 0;
2664}
2665
Ben Widawskyabd58f02013-11-02 21:07:09 -07002666static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2667{
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002670
Ben Widawskyabd58f02013-11-02 21:07:09 -07002671 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002672 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2673 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2674 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002675 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2676 return 0;
2677}
2678
Keith Packard42f52ef2008-10-18 19:39:29 -07002679/* Called from drm generic code, passed 'crtc' which
2680 * we use as a pipe index
2681 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002682static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002683{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002684 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002685 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002686
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002687 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002688 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002689 PIPE_VBLANK_INTERRUPT_STATUS |
2690 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002691 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2692}
2693
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002694static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002695{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002696 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002697 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002698 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c2013-10-21 18:04:36 +02002699 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002700
2701 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002702 ironlake_disable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002703 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2704}
2705
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002706static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2707{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002708 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002709 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002710
2711 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002712 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002713 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002714 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2715}
2716
Ben Widawskyabd58f02013-11-02 21:07:09 -07002717static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2718{
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002721
Ben Widawskyabd58f02013-11-02 21:07:09 -07002722 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002723 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2724 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2725 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002726 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2727}
2728
Chris Wilson9107e9d2013-06-10 11:20:20 +01002729static bool
Tomas Elf94f7bbe2015-07-09 15:30:57 +01002730ring_idle(struct intel_engine_cs *ring, u32 seqno)
Chris Wilson893eead2010-10-27 14:44:35 +01002731{
Chris Wilson9107e9d2013-06-10 11:20:20 +01002732 return (list_empty(&ring->request_list) ||
Tomas Elf94f7bbe2015-07-09 15:30:57 +01002733 i915_seqno_passed(seqno, ring->last_submitted_seqno));
Ben Gamarif65d9422009-09-14 17:48:44 -04002734}
2735
Daniel Vettera028c4b2014-03-15 00:08:56 +01002736static bool
2737ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2738{
2739 if (INTEL_INFO(dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002740 return (ipehr >> 23) == 0x1c;
Daniel Vettera028c4b2014-03-15 00:08:56 +01002741 } else {
2742 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2743 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2744 MI_SEMAPHORE_REGISTER);
2745 }
2746}
2747
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002748static struct intel_engine_cs *
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002749semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
Daniel Vetter921d42e2014-03-18 10:26:04 +01002750{
2751 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002752 struct intel_engine_cs *signaller;
Daniel Vetter921d42e2014-03-18 10:26:04 +01002753 int i;
2754
2755 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002756 for_each_ring(signaller, dev_priv, i) {
2757 if (ring == signaller)
2758 continue;
2759
2760 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2761 return signaller;
2762 }
Daniel Vetter921d42e2014-03-18 10:26:04 +01002763 } else {
2764 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2765
2766 for_each_ring(signaller, dev_priv, i) {
2767 if(ring == signaller)
2768 continue;
2769
Ben Widawskyebc348b2014-04-29 14:52:28 -07002770 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
Daniel Vetter921d42e2014-03-18 10:26:04 +01002771 return signaller;
2772 }
2773 }
2774
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002775 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2776 ring->id, ipehr, offset);
Daniel Vetter921d42e2014-03-18 10:26:04 +01002777
2778 return NULL;
2779}
2780
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002781static struct intel_engine_cs *
2782semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
Chris Wilsona24a11e2013-03-14 17:52:05 +02002783{
2784 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002785 u32 cmd, ipehr, head;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002786 u64 offset = 0;
2787 int i, backwards;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002788
Tomas Elf381e8ae2015-10-08 19:31:33 +01002789 /*
2790 * This function does not support execlist mode - any attempt to
2791 * proceed further into this function will result in a kernel panic
2792 * when dereferencing ring->buffer, which is not set up in execlist
2793 * mode.
2794 *
2795 * The correct way of doing it would be to derive the currently
2796 * executing ring buffer from the current context, which is derived
2797 * from the currently running request. Unfortunately, to get the
2798 * current request we would have to grab the struct_mutex before doing
2799 * anything else, which would be ill-advised since some other thread
2800 * might have grabbed it already and managed to hang itself, causing
2801 * the hang checker to deadlock.
2802 *
2803 * Therefore, this function does not support execlist mode in its
2804 * current form. Just return NULL and move on.
2805 */
2806 if (ring->buffer == NULL)
2807 return NULL;
2808
Chris Wilsona24a11e2013-03-14 17:52:05 +02002809 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
Daniel Vettera028c4b2014-03-15 00:08:56 +01002810 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
Chris Wilson6274f212013-06-10 11:20:21 +01002811 return NULL;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002812
Daniel Vetter88fe4292014-03-15 00:08:55 +01002813 /*
2814 * HEAD is likely pointing to the dword after the actual command,
2815 * so scan backwards until we find the MBOX. But limit it to just 3
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002816 * or 4 dwords depending on the semaphore wait command size.
2817 * Note that we don't care about ACTHD here since that might
Daniel Vetter88fe4292014-03-15 00:08:55 +01002818 * point at at batch, and semaphores are always emitted into the
2819 * ringbuffer itself.
Chris Wilsona24a11e2013-03-14 17:52:05 +02002820 */
Daniel Vetter88fe4292014-03-15 00:08:55 +01002821 head = I915_READ_HEAD(ring) & HEAD_ADDR;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002822 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002823
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002824 for (i = backwards; i; --i) {
Daniel Vetter88fe4292014-03-15 00:08:55 +01002825 /*
2826 * Be paranoid and presume the hw has gone off into the wild -
2827 * our ring is smaller than what the hardware (and hence
2828 * HEAD_ADDR) allows. Also handles wrap-around.
2829 */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002830 head &= ring->buffer->size - 1;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002831
2832 /* This here seems to blow up */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002833 cmd = ioread32(ring->buffer->virtual_start + head);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002834 if (cmd == ipehr)
2835 break;
2836
Daniel Vetter88fe4292014-03-15 00:08:55 +01002837 head -= 4;
2838 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002839
Daniel Vetter88fe4292014-03-15 00:08:55 +01002840 if (!i)
2841 return NULL;
2842
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002843 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002844 if (INTEL_INFO(ring->dev)->gen >= 8) {
2845 offset = ioread32(ring->buffer->virtual_start + head + 12);
2846 offset <<= 32;
2847 offset = ioread32(ring->buffer->virtual_start + head + 8);
2848 }
2849 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002850}
2851
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002852static int semaphore_passed(struct intel_engine_cs *ring)
Chris Wilson6274f212013-06-10 11:20:21 +01002853{
2854 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002855 struct intel_engine_cs *signaller;
Chris Wilsona0d036b2014-07-19 12:40:42 +01002856 u32 seqno;
Chris Wilson6274f212013-06-10 11:20:21 +01002857
Chris Wilson4be17382014-06-06 10:22:29 +01002858 ring->hangcheck.deadlock++;
Chris Wilson6274f212013-06-10 11:20:21 +01002859
2860 signaller = semaphore_waits_for(ring, &seqno);
Chris Wilson4be17382014-06-06 10:22:29 +01002861 if (signaller == NULL)
2862 return -1;
2863
2864 /* Prevent pathological recursion due to driver bugs */
2865 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
Chris Wilson6274f212013-06-10 11:20:21 +01002866 return -1;
2867
Chris Wilson4be17382014-06-06 10:22:29 +01002868 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2869 return 1;
2870
Chris Wilsona0d036b2014-07-19 12:40:42 +01002871 /* cursory check for an unkickable deadlock */
2872 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2873 semaphore_passed(signaller) < 0)
Chris Wilson4be17382014-06-06 10:22:29 +01002874 return -1;
2875
2876 return 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002877}
2878
2879static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2880{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002881 struct intel_engine_cs *ring;
Chris Wilson6274f212013-06-10 11:20:21 +01002882 int i;
2883
2884 for_each_ring(ring, dev_priv, i)
Chris Wilson4be17382014-06-06 10:22:29 +01002885 ring->hangcheck.deadlock = 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002886}
2887
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002888static enum intel_ring_hangcheck_action
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002889ring_stuck(struct intel_engine_cs *ring, u64 acthd)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002890{
2891 struct drm_device *dev = ring->dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002893 u32 tmp;
2894
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03002895 if (acthd != ring->hangcheck.acthd) {
2896 if (acthd > ring->hangcheck.max_acthd) {
2897 ring->hangcheck.max_acthd = acthd;
2898 return HANGCHECK_ACTIVE;
2899 }
2900
2901 return HANGCHECK_ACTIVE_LOOP;
2902 }
Chris Wilson6274f212013-06-10 11:20:21 +01002903
Chris Wilson9107e9d2013-06-10 11:20:20 +01002904 if (IS_GEN2(dev))
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002905 return HANGCHECK_HUNG;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002906
2907 /* Is the chip hanging on a WAIT_FOR_EVENT?
2908 * If so we can simply poke the RB_WAIT bit
2909 * and break the hang. This should work on
2910 * all but the second generation chipsets.
2911 */
2912 tmp = I915_READ_CTL(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002913 if (tmp & RING_WAIT) {
Mika Kuoppala58174462014-02-25 17:11:26 +02002914 i915_handle_error(dev, false,
2915 "Kicking stuck wait on %s",
2916 ring->name);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002917 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002918 return HANGCHECK_KICK;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002919 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002920
Chris Wilson6274f212013-06-10 11:20:21 +01002921 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2922 switch (semaphore_passed(ring)) {
2923 default:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002924 return HANGCHECK_HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002925 case 1:
Mika Kuoppala58174462014-02-25 17:11:26 +02002926 i915_handle_error(dev, false,
2927 "Kicking stuck semaphore on %s",
2928 ring->name);
Chris Wilson6274f212013-06-10 11:20:21 +01002929 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002930 return HANGCHECK_KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002931 case 0:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002932 return HANGCHECK_WAIT;
Chris Wilson6274f212013-06-10 11:20:21 +01002933 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002934 }
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002935
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002936 return HANGCHECK_HUNG;
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002937}
2938
Chris Wilson737b1502015-01-26 18:03:03 +02002939/*
Ben Gamarif65d9422009-09-14 17:48:44 -04002940 * This is called when the chip hasn't reported back with completed
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002941 * batchbuffers in a long time. We keep track per ring seqno progress and
2942 * if there are no progress, hangcheck score for that ring is increased.
2943 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2944 * we kick the ring. If we see no progress on three subsequent calls
2945 * we assume chip is wedged and try to fix it by resetting the chip.
Ben Gamarif65d9422009-09-14 17:48:44 -04002946 */
Chris Wilson737b1502015-01-26 18:03:03 +02002947static void i915_hangcheck_elapsed(struct work_struct *work)
Ben Gamarif65d9422009-09-14 17:48:44 -04002948{
Chris Wilson737b1502015-01-26 18:03:03 +02002949 struct drm_i915_private *dev_priv =
2950 container_of(work, typeof(*dev_priv),
2951 gpu_error.hangcheck_work.work);
2952 struct drm_device *dev = dev_priv->dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002953 struct intel_engine_cs *ring;
Chris Wilsonb4519512012-05-11 14:29:30 +01002954 int i;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002955 int busy_count = 0, rings_hung = 0;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002956 bool stuck[I915_NUM_RINGS] = { 0 };
2957#define BUSY 1
2958#define KICK 5
2959#define HUNG 20
Chris Wilson893eead2010-10-27 14:44:35 +01002960
Jani Nikulad330a952014-01-21 11:24:25 +02002961 if (!i915.enable_hangcheck)
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07002962 return;
2963
Chris Wilsonb4519512012-05-11 14:29:30 +01002964 for_each_ring(ring, dev_priv, i) {
Chris Wilson50877442014-03-21 12:41:53 +00002965 u64 acthd;
2966 u32 seqno;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002967 bool busy = true;
Chris Wilsonb4519512012-05-11 14:29:30 +01002968
Chris Wilson6274f212013-06-10 11:20:21 +01002969 semaphore_clear_deadlocks(dev_priv);
2970
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002971 seqno = ring->get_seqno(ring, false);
2972 acthd = intel_ring_get_active_head(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01002973
Chris Wilson9107e9d2013-06-10 11:20:20 +01002974 if (ring->hangcheck.seqno == seqno) {
Tomas Elf94f7bbe2015-07-09 15:30:57 +01002975 if (ring_idle(ring, seqno)) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002976 ring->hangcheck.action = HANGCHECK_IDLE;
2977
Chris Wilson9107e9d2013-06-10 11:20:20 +01002978 if (waitqueue_active(&ring->irq_queue)) {
2979 /* Issue a wake-up to catch stuck h/w. */
Chris Wilson094f9a52013-09-25 17:34:55 +01002980 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
Daniel Vetterf4adcd22013-10-28 09:24:13 +01002981 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2982 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2983 ring->name);
2984 else
2985 DRM_INFO("Fake missed irq on %s\n",
2986 ring->name);
Chris Wilson094f9a52013-09-25 17:34:55 +01002987 wake_up_all(&ring->irq_queue);
2988 }
2989 /* Safeguard against driver failure */
2990 ring->hangcheck.score += BUSY;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002991 } else
2992 busy = false;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002993 } else {
Chris Wilson6274f212013-06-10 11:20:21 +01002994 /* We always increment the hangcheck score
2995 * if the ring is busy and still processing
2996 * the same request, so that no single request
2997 * can run indefinitely (such as a chain of
2998 * batches). The only time we do not increment
2999 * the hangcheck score on this ring, if this
3000 * ring is in a legitimate wait for another
3001 * ring. In that case the waiting ring is a
3002 * victim and we want to be sure we catch the
3003 * right culprit. Then every time we do kick
3004 * the ring, add a small increment to the
3005 * score so that we can catch a batch that is
3006 * being repeatedly kicked and so responsible
3007 * for stalling the machine.
3008 */
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03003009 ring->hangcheck.action = ring_stuck(ring,
3010 acthd);
3011
3012 switch (ring->hangcheck.action) {
Mika Kuoppalada661462013-09-06 16:03:28 +03003013 case HANGCHECK_IDLE:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003014 case HANGCHECK_WAIT:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003015 case HANGCHECK_ACTIVE:
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03003016 break;
3017 case HANGCHECK_ACTIVE_LOOP:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003018 ring->hangcheck.score += BUSY;
Chris Wilson6274f212013-06-10 11:20:21 +01003019 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003020 case HANGCHECK_KICK:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003021 ring->hangcheck.score += KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01003022 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03003023 case HANGCHECK_HUNG:
Jani Nikulaea04cb32013-08-11 12:44:02 +03003024 ring->hangcheck.score += HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01003025 stuck[i] = true;
3026 break;
3027 }
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003028 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01003029 } else {
Mika Kuoppalada661462013-09-06 16:03:28 +03003030 ring->hangcheck.action = HANGCHECK_ACTIVE;
3031
Chris Wilson9107e9d2013-06-10 11:20:20 +01003032 /* Gradually reduce the count so that we catch DoS
3033 * attempts across multiple batches.
3034 */
3035 if (ring->hangcheck.score > 0)
3036 ring->hangcheck.score--;
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03003037
3038 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
Chris Wilsond1e61e72012-04-10 17:00:41 +01003039 }
3040
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003041 ring->hangcheck.seqno = seqno;
3042 ring->hangcheck.acthd = acthd;
Chris Wilson9107e9d2013-06-10 11:20:20 +01003043 busy_count += busy;
Chris Wilson893eead2010-10-27 14:44:35 +01003044 }
Eric Anholtb9201c12010-01-08 14:25:16 -08003045
Mika Kuoppala92cab732013-05-24 17:16:07 +03003046 for_each_ring(ring, dev_priv, i) {
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02003047 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
Daniel Vetterb8d88d12013-08-28 10:57:59 +02003048 DRM_INFO("%s on %s\n",
3049 stuck[i] ? "stuck" : "no progress",
3050 ring->name);
Chris Wilsona43adf02013-06-10 11:20:22 +01003051 rings_hung++;
Mika Kuoppala92cab732013-05-24 17:16:07 +03003052 }
3053 }
3054
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003055 if (rings_hung)
Mika Kuoppala58174462014-02-25 17:11:26 +02003056 return i915_handle_error(dev, true, "Ring hung");
Ben Gamarif65d9422009-09-14 17:48:44 -04003057
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003058 if (busy_count)
3059 /* Reset timer case chip hangs without another request
3060 * being added */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003061 i915_queue_hangcheck(dev);
3062}
3063
3064void i915_queue_hangcheck(struct drm_device *dev)
3065{
Chris Wilson737b1502015-01-26 18:03:03 +02003066 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
Chris Wilson672e7b72014-11-19 09:47:19 +00003067
Jani Nikulad330a952014-01-21 11:24:25 +02003068 if (!i915.enable_hangcheck)
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003069 return;
3070
Chris Wilson737b1502015-01-26 18:03:03 +02003071 /* Don't continually defer the hangcheck so that it is always run at
3072 * least once after work has been scheduled on any ring. Otherwise,
3073 * we will ignore a hung ring if a second ring is kept busy.
3074 */
3075
3076 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3077 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04003078}
3079
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003080static void ibx_irq_reset(struct drm_device *dev)
Paulo Zanoni91738a92013-06-05 14:21:51 -03003081{
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083
3084 if (HAS_PCH_NOP(dev))
3085 return;
3086
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003087 GEN5_IRQ_RESET(SDE);
Paulo Zanoni105b1222014-04-01 15:37:17 -03003088
3089 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3090 I915_WRITE(SERR_INT, 0xffffffff);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003091}
Paulo Zanoni105b1222014-04-01 15:37:17 -03003092
Paulo Zanoni622364b2014-04-01 15:37:22 -03003093/*
3094 * SDEIER is also touched by the interrupt handler to work around missed PCH
3095 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3096 * instead we unconditionally enable all PCH interrupt sources here, but then
3097 * only unmask them as needed with SDEIMR.
3098 *
3099 * This function needs to be called before interrupts are enabled.
3100 */
3101static void ibx_irq_pre_postinstall(struct drm_device *dev)
3102{
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3104
3105 if (HAS_PCH_NOP(dev))
3106 return;
3107
3108 WARN_ON(I915_READ(SDEIER) != 0);
Paulo Zanoni91738a92013-06-05 14:21:51 -03003109 I915_WRITE(SDEIER, 0xffffffff);
3110 POSTING_READ(SDEIER);
3111}
3112
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003113static void gen5_gt_irq_reset(struct drm_device *dev)
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003114{
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003117 GEN5_IRQ_RESET(GT);
Paulo Zanonia9d356a2014-04-01 15:37:09 -03003118 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003119 GEN5_IRQ_RESET(GEN6_PM);
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003120}
3121
Linus Torvalds1da177e2005-04-16 15:20:36 -07003122/* drm_dma.h hooks
3123*/
Paulo Zanonibe30b292014-04-01 15:37:25 -03003124static void ironlake_irq_reset(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003125{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003126 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003127
Paulo Zanoni0c841212014-04-01 15:37:27 -03003128 I915_WRITE(HWSTAM, 0xffffffff);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01003129
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003130 GEN5_IRQ_RESET(DE);
Paulo Zanonic6d954c2014-04-01 15:37:18 -03003131 if (IS_GEN7(dev))
3132 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003133
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003134 gen5_gt_irq_reset(dev);
Zhenyu Wangc6501562009-11-03 18:57:21 +00003135
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003136 ibx_irq_reset(dev);
Ben Widawsky7d991632013-05-28 19:22:25 -07003137}
3138
Ville Syrjälä70591a42014-10-30 19:42:58 +02003139static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3140{
3141 enum pipe pipe;
3142
Egbert Eich0706f172015-09-23 16:15:27 +02003143 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
Ville Syrjälä70591a42014-10-30 19:42:58 +02003144 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3145
3146 for_each_pipe(dev_priv, pipe)
3147 I915_WRITE(PIPESTAT(pipe), 0xffff);
3148
3149 GEN5_IRQ_RESET(VLV_);
3150}
3151
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003152static void valleyview_irq_preinstall(struct drm_device *dev)
3153{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003154 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003155
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003156 /* VLV magic */
3157 I915_WRITE(VLV_IMR, 0);
3158 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3159 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3160 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3161
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003162 gen5_gt_irq_reset(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003163
Ville Syrjälä7c4cde32014-10-30 19:42:51 +02003164 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003165
Ville Syrjälä70591a42014-10-30 19:42:58 +02003166 vlv_display_irq_reset(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003167}
3168
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003169static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3170{
3171 GEN8_IRQ_RESET_NDX(GT, 0);
3172 GEN8_IRQ_RESET_NDX(GT, 1);
3173 GEN8_IRQ_RESET_NDX(GT, 2);
3174 GEN8_IRQ_RESET_NDX(GT, 3);
3175}
3176
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003177static void gen8_irq_reset(struct drm_device *dev)
Ben Widawskyabd58f02013-11-02 21:07:09 -07003178{
3179 struct drm_i915_private *dev_priv = dev->dev_private;
3180 int pipe;
3181
Ben Widawskyabd58f02013-11-02 21:07:09 -07003182 I915_WRITE(GEN8_MASTER_IRQ, 0);
3183 POSTING_READ(GEN8_MASTER_IRQ);
3184
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003185 gen8_gt_irq_reset(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003186
Damien Lespiau055e3932014-08-18 13:49:10 +01003187 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003188 if (intel_display_power_is_enabled(dev_priv,
3189 POWER_DOMAIN_PIPE(pipe)))
Paulo Zanoni813bde42014-07-04 11:50:29 -03003190 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003191
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003192 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3193 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3194 GEN5_IRQ_RESET(GEN8_PCU_);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003195
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303196 if (HAS_PCH_SPLIT(dev))
3197 ibx_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003198}
Ben Widawskyabd58f02013-11-02 21:07:09 -07003199
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00003200void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3201 unsigned int pipe_mask)
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003202{
Paulo Zanoni1180e202014-10-07 18:02:52 -03003203 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003204
Daniel Vetter13321782014-09-15 14:55:29 +02003205 spin_lock_irq(&dev_priv->irq_lock);
Damien Lespiaud14c0342015-03-06 18:50:51 +00003206 if (pipe_mask & 1 << PIPE_A)
3207 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3208 dev_priv->de_irq_mask[PIPE_A],
3209 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00003210 if (pipe_mask & 1 << PIPE_B)
3211 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3212 dev_priv->de_irq_mask[PIPE_B],
3213 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3214 if (pipe_mask & 1 << PIPE_C)
3215 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3216 dev_priv->de_irq_mask[PIPE_C],
3217 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
Daniel Vetter13321782014-09-15 14:55:29 +02003218 spin_unlock_irq(&dev_priv->irq_lock);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003219}
3220
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003221static void cherryview_irq_preinstall(struct drm_device *dev)
3222{
3223 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003224
3225 I915_WRITE(GEN8_MASTER_IRQ, 0);
3226 POSTING_READ(GEN8_MASTER_IRQ);
3227
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003228 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003229
3230 GEN5_IRQ_RESET(GEN8_PCU_);
3231
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003232 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3233
Ville Syrjälä70591a42014-10-30 19:42:58 +02003234 vlv_display_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003235}
3236
Ville Syrjälä87a02102015-08-27 23:55:57 +03003237static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3238 const u32 hpd[HPD_NUM_PINS])
3239{
3240 struct drm_i915_private *dev_priv = to_i915(dev);
3241 struct intel_encoder *encoder;
3242 u32 enabled_irqs = 0;
3243
3244 for_each_intel_encoder(dev, encoder)
3245 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3246 enabled_irqs |= hpd[encoder->hpd_pin];
3247
3248 return enabled_irqs;
3249}
3250
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003251static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07003252{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003253 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä87a02102015-08-27 23:55:57 +03003254 u32 hotplug_irqs, hotplug, enabled_irqs;
Keith Packard7fe0b972011-09-19 13:31:02 -07003255
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003256 if (HAS_PCH_IBX(dev)) {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003257 hotplug_irqs = SDE_HOTPLUG_MASK;
Ville Syrjälä87a02102015-08-27 23:55:57 +03003258 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003259 } else {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003260 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
Ville Syrjälä87a02102015-08-27 23:55:57 +03003261 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003262 }
3263
Daniel Vetterfee884e2013-07-04 23:35:21 +02003264 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003265
3266 /*
3267 * Enable digital hotplug on the PCH, and configure the DP short pulse
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003268 * duration to 2ms (which is the minimum in the Display Port spec).
3269 * The pulse duration bits are reserved on LPT+.
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003270 */
Keith Packard7fe0b972011-09-19 13:31:02 -07003271 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3272 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3273 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3274 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3275 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
Ville Syrjälä0b2eb332015-08-27 23:56:05 +03003276 /*
3277 * When CPU and PCH are on the same package, port A
3278 * HPD must be enabled in both north and south.
3279 */
3280 if (HAS_PCH_LPT_LP(dev))
3281 hotplug |= PORTA_HOTPLUG_ENABLE;
Keith Packard7fe0b972011-09-19 13:31:02 -07003282 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003283}
Xiong Zhang26951ca2015-08-17 15:55:50 +08003284
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003285static void spt_hpd_irq_setup(struct drm_device *dev)
3286{
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 u32 hotplug_irqs, hotplug, enabled_irqs;
3289
3290 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3291 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3292
3293 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3294
3295 /* Enable digital hotplug on the PCH */
3296 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3297 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
Ville Syrjälä74c0b392015-08-27 23:56:07 +03003298 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03003299 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3300
3301 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3302 hotplug |= PORTE_HOTPLUG_ENABLE;
3303 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
Keith Packard7fe0b972011-09-19 13:31:02 -07003304}
3305
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003306static void ilk_hpd_irq_setup(struct drm_device *dev)
3307{
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 u32 hotplug_irqs, hotplug, enabled_irqs;
3310
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003311 if (INTEL_INFO(dev)->gen >= 8) {
3312 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3313 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3314
3315 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3316 } else if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003317 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3318 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003319
3320 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003321 } else {
3322 hotplug_irqs = DE_DP_A_HOTPLUG;
3323 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003324
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003325 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3326 }
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003327
3328 /*
3329 * Enable digital hotplug on the CPU, and configure the DP short pulse
3330 * duration to 2ms (which is the minimum in the Display Port spec)
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003331 * The pulse duration bits are reserved on HSW+.
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003332 */
3333 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3334 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3335 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3336 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3337
3338 ibx_hpd_irq_setup(dev);
3339}
3340
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003341static void bxt_hpd_irq_setup(struct drm_device *dev)
3342{
3343 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003344 u32 hotplug_irqs, hotplug, enabled_irqs;
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003345
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003346 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3347 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003348
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003349 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003350
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003351 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3352 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3353 PORTA_HOTPLUG_ENABLE;
3354 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003355}
3356
Paulo Zanonid46da432013-02-08 17:35:15 -02003357static void ibx_irq_postinstall(struct drm_device *dev)
3358{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003359 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003360 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02003361
Daniel Vetter692a04c2013-05-29 21:43:05 +02003362 if (HAS_PCH_NOP(dev))
3363 return;
3364
Paulo Zanoni105b1222014-04-01 15:37:17 -03003365 if (HAS_PCH_IBX(dev))
Daniel Vetter5c673b62014-03-07 20:34:46 +01003366 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
Paulo Zanoni105b1222014-04-01 15:37:17 -03003367 else
Daniel Vetter5c673b62014-03-07 20:34:46 +01003368 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
Paulo Zanoni86642812013-04-12 17:57:57 -03003369
Ville Syrjäläb51a2842015-09-18 20:03:41 +03003370 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
Paulo Zanonid46da432013-02-08 17:35:15 -02003371 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02003372}
3373
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003374static void gen5_gt_irq_postinstall(struct drm_device *dev)
3375{
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 u32 pm_irqs, gt_irqs;
3378
3379 pm_irqs = gt_irqs = 0;
3380
3381 dev_priv->gt_irq_mask = ~0;
Ben Widawsky040d2ba2013-09-19 11:01:40 -07003382 if (HAS_L3_DPF(dev)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003383 /* L3 parity interrupt is always unmasked. */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003384 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3385 gt_irqs |= GT_PARITY_ERROR(dev);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003386 }
3387
3388 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3389 if (IS_GEN5(dev)) {
3390 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3391 ILK_BSD_USER_INTERRUPT;
3392 } else {
3393 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3394 }
3395
Paulo Zanoni35079892014-04-01 15:37:15 -03003396 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003397
3398 if (INTEL_INFO(dev)->gen >= 6) {
Imre Deak78e68d32014-12-15 18:59:27 +02003399 /*
3400 * RPS interrupts will get enabled/disabled on demand when RPS
3401 * itself is enabled/disabled.
3402 */
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003403 if (HAS_VEBOX(dev))
3404 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3405
Paulo Zanoni605cd252013-08-06 18:57:15 -03003406 dev_priv->pm_irq_mask = 0xffffffff;
Paulo Zanoni35079892014-04-01 15:37:15 -03003407 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003408 }
3409}
3410
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003411static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003412{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003413 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003414 u32 display_mask, extra_mask;
3415
3416 if (INTEL_INFO(dev)->gen >= 7) {
3417 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3418 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3419 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003420 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003421 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03003422 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3423 DE_DP_A_HOTPLUG_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003424 } else {
3425 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3426 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003427 DE_AUX_CHANNEL_A |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003428 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3429 DE_POISON);
Ville Syrjäläe4ce95a2015-08-27 23:56:03 +03003430 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3431 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3432 DE_DP_A_HOTPLUG);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003433 }
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003434
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003435 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003436
Paulo Zanoni0c841212014-04-01 15:37:27 -03003437 I915_WRITE(HWSTAM, 0xeffe);
3438
Paulo Zanoni622364b2014-04-01 15:37:22 -03003439 ibx_irq_pre_postinstall(dev);
3440
Paulo Zanoni35079892014-04-01 15:37:15 -03003441 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003442
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003443 gen5_gt_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003444
Paulo Zanonid46da432013-02-08 17:35:15 -02003445 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07003446
Jesse Barnesf97108d2010-01-29 11:27:07 -08003447 if (IS_IRONLAKE_M(dev)) {
Daniel Vetter6005ce42013-06-27 13:44:59 +02003448 /* Enable PCU event interrupts
3449 *
3450 * spinlocking not required here for correctness since interrupt
Daniel Vetter4bc9d432013-06-27 13:44:58 +02003451 * setup is guaranteed to run in single-threaded context. But we
3452 * need it to make the assert_spin_locked happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003453 spin_lock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003454 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
Daniel Vetterd6207432014-09-15 14:55:27 +02003455 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003456 }
3457
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003458 return 0;
3459}
3460
Imre Deakf8b79e52014-03-04 19:23:07 +02003461static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3462{
3463 u32 pipestat_mask;
3464 u32 iir_mask;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003465 enum pipe pipe;
Imre Deakf8b79e52014-03-04 19:23:07 +02003466
3467 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3468 PIPE_FIFO_UNDERRUN_STATUS;
3469
Ville Syrjälä120dda42014-10-30 19:42:57 +02003470 for_each_pipe(dev_priv, pipe)
3471 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003472 POSTING_READ(PIPESTAT(PIPE_A));
3473
3474 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3475 PIPE_CRC_DONE_INTERRUPT_STATUS;
3476
Ville Syrjälä120dda42014-10-30 19:42:57 +02003477 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3478 for_each_pipe(dev_priv, pipe)
3479 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003480
3481 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3482 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3483 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003484 if (IS_CHERRYVIEW(dev_priv))
3485 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
Imre Deakf8b79e52014-03-04 19:23:07 +02003486 dev_priv->irq_mask &= ~iir_mask;
3487
3488 I915_WRITE(VLV_IIR, iir_mask);
3489 I915_WRITE(VLV_IIR, iir_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003490 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003491 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3492 POSTING_READ(VLV_IMR);
Imre Deakf8b79e52014-03-04 19:23:07 +02003493}
3494
3495static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3496{
3497 u32 pipestat_mask;
3498 u32 iir_mask;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003499 enum pipe pipe;
Imre Deakf8b79e52014-03-04 19:23:07 +02003500
3501 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3502 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Imre Deak6c7fba02014-03-10 19:44:48 +02003503 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003504 if (IS_CHERRYVIEW(dev_priv))
3505 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
Imre Deakf8b79e52014-03-04 19:23:07 +02003506
3507 dev_priv->irq_mask |= iir_mask;
Imre Deakf8b79e52014-03-04 19:23:07 +02003508 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003509 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003510 I915_WRITE(VLV_IIR, iir_mask);
3511 I915_WRITE(VLV_IIR, iir_mask);
3512 POSTING_READ(VLV_IIR);
3513
3514 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3515 PIPE_CRC_DONE_INTERRUPT_STATUS;
3516
Ville Syrjälä120dda42014-10-30 19:42:57 +02003517 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3518 for_each_pipe(dev_priv, pipe)
3519 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003520
3521 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3522 PIPE_FIFO_UNDERRUN_STATUS;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003523
3524 for_each_pipe(dev_priv, pipe)
3525 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003526 POSTING_READ(PIPESTAT(PIPE_A));
3527}
3528
3529void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3530{
3531 assert_spin_locked(&dev_priv->irq_lock);
3532
3533 if (dev_priv->display_irqs_enabled)
3534 return;
3535
3536 dev_priv->display_irqs_enabled = true;
3537
Imre Deak950eaba2014-09-08 15:21:09 +03003538 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003539 valleyview_display_irqs_install(dev_priv);
3540}
3541
3542void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3543{
3544 assert_spin_locked(&dev_priv->irq_lock);
3545
3546 if (!dev_priv->display_irqs_enabled)
3547 return;
3548
3549 dev_priv->display_irqs_enabled = false;
3550
Imre Deak950eaba2014-09-08 15:21:09 +03003551 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003552 valleyview_display_irqs_uninstall(dev_priv);
3553}
3554
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003555static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003556{
Imre Deakf8b79e52014-03-04 19:23:07 +02003557 dev_priv->irq_mask = ~0;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003558
Egbert Eich0706f172015-09-23 16:15:27 +02003559 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003560 POSTING_READ(PORT_HOTPLUG_EN);
3561
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003562 I915_WRITE(VLV_IIR, 0xffffffff);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003563 I915_WRITE(VLV_IIR, 0xffffffff);
3564 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3565 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3566 POSTING_READ(VLV_IMR);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003567
Daniel Vetterb79480b2013-06-27 17:52:10 +02003568 /* Interrupt setup is already guaranteed to be single-threaded, this is
3569 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003570 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003571 if (dev_priv->display_irqs_enabled)
3572 valleyview_display_irqs_install(dev_priv);
Daniel Vetterd6207432014-09-15 14:55:27 +02003573 spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003574}
3575
3576static int valleyview_irq_postinstall(struct drm_device *dev)
3577{
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579
3580 vlv_display_irq_postinstall(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003581
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003582 gen5_gt_irq_postinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003583
3584 /* ack & enable invalid PTE error interrupts */
3585#if 0 /* FIXME: add support to irq handler for checking these bits */
3586 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3587 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3588#endif
3589
3590 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003591
3592 return 0;
3593}
3594
Ben Widawskyabd58f02013-11-02 21:07:09 -07003595static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3596{
Ben Widawskyabd58f02013-11-02 21:07:09 -07003597 /* These are interrupts we'll toggle with the ring mask register */
3598 uint32_t gt_interrupts[] = {
3599 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003600 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Ben Widawskyabd58f02013-11-02 21:07:09 -07003601 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003602 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3603 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003604 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003605 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3606 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3607 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003608 0,
Oscar Mateo73d477f2014-07-24 17:04:31 +01003609 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3610 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
Ben Widawskyabd58f02013-11-02 21:07:09 -07003611 };
3612
Ben Widawsky09610212014-05-15 20:58:08 +03003613 dev_priv->pm_irq_mask = 0xffffffff;
Deepak S9a2d2d82014-08-22 08:32:40 +05303614 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3615 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
Imre Deak78e68d32014-12-15 18:59:27 +02003616 /*
3617 * RPS interrupts will get enabled/disabled on demand when RPS itself
3618 * is enabled/disabled.
3619 */
3620 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
Deepak S9a2d2d82014-08-22 08:32:40 +05303621 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003622}
3623
3624static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3625{
Damien Lespiau770de832014-03-20 20:45:01 +00003626 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3627 uint32_t de_pipe_enables;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003628 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3629 u32 de_port_enables;
3630 enum pipe pipe;
Damien Lespiau770de832014-03-20 20:45:01 +00003631
Rodrigo Vivib4834a52015-09-02 15:19:24 -07003632 if (INTEL_INFO(dev_priv)->gen >= 9) {
Damien Lespiau770de832014-03-20 20:45:01 +00003633 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3634 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003635 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3636 GEN9_AUX_CHANNEL_D;
Shashank Sharma9e637432014-08-22 17:40:43 +05303637 if (IS_BROXTON(dev_priv))
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003638 de_port_masked |= BXT_DE_PORT_GMBUS;
3639 } else {
Damien Lespiau770de832014-03-20 20:45:01 +00003640 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3641 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003642 }
Damien Lespiau770de832014-03-20 20:45:01 +00003643
3644 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3645 GEN8_PIPE_FIFO_UNDERRUN;
3646
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003647 de_port_enables = de_port_masked;
Ville Syrjäläa52bb152015-08-27 23:56:11 +03003648 if (IS_BROXTON(dev_priv))
3649 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3650 else if (IS_BROADWELL(dev_priv))
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003651 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3652
Daniel Vetter13b3a0a2013-11-07 15:31:52 +01003653 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3654 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3655 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003656
Damien Lespiau055e3932014-08-18 13:49:10 +01003657 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003658 if (intel_display_power_is_enabled(dev_priv,
Paulo Zanoni813bde42014-07-04 11:50:29 -03003659 POWER_DOMAIN_PIPE(pipe)))
3660 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3661 dev_priv->de_irq_mask[pipe],
3662 de_pipe_enables);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003663
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03003664 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003665}
3666
3667static int gen8_irq_postinstall(struct drm_device *dev)
3668{
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303671 if (HAS_PCH_SPLIT(dev))
3672 ibx_irq_pre_postinstall(dev);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003673
Ben Widawskyabd58f02013-11-02 21:07:09 -07003674 gen8_gt_irq_postinstall(dev_priv);
3675 gen8_de_irq_postinstall(dev_priv);
3676
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303677 if (HAS_PCH_SPLIT(dev))
3678 ibx_irq_postinstall(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003679
3680 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3681 POSTING_READ(GEN8_MASTER_IRQ);
3682
3683 return 0;
3684}
3685
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003686static int cherryview_irq_postinstall(struct drm_device *dev)
3687{
3688 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003689
Ville Syrjäläc2b66792014-10-30 19:43:02 +02003690 vlv_display_irq_postinstall(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003691
3692 gen8_gt_irq_postinstall(dev_priv);
3693
3694 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3695 POSTING_READ(GEN8_MASTER_IRQ);
3696
3697 return 0;
3698}
3699
Ben Widawskyabd58f02013-11-02 21:07:09 -07003700static void gen8_irq_uninstall(struct drm_device *dev)
3701{
3702 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003703
3704 if (!dev_priv)
3705 return;
3706
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003707 gen8_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003708}
3709
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003710static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3711{
3712 /* Interrupt setup is already guaranteed to be single-threaded, this is
3713 * just to make the assert_spin_locked check happy. */
3714 spin_lock_irq(&dev_priv->irq_lock);
3715 if (dev_priv->display_irqs_enabled)
3716 valleyview_display_irqs_uninstall(dev_priv);
3717 spin_unlock_irq(&dev_priv->irq_lock);
3718
3719 vlv_display_irq_reset(dev_priv);
3720
Imre Deakc352d1b2014-11-20 16:05:55 +02003721 dev_priv->irq_mask = ~0;
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003722}
3723
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003724static void valleyview_irq_uninstall(struct drm_device *dev)
3725{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003726 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003727
3728 if (!dev_priv)
3729 return;
3730
Imre Deak843d0e72014-04-14 20:24:23 +03003731 I915_WRITE(VLV_MASTER_IER, 0);
3732
Ville Syrjälä893fce82014-10-30 19:42:56 +02003733 gen5_gt_irq_reset(dev);
3734
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003735 I915_WRITE(HWSTAM, 0xffffffff);
Imre Deakf8b79e52014-03-04 19:23:07 +02003736
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003737 vlv_display_irq_uninstall(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003738}
3739
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003740static void cherryview_irq_uninstall(struct drm_device *dev)
3741{
3742 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003743
3744 if (!dev_priv)
3745 return;
3746
3747 I915_WRITE(GEN8_MASTER_IRQ, 0);
3748 POSTING_READ(GEN8_MASTER_IRQ);
3749
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003750 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003751
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003752 GEN5_IRQ_RESET(GEN8_PCU_);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003753
Ville Syrjäläc2b66792014-10-30 19:43:02 +02003754 vlv_display_irq_uninstall(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003755}
3756
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003757static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003758{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003759 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07003760
3761 if (!dev_priv)
3762 return;
3763
Paulo Zanonibe30b292014-04-01 15:37:25 -03003764 ironlake_irq_reset(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003765}
3766
Chris Wilsonc2798b12012-04-22 21:13:57 +01003767static void i8xx_irq_preinstall(struct drm_device * dev)
3768{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003769 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003770 int pipe;
3771
Damien Lespiau055e3932014-08-18 13:49:10 +01003772 for_each_pipe(dev_priv, pipe)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003773 I915_WRITE(PIPESTAT(pipe), 0);
3774 I915_WRITE16(IMR, 0xffff);
3775 I915_WRITE16(IER, 0x0);
3776 POSTING_READ16(IER);
3777}
3778
3779static int i8xx_irq_postinstall(struct drm_device *dev)
3780{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003781 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003782
Chris Wilsonc2798b12012-04-22 21:13:57 +01003783 I915_WRITE16(EMR,
3784 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3785
3786 /* Unmask the interrupts that we always want on. */
3787 dev_priv->irq_mask =
3788 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3789 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3790 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003791 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003792 I915_WRITE16(IMR, dev_priv->irq_mask);
3793
3794 I915_WRITE16(IER,
3795 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3796 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilsonc2798b12012-04-22 21:13:57 +01003797 I915_USER_INTERRUPT);
3798 POSTING_READ16(IER);
3799
Daniel Vetter379ef822013-10-16 22:55:56 +02003800 /* Interrupt setup is already guaranteed to be single-threaded, this is
3801 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003802 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003803 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3804 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003805 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003806
Chris Wilsonc2798b12012-04-22 21:13:57 +01003807 return 0;
3808}
3809
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003810/*
3811 * Returns true when a page flip has completed.
3812 */
3813static bool i8xx_handle_vblank(struct drm_device *dev,
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003814 int plane, int pipe, u32 iir)
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003815{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003816 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003817 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003818
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03003819 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003820 return false;
3821
3822 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003823 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003824
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003825 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3826 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3827 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3828 * the flip is completed (no longer pending). Since this doesn't raise
3829 * an interrupt per se, we watch for the change at vblank.
3830 */
3831 if (I915_READ16(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003832 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003833
Ville Syrjälä7d475592014-12-17 23:08:03 +02003834 intel_prepare_page_flip(dev, plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003835 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003836 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003837
3838check_page_flip:
3839 intel_check_page_flip(dev, pipe);
3840 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003841}
3842
Daniel Vetterff1f5252012-10-02 15:10:55 +02003843static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003844{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003845 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03003846 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003847 u16 iir, new_iir;
3848 u32 pipe_stats[2];
Chris Wilsonc2798b12012-04-22 21:13:57 +01003849 int pipe;
3850 u16 flip_mask =
3851 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3852 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3853
Imre Deak2dd2a882015-02-24 11:14:30 +02003854 if (!intel_irqs_enabled(dev_priv))
3855 return IRQ_NONE;
3856
Chris Wilsonc2798b12012-04-22 21:13:57 +01003857 iir = I915_READ16(IIR);
3858 if (iir == 0)
3859 return IRQ_NONE;
3860
3861 while (iir & ~flip_mask) {
3862 /* Can't rely on pipestat interrupt bit in iir as it might
3863 * have been cleared after the pipestat interrupt was received.
3864 * It doesn't set the bit in iir again, but it still produces
3865 * interrupts (for non-MSI).
3866 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003867 spin_lock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003868 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01003869 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003870
Damien Lespiau055e3932014-08-18 13:49:10 +01003871 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003872 int reg = PIPESTAT(pipe);
3873 pipe_stats[pipe] = I915_READ(reg);
3874
3875 /*
3876 * Clear the PIPE*STAT regs before the IIR
3877 */
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003878 if (pipe_stats[pipe] & 0x8000ffff)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003879 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003880 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003881 spin_unlock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003882
3883 I915_WRITE16(IIR, iir & ~flip_mask);
3884 new_iir = I915_READ16(IIR); /* Flush posted writes */
3885
Chris Wilsonc2798b12012-04-22 21:13:57 +01003886 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01003887 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003888
Damien Lespiau055e3932014-08-18 13:49:10 +01003889 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003890 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01003891 if (HAS_FBC(dev))
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003892 plane = !plane;
3893
Daniel Vetter4356d582013-10-16 22:55:55 +02003894 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003895 i8xx_handle_vblank(dev, plane, pipe, iir))
3896 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003897
Daniel Vetter4356d582013-10-16 22:55:55 +02003898 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02003899 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003900
Daniel Vetter1f7247c2014-09-30 10:56:48 +02003901 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3902 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3903 pipe);
Daniel Vetter4356d582013-10-16 22:55:55 +02003904 }
Chris Wilsonc2798b12012-04-22 21:13:57 +01003905
3906 iir = new_iir;
3907 }
3908
3909 return IRQ_HANDLED;
3910}
3911
3912static void i8xx_irq_uninstall(struct drm_device * dev)
3913{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003914 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003915 int pipe;
3916
Damien Lespiau055e3932014-08-18 13:49:10 +01003917 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003918 /* Clear enable bits; then clear status bits */
3919 I915_WRITE(PIPESTAT(pipe), 0);
3920 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3921 }
3922 I915_WRITE16(IMR, 0xffff);
3923 I915_WRITE16(IER, 0x0);
3924 I915_WRITE16(IIR, I915_READ16(IIR));
3925}
3926
Chris Wilsona266c7d2012-04-24 22:59:44 +01003927static void i915_irq_preinstall(struct drm_device * dev)
3928{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003929 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003930 int pipe;
3931
Chris Wilsona266c7d2012-04-24 22:59:44 +01003932 if (I915_HAS_HOTPLUG(dev)) {
Egbert Eich0706f172015-09-23 16:15:27 +02003933 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003934 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3935 }
3936
Chris Wilson00d98eb2012-04-24 22:59:48 +01003937 I915_WRITE16(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01003938 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003939 I915_WRITE(PIPESTAT(pipe), 0);
3940 I915_WRITE(IMR, 0xffffffff);
3941 I915_WRITE(IER, 0x0);
3942 POSTING_READ(IER);
3943}
3944
3945static int i915_irq_postinstall(struct drm_device *dev)
3946{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003947 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01003948 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003949
Chris Wilson38bde182012-04-24 22:59:50 +01003950 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3951
3952 /* Unmask the interrupts that we always want on. */
3953 dev_priv->irq_mask =
3954 ~(I915_ASLE_INTERRUPT |
3955 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3956 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3957 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003958 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilson38bde182012-04-24 22:59:50 +01003959
3960 enable_mask =
3961 I915_ASLE_INTERRUPT |
3962 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3963 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilson38bde182012-04-24 22:59:50 +01003964 I915_USER_INTERRUPT;
3965
Chris Wilsona266c7d2012-04-24 22:59:44 +01003966 if (I915_HAS_HOTPLUG(dev)) {
Egbert Eich0706f172015-09-23 16:15:27 +02003967 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003968 POSTING_READ(PORT_HOTPLUG_EN);
3969
Chris Wilsona266c7d2012-04-24 22:59:44 +01003970 /* Enable in IER... */
3971 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3972 /* and unmask in IMR */
3973 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3974 }
3975
Chris Wilsona266c7d2012-04-24 22:59:44 +01003976 I915_WRITE(IMR, dev_priv->irq_mask);
3977 I915_WRITE(IER, enable_mask);
3978 POSTING_READ(IER);
3979
Jani Nikulaf49e38d2013-04-29 13:02:54 +03003980 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003981
Daniel Vetter379ef822013-10-16 22:55:56 +02003982 /* Interrupt setup is already guaranteed to be single-threaded, this is
3983 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003984 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003985 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3986 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003987 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003988
Daniel Vetter20afbda2012-12-11 14:05:07 +01003989 return 0;
3990}
3991
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003992/*
3993 * Returns true when a page flip has completed.
3994 */
3995static bool i915_handle_vblank(struct drm_device *dev,
3996 int plane, int pipe, u32 iir)
3997{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003998 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003999 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4000
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03004001 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004002 return false;
4003
4004 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004005 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004006
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004007 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4008 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4009 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4010 * the flip is completed (no longer pending). Since this doesn't raise
4011 * an interrupt per se, we watch for the change at vblank.
4012 */
4013 if (I915_READ(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004014 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004015
Ville Syrjälä7d475592014-12-17 23:08:03 +02004016 intel_prepare_page_flip(dev, plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004017 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004018 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01004019
4020check_page_flip:
4021 intel_check_page_flip(dev, pipe);
4022 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004023}
4024
Daniel Vetterff1f5252012-10-02 15:10:55 +02004025static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004026{
Daniel Vetter45a83f82014-05-12 19:17:55 +02004027 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03004028 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01004029 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilson38bde182012-04-24 22:59:50 +01004030 u32 flip_mask =
4031 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4032 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01004033 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004034
Imre Deak2dd2a882015-02-24 11:14:30 +02004035 if (!intel_irqs_enabled(dev_priv))
4036 return IRQ_NONE;
4037
Chris Wilsona266c7d2012-04-24 22:59:44 +01004038 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01004039 do {
4040 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01004041 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004042
4043 /* Can't rely on pipestat interrupt bit in iir as it might
4044 * have been cleared after the pipestat interrupt was received.
4045 * It doesn't set the bit in iir again, but it still produces
4046 * interrupts (for non-MSI).
4047 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02004048 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004049 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01004050 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004051
Damien Lespiau055e3932014-08-18 13:49:10 +01004052 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004053 int reg = PIPESTAT(pipe);
4054 pipe_stats[pipe] = I915_READ(reg);
4055
Chris Wilson38bde182012-04-24 22:59:50 +01004056 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01004057 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004058 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01004059 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004060 }
4061 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02004062 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004063
4064 if (!irq_received)
4065 break;
4066
Chris Wilsona266c7d2012-04-24 22:59:44 +01004067 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03004068 if (I915_HAS_HOTPLUG(dev) &&
4069 iir & I915_DISPLAY_PORT_INTERRUPT)
4070 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004071
Chris Wilson38bde182012-04-24 22:59:50 +01004072 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004073 new_iir = I915_READ(IIR); /* Flush posted writes */
4074
Chris Wilsona266c7d2012-04-24 22:59:44 +01004075 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01004076 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004077
Damien Lespiau055e3932014-08-18 13:49:10 +01004078 for_each_pipe(dev_priv, pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01004079 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01004080 if (HAS_FBC(dev))
Chris Wilson38bde182012-04-24 22:59:50 +01004081 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02004082
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004083 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4084 i915_handle_vblank(dev, plane, pipe, iir))
4085 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004086
4087 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4088 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004089
4090 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004091 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004092
Daniel Vetter1f7247c2014-09-30 10:56:48 +02004093 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4094 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4095 pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004096 }
4097
Chris Wilsona266c7d2012-04-24 22:59:44 +01004098 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4099 intel_opregion_asle_intr(dev);
4100
4101 /* With MSI, interrupts are only generated when iir
4102 * transitions from zero to nonzero. If another bit got
4103 * set while we were handling the existing iir bits, then
4104 * we would never get another interrupt.
4105 *
4106 * This is fine on non-MSI as well, as if we hit this path
4107 * we avoid exiting the interrupt handler only to generate
4108 * another one.
4109 *
4110 * Note that for MSI this could cause a stray interrupt report
4111 * if an interrupt landed in the time between writing IIR and
4112 * the posting read. This should be rare enough to never
4113 * trigger the 99% of 100,000 interrupts test for disabling
4114 * stray interrupts.
4115 */
Chris Wilson38bde182012-04-24 22:59:50 +01004116 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004117 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01004118 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004119
4120 return ret;
4121}
4122
4123static void i915_irq_uninstall(struct drm_device * dev)
4124{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004125 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004126 int pipe;
4127
Chris Wilsona266c7d2012-04-24 22:59:44 +01004128 if (I915_HAS_HOTPLUG(dev)) {
Egbert Eich0706f172015-09-23 16:15:27 +02004129 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004130 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4131 }
4132
Chris Wilson00d98eb2012-04-24 22:59:48 +01004133 I915_WRITE16(HWSTAM, 0xffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004134 for_each_pipe(dev_priv, pipe) {
Chris Wilson55b39752012-04-24 22:59:49 +01004135 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01004136 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01004137 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4138 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004139 I915_WRITE(IMR, 0xffffffff);
4140 I915_WRITE(IER, 0x0);
4141
Chris Wilsona266c7d2012-04-24 22:59:44 +01004142 I915_WRITE(IIR, I915_READ(IIR));
4143}
4144
4145static void i965_irq_preinstall(struct drm_device * dev)
4146{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004147 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004148 int pipe;
4149
Egbert Eich0706f172015-09-23 16:15:27 +02004150 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsonadca4732012-05-11 18:01:31 +01004151 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004152
4153 I915_WRITE(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01004154 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004155 I915_WRITE(PIPESTAT(pipe), 0);
4156 I915_WRITE(IMR, 0xffffffff);
4157 I915_WRITE(IER, 0x0);
4158 POSTING_READ(IER);
4159}
4160
4161static int i965_irq_postinstall(struct drm_device *dev)
4162{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004163 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004164 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004165 u32 error_mask;
4166
Chris Wilsona266c7d2012-04-24 22:59:44 +01004167 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004168 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01004169 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004170 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4171 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4172 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4173 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4174 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4175
4176 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004177 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4178 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004179 enable_mask |= I915_USER_INTERRUPT;
4180
4181 if (IS_G4X(dev))
4182 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004183
Daniel Vetterb79480b2013-06-27 17:52:10 +02004184 /* Interrupt setup is already guaranteed to be single-threaded, this is
4185 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02004186 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02004187 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4188 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4189 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02004190 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004191
Chris Wilsona266c7d2012-04-24 22:59:44 +01004192 /*
4193 * Enable some error detection, note the instruction error mask
4194 * bit is reserved, so we leave it masked.
4195 */
4196 if (IS_G4X(dev)) {
4197 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4198 GM45_ERROR_MEM_PRIV |
4199 GM45_ERROR_CP_PRIV |
4200 I915_ERROR_MEMORY_REFRESH);
4201 } else {
4202 error_mask = ~(I915_ERROR_PAGE_TABLE |
4203 I915_ERROR_MEMORY_REFRESH);
4204 }
4205 I915_WRITE(EMR, error_mask);
4206
4207 I915_WRITE(IMR, dev_priv->irq_mask);
4208 I915_WRITE(IER, enable_mask);
4209 POSTING_READ(IER);
4210
Egbert Eich0706f172015-09-23 16:15:27 +02004211 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004212 POSTING_READ(PORT_HOTPLUG_EN);
4213
Jani Nikulaf49e38d2013-04-29 13:02:54 +03004214 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004215
4216 return 0;
4217}
4218
Egbert Eichbac56d52013-02-25 12:06:51 -05004219static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01004220{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004221 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004222 u32 hotplug_en;
4223
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02004224 assert_spin_locked(&dev_priv->irq_lock);
4225
Ville Syrjälä778eb332015-01-09 14:21:13 +02004226 /* Note HDMI and DP share hotplug bits */
4227 /* enable bits are the same for all generations */
Egbert Eich0706f172015-09-23 16:15:27 +02004228 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
Ville Syrjälä778eb332015-01-09 14:21:13 +02004229 /* Programming the CRT detection parameters tends
4230 to generate a spurious hotplug event about three
4231 seconds later. So just do it once.
4232 */
4233 if (IS_G4X(dev))
4234 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Ville Syrjälä778eb332015-01-09 14:21:13 +02004235 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004236
Ville Syrjälä778eb332015-01-09 14:21:13 +02004237 /* Ignore TV since it's buggy */
Egbert Eich0706f172015-09-23 16:15:27 +02004238 i915_hotplug_interrupt_update_locked(dev_priv,
4239 (HOTPLUG_INT_EN_MASK
4240 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK),
4241 hotplug_en);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004242}
4243
Daniel Vetterff1f5252012-10-02 15:10:55 +02004244static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004245{
Daniel Vetter45a83f82014-05-12 19:17:55 +02004246 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03004247 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004248 u32 iir, new_iir;
4249 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01004250 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004251 u32 flip_mask =
4252 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4253 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004254
Imre Deak2dd2a882015-02-24 11:14:30 +02004255 if (!intel_irqs_enabled(dev_priv))
4256 return IRQ_NONE;
4257
Chris Wilsona266c7d2012-04-24 22:59:44 +01004258 iir = I915_READ(IIR);
4259
Chris Wilsona266c7d2012-04-24 22:59:44 +01004260 for (;;) {
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004261 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson2c8ba292012-04-24 22:59:46 +01004262 bool blc_event = false;
4263
Chris Wilsona266c7d2012-04-24 22:59:44 +01004264 /* Can't rely on pipestat interrupt bit in iir as it might
4265 * have been cleared after the pipestat interrupt was received.
4266 * It doesn't set the bit in iir again, but it still produces
4267 * interrupts (for non-MSI).
4268 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02004269 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004270 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01004271 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004272
Damien Lespiau055e3932014-08-18 13:49:10 +01004273 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004274 int reg = PIPESTAT(pipe);
4275 pipe_stats[pipe] = I915_READ(reg);
4276
4277 /*
4278 * Clear the PIPE*STAT regs before the IIR
4279 */
4280 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004281 I915_WRITE(reg, pipe_stats[pipe]);
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004282 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004283 }
4284 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02004285 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004286
4287 if (!irq_received)
4288 break;
4289
4290 ret = IRQ_HANDLED;
4291
4292 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03004293 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4294 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004295
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004296 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004297 new_iir = I915_READ(IIR); /* Flush posted writes */
4298
Chris Wilsona266c7d2012-04-24 22:59:44 +01004299 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01004300 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004301 if (iir & I915_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01004302 notify_ring(&dev_priv->ring[VCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004303
Damien Lespiau055e3932014-08-18 13:49:10 +01004304 for_each_pipe(dev_priv, pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01004305 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004306 i915_handle_vblank(dev, pipe, pipe, iir))
4307 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004308
4309 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4310 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004311
4312 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004313 i9xx_pipe_crc_irq_handler(dev, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004314
Daniel Vetter1f7247c2014-09-30 10:56:48 +02004315 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4316 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004317 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004318
4319 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4320 intel_opregion_asle_intr(dev);
4321
Daniel Vetter515ac2b2012-12-01 13:53:44 +01004322 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4323 gmbus_irq_handler(dev);
4324
Chris Wilsona266c7d2012-04-24 22:59:44 +01004325 /* With MSI, interrupts are only generated when iir
4326 * transitions from zero to nonzero. If another bit got
4327 * set while we were handling the existing iir bits, then
4328 * we would never get another interrupt.
4329 *
4330 * This is fine on non-MSI as well, as if we hit this path
4331 * we avoid exiting the interrupt handler only to generate
4332 * another one.
4333 *
4334 * Note that for MSI this could cause a stray interrupt report
4335 * if an interrupt landed in the time between writing IIR and
4336 * the posting read. This should be rare enough to never
4337 * trigger the 99% of 100,000 interrupts test for disabling
4338 * stray interrupts.
4339 */
4340 iir = new_iir;
4341 }
4342
4343 return ret;
4344}
4345
4346static void i965_irq_uninstall(struct drm_device * dev)
4347{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004348 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004349 int pipe;
4350
4351 if (!dev_priv)
4352 return;
4353
Egbert Eich0706f172015-09-23 16:15:27 +02004354 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
Chris Wilsonadca4732012-05-11 18:01:31 +01004355 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004356
4357 I915_WRITE(HWSTAM, 0xffffffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004358 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004359 I915_WRITE(PIPESTAT(pipe), 0);
4360 I915_WRITE(IMR, 0xffffffff);
4361 I915_WRITE(IER, 0x0);
4362
Damien Lespiau055e3932014-08-18 13:49:10 +01004363 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004364 I915_WRITE(PIPESTAT(pipe),
4365 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4366 I915_WRITE(IIR, I915_READ(IIR));
4367}
4368
Daniel Vetterfca52a52014-09-30 10:56:45 +02004369/**
4370 * intel_irq_init - initializes irq support
4371 * @dev_priv: i915 device instance
4372 *
4373 * This function initializes all the irq support including work items, timers
4374 * and all the vtables. It does not setup the interrupt itself though.
4375 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004376void intel_irq_init(struct drm_i915_private *dev_priv)
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004377{
Daniel Vetterb9632912014-09-30 10:56:44 +02004378 struct drm_device *dev = dev_priv->dev;
Chris Wilson8b2e3262012-04-24 22:59:41 +01004379
Jani Nikula77913b32015-06-18 13:06:16 +03004380 intel_hpd_init_work(dev_priv);
4381
Daniel Vetterc6a828d2012-08-08 23:35:35 +02004382 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01004383 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01004384
Deepak Sa6706b42014-03-15 20:23:22 +05304385 /* Let's track the enabled rps events */
Daniel Vetterb9632912014-09-30 10:56:44 +02004386 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä6c65a582014-08-29 14:14:07 +03004387 /* WaGsvRC0ResidencyMethod:vlv */
Chris Wilson6f4b12f82015-03-18 09:48:23 +00004388 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
Deepak S31685c22014-07-03 17:33:01 -04004389 else
4390 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
Deepak Sa6706b42014-03-15 20:23:22 +05304391
Chris Wilson737b1502015-01-26 18:03:03 +02004392 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4393 i915_hangcheck_elapsed);
Daniel Vetter61bac782012-12-01 21:03:21 +01004394
Tomas Janousek97a19a22012-12-08 13:48:13 +01004395 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01004396
Daniel Vetterb9632912014-09-30 10:56:44 +02004397 if (IS_GEN2(dev_priv)) {
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +03004398 dev->max_vblank_count = 0;
4399 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
Daniel Vetterb9632912014-09-30 10:56:44 +02004400 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004401 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
Ville Syrjäläfd8f5072015-09-18 20:03:42 +03004402 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
Ville Syrjälä391f75e2013-09-25 19:55:26 +03004403 } else {
4404 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4405 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004406 }
4407
Ville Syrjälä21da2702014-08-06 14:49:55 +03004408 /*
4409 * Opt out of the vblank disable timer on everything except gen2.
4410 * Gen2 doesn't have a hardware frame counter and so depends on
4411 * vblank interrupts to produce sane vblank seuquence numbers.
4412 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004413 if (!IS_GEN2(dev_priv))
Ville Syrjälä21da2702014-08-06 14:49:55 +03004414 dev->vblank_disable_immediate = true;
4415
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +01004416 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4417 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004418
Daniel Vetterb9632912014-09-30 10:56:44 +02004419 if (IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä43f328d2014-04-09 20:40:52 +03004420 dev->driver->irq_handler = cherryview_irq_handler;
4421 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4422 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4423 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4424 dev->driver->enable_vblank = valleyview_enable_vblank;
4425 dev->driver->disable_vblank = valleyview_disable_vblank;
4426 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004427 } else if (IS_VALLEYVIEW(dev_priv)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07004428 dev->driver->irq_handler = valleyview_irq_handler;
4429 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4430 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4431 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4432 dev->driver->enable_vblank = valleyview_enable_vblank;
4433 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05004434 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004435 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07004436 dev->driver->irq_handler = gen8_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004437 dev->driver->irq_preinstall = gen8_irq_reset;
Ben Widawskyabd58f02013-11-02 21:07:09 -07004438 dev->driver->irq_postinstall = gen8_irq_postinstall;
4439 dev->driver->irq_uninstall = gen8_irq_uninstall;
4440 dev->driver->enable_vblank = gen8_enable_vblank;
4441 dev->driver->disable_vblank = gen8_disable_vblank;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03004442 if (IS_BROXTON(dev))
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02004443 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
Ville Syrjälä6dbf30c2015-08-27 23:56:02 +03004444 else if (HAS_PCH_SPT(dev))
4445 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4446 else
Ville Syrjälä3a3b3c72015-08-27 23:56:06 +03004447 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004448 } else if (HAS_PCH_SPLIT(dev)) {
4449 dev->driver->irq_handler = ironlake_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004450 dev->driver->irq_preinstall = ironlake_irq_reset;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004451 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4452 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4453 dev->driver->enable_vblank = ironlake_enable_vblank;
4454 dev->driver->disable_vblank = ironlake_disable_vblank;
Ville Syrjälä23bb4cb2015-08-27 23:56:04 +03004455 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004456 } else {
Daniel Vetterb9632912014-09-30 10:56:44 +02004457 if (INTEL_INFO(dev_priv)->gen == 2) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01004458 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4459 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4460 dev->driver->irq_handler = i8xx_irq_handler;
4461 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Daniel Vetterb9632912014-09-30 10:56:44 +02004462 } else if (INTEL_INFO(dev_priv)->gen == 3) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004463 dev->driver->irq_preinstall = i915_irq_preinstall;
4464 dev->driver->irq_postinstall = i915_irq_postinstall;
4465 dev->driver->irq_uninstall = i915_irq_uninstall;
4466 dev->driver->irq_handler = i915_irq_handler;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004467 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004468 dev->driver->irq_preinstall = i965_irq_preinstall;
4469 dev->driver->irq_postinstall = i965_irq_postinstall;
4470 dev->driver->irq_uninstall = i965_irq_uninstall;
4471 dev->driver->irq_handler = i965_irq_handler;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004472 }
Ville Syrjälä778eb332015-01-09 14:21:13 +02004473 if (I915_HAS_HOTPLUG(dev_priv))
4474 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004475 dev->driver->enable_vblank = i915_enable_vblank;
4476 dev->driver->disable_vblank = i915_disable_vblank;
4477 }
4478}
Daniel Vetter20afbda2012-12-11 14:05:07 +01004479
Daniel Vetterfca52a52014-09-30 10:56:45 +02004480/**
Daniel Vetterfca52a52014-09-30 10:56:45 +02004481 * intel_irq_install - enables the hardware interrupt
4482 * @dev_priv: i915 device instance
4483 *
4484 * This function enables the hardware interrupt handling, but leaves the hotplug
4485 * handling still disabled. It is called after intel_irq_init().
4486 *
4487 * In the driver load and resume code we need working interrupts in a few places
4488 * but don't want to deal with the hassle of concurrent probe and hotplug
4489 * workers. Hence the split into this two-stage approach.
4490 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004491int intel_irq_install(struct drm_i915_private *dev_priv)
4492{
4493 /*
4494 * We enable some interrupt sources in our postinstall hooks, so mark
4495 * interrupts as enabled _before_ actually enabling them to avoid
4496 * special cases in our ordering checks.
4497 */
4498 dev_priv->pm.irqs_enabled = true;
4499
4500 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4501}
4502
Daniel Vetterfca52a52014-09-30 10:56:45 +02004503/**
4504 * intel_irq_uninstall - finilizes all irq handling
4505 * @dev_priv: i915 device instance
4506 *
4507 * This stops interrupt and hotplug handling and unregisters and frees all
4508 * resources acquired in the init functions.
4509 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004510void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4511{
4512 drm_irq_uninstall(dev_priv->dev);
4513 intel_hpd_cancel_work(dev_priv);
4514 dev_priv->pm.irqs_enabled = false;
4515}
4516
Daniel Vetterfca52a52014-09-30 10:56:45 +02004517/**
4518 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4519 * @dev_priv: i915 device instance
4520 *
4521 * This function is used to disable interrupts at runtime, both in the runtime
4522 * pm and the system suspend/resume code.
4523 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004524void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004525{
Daniel Vetterb9632912014-09-30 10:56:44 +02004526 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004527 dev_priv->pm.irqs_enabled = false;
Imre Deak2dd2a882015-02-24 11:14:30 +02004528 synchronize_irq(dev_priv->dev->irq);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004529}
4530
Daniel Vetterfca52a52014-09-30 10:56:45 +02004531/**
4532 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4533 * @dev_priv: i915 device instance
4534 *
4535 * This function is used to enable interrupts at runtime, both in the runtime
4536 * pm and the system suspend/resume code.
4537 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004538void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004539{
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004540 dev_priv->pm.irqs_enabled = true;
Daniel Vetterb9632912014-09-30 10:56:44 +02004541 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4542 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004543}