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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Jesse Barnes5669fca2009-02-17 15:13:31 -080030#include <linux/device.h>
Jesse Barnese5747e32014-06-12 08:35:47 -070031#include <linux/acpi.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drv.h"
Chris Wilson990bbda2012-07-02 11:51:02 -030035#include "i915_trace.h"
Kenneth Graunkef49f0582010-09-11 01:19:14 -070036#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040039#include <linux/module.h>
Imre Deakd6102972014-05-07 19:57:49 +030040#include <linux/pm_runtime.h>
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/drm_crtc_helper.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080042
Kristian Høgsberg112b7152009-01-04 16:55:33 -050043static struct drm_driver driver;
44
Antti Koskipaaa57c7742014-02-04 14:22:24 +020045#define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
Antti Koskipaaa57c7742014-02-04 14:22:24 +020050 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030052#define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
Rafael Barbalho84fd4f42014-04-28 14:00:42 +030057 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
Antti Koskipaaa57c7742014-02-04 14:22:24 +020059
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030060#define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63#define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
Tobias Klauser9a7e8492010-05-20 10:33:46 +020066static const struct intel_device_info intel_i830_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070067 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +010068 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070069 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020070 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030071 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050072};
73
Tobias Klauser9a7e8492010-05-20 10:33:46 +020074static const struct intel_device_info intel_845g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070075 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010076 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070077 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020078 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030079 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050080};
81
Tobias Klauser9a7e8492010-05-20 10:33:46 +020082static const struct intel_device_info intel_i85x_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070083 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
Adam Jackson5ce8ba72010-04-15 14:03:30 -040084 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +010085 .has_overlay = 1, .overlay_needs_physical = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +020086 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070087 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020088 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030089 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050090};
91
Tobias Klauser9a7e8492010-05-20 10:33:46 +020092static const struct intel_device_info intel_i865g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -070093 .gen = 2, .num_pipes = 1,
Chris Wilson315781482010-08-12 09:42:51 +010094 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -070095 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +020096 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030097 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -050098};
99
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200100static const struct intel_device_info intel_i915g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100102 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700103 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200104 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300105 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500106};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200107static const struct intel_device_info intel_i915gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500109 .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100110 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100111 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200112 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700113 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200114 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300115 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500116};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200117static const struct intel_device_info intel_i945g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
Chris Wilson315781482010-08-12 09:42:51 +0100119 .has_overlay = 1, .overlay_needs_physical = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700120 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200121 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300122 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500123};
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200124static const struct intel_device_info intel_i945gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -0500126 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100128 .supports_tv = 1,
Ville Syrjäläfd70d522013-11-28 17:30:02 +0200129 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700130 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200131 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300132 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500133};
134
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200135static const struct intel_device_info intel_i965g_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100137 .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100138 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700139 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200140 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300141 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500142};
143
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200144static const struct intel_device_info intel_i965gm_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100147 .has_overlay = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100148 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700149 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200150 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300151 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500152};
153
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200154static const struct intel_device_info intel_g33_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100156 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100157 .has_overlay = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700158 .ring_mask = RENDER_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200159 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300160 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500161};
162
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200163static const struct intel_device_info intel_g45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100165 .has_pipe_cxsr = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700166 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200167 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300168 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500169};
170
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200171static const struct intel_device_info intel_gm45_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100174 .has_pipe_cxsr = 1, .has_hotplug = 1,
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100175 .supports_tv = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700176 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200177 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300178 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500179};
180
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200181static const struct intel_device_info intel_pineview_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100183 .need_gfx_hws = 1, .has_hotplug = 1,
Chris Wilson315781482010-08-12 09:42:51 +0100184 .has_overlay = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200185 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300186 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500187};
188
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200189static const struct intel_device_info intel_ironlake_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700190 .gen = 5, .num_pipes = 2,
Eugeni Dodonov5a117db2012-01-05 09:34:29 -0200191 .need_gfx_hws = 1, .has_hotplug = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700192 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200193 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300194 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500195};
196
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200197static const struct intel_device_info intel_ironlake_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
Chris Wilsone3c4e5d2010-12-05 16:49:51 +0000199 .need_gfx_hws = 1, .has_hotplug = 1,
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700200 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700201 .ring_mask = RENDER_RING | BSD_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200202 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300203 CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500204};
205
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200206static const struct intel_device_info intel_sandybridge_d_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700207 .gen = 6, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100208 .need_gfx_hws = 1, .has_hotplug = 1,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200209 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200211 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200212 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300213 CURSOR_OFFSETS,
Eric Anholtf6e450a2009-11-02 12:08:22 -0800214};
215
Tobias Klauser9a7e8492010-05-20 10:33:46 +0200216static const struct intel_device_info intel_sandybridge_m_info = {
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100218 .need_gfx_hws = 1, .has_hotplug = 1,
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800219 .has_fbc = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200221 .has_llc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200222 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300223 CURSOR_OFFSETS,
Eric Anholta13e4092010-01-07 15:08:18 -0800224};
225
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700226#define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200229 .has_fbc = 1, \
Ben Widawsky73ae4782013-10-15 10:02:57 -0700230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
Ben Widawskyab484f82013-10-05 17:57:11 -0700231 .has_llc = 1
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700232
Jesse Barnesc76b6152011-04-28 14:32:07 -0700233static const struct intel_device_info intel_ivybridge_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700234 GEN7_FEATURES,
235 .is_ivybridge = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200236 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300237 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700238};
239
240static const struct intel_device_info intel_ivybridge_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200244 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300245 IVB_CURSOR_OFFSETS,
Jesse Barnesc76b6152011-04-28 14:32:07 -0700246};
247
Ben Widawsky999bcde2013-04-05 13:12:45 -0700248static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200252 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300253 IVB_CURSOR_OFFSETS,
Ben Widawsky999bcde2013-04-05 13:12:45 -0700254};
255
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700256static const struct intel_device_info intel_valleyview_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700260 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200261 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200262 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700263 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200264 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300265 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700266};
267
268static const struct intel_device_info intel_valleyview_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700269 GEN7_FEATURES,
270 .num_pipes = 2,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700271 .is_valleyview = 1,
Ville Syrjäläfba5d532013-01-24 15:29:56 +0200272 .display_mmio_offset = VLV_DISPLAY_BASE,
Ville Syrjäläcbaef0f2013-11-06 23:02:24 +0200273 .has_fbc = 0, /* legal, last one wins */
Ben Widawsky30ccd962013-04-15 21:48:03 -0700274 .has_llc = 0, /* legal, last one wins */
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200275 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300276 CURSOR_OFFSETS,
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700277};
278
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300279static const struct intel_device_info intel_haswell_d_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700280 GEN7_FEATURES,
281 .is_haswell = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100282 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100283 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200285 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300286 IVB_CURSOR_OFFSETS,
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300287};
288
289static const struct intel_device_info intel_haswell_m_info = {
Ben Widawsky219f4fd2013-03-15 11:17:54 -0700290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
Damien Lespiaudd93be52013-04-22 18:40:39 +0100293 .has_ddi = 1,
Damien Lespiau30568c42013-04-22 18:40:41 +0100294 .has_fpga_dbg = 1,
Ben Widawsky73ae4782013-10-15 10:02:57 -0700295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200296 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300297 IVB_CURSOR_OFFSETS,
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500298};
299
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800300static const struct intel_device_info intel_broadwell_d_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700301 .gen = 8, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300306 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800307 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200308 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300309 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800310};
311
312static const struct intel_device_info intel_broadwell_m_info = {
Damien Lespiau4b305532013-11-02 21:07:32 -0700313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
316 .has_llc = 1,
317 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300318 .has_fpga_dbg = 1,
Ben Widawsky8f94d242014-02-20 16:01:20 -0800319 .has_fbc = 1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200320 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700321 IVB_CURSOR_OFFSETS,
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800322};
323
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800324static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800328 .has_llc = 1,
329 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300330 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800331 .has_fbc = 1,
332 GEN_DEFAULT_PIPEOFFSETS,
Rodrigo Vivi15d24aa2014-06-04 17:09:30 -0700333 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800334};
335
336static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
Zhao Yakui845f74a2014-04-17 10:37:37 +0800339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800340 .has_llc = 1,
341 .has_ddi = 1,
Paulo Zanoni66bc2ca2014-07-16 17:49:30 -0300342 .has_fpga_dbg = 1,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800343 .has_fbc = 1,
344 GEN_DEFAULT_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300345 IVB_CURSOR_OFFSETS,
Zhao Yakuifd3c2692014-04-17 10:37:35 +0800346};
347
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300348static const struct intel_device_info intel_cherryview_info = {
Ville Syrjälä07fddb12014-04-09 13:28:54 +0300349 .gen = 8, .num_pipes = 3,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 .is_valleyview = 1,
353 .display_mmio_offset = VLV_DISPLAY_BASE,
Rafael Barbalho84fd4f42014-04-28 14:00:42 +0300354 GEN_CHV_PIPEOFFSETS,
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300355 CURSOR_OFFSETS,
Ville Syrjälä7d87a7f2014-04-09 18:19:04 +0300356};
357
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000358static const struct intel_device_info intel_skylake_info = {
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530359 .is_skylake = 1,
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000360 .gen = 9, .num_pipes = 3,
361 .need_gfx_hws = 1, .has_hotplug = 1,
362 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
363 .has_llc = 1,
364 .has_ddi = 1,
Paulo Zanoni6c908bf2015-08-25 19:03:41 -0300365 .has_fpga_dbg = 1,
Daisy Sun043efb12014-04-23 17:13:09 -0700366 .has_fbc = 1,
Damien Lespiau72bbf0a2013-02-13 15:27:37 +0000367 GEN_DEFAULT_PIPEOFFSETS,
368 IVB_CURSOR_OFFSETS,
369};
370
Damien Lespiau719388e2015-02-04 13:22:27 +0000371static const struct intel_device_info intel_skylake_gt3_info = {
Damien Lespiau719388e2015-02-04 13:22:27 +0000372 .is_skylake = 1,
373 .gen = 9, .num_pipes = 3,
374 .need_gfx_hws = 1, .has_hotplug = 1,
375 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
376 .has_llc = 1,
377 .has_ddi = 1,
Paulo Zanoni6c908bf2015-08-25 19:03:41 -0300378 .has_fpga_dbg = 1,
Damien Lespiau719388e2015-02-04 13:22:27 +0000379 .has_fbc = 1,
380 GEN_DEFAULT_PIPEOFFSETS,
381 IVB_CURSOR_OFFSETS,
382};
383
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200384static const struct intel_device_info intel_broxton_info = {
385 .is_preliminary = 1,
Rodrigo Vivi7526ac12015-10-27 10:14:54 -0700386 .is_broxton = 1,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200387 .gen = 9,
388 .need_gfx_hws = 1, .has_hotplug = 1,
389 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
390 .num_pipes = 3,
391 .has_ddi = 1,
Paulo Zanoni6c908bf2015-08-25 19:03:41 -0300392 .has_fpga_dbg = 1,
Daisy Sunce89db22015-03-17 11:39:28 +0200393 .has_fbc = 1,
Damien Lespiau1347f5b2015-03-17 11:39:27 +0200394 GEN_DEFAULT_PIPEOFFSETS,
395 IVB_CURSOR_OFFSETS,
396};
397
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700398static const struct intel_device_info intel_kabylake_info = {
399 .is_preliminary = 1,
400 .is_kabylake = 1,
401 .gen = 9,
402 .num_pipes = 3,
403 .need_gfx_hws = 1, .has_hotplug = 1,
404 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
405 .has_llc = 1,
406 .has_ddi = 1,
407 .has_fpga_dbg = 1,
408 .has_fbc = 1,
409 GEN_DEFAULT_PIPEOFFSETS,
410 IVB_CURSOR_OFFSETS,
411};
412
413static const struct intel_device_info intel_kabylake_gt3_info = {
414 .is_preliminary = 1,
415 .is_kabylake = 1,
416 .gen = 9,
417 .num_pipes = 3,
418 .need_gfx_hws = 1, .has_hotplug = 1,
419 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
420 .has_llc = 1,
421 .has_ddi = 1,
422 .has_fpga_dbg = 1,
423 .has_fbc = 1,
424 GEN_DEFAULT_PIPEOFFSETS,
425 IVB_CURSOR_OFFSETS,
426};
427
Jesse Barnesa0a18072013-07-26 13:32:51 -0700428/*
429 * Make sure any device matches here are from most specific to most
430 * general. For example, since the Quanta match is based on the subsystem
431 * and subvendor IDs, we need it to come before the more general IVB
432 * PCI ID matches, otherwise we'll use the wrong info struct above.
433 */
Jani Nikula3cb27f32015-10-28 19:33:09 +0200434static const struct pci_device_id pciidlist[] = {
435 INTEL_I830_IDS(&intel_i830_info),
436 INTEL_I845G_IDS(&intel_845g_info),
437 INTEL_I85X_IDS(&intel_i85x_info),
438 INTEL_I865G_IDS(&intel_i865g_info),
439 INTEL_I915G_IDS(&intel_i915g_info),
440 INTEL_I915GM_IDS(&intel_i915gm_info),
441 INTEL_I945G_IDS(&intel_i945g_info),
442 INTEL_I945GM_IDS(&intel_i945gm_info),
443 INTEL_I965G_IDS(&intel_i965g_info),
444 INTEL_G33_IDS(&intel_g33_info),
445 INTEL_I965GM_IDS(&intel_i965gm_info),
446 INTEL_GM45_IDS(&intel_gm45_info),
447 INTEL_G45_IDS(&intel_g45_info),
448 INTEL_PINEVIEW_IDS(&intel_pineview_info),
449 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
450 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
451 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
452 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
453 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
454 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
455 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
456 INTEL_HSW_D_IDS(&intel_haswell_d_info),
457 INTEL_HSW_M_IDS(&intel_haswell_m_info),
458 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
459 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
460 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
461 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
462 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
463 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
464 INTEL_CHV_IDS(&intel_cherryview_info),
465 INTEL_SKL_GT1_IDS(&intel_skylake_info),
466 INTEL_SKL_GT2_IDS(&intel_skylake_info),
467 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
468 INTEL_BXT_IDS(&intel_broxton_info),
Deepak Sd97044b2015-10-28 12:19:51 -0700469 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
470 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
471 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
Kristian Høgsberg49ae35f2009-12-16 15:16:15 -0500472 {0, 0, 0}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473};
474
Jesse Barnes79e53942008-11-07 14:24:08 -0800475MODULE_DEVICE_TABLE(pci, pciidlist);
Jesse Barnes79e53942008-11-07 14:24:08 -0800476
Robert Beckett30c964a2015-08-28 13:10:22 +0100477static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
478{
479 enum intel_pch ret = PCH_NOP;
480
481 /*
482 * In a virtualized passthrough environment we can be in a
483 * setup where the ISA bridge is not able to be passed through.
484 * In this case, a south bridge can be emulated and we have to
485 * make an educated guess as to which PCH is really there.
486 */
487
488 if (IS_GEN5(dev)) {
489 ret = PCH_IBX;
490 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
491 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
492 ret = PCH_CPT;
493 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
494 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
495 ret = PCH_LPT;
496 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700497 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Robert Beckett30c964a2015-08-28 13:10:22 +0100498 ret = PCH_SPT;
499 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
500 }
501
502 return ret;
503}
504
Akshay Joshi0206e352011-08-16 15:34:10 -0400505void intel_detect_pch(struct drm_device *dev)
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800506{
507 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbcdb72a2014-02-14 20:23:54 +0200508 struct pci_dev *pch = NULL;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800509
Ben Widawskyce1bb322013-04-05 13:12:44 -0700510 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
511 * (which really amounts to a PCH but no South Display).
512 */
513 if (INTEL_INFO(dev)->num_pipes == 0) {
514 dev_priv->pch_type = PCH_NOP;
Ben Widawskyce1bb322013-04-05 13:12:44 -0700515 return;
516 }
517
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800518 /*
519 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
520 * make graphics device passthrough work easy for VMM, that only
521 * need to expose ISA bridge to let driver know the real hardware
522 * underneath. This is a requirement from virtualization team.
Rui Guo6a9c4b32013-06-19 21:10:23 +0800523 *
524 * In some virtualized environments (e.g. XEN), there is irrelevant
525 * ISA bridge in the system. To work reliably, we should scan trhough
526 * all the ISA bridge devices and check for the first match, instead
527 * of only checking the first one.
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800528 */
Imre Deakbcdb72a2014-02-14 20:23:54 +0200529 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800530 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
Imre Deakbcdb72a2014-02-14 20:23:54 +0200531 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
Paulo Zanoni17a303e2012-11-20 15:12:07 -0200532 dev_priv->pch_id = id;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800533
Jesse Barnes90711d52011-04-28 14:48:02 -0700534 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
535 dev_priv->pch_type = PCH_IBX;
536 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100537 WARN_ON(!IS_GEN5(dev));
Jesse Barnes90711d52011-04-28 14:48:02 -0700538 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800539 dev_priv->pch_type = PCH_CPT;
540 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100541 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Jesse Barnesc7925132011-04-07 12:33:56 -0700542 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
543 /* PantherPoint is CPT compatible */
544 dev_priv->pch_type = PCH_CPT;
Jani Nikula492ab662013-10-01 12:12:33 +0300545 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
Daniel Vetter7fcb83c2012-10-31 22:52:27 +0100546 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300547 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
548 dev_priv->pch_type = PCH_LPT;
549 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800550 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
551 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
Ben Widawskye76e0632013-11-07 21:40:41 -0800552 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
553 dev_priv->pch_type = PCH_LPT;
554 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
Rodrigo Vivia35cc9d02015-01-21 10:33:53 -0800555 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
556 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530557 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
558 dev_priv->pch_type = PCH_SPT;
559 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700560 WARN_ON(!IS_SKYLAKE(dev) &&
561 !IS_KABYLAKE(dev));
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530562 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
563 dev_priv->pch_type = PCH_SPT;
564 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700565 WARN_ON(!IS_SKYLAKE(dev) &&
566 !IS_KABYLAKE(dev));
Robert Beckett30c964a2015-08-28 13:10:22 +0100567 } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE) {
568 dev_priv->pch_type = intel_virt_detect_pch(dev);
Imre Deakbcdb72a2014-02-14 20:23:54 +0200569 } else
570 continue;
571
Rui Guo6a9c4b32013-06-19 21:10:23 +0800572 break;
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800573 }
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800574 }
Rui Guo6a9c4b32013-06-19 21:10:23 +0800575 if (!pch)
Imre Deakbcdb72a2014-02-14 20:23:54 +0200576 DRM_DEBUG_KMS("No PCH found.\n");
577
578 pci_dev_put(pch);
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800579}
580
Ben Widawsky2911a352012-04-05 14:47:36 -0700581bool i915_semaphore_is_enabled(struct drm_device *dev)
582{
583 if (INTEL_INFO(dev)->gen < 6)
Daniel Vettera08acaf2013-12-17 09:56:53 +0100584 return false;
Ben Widawsky2911a352012-04-05 14:47:36 -0700585
Jani Nikulad330a952014-01-21 11:24:25 +0200586 if (i915.semaphores >= 0)
587 return i915.semaphores;
Ben Widawsky2911a352012-04-05 14:47:36 -0700588
Oscar Mateo71386ef2014-07-24 17:04:44 +0100589 /* TODO: make semaphores and Execlists play nicely together */
590 if (i915.enable_execlists)
591 return false;
592
Rodrigo Vivibe71eab2014-08-04 11:15:19 -0700593 /* Until we get further testing... */
594 if (IS_GEN8(dev))
595 return false;
596
Daniel Vetter59de3292012-04-02 20:48:43 +0200597#ifdef CONFIG_INTEL_IOMMU
Ben Widawsky2911a352012-04-05 14:47:36 -0700598 /* Enable semaphores on SNB when IO remapping is off */
Daniel Vetter59de3292012-04-02 20:48:43 +0200599 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
600 return false;
601#endif
Ben Widawsky2911a352012-04-05 14:47:36 -0700602
Daniel Vettera08acaf2013-12-17 09:56:53 +0100603 return true;
Ben Widawsky2911a352012-04-05 14:47:36 -0700604}
605
Daniel Vettereb805622015-05-04 14:58:44 +0200606void i915_firmware_load_error_print(const char *fw_path, int err)
607{
608 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
609
610 /*
611 * If the reason is not known assume -ENOENT since that's the most
612 * usual failure mode.
613 */
614 if (!err)
615 err = -ENOENT;
616
617 if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
618 return;
619
620 DRM_ERROR(
621 "The driver is built-in, so to load the firmware you need to\n"
622 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
623 "in your initrd/initramfs image.\n");
624}
625
Imre Deak07f9cd02014-08-18 14:42:45 +0300626static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
627{
628 struct drm_device *dev = dev_priv->dev;
629 struct drm_encoder *encoder;
630
631 drm_modeset_lock_all(dev);
632 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
633 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
634
635 if (intel_encoder->suspend)
636 intel_encoder->suspend(intel_encoder);
637 }
638 drm_modeset_unlock_all(dev);
639}
640
Sagar Kambleebc32822014-08-13 23:07:05 +0530641static int intel_suspend_complete(struct drm_i915_private *dev_priv);
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200642static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
643 bool rpm_resume);
Suketu Shahf75a1982015-04-16 14:22:11 +0530644static int skl_resume_prepare(struct drm_i915_private *dev_priv);
Damien Lespiaua9a6b732015-05-20 14:45:14 +0100645static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +0530646
Sagar Kambleebc32822014-08-13 23:07:05 +0530647
Imre Deak5e365c32014-10-23 19:23:25 +0300648static int i915_drm_suspend(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100649{
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100650 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnese5747e32014-06-12 08:35:47 -0700651 pci_power_t opregion_target_state;
Daniel Vetterd5818932015-02-23 12:03:26 +0100652 int error;
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100653
Zhang Ruib8efb172013-02-05 15:41:53 +0800654 /* ignore lid events during suspend */
655 mutex_lock(&dev_priv->modeset_restore_lock);
656 dev_priv->modeset_restore = MODESET_SUSPENDED;
657 mutex_unlock(&dev_priv->modeset_restore_lock);
658
Paulo Zanonic67a4702013-08-19 13:18:09 -0300659 /* We do a lot of poking in a lot of registers, make sure they work
660 * properly. */
Imre Deakda7e29b2014-02-18 00:02:02 +0200661 intel_display_set_init_power(dev_priv, true);
Paulo Zanonicb107992013-01-25 16:59:15 -0200662
Dave Airlie5bcf7192010-12-07 09:20:40 +1000663 drm_kms_helper_poll_disable(dev);
664
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100665 pci_save_state(dev->pdev);
666
Daniel Vetterd5818932015-02-23 12:03:26 +0100667 error = i915_gem_suspend(dev);
668 if (error) {
669 dev_err(&dev->pdev->dev,
670 "GEM idle failed, resume might fail\n");
671 return error;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100672 }
673
Alex Daia1c41992015-09-30 09:46:37 -0700674 intel_guc_suspend(dev);
675
Daniel Vetterd5818932015-02-23 12:03:26 +0100676 intel_suspend_gt_powersave(dev);
677
678 /*
679 * Disable CRTCs directly since we want to preserve sw state
680 * for _thaw. Also, power gate the CRTC power wells.
681 */
682 drm_modeset_lock_all(dev);
Maarten Lankhorst6b72d482015-06-01 12:49:47 +0200683 intel_display_suspend(dev);
Daniel Vetterd5818932015-02-23 12:03:26 +0100684 drm_modeset_unlock_all(dev);
685
686 intel_dp_mst_suspend(dev);
687
688 intel_runtime_pm_disable_interrupts(dev_priv);
689 intel_hpd_cancel_work(dev_priv);
690
691 intel_suspend_encoders(dev_priv);
692
693 intel_suspend_hw(dev);
694
Ben Widawsky828c7902013-10-16 09:21:30 -0700695 i915_gem_suspend_gtt_mappings(dev);
696
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100697 i915_save_state(dev);
698
Imre Deak95fa2ee2014-06-23 15:46:02 +0300699 opregion_target_state = PCI_D3cold;
700#if IS_ENABLED(CONFIG_ACPI_SLEEP)
701 if (acpi_target_system_state() < ACPI_STATE_S3)
Jesse Barnese5747e32014-06-12 08:35:47 -0700702 opregion_target_state = PCI_D1;
Imre Deak95fa2ee2014-06-23 15:46:02 +0300703#endif
Jesse Barnese5747e32014-06-12 08:35:47 -0700704 intel_opregion_notify_adapter(dev, opregion_target_state);
705
Jesse Barnes156c7ca2014-06-12 08:35:45 -0700706 intel_uncore_forcewake_reset(dev, false);
Chris Wilson44834a62010-08-19 16:09:23 +0100707 intel_opregion_fini(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100708
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100709 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
Dave Airlie3fa016a2012-03-28 10:48:49 +0100710
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200711 dev_priv->suspend_count++;
712
Kristen Carlson Accardi85e90672014-06-12 08:35:44 -0700713 intel_display_set_init_power(dev_priv, false);
714
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100715 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100716}
717
Imre Deakab3be732015-03-02 13:04:41 +0200718static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
Imre Deakc3c09c92014-10-23 19:23:15 +0300719{
720 struct drm_i915_private *dev_priv = drm_dev->dev_private;
721 int ret;
722
723 ret = intel_suspend_complete(dev_priv);
724
725 if (ret) {
726 DRM_ERROR("Suspend complete failed: %d\n", ret);
727
728 return ret;
729 }
730
731 pci_disable_device(drm_dev->pdev);
Imre Deakab3be732015-03-02 13:04:41 +0200732 /*
Imre Deak54875572015-06-30 17:06:47 +0300733 * During hibernation on some platforms the BIOS may try to access
Imre Deakab3be732015-03-02 13:04:41 +0200734 * the device even though it's already in D3 and hang the machine. So
735 * leave the device in D0 on those platforms and hope the BIOS will
Imre Deak54875572015-06-30 17:06:47 +0300736 * power down the device properly. The issue was seen on multiple old
737 * GENs with different BIOS vendors, so having an explicit blacklist
738 * is inpractical; apply the workaround on everything pre GEN6. The
739 * platforms where the issue was seen:
740 * Lenovo Thinkpad X301, X61s, X60, T60, X41
741 * Fujitsu FSC S7110
742 * Acer Aspire 1830T
Imre Deakab3be732015-03-02 13:04:41 +0200743 */
Imre Deak54875572015-06-30 17:06:47 +0300744 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
Imre Deakab3be732015-03-02 13:04:41 +0200745 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
Imre Deakc3c09c92014-10-23 19:23:15 +0300746
747 return 0;
748}
749
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +0200750int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100751{
752 int error;
753
754 if (!dev || !dev->dev_private) {
755 DRM_ERROR("dev: %p\n", dev);
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700756 DRM_ERROR("DRM not initialized, aborting suspend.\n");
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000757 return -ENODEV;
758 }
759
Imre Deak0b14cbd2014-09-10 18:16:55 +0300760 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
761 state.event != PM_EVENT_FREEZE))
762 return -EINVAL;
Dave Airlie5bcf7192010-12-07 09:20:40 +1000763
764 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
765 return 0;
Chris Wilson6eecba32010-09-08 09:45:11 +0100766
Imre Deak5e365c32014-10-23 19:23:25 +0300767 error = i915_drm_suspend(dev);
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100768 if (error)
769 return error;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000770
Imre Deakab3be732015-03-02 13:04:41 +0200771 return i915_drm_suspend_late(dev, false);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000772}
773
Imre Deak5e365c32014-10-23 19:23:25 +0300774static int i915_drm_resume(struct drm_device *dev)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000775{
Jesse Barnes5669fca2009-02-17 15:13:31 -0800776 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100777
Daniel Vetterd5818932015-02-23 12:03:26 +0100778 mutex_lock(&dev->struct_mutex);
779 i915_gem_restore_gtt_mappings(dev);
780 mutex_unlock(&dev->struct_mutex);
Paulo Zanoni9d49c0e2013-09-12 18:06:43 -0300781
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100782 i915_restore_state(dev);
Chris Wilson44834a62010-08-19 16:09:23 +0100783 intel_opregion_setup(dev);
Rafael J. Wysocki61caf872010-02-18 23:06:27 +0100784
Daniel Vetterd5818932015-02-23 12:03:26 +0100785 intel_init_pch_refclk(dev);
786 drm_mode_config_reset(dev);
Chris Wilson1833b132012-05-09 11:56:28 +0100787
Peter Antoine364aece2015-05-11 08:50:45 +0100788 /*
789 * Interrupts have to be enabled before any batches are run. If not the
790 * GPU will hang. i915_gem_init_hw() will initiate batches to
791 * update/restore the context.
792 *
793 * Modeset enabling in intel_modeset_init_hw() also needs working
794 * interrupts.
795 */
796 intel_runtime_pm_enable_interrupts(dev_priv);
797
Daniel Vetterd5818932015-02-23 12:03:26 +0100798 mutex_lock(&dev->struct_mutex);
799 if (i915_gem_init_hw(dev)) {
800 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
Peter Zijlstra805de8f42015-04-24 01:12:32 +0200801 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
Jesse Barnesd5bb0812011-01-05 12:01:26 -0800802 }
Daniel Vetterd5818932015-02-23 12:03:26 +0100803 mutex_unlock(&dev->struct_mutex);
804
Alex Daia1c41992015-09-30 09:46:37 -0700805 intel_guc_resume(dev);
806
Daniel Vetterd5818932015-02-23 12:03:26 +0100807 intel_modeset_init_hw(dev);
808
809 spin_lock_irq(&dev_priv->irq_lock);
810 if (dev_priv->display.hpd_irq_setup)
811 dev_priv->display.hpd_irq_setup(dev);
812 spin_unlock_irq(&dev_priv->irq_lock);
813
814 drm_modeset_lock_all(dev);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +0200815 intel_display_resume(dev);
Daniel Vetterd5818932015-02-23 12:03:26 +0100816 drm_modeset_unlock_all(dev);
817
818 intel_dp_mst_resume(dev);
819
820 /*
821 * ... but also need to make sure that hotplug processing
822 * doesn't cause havoc. Like in the driver load code we don't
823 * bother with the tiny race here where we might loose hotplug
824 * notifications.
825 * */
826 intel_hpd_init(dev_priv);
827 /* Config may have changed between suspend and resume */
828 drm_helper_hpd_irq_event(dev);
Jesse Barnes1daed3f2011-01-05 12:01:25 -0800829
Chris Wilson44834a62010-08-19 16:09:23 +0100830 intel_opregion_init(dev);
831
Chris Wilson82e3b8c2014-08-13 13:09:46 +0100832 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
Jesse Barnes073f34d2012-11-02 11:13:59 -0700833
Zhang Ruib8efb172013-02-05 15:41:53 +0800834 mutex_lock(&dev_priv->modeset_restore_lock);
835 dev_priv->modeset_restore = MODESET_DONE;
836 mutex_unlock(&dev_priv->modeset_restore_lock);
Paulo Zanoni8a187452013-12-06 20:32:13 -0200837
Jesse Barnese5747e32014-06-12 08:35:47 -0700838 intel_opregion_notify_adapter(dev, PCI_D0);
839
Imre Deakee6f2802014-10-23 19:23:22 +0300840 drm_kms_helper_poll_enable(dev);
841
Chris Wilson074c6ad2014-04-09 09:19:43 +0100842 return 0;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100843}
844
Imre Deak5e365c32014-10-23 19:23:25 +0300845static int i915_drm_resume_early(struct drm_device *dev)
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100846{
Imre Deak36d61e62014-10-23 19:23:24 +0300847 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200848 int ret = 0;
Imre Deak36d61e62014-10-23 19:23:24 +0300849
Imre Deak76c4b252014-04-01 19:55:22 +0300850 /*
851 * We have a resume ordering issue with the snd-hda driver also
852 * requiring our device to be power up. Due to the lack of a
853 * parent/child relationship we currently solve this with an early
854 * resume hook.
855 *
856 * FIXME: This should be solved with a special hdmi sink device or
857 * similar so that power domains can be employed.
858 */
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +0100859 if (pci_enable_device(dev->pdev))
860 return -EIO;
861
862 pci_set_master(dev->pdev);
863
Paulo Zanoniefee8332014-10-27 17:54:33 -0200864 if (IS_VALLEYVIEW(dev_priv))
Paulo Zanoni1a5df182014-10-27 17:54:32 -0200865 ret = vlv_resume_prepare(dev_priv, false);
Imre Deak36d61e62014-10-23 19:23:24 +0300866 if (ret)
Damien Lespiauff0b1872015-05-20 14:45:15 +0100867 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
868 ret);
Imre Deak36d61e62014-10-23 19:23:24 +0300869
870 intel_uncore_early_sanitize(dev, true);
Paulo Zanoniefee8332014-10-27 17:54:33 -0200871
Damien Lespiaua9a6b732015-05-20 14:45:14 +0100872 if (IS_BROXTON(dev))
873 ret = bxt_resume_prepare(dev_priv);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700874 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Suketu Shahf75a1982015-04-16 14:22:11 +0530875 ret = skl_resume_prepare(dev_priv);
Damien Lespiaua9a6b732015-05-20 14:45:14 +0100876 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
877 hsw_disable_pc8(dev_priv);
Paulo Zanoniefee8332014-10-27 17:54:33 -0200878
Imre Deak36d61e62014-10-23 19:23:24 +0300879 intel_uncore_sanitize(dev);
880 intel_power_domains_init_hw(dev_priv);
881
882 return ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300883}
884
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +0200885int i915_resume_switcheroo(struct drm_device *dev)
Imre Deak76c4b252014-04-01 19:55:22 +0300886{
Imre Deak50a00722014-10-23 19:23:17 +0300887 int ret;
Imre Deak76c4b252014-04-01 19:55:22 +0300888
Imre Deak097dd832014-10-23 19:23:19 +0300889 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
890 return 0;
891
Imre Deak5e365c32014-10-23 19:23:25 +0300892 ret = i915_drm_resume_early(dev);
Imre Deak50a00722014-10-23 19:23:17 +0300893 if (ret)
894 return ret;
895
Imre Deak5a175142014-10-23 19:23:18 +0300896 return i915_drm_resume(dev);
897}
898
Ben Gamari11ed50e2009-09-14 17:48:45 -0400899/**
Eugeni Dodonovf3953dc2011-11-28 16:15:17 -0200900 * i915_reset - reset chip after a hang
Ben Gamari11ed50e2009-09-14 17:48:45 -0400901 * @dev: drm device to reset
Ben Gamari11ed50e2009-09-14 17:48:45 -0400902 *
903 * Reset the chip. Useful if a hang is detected. Returns zero on successful
904 * reset or otherwise an error code.
905 *
906 * Procedure is fairly simple:
907 * - reset the chip using the reset reg
908 * - re-init context state
909 * - re-init hardware status page
910 * - re-init ring buffer
911 * - re-init interrupt state
912 * - re-init display
913 */
Daniel Vetterd4b8bb22012-04-27 15:17:44 +0200914int i915_reset(struct drm_device *dev)
Ben Gamari11ed50e2009-09-14 17:48:45 -0400915{
Jani Nikula50227e12014-03-31 14:27:21 +0300916 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100917 bool simulated;
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700918 int ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400919
Imre Deakdbea3ce2014-12-15 18:59:28 +0200920 intel_reset_gt_powersave(dev);
921
Daniel Vetterd54a02c2012-07-04 22:18:39 +0200922 mutex_lock(&dev->struct_mutex);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400923
Chris Wilson069efc12010-09-30 16:53:18 +0100924 i915_gem_reset(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -0400925
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100926 simulated = dev_priv->gpu_error.stop_rings != 0;
927
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300928 ret = intel_gpu_reset(dev);
Daniel Vetter350d2702012-04-27 15:17:42 +0200929
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300930 /* Also reset the gpu hangman. */
931 if (simulated) {
932 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
933 dev_priv->gpu_error.stop_rings = 0;
934 if (ret == -ENODEV) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100935 DRM_INFO("Reset not implemented, but ignoring "
936 "error for simulated gpu hangs\n");
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300937 ret = 0;
938 }
Chris Wilson2e7c8ee2013-05-28 10:38:44 +0100939 }
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300940
Daniel Vetterd8f27162014-10-01 01:02:04 +0200941 if (i915_stop_ring_allow_warn(dev_priv))
942 pr_notice("drm/i915: Resetting chip after gpu hang\n");
943
Kenneth Graunke0573ed42010-09-11 03:17:19 -0700944 if (ret) {
Daniel Vetterf2d91a22013-11-07 09:48:57 +0100945 DRM_ERROR("Failed to reset chip: %i\n", ret);
Daniel J Bluemanf953c932010-05-17 14:23:52 +0100946 mutex_unlock(&dev->struct_mutex);
Chris Wilsonf803aa52010-09-19 12:38:26 +0100947 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400948 }
949
Ville Syrjälä1362b772014-11-26 17:07:29 +0200950 intel_overlay_reset(dev_priv);
951
Ben Gamari11ed50e2009-09-14 17:48:45 -0400952 /* Ok, now get things going again... */
953
954 /*
955 * Everything depends on having the GTT running, so we need to start
956 * there. Fortunately we don't need to do this unless we reset the
957 * chip at a PCI level.
958 *
959 * Next we need to restore the context, but we don't use those
960 * yet either...
961 *
962 * Ring buffer needs to be re-initialized in the KMS case, or if X
963 * was running at the time of the reset (i.e. we weren't VT
964 * switched away).
965 */
McAulay, Alistair6689c162014-08-15 18:51:35 +0100966
Daniel Vetter33d30a92015-02-23 12:03:27 +0100967 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
968 dev_priv->gpu_error.reload_in_reset = true;
McAulay, Alistair6689c162014-08-15 18:51:35 +0100969
Daniel Vetter33d30a92015-02-23 12:03:27 +0100970 ret = i915_gem_init_hw(dev);
McAulay, Alistair6689c162014-08-15 18:51:35 +0100971
Daniel Vetter33d30a92015-02-23 12:03:27 +0100972 dev_priv->gpu_error.reload_in_reset = false;
Daniel Vetterf8175862012-04-10 15:50:11 +0200973
Daniel Vetter33d30a92015-02-23 12:03:27 +0100974 mutex_unlock(&dev->struct_mutex);
975 if (ret) {
976 DRM_ERROR("Failed hw init on reset %d\n", ret);
977 return ret;
Ben Gamari11ed50e2009-09-14 17:48:45 -0400978 }
979
Daniel Vetter33d30a92015-02-23 12:03:27 +0100980 /*
Daniel Vetter33d30a92015-02-23 12:03:27 +0100981 * rps/rc6 re-init is necessary to restore state lost after the
982 * reset and the re-install of gt irqs. Skip for ironlake per
983 * previous concerns that it doesn't respond well to some forms
984 * of re-init after reset.
985 */
986 if (INTEL_INFO(dev)->gen > 5)
987 intel_enable_gt_powersave(dev);
988
Ben Gamari11ed50e2009-09-14 17:48:45 -0400989 return 0;
990}
991
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800992static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
Kristian Høgsberg112b7152009-01-04 16:55:33 -0500993{
Daniel Vetter01a06852012-06-25 15:58:49 +0200994 struct intel_device_info *intel_info =
995 (struct intel_device_info *) ent->driver_data;
996
Jani Nikulad330a952014-01-21 11:24:25 +0200997 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
Ben Widawskyb833d682013-08-23 16:00:07 -0700998 DRM_INFO("This hardware requires preliminary hardware support.\n"
999 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1000 return -ENODEV;
1001 }
1002
Chris Wilson5fe49d82011-02-01 19:43:02 +00001003 /* Only bind to function 0 of the device. Early generations
1004 * used function 1 as a placeholder for multi-head. This causes
1005 * us confusion instead, especially on the systems where both
1006 * functions have the same PCI-ID!
1007 */
1008 if (PCI_FUNC(pdev->devfn))
1009 return -ENODEV;
1010
Jordan Crousedcdb1672010-05-27 13:40:25 -06001011 return drm_get_pci_dev(pdev, ent, &driver);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001012}
1013
1014static void
1015i915_pci_remove(struct pci_dev *pdev)
1016{
1017 struct drm_device *dev = pci_get_drvdata(pdev);
1018
1019 drm_put_dev(dev);
1020}
1021
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001022static int i915_pm_suspend(struct device *dev)
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001023{
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001024 struct pci_dev *pdev = to_pci_dev(dev);
1025 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001026
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001027 if (!drm_dev || !drm_dev->dev_private) {
1028 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1029 return -ENODEV;
1030 }
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001031
Dave Airlie5bcf7192010-12-07 09:20:40 +10001032 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1033 return 0;
1034
Imre Deak5e365c32014-10-23 19:23:25 +03001035 return i915_drm_suspend(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001036}
1037
1038static int i915_pm_suspend_late(struct device *dev)
1039{
Imre Deak888d0d42015-01-08 17:54:13 +02001040 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +03001041
1042 /*
Damien Lespiauc965d9952015-05-18 19:53:48 +01001043 * We have a suspend ordering issue with the snd-hda driver also
Imre Deak76c4b252014-04-01 19:55:22 +03001044 * requiring our device to be power up. Due to the lack of a
1045 * parent/child relationship we currently solve this with an late
1046 * suspend hook.
1047 *
1048 * FIXME: This should be solved with a special hdmi sink device or
1049 * similar so that power domains can be employed.
1050 */
1051 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1052 return 0;
Kristian Høgsberg112b7152009-01-04 16:55:33 -05001053
Imre Deakab3be732015-03-02 13:04:41 +02001054 return i915_drm_suspend_late(drm_dev, false);
1055}
1056
1057static int i915_pm_poweroff_late(struct device *dev)
1058{
1059 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1060
1061 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1062 return 0;
1063
1064 return i915_drm_suspend_late(drm_dev, true);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001065}
1066
Imre Deak76c4b252014-04-01 19:55:22 +03001067static int i915_pm_resume_early(struct device *dev)
1068{
Imre Deak888d0d42015-01-08 17:54:13 +02001069 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Imre Deak76c4b252014-04-01 19:55:22 +03001070
Imre Deak097dd832014-10-23 19:23:19 +03001071 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1072 return 0;
1073
Imre Deak5e365c32014-10-23 19:23:25 +03001074 return i915_drm_resume_early(drm_dev);
Imre Deak76c4b252014-04-01 19:55:22 +03001075}
1076
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001077static int i915_pm_resume(struct device *dev)
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001078{
Imre Deak888d0d42015-01-08 17:54:13 +02001079 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
Rafael J. Wysocki84b79f82010-02-07 21:48:24 +01001080
Imre Deak097dd832014-10-23 19:23:19 +03001081 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1082 return 0;
1083
Imre Deak5a175142014-10-23 19:23:18 +03001084 return i915_drm_resume(drm_dev);
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001085}
1086
Suketu Shahf75a1982015-04-16 14:22:11 +05301087static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1088{
Animesh Manna0a9d2be2015-09-29 11:01:59 +05301089 enum csr_state state;
Suketu Shahf75a1982015-04-16 14:22:11 +05301090 /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1091
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001092 skl_uninit_cdclk(dev_priv);
1093
Animesh Manna0a9d2be2015-09-29 11:01:59 +05301094 /* TODO: wait for a completion event or
1095 * similar here instead of busy
1096 * waiting using wait_for function.
1097 */
1098 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
1099 FW_UNINITIALIZED, 1000);
1100 if (state == FW_LOADED)
1101 skl_enable_dc6(dev_priv);
1102
Suketu Shahf75a1982015-04-16 14:22:11 +05301103 return 0;
1104}
1105
Sagar Kambleebc32822014-08-13 23:07:05 +05301106static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
Paulo Zanoni97bea202014-03-07 20:12:33 -03001107{
Paulo Zanoni414de7a2014-03-07 20:12:35 -03001108 hsw_enable_pc8(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001109
1110 return 0;
Paulo Zanoni97bea202014-03-07 20:12:33 -03001111}
1112
Suketu Shah31335ce2014-11-24 13:37:45 +05301113static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1114{
1115 struct drm_device *dev = dev_priv->dev;
1116
1117 /* TODO: when DC5 support is added disable DC5 here. */
1118
1119 broxton_ddi_phy_uninit(dev);
1120 broxton_uninit_cdclk(dev);
1121 bxt_enable_dc9(dev_priv);
1122
1123 return 0;
1124}
1125
1126static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1127{
1128 struct drm_device *dev = dev_priv->dev;
1129
1130 /* TODO: when CSR FW support is added make sure the FW is loaded */
1131
1132 bxt_disable_dc9(dev_priv);
1133
1134 /*
1135 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1136 * is available.
1137 */
1138 broxton_init_cdclk(dev);
1139 broxton_ddi_phy_init(dev);
1140 intel_prepare_ddi(dev);
1141
1142 return 0;
1143}
1144
Suketu Shahf75a1982015-04-16 14:22:11 +05301145static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1146{
1147 struct drm_device *dev = dev_priv->dev;
1148
Animesh Manna0a9d2be2015-09-29 11:01:59 +05301149 if (intel_csr_load_status_get(dev_priv) == FW_LOADED)
1150 skl_disable_dc6(dev_priv);
1151
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001152 skl_init_cdclk(dev_priv);
Suketu Shahf75a1982015-04-16 14:22:11 +05301153 intel_csr_load_program(dev);
1154
1155 return 0;
1156}
1157
Imre Deakddeea5b2014-05-05 15:19:56 +03001158/*
1159 * Save all Gunit registers that may be lost after a D3 and a subsequent
1160 * S0i[R123] transition. The list of registers needing a save/restore is
1161 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1162 * registers in the following way:
1163 * - Driver: saved/restored by the driver
1164 * - Punit : saved/restored by the Punit firmware
1165 * - No, w/o marking: no need to save/restore, since the register is R/O or
1166 * used internally by the HW in a way that doesn't depend
1167 * keeping the content across a suspend/resume.
1168 * - Debug : used for debugging
1169 *
1170 * We save/restore all registers marked with 'Driver', with the following
1171 * exceptions:
1172 * - Registers out of use, including also registers marked with 'Debug'.
1173 * These have no effect on the driver's operation, so we don't save/restore
1174 * them to reduce the overhead.
1175 * - Registers that are fully setup by an initialization function called from
1176 * the resume path. For example many clock gating and RPS/RC6 registers.
1177 * - Registers that provide the right functionality with their reset defaults.
1178 *
1179 * TODO: Except for registers that based on the above 3 criteria can be safely
1180 * ignored, we save/restore all others, practically treating the HW context as
1181 * a black-box for the driver. Further investigation is needed to reduce the
1182 * saved/restored registers even further, by following the same 3 criteria.
1183 */
1184static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1185{
1186 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1187 int i;
1188
1189 /* GAM 0x4000-0x4770 */
1190 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1191 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1192 s->arb_mode = I915_READ(ARB_MODE);
1193 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1194 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1195
1196 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001197 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03001198
1199 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
Imre Deakb5f1c972015-04-15 16:52:30 -07001200 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
Imre Deakddeea5b2014-05-05 15:19:56 +03001201
1202 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1203 s->ecochk = I915_READ(GAM_ECOCHK);
1204 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1205 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1206
1207 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1208
1209 /* MBC 0x9024-0x91D0, 0x8500 */
1210 s->g3dctl = I915_READ(VLV_G3DCTL);
1211 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1212 s->mbctl = I915_READ(GEN6_MBCTL);
1213
1214 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1215 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1216 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1217 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1218 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1219 s->rstctl = I915_READ(GEN6_RSTCTL);
1220 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1221
1222 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1223 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1224 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1225 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1226 s->ecobus = I915_READ(ECOBUS);
1227 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1228 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1229 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1230 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1231 s->rcedata = I915_READ(VLV_RCEDATA);
1232 s->spare2gh = I915_READ(VLV_SPAREG2H);
1233
1234 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1235 s->gt_imr = I915_READ(GTIMR);
1236 s->gt_ier = I915_READ(GTIER);
1237 s->pm_imr = I915_READ(GEN6_PMIMR);
1238 s->pm_ier = I915_READ(GEN6_PMIER);
1239
1240 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001241 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
Imre Deakddeea5b2014-05-05 15:19:56 +03001242
1243 /* GT SA CZ domain, 0x100000-0x138124 */
1244 s->tilectl = I915_READ(TILECTL);
1245 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1246 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1247 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1248 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1249
1250 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1251 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1252 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001253 s->pcbr = I915_READ(VLV_PCBR);
Imre Deakddeea5b2014-05-05 15:19:56 +03001254 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1255
1256 /*
1257 * Not saving any of:
1258 * DFT, 0x9800-0x9EC0
1259 * SARB, 0xB000-0xB1FC
1260 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1261 * PCI CFG
1262 */
1263}
1264
1265static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1266{
1267 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1268 u32 val;
1269 int i;
1270
1271 /* GAM 0x4000-0x4770 */
1272 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1273 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1274 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1275 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1276 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1277
1278 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001279 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03001280
1281 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
Imre Deakb5f1c972015-04-15 16:52:30 -07001282 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
Imre Deakddeea5b2014-05-05 15:19:56 +03001283
1284 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1285 I915_WRITE(GAM_ECOCHK, s->ecochk);
1286 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1287 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1288
1289 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1290
1291 /* MBC 0x9024-0x91D0, 0x8500 */
1292 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1293 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1294 I915_WRITE(GEN6_MBCTL, s->mbctl);
1295
1296 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1297 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1298 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1299 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1300 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1301 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1302 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1303
1304 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1305 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1306 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1307 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1308 I915_WRITE(ECOBUS, s->ecobus);
1309 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1310 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1311 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1312 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1313 I915_WRITE(VLV_RCEDATA, s->rcedata);
1314 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1315
1316 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1317 I915_WRITE(GTIMR, s->gt_imr);
1318 I915_WRITE(GTIER, s->gt_ier);
1319 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1320 I915_WRITE(GEN6_PMIER, s->pm_ier);
1321
1322 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
Ville Syrjälä22dfe792015-09-18 20:03:16 +03001323 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
Imre Deakddeea5b2014-05-05 15:19:56 +03001324
1325 /* GT SA CZ domain, 0x100000-0x138124 */
1326 I915_WRITE(TILECTL, s->tilectl);
1327 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1328 /*
1329 * Preserve the GT allow wake and GFX force clock bit, they are not
1330 * be restored, as they are used to control the s0ix suspend/resume
1331 * sequence by the caller.
1332 */
1333 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1334 val &= VLV_GTLC_ALLOWWAKEREQ;
1335 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1336 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1337
1338 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1339 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1340 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1341 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1342
1343 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1344
1345 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1346 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1347 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
Jesse Barnes9c252102015-04-01 14:22:57 -07001348 I915_WRITE(VLV_PCBR, s->pcbr);
Imre Deakddeea5b2014-05-05 15:19:56 +03001349 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1350}
1351
Imre Deak650ad972014-04-18 16:35:02 +03001352int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1353{
1354 u32 val;
1355 int err;
1356
Imre Deak650ad972014-04-18 16:35:02 +03001357#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
Imre Deak650ad972014-04-18 16:35:02 +03001358
1359 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1360 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1361 if (force_on)
1362 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1363 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1364
1365 if (!force_on)
1366 return 0;
1367
Imre Deak8d4eee92014-04-14 20:24:43 +03001368 err = wait_for(COND, 20);
Imre Deak650ad972014-04-18 16:35:02 +03001369 if (err)
1370 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1371 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1372
1373 return err;
1374#undef COND
1375}
1376
Imre Deakddeea5b2014-05-05 15:19:56 +03001377static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1378{
1379 u32 val;
1380 int err = 0;
1381
1382 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1383 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1384 if (allow)
1385 val |= VLV_GTLC_ALLOWWAKEREQ;
1386 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1387 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1388
1389#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1390 allow)
1391 err = wait_for(COND, 1);
1392 if (err)
1393 DRM_ERROR("timeout disabling GT waking\n");
1394 return err;
1395#undef COND
1396}
1397
1398static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1399 bool wait_for_on)
1400{
1401 u32 mask;
1402 u32 val;
1403 int err;
1404
1405 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1406 val = wait_for_on ? mask : 0;
1407#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1408 if (COND)
1409 return 0;
1410
1411 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1412 wait_for_on ? "on" : "off",
1413 I915_READ(VLV_GTLC_PW_STATUS));
1414
1415 /*
1416 * RC6 transitioning can be delayed up to 2 msec (see
1417 * valleyview_enable_rps), use 3 msec for safety.
1418 */
1419 err = wait_for(COND, 3);
1420 if (err)
1421 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1422 wait_for_on ? "on" : "off");
1423
1424 return err;
1425#undef COND
1426}
1427
1428static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1429{
1430 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1431 return;
1432
1433 DRM_ERROR("GT register access while GT waking disabled\n");
1434 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1435}
1436
Sagar Kambleebc32822014-08-13 23:07:05 +05301437static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
Imre Deakddeea5b2014-05-05 15:19:56 +03001438{
1439 u32 mask;
1440 int err;
1441
1442 /*
1443 * Bspec defines the following GT well on flags as debug only, so
1444 * don't treat them as hard failures.
1445 */
1446 (void)vlv_wait_for_gt_wells(dev_priv, false);
1447
1448 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1449 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1450
1451 vlv_check_no_gt_access(dev_priv);
1452
1453 err = vlv_force_gfx_clock(dev_priv, true);
1454 if (err)
1455 goto err1;
1456
1457 err = vlv_allow_gt_wake(dev_priv, false);
1458 if (err)
1459 goto err2;
Deepak S98711162014-12-12 14:18:16 +05301460
1461 if (!IS_CHERRYVIEW(dev_priv->dev))
1462 vlv_save_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001463
1464 err = vlv_force_gfx_clock(dev_priv, false);
1465 if (err)
1466 goto err2;
1467
1468 return 0;
1469
1470err2:
1471 /* For safety always re-enable waking and disable gfx clock forcing */
1472 vlv_allow_gt_wake(dev_priv, true);
1473err1:
1474 vlv_force_gfx_clock(dev_priv, false);
1475
1476 return err;
1477}
1478
Sagar Kamble016970b2014-08-13 23:07:06 +05301479static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1480 bool rpm_resume)
Imre Deakddeea5b2014-05-05 15:19:56 +03001481{
1482 struct drm_device *dev = dev_priv->dev;
1483 int err;
1484 int ret;
1485
1486 /*
1487 * If any of the steps fail just try to continue, that's the best we
1488 * can do at this point. Return the first error code (which will also
1489 * leave RPM permanently disabled).
1490 */
1491 ret = vlv_force_gfx_clock(dev_priv, true);
1492
Deepak S98711162014-12-12 14:18:16 +05301493 if (!IS_CHERRYVIEW(dev_priv->dev))
1494 vlv_restore_gunit_s0ix_state(dev_priv);
Imre Deakddeea5b2014-05-05 15:19:56 +03001495
1496 err = vlv_allow_gt_wake(dev_priv, true);
1497 if (!ret)
1498 ret = err;
1499
1500 err = vlv_force_gfx_clock(dev_priv, false);
1501 if (!ret)
1502 ret = err;
1503
1504 vlv_check_no_gt_access(dev_priv);
1505
Sagar Kamble016970b2014-08-13 23:07:06 +05301506 if (rpm_resume) {
1507 intel_init_clock_gating(dev);
1508 i915_gem_restore_fences(dev);
1509 }
Imre Deakddeea5b2014-05-05 15:19:56 +03001510
1511 return ret;
1512}
1513
Paulo Zanoni97bea202014-03-07 20:12:33 -03001514static int intel_runtime_suspend(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001515{
1516 struct pci_dev *pdev = to_pci_dev(device);
1517 struct drm_device *dev = pci_get_drvdata(pdev);
1518 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001519 int ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001520
Imre Deakaeab0b52014-04-14 20:24:36 +03001521 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
Imre Deakc6df39b2014-04-14 20:24:29 +03001522 return -ENODEV;
1523
Imre Deak604effb2014-08-26 13:26:56 +03001524 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1525 return -ENODEV;
1526
Paulo Zanoni8a187452013-12-06 20:32:13 -02001527 DRM_DEBUG_KMS("Suspending device\n");
1528
Imre Deak9486db62014-04-22 20:21:07 +03001529 /*
Imre Deakd6102972014-05-07 19:57:49 +03001530 * We could deadlock here in case another thread holding struct_mutex
1531 * calls RPM suspend concurrently, since the RPM suspend will wait
1532 * first for this RPM suspend to finish. In this case the concurrent
1533 * RPM resume will be followed by its RPM suspend counterpart. Still
1534 * for consistency return -EAGAIN, which will reschedule this suspend.
1535 */
1536 if (!mutex_trylock(&dev->struct_mutex)) {
1537 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1538 /*
1539 * Bump the expiration timestamp, otherwise the suspend won't
1540 * be rescheduled.
1541 */
1542 pm_runtime_mark_last_busy(device);
1543
1544 return -EAGAIN;
1545 }
1546 /*
1547 * We are safe here against re-faults, since the fault handler takes
1548 * an RPM reference.
1549 */
1550 i915_gem_release_all_mmaps(dev_priv);
1551 mutex_unlock(&dev->struct_mutex);
1552
Alex Daia1c41992015-09-30 09:46:37 -07001553 intel_guc_suspend(dev);
1554
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001555 intel_suspend_gt_powersave(dev);
Imre Deak2eb52522014-11-19 15:30:05 +02001556 intel_runtime_pm_disable_interrupts(dev_priv);
Imre Deakb5478bc2014-04-14 20:24:37 +03001557
Sagar Kambleebc32822014-08-13 23:07:05 +05301558 ret = intel_suspend_complete(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001559 if (ret) {
1560 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
Daniel Vetterb9632912014-09-30 10:56:44 +02001561 intel_runtime_pm_enable_interrupts(dev_priv);
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001562
1563 return ret;
1564 }
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001565
Chris Wilson737b1502015-01-26 18:03:03 +02001566 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
Chris Wilsondc9fb092015-01-16 11:34:34 +02001567 intel_uncore_forcewake_reset(dev, false);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001568 dev_priv->pm.suspended = true;
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001569
1570 /*
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001571 * FIXME: We really should find a document that references the arguments
1572 * used below!
Kristen Carlson Accardi1fb23622014-01-14 15:36:15 -08001573 */
Paulo Zanonid37ae192015-07-30 18:20:29 -03001574 if (IS_BROADWELL(dev)) {
1575 /*
1576 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1577 * being detected, and the call we do at intel_runtime_resume()
1578 * won't be able to restore them. Since PCI_D3hot matches the
1579 * actual specification and appears to be working, use it.
1580 */
1581 intel_opregion_notify_adapter(dev, PCI_D3hot);
1582 } else {
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001583 /*
1584 * current versions of firmware which depend on this opregion
1585 * notification have repurposed the D1 definition to mean
1586 * "runtime suspended" vs. what you would normally expect (D3)
1587 * to distinguish it from notifications that might be sent via
1588 * the suspend path.
1589 */
1590 intel_opregion_notify_adapter(dev, PCI_D1);
Paulo Zanonic8a0bd42014-08-21 17:09:38 -03001591 }
Paulo Zanoni8a187452013-12-06 20:32:13 -02001592
Mika Kuoppala59bad942015-01-16 11:34:40 +02001593 assert_forcewakes_inactive(dev_priv);
Chris Wilsondc9fb092015-01-16 11:34:34 +02001594
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001595 DRM_DEBUG_KMS("Device suspended\n");
Paulo Zanoni8a187452013-12-06 20:32:13 -02001596 return 0;
1597}
1598
Paulo Zanoni97bea202014-03-07 20:12:33 -03001599static int intel_runtime_resume(struct device *device)
Paulo Zanoni8a187452013-12-06 20:32:13 -02001600{
1601 struct pci_dev *pdev = to_pci_dev(device);
1602 struct drm_device *dev = pci_get_drvdata(pdev);
1603 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001604 int ret = 0;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001605
Imre Deak604effb2014-08-26 13:26:56 +03001606 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1607 return -ENODEV;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001608
1609 DRM_DEBUG_KMS("Resuming device\n");
1610
Paulo Zanonicd2e9e92013-12-06 20:34:21 -02001611 intel_opregion_notify_adapter(dev, PCI_D0);
Paulo Zanoni8a187452013-12-06 20:32:13 -02001612 dev_priv->pm.suspended = false;
1613
Alex Daia1c41992015-09-30 09:46:37 -07001614 intel_guc_resume(dev);
1615
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001616 if (IS_GEN6(dev_priv))
1617 intel_init_pch_refclk(dev);
Suketu Shah31335ce2014-11-24 13:37:45 +05301618
1619 if (IS_BROXTON(dev))
1620 ret = bxt_resume_prepare(dev_priv);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001621 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Suketu Shahf75a1982015-04-16 14:22:11 +05301622 ret = skl_resume_prepare(dev_priv);
Paulo Zanoni1a5df182014-10-27 17:54:32 -02001623 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1624 hsw_disable_pc8(dev_priv);
1625 else if (IS_VALLEYVIEW(dev_priv))
1626 ret = vlv_resume_prepare(dev_priv, true);
1627
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001628 /*
1629 * No point of rolling back things in case of an error, as the best
1630 * we can do is to hope that things will still work (and disable RPM).
1631 */
Imre Deak92b806d2014-04-14 20:24:39 +03001632 i915_gem_init_swizzling(dev);
1633 gen6_update_ring_freq(dev);
1634
Daniel Vetterb9632912014-09-30 10:56:44 +02001635 intel_runtime_pm_enable_interrupts(dev_priv);
Ville Syrjälä08d8a232015-08-27 23:56:08 +03001636
1637 /*
1638 * On VLV/CHV display interrupts are part of the display
1639 * power well, so hpd is reinitialized from there. For
1640 * everyone else do it here.
1641 */
1642 if (!IS_VALLEYVIEW(dev_priv))
1643 intel_hpd_init(dev_priv);
1644
Paulo Zanonifac6adb2014-10-30 15:59:31 -02001645 intel_enable_gt_powersave(dev);
Imre Deakb5478bc2014-04-14 20:24:37 +03001646
Imre Deak0ab9cfe2014-04-15 16:39:45 +03001647 if (ret)
1648 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1649 else
1650 DRM_DEBUG_KMS("Device resumed\n");
1651
1652 return ret;
Paulo Zanoni8a187452013-12-06 20:32:13 -02001653}
1654
Sagar Kamble016970b2014-08-13 23:07:06 +05301655/*
1656 * This function implements common functionality of runtime and system
1657 * suspend sequence.
1658 */
Sagar Kambleebc32822014-08-13 23:07:05 +05301659static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1660{
Sagar Kambleebc32822014-08-13 23:07:05 +05301661 int ret;
1662
Damien Lespiau16e44e32015-05-20 14:45:16 +01001663 if (IS_BROXTON(dev_priv))
Suketu Shah31335ce2014-11-24 13:37:45 +05301664 ret = bxt_suspend_complete(dev_priv);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001665 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Suketu Shahf75a1982015-04-16 14:22:11 +05301666 ret = skl_suspend_complete(dev_priv);
Damien Lespiau16e44e32015-05-20 14:45:16 +01001667 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Sagar Kambleebc32822014-08-13 23:07:05 +05301668 ret = hsw_suspend_complete(dev_priv);
Damien Lespiau16e44e32015-05-20 14:45:16 +01001669 else if (IS_VALLEYVIEW(dev_priv))
Sagar Kambleebc32822014-08-13 23:07:05 +05301670 ret = vlv_suspend_complete(dev_priv);
Imre Deak604effb2014-08-26 13:26:56 +03001671 else
1672 ret = 0;
Sagar Kambleebc32822014-08-13 23:07:05 +05301673
1674 return ret;
1675}
1676
Chris Wilsonb4b78d12010-06-06 15:40:20 +01001677static const struct dev_pm_ops i915_pm_ops = {
Imre Deak5545dbb2014-10-23 19:23:28 +03001678 /*
1679 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1680 * PMSG_RESUME]
1681 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001682 .suspend = i915_pm_suspend,
Imre Deak76c4b252014-04-01 19:55:22 +03001683 .suspend_late = i915_pm_suspend_late,
1684 .resume_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001685 .resume = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001686
1687 /*
1688 * S4 event handlers
1689 * @freeze, @freeze_late : called (1) before creating the
1690 * hibernation image [PMSG_FREEZE] and
1691 * (2) after rebooting, before restoring
1692 * the image [PMSG_QUIESCE]
1693 * @thaw, @thaw_early : called (1) after creating the hibernation
1694 * image, before writing it [PMSG_THAW]
1695 * and (2) after failing to create or
1696 * restore the image [PMSG_RECOVER]
1697 * @poweroff, @poweroff_late: called after writing the hibernation
1698 * image, before rebooting [PMSG_HIBERNATE]
1699 * @restore, @restore_early : called after rebooting and restoring the
1700 * hibernation image [PMSG_RESTORE]
1701 */
Imre Deak36d61e62014-10-23 19:23:24 +03001702 .freeze = i915_pm_suspend,
1703 .freeze_late = i915_pm_suspend_late,
1704 .thaw_early = i915_pm_resume_early,
1705 .thaw = i915_pm_resume,
1706 .poweroff = i915_pm_suspend,
Imre Deakab3be732015-03-02 13:04:41 +02001707 .poweroff_late = i915_pm_poweroff_late,
Imre Deak76c4b252014-04-01 19:55:22 +03001708 .restore_early = i915_pm_resume_early,
Akshay Joshi0206e352011-08-16 15:34:10 -04001709 .restore = i915_pm_resume,
Imre Deak5545dbb2014-10-23 19:23:28 +03001710
1711 /* S0ix (via runtime suspend) event handlers */
Paulo Zanoni97bea202014-03-07 20:12:33 -03001712 .runtime_suspend = intel_runtime_suspend,
1713 .runtime_resume = intel_runtime_resume,
Zhenyu Wangcbda12d2009-12-16 13:36:10 +08001714};
1715
Laurent Pinchart78b68552012-05-17 13:27:22 +02001716static const struct vm_operations_struct i915_gem_vm_ops = {
Jesse Barnesde151cf2008-11-12 10:03:55 -08001717 .fault = i915_gem_fault,
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001718 .open = drm_gem_vm_open,
1719 .close = drm_gem_vm_close,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001720};
1721
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001722static const struct file_operations i915_driver_fops = {
1723 .owner = THIS_MODULE,
1724 .open = drm_open,
1725 .release = drm_release,
1726 .unlocked_ioctl = drm_ioctl,
1727 .mmap = drm_gem_mmap,
1728 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001729 .read = drm_read,
1730#ifdef CONFIG_COMPAT
1731 .compat_ioctl = i915_compat_ioctl,
1732#endif
1733 .llseek = noop_llseek,
1734};
1735
Linus Torvalds1da177e2005-04-16 15:20:36 -07001736static struct drm_driver driver = {
Michael Witten0c547812011-08-25 17:55:54 +00001737 /* Don't use MTRRs here; the Xserver or userspace app should
1738 * deal with them for Intel hardware.
Dave Airlie792d2b92005-11-11 23:30:27 +11001739 */
Eric Anholt673a3942008-07-30 12:06:12 -07001740 .driver_features =
Kristian Høgsberg10ba5012013-08-25 18:29:01 +02001741 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +02001742 DRIVER_RENDER | DRIVER_MODESET,
Dave Airlie22eae942005-11-10 22:16:34 +11001743 .load = i915_driver_load,
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001744 .unload = i915_driver_unload,
Eric Anholt673a3942008-07-30 12:06:12 -07001745 .open = i915_driver_open,
Dave Airlie22eae942005-11-10 22:16:34 +11001746 .lastclose = i915_driver_lastclose,
1747 .preclose = i915_driver_preclose,
Eric Anholt673a3942008-07-30 12:06:12 -07001748 .postclose = i915_driver_postclose,
David Herrmann915b4d12014-08-29 12:12:43 +02001749 .set_busid = drm_pci_set_busid,
Rafael J. Wysockid8e29202010-01-09 00:45:33 +01001750
Ben Gamari955b12d2009-02-17 20:08:49 -05001751#if defined(CONFIG_DEBUG_FS)
Ben Gamari27c202a2009-07-01 22:26:52 -04001752 .debugfs_init = i915_debugfs_init,
1753 .debugfs_cleanup = i915_debugfs_cleanup,
Ben Gamari955b12d2009-02-17 20:08:49 -05001754#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001755 .gem_free_object = i915_gem_free_object,
Jesse Barnesde151cf2008-11-12 10:03:55 -08001756 .gem_vm_ops = &i915_gem_vm_ops,
Daniel Vetter1286ff72012-05-10 15:25:09 +02001757
1758 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1759 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1760 .gem_prime_export = i915_gem_prime_export,
1761 .gem_prime_import = i915_gem_prime_import,
1762
Dave Airlieff72145b2011-02-07 12:16:14 +10001763 .dumb_create = i915_gem_dumb_create,
Dave Airlieda6b51d2014-12-24 13:11:17 +10001764 .dumb_map_offset = i915_gem_mmap_gtt,
Daniel Vetter43387b32013-07-16 09:12:04 +02001765 .dumb_destroy = drm_gem_dumb_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766 .ioctls = i915_ioctls,
Arjan van de Vene08e96d2011-10-31 07:28:57 -07001767 .fops = &i915_driver_fops,
Dave Airlie22eae942005-11-10 22:16:34 +11001768 .name = DRIVER_NAME,
1769 .desc = DRIVER_DESC,
1770 .date = DRIVER_DATE,
1771 .major = DRIVER_MAJOR,
1772 .minor = DRIVER_MINOR,
1773 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774};
1775
Dave Airlie8410ea32010-12-15 03:16:38 +10001776static struct pci_driver i915_pci_driver = {
1777 .name = DRIVER_NAME,
1778 .id_table = pciidlist,
1779 .probe = i915_pci_probe,
1780 .remove = i915_pci_remove,
1781 .driver.pm = &i915_pm_ops,
1782};
1783
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784static int __init i915_init(void)
1785{
1786 driver.num_ioctls = i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -08001787
1788 /*
Chris Wilsonfd930472015-06-19 20:27:27 +01001789 * Enable KMS by default, unless explicitly overriden by
1790 * either the i915.modeset prarameter or by the
1791 * vga_text_mode_force boot option.
Jesse Barnes79e53942008-11-07 14:24:08 -08001792 */
Chris Wilsonfd930472015-06-19 20:27:27 +01001793
1794 if (i915.modeset == 0)
1795 driver.driver_features &= ~DRIVER_MODESET;
Jesse Barnes79e53942008-11-07 14:24:08 -08001796
1797#ifdef CONFIG_VGA_CONSOLE
Jani Nikulad330a952014-01-21 11:24:25 +02001798 if (vgacon_text_force() && i915.modeset == -1)
Jesse Barnes79e53942008-11-07 14:24:08 -08001799 driver.driver_features &= ~DRIVER_MODESET;
1800#endif
1801
Daniel Vetterb30324a2013-11-13 22:11:25 +01001802 if (!(driver.driver_features & DRIVER_MODESET)) {
Daniel Vetterb30324a2013-11-13 22:11:25 +01001803 /* Silently fail loading to not upset userspace. */
Jani Nikulac9cd7b62014-06-02 16:58:30 +03001804 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
Daniel Vetterb30324a2013-11-13 22:11:25 +01001805 return 0;
Daniel Vetterb30324a2013-11-13 22:11:25 +01001806 }
Chris Wilson3885c6b2011-01-23 10:45:14 +00001807
Maarten Lankhorstc5b852f2015-08-26 09:29:56 +02001808 if (i915.nuclear_pageflip)
Matt Roperb2e77232015-01-22 16:53:12 -08001809 driver.driver_features |= DRIVER_ATOMIC;
1810
Dave Airlie8410ea32010-12-15 03:16:38 +10001811 return drm_pci_init(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001812}
1813
1814static void __exit i915_exit(void)
1815{
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001816 if (!(driver.driver_features & DRIVER_MODESET))
1817 return; /* Never loaded a driver. */
Daniel Vetterb33ecdd2013-11-15 17:16:33 +01001818
Dave Airlie8410ea32010-12-15 03:16:38 +10001819 drm_pci_exit(&driver, &i915_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820}
1821
1822module_init(i915_init);
1823module_exit(i915_exit);
1824
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001825MODULE_AUTHOR("Tungsten Graphics, Inc.");
Damien Lespiau1eab9232014-08-27 11:30:21 +01001826MODULE_AUTHOR("Intel Corporation");
Damien Lespiau0a6d1632014-08-27 11:30:20 +01001827
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001828MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001829MODULE_LICENSE("GPL and additional rights");