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Andrew Victor62c16602006-11-30 12:27:38 +01001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * arch/arm/mach-at91/at91sam9260.c
Andrew Victor62c16602006-11-30 12:27:38 +01003 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
Andrew Victor3ef2fb42008-04-02 21:36:06 +010014#include <linux/pm.h>
Andrew Victor62c16602006-11-30 12:27:38 +010015
Russell King80b02c12009-01-08 10:01:47 +000016#include <asm/irq.h>
Andrew Victor62c16602006-11-30 12:27:38 +010017#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/cpu.h>
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +080020#include <mach/at91_dbgu.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/at91sam9260.h>
22#include <mach/at91_pmc.h>
23#include <mach/at91_rstc.h>
24#include <mach/at91_shdwc.h>
Andrew Victor62c16602006-11-30 12:27:38 +010025
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080026#include "soc.h"
Andrew Victor62c16602006-11-30 12:27:38 +010027#include "generic.h"
28#include "clock.h"
29
Andrew Victorf7eee892007-02-15 08:17:38 +010030static struct map_desc at91sam9260_sram_desc[] __initdata = {
31 {
Andrew Victor62c16602006-11-30 12:27:38 +010032 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
33 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
34 .length = AT91SAM9260_SRAM0_SIZE,
35 .type = MT_DEVICE,
36 }, {
37 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
38 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
39 .length = AT91SAM9260_SRAM1_SIZE,
40 .type = MT_DEVICE,
Andrew Victorf7eee892007-02-15 08:17:38 +010041 }
42};
43
sedji gaouaou61352662008-07-10 10:15:35 +010044static struct map_desc at91sam9g20_sram_desc[] __initdata = {
45 {
46 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
47 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
48 .length = AT91SAM9G20_SRAM0_SIZE,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
52 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
53 .length = AT91SAM9G20_SRAM1_SIZE,
54 .type = MT_DEVICE,
55 }
56};
57
Andrew Victorf7eee892007-02-15 08:17:38 +010058static struct map_desc at91sam9xe_sram_desc[] __initdata = {
59 {
60 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
61 .type = MT_DEVICE,
62 }
Andrew Victor62c16602006-11-30 12:27:38 +010063};
64
65/* --------------------------------------------------------------------
66 * Clocks
67 * -------------------------------------------------------------------- */
68
69/*
70 * The peripheral clocks.
71 */
72static struct clk pioA_clk = {
73 .name = "pioA_clk",
74 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk pioB_clk = {
78 .name = "pioB_clk",
79 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk pioC_clk = {
83 .name = "pioC_clk",
84 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk adc_clk = {
88 .name = "adc_clk",
89 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk usart0_clk = {
93 .name = "usart0_clk",
94 .pmc_mask = 1 << AT91SAM9260_ID_US0,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk usart1_clk = {
98 .name = "usart1_clk",
99 .pmc_mask = 1 << AT91SAM9260_ID_US1,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk usart2_clk = {
103 .name = "usart2_clk",
104 .pmc_mask = 1 << AT91SAM9260_ID_US2,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk mmc_clk = {
108 .name = "mci_clk",
109 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk udc_clk = {
113 .name = "udc_clk",
114 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk twi_clk = {
118 .name = "twi_clk",
119 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk spi0_clk = {
123 .name = "spi0_clk",
124 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk spi1_clk = {
128 .name = "spi1_clk",
129 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
130 .type = CLK_TYPE_PERIPHERAL,
131};
Andrew Victore8788ba2007-05-02 17:14:57 +0100132static struct clk ssc_clk = {
133 .name = "ssc_clk",
134 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100137static struct clk tc0_clk = {
138 .name = "tc0_clk",
139 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk tc1_clk = {
143 .name = "tc1_clk",
144 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk tc2_clk = {
148 .name = "tc2_clk",
149 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
150 .type = CLK_TYPE_PERIPHERAL,
151};
Andrew Victor62c16602006-11-30 12:27:38 +0100152static struct clk ohci_clk = {
153 .name = "ohci_clk",
154 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
155 .type = CLK_TYPE_PERIPHERAL,
156};
Andrew Victor69b2e992007-02-14 08:44:43 +0100157static struct clk macb_clk = {
158 .name = "macb_clk",
Andrew Victor62c16602006-11-30 12:27:38 +0100159 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162static struct clk isi_clk = {
163 .name = "isi_clk",
164 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk usart3_clk = {
168 .name = "usart3_clk",
169 .pmc_mask = 1 << AT91SAM9260_ID_US3,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172static struct clk usart4_clk = {
173 .name = "usart4_clk",
174 .pmc_mask = 1 << AT91SAM9260_ID_US4,
175 .type = CLK_TYPE_PERIPHERAL,
176};
177static struct clk usart5_clk = {
178 .name = "usart5_clk",
179 .pmc_mask = 1 << AT91SAM9260_ID_US5,
180 .type = CLK_TYPE_PERIPHERAL,
181};
Andrew Victorc177a1e2007-02-08 10:25:38 +0100182static struct clk tc3_clk = {
183 .name = "tc3_clk",
184 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
185 .type = CLK_TYPE_PERIPHERAL,
186};
187static struct clk tc4_clk = {
188 .name = "tc4_clk",
189 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
190 .type = CLK_TYPE_PERIPHERAL,
191};
192static struct clk tc5_clk = {
193 .name = "tc5_clk",
194 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
195 .type = CLK_TYPE_PERIPHERAL,
196};
Andrew Victor62c16602006-11-30 12:27:38 +0100197
198static struct clk *periph_clocks[] __initdata = {
199 &pioA_clk,
200 &pioB_clk,
201 &pioC_clk,
202 &adc_clk,
203 &usart0_clk,
204 &usart1_clk,
205 &usart2_clk,
206 &mmc_clk,
207 &udc_clk,
208 &twi_clk,
209 &spi0_clk,
210 &spi1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100211 &ssc_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100212 &tc0_clk,
213 &tc1_clk,
214 &tc2_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100215 &ohci_clk,
Andrew Victor69b2e992007-02-14 08:44:43 +0100216 &macb_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100217 &isi_clk,
218 &usart3_clk,
219 &usart4_clk,
220 &usart5_clk,
Andrew Victorc177a1e2007-02-08 10:25:38 +0100221 &tc3_clk,
222 &tc4_clk,
223 &tc5_clk,
Andrew Victor62c16602006-11-30 12:27:38 +0100224 // irq0 .. irq2
225};
226
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100227static struct clk_lookup periph_clocks_lookups[] = {
228 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
229 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
230 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
231 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
232 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
233 CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
234 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
235 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
236 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
237};
238
239static struct clk_lookup usart_clocks_lookups[] = {
240 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
241 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
242 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
243 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
244 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
245 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
246 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
247};
248
Andrew Victor62c16602006-11-30 12:27:38 +0100249/*
250 * The two programmable clocks.
251 * You must configure pin multiplexing to bring these signals out.
252 */
253static struct clk pck0 = {
254 .name = "pck0",
255 .pmc_mask = AT91_PMC_PCK0,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 0,
258};
259static struct clk pck1 = {
260 .name = "pck1",
261 .pmc_mask = AT91_PMC_PCK1,
262 .type = CLK_TYPE_PROGRAMMABLE,
263 .id = 1,
264};
265
266static void __init at91sam9260_register_clocks(void)
267{
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
272
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
277
Andrew Victor62c16602006-11-30 12:27:38 +0100278 clk_register(&pck0);
279 clk_register(&pck1);
280}
281
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100282static struct clk_lookup console_clock_lookup;
283
284void __init at91sam9260_set_console_clock(int id)
285{
286 if (id >= ARRAY_SIZE(usart_clocks_lookups))
287 return;
288
289 console_clock_lookup.con_id = "usart";
290 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
291 clkdev_add(&console_clock_lookup);
292}
293
Andrew Victor62c16602006-11-30 12:27:38 +0100294/* --------------------------------------------------------------------
295 * GPIO
296 * -------------------------------------------------------------------- */
297
298static struct at91_gpio_bank at91sam9260_gpio[] = {
299 {
300 .id = AT91SAM9260_ID_PIOA,
301 .offset = AT91_PIOA,
302 .clock = &pioA_clk,
303 }, {
304 .id = AT91SAM9260_ID_PIOB,
305 .offset = AT91_PIOB,
306 .clock = &pioB_clk,
307 }, {
308 .id = AT91SAM9260_ID_PIOC,
309 .offset = AT91_PIOC,
310 .clock = &pioC_clk,
311 }
312};
313
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100314static void at91sam9260_poweroff(void)
315{
316 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
317}
318
Andrew Victor62c16602006-11-30 12:27:38 +0100319
320/* --------------------------------------------------------------------
321 * AT91SAM9260 processor initialization
322 * -------------------------------------------------------------------- */
323
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800324static void __init at91sam9xe_map_io(void)
Andrew Victorf7eee892007-02-15 08:17:38 +0100325{
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800326 unsigned long sram_size;
Andrew Victorf7eee892007-02-15 08:17:38 +0100327
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800328 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
Andrew Victorf7eee892007-02-15 08:17:38 +0100329 case AT91_CIDR_SRAMSIZ_32K:
330 sram_size = 2 * SZ_16K;
331 break;
332 case AT91_CIDR_SRAMSIZ_16K:
333 default:
334 sram_size = SZ_16K;
335 }
336
337 at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
338 at91sam9xe_sram_desc->length = sram_size;
339
340 iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
341}
342
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800343static void __init at91sam9260_map_io(void)
Andrew Victor62c16602006-11-30 12:27:38 +0100344{
Andrew Victorf7eee892007-02-15 08:17:38 +0100345 if (cpu_is_at91sam9xe())
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800346 at91sam9xe_map_io();
sedji gaouaou61352662008-07-10 10:15:35 +0100347 else if (cpu_is_at91sam9g20())
348 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
Andrew Victorf7eee892007-02-15 08:17:38 +0100349 else
350 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800351}
Andrew Victorf7eee892007-02-15 08:17:38 +0100352
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800353static void __init at91sam9260_initialize(unsigned long main_clock)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800354{
Nicolas Ferrebb413db2010-10-14 19:14:00 +0200355 at91_arch_reset = at91sam9_alt_reset;
Andrew Victor3ef2fb42008-04-02 21:36:06 +0100356 pm_power_off = at91sam9260_poweroff;
Andrew Victor62c16602006-11-30 12:27:38 +0100357 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
358 | (1 << AT91SAM9260_ID_IRQ2);
359
360 /* Init clock subsystem */
361 at91_clock_init(main_clock);
362
363 /* Register the processor-specific clocks */
364 at91sam9260_register_clocks();
365
366 /* Register GPIO subsystem */
367 at91_gpio_init(at91sam9260_gpio, 3);
368}
369
370/* --------------------------------------------------------------------
371 * Interrupt initialization
372 * -------------------------------------------------------------------- */
373
374/*
375 * The default interrupt priority levels (0 = lowest, 7 = highest).
376 */
377static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
378 7, /* Advanced Interrupt Controller */
379 7, /* System Peripherals */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100380 1, /* Parallel IO Controller A */
381 1, /* Parallel IO Controller B */
382 1, /* Parallel IO Controller C */
Andrew Victor62c16602006-11-30 12:27:38 +0100383 0, /* Analog-to-Digital Converter */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100384 5, /* USART 0 */
385 5, /* USART 1 */
386 5, /* USART 2 */
Andrew Victor62c16602006-11-30 12:27:38 +0100387 0, /* Multimedia Card Interface */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100388 2, /* USB Device Port */
389 6, /* Two-Wire Interface */
390 5, /* Serial Peripheral Interface 0 */
391 5, /* Serial Peripheral Interface 1 */
Andrew Victor62c16602006-11-30 12:27:38 +0100392 5, /* Serial Synchronous Controller */
393 0,
394 0,
395 0, /* Timer Counter 0 */
396 0, /* Timer Counter 1 */
397 0, /* Timer Counter 2 */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100398 2, /* USB Host port */
Andrew Victor62c16602006-11-30 12:27:38 +0100399 3, /* Ethernet */
400 0, /* Image Sensor Interface */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100401 5, /* USART 3 */
402 5, /* USART 4 */
403 5, /* USART 5 */
Andrew Victor62c16602006-11-30 12:27:38 +0100404 0, /* Timer Counter 3 */
405 0, /* Timer Counter 4 */
406 0, /* Timer Counter 5 */
407 0, /* Advanced Interrupt Controller */
408 0, /* Advanced Interrupt Controller */
409 0, /* Advanced Interrupt Controller */
410};
411
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800412struct at91_init_soc __initdata at91sam9260_soc = {
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800413 .map_io = at91sam9260_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800414 .default_irq_priority = at91sam9260_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800415 .init = at91sam9260_initialize,
416};