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Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl.h - HD Audio skylake defintions.
3 *
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 *
19 */
20
21#ifndef __SOUND_SOC_SKL_H
22#define __SOUND_SOC_SKL_H
23
24#include <sound/hda_register.h>
25#include <sound/hdaudio_ext.h>
Jeeja KP473eb872015-07-21 23:53:55 +053026#include "skl-nhlt.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053027
28#define SKL_SUSPEND_DELAY 2000
29
Dharageswari R51a01b82016-06-03 18:29:37 +053030#define AZX_PCIREG_PGCTL 0x44
31#define AZX_PGCTL_LSRMD_MASK (1 << 4)
Jayachandran B0c8ba9d2015-12-18 15:12:03 +053032#define AZX_PCIREG_CGCTL 0x48
33#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
Pardha Saradhi Ka26a3f52016-11-03 17:07:16 +053034/* D0I3C Register fields */
35#define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
36#define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
Jayachandran B0c8ba9d2015-12-18 15:12:03 +053037
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010038struct skl_dsp_resource {
39 u32 max_mcps;
40 u32 max_mem;
41 u32 mcps;
42 u32 mem;
43};
44
Jeeja KPa40e6932015-07-09 15:20:08 +053045struct skl {
46 struct hdac_ext_bus ebus;
47 struct pci_dev *pci;
48
49 unsigned int init_failed:1; /* delayed init failed */
50 struct platform_device *dmic_dev;
Vinod Koulcc18c5f2015-11-05 21:34:13 +053051 struct platform_device *i2s_dev;
Dharageswari Rfe3f4442016-06-03 18:29:39 +053052 struct snd_soc_platform *platform;
Jeeja KP473eb872015-07-21 23:53:55 +053053
Jeeja KPc286b3f2016-05-05 11:19:19 +053054 struct nhlt_acpi_table *nhlt; /* nhlt ptr */
Jeeja KPd255b092015-07-21 23:53:56 +053055 struct skl_sst *skl_sst; /* sst skl ctx */
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010056
57 struct skl_dsp_resource resource;
58 struct list_head ppl_list;
Jeeja KPb8c722d2017-03-24 23:10:34 +053059 struct list_head bind_list;
Vinod Koulaecf6fd2015-11-05 21:34:15 +053060
61 const char *fw_name;
Vinod Koul4b235c42016-02-19 11:42:34 +053062 char tplg_name[64];
63 unsigned short pci_id;
Vinod Kould8018362016-01-05 17:16:04 +053064 const struct firmware *tplg;
Jeeja KP4557c302015-12-03 23:30:00 +053065
66 int supend_active;
Jeeja KPa40e6932015-07-09 15:20:08 +053067};
68
69#define skl_to_ebus(s) (&(s)->ebus)
70#define ebus_to_skl(sbus) \
71 container_of(sbus, struct skl, sbus)
72
73/* to pass dai dma data */
74struct skl_dma_params {
75 u32 format;
76 u8 stream_tag;
77};
78
Yong Zhif65cf7d62016-05-26 21:30:15 -070079/* to pass dmic data */
80struct skl_machine_pdata {
81 u32 dmic_num;
82};
83
Jeeja KPbc23ca32016-03-11 10:12:53 +053084struct skl_dsp_ops {
85 int id;
86 struct skl_dsp_loader_ops (*loader_ops)(void);
87 int (*init)(struct device *dev, void __iomem *mmio_base,
88 int irq, const char *fw_name,
89 struct skl_dsp_loader_ops loader_ops,
90 struct skl_sst **skl_sst);
Vinod Koul78cdbbd2016-07-26 18:06:42 +053091 int (*init_fw)(struct device *dev, struct skl_sst *ctx);
Jeeja KPbc23ca32016-03-11 10:12:53 +053092 void (*cleanup)(struct device *dev, struct skl_sst *ctx);
93};
94
Jeeja KPa40e6932015-07-09 15:20:08 +053095int skl_platform_unregister(struct device *dev);
96int skl_platform_register(struct device *dev);
97
Jeeja KPc286b3f2016-05-05 11:19:19 +053098struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
99void skl_nhlt_free(struct nhlt_acpi_table *addr);
Jeeja KP473eb872015-07-21 23:53:55 +0530100struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530101 u8 link_type, u8 s_fmt, u8 no_ch,
102 u32 s_rate, u8 dirn, u8 dev_type);
Jeeja KPd255b092015-07-21 23:53:56 +0530103
Yong Zhif65cf7d62016-05-26 21:30:15 -0700104int skl_get_dmic_geo(struct skl *skl);
Vinod Koul4b235c42016-02-19 11:42:34 +0530105int skl_nhlt_update_topology_bin(struct skl *skl);
Jeeja KPd255b092015-07-21 23:53:56 +0530106int skl_init_dsp(struct skl *skl);
Jeeja KPbc23ca32016-03-11 10:12:53 +0530107int skl_free_dsp(struct skl *skl);
Jayachandran B8b4a1332016-11-03 17:07:21 +0530108int skl_suspend_late_dsp(struct skl *skl);
Jeeja KPd255b092015-07-21 23:53:56 +0530109int skl_suspend_dsp(struct skl *skl);
110int skl_resume_dsp(struct skl *skl);
Dharageswari Rfe3f4442016-06-03 18:29:39 +0530111void skl_cleanup_resources(struct skl *skl);
Vinod Koul73a67582016-07-26 18:06:41 +0530112const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
Pardha Saradhi Ka26a3f52016-11-03 17:07:16 +0530113void skl_update_d0i3c(struct device *dev, bool enable);
Subhransu S. Prusty0cf5a172017-01-11 16:31:02 +0530114int skl_nhlt_create_sysfs(struct skl *skl);
115void skl_nhlt_remove_sysfs(struct skl *skl);
Pardha Saradhi Ka26a3f52016-11-03 17:07:16 +0530116
Jeeja KPa40e6932015-07-09 15:20:08 +0530117#endif /* __SOUND_SOC_SKL_H */