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gerrit-public.fairphone.software / kernel / msm-4.19 / 97238b35d5bbb5d5312d83c30a429824b777619f / . / arch / arm / boot / dts / am33xx.dtsi
blob: e1e773cd25568e7d65326426bafa5e23c995a379 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame^]29 usb0 = &usb0;
30 usb1 = &usb1;
31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]33 };
34
35 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]36 #address-cells = <1>;
37 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 cpu@0 {
39 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]40 device_type = "cpu";
41 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]42
43 /*
44 * To consider voltage drop between PMIC and SoC,
45 * tolerance value is reduced to 2% from 4% and
46 * voltage value is increased as a precaution.
47 */
48 operating-points = <
49 /* kHz uV */
50 720000 1285000
51 600000 1225000
52 500000 1125000
53 275000 1125000
54 >;
55 voltage-tolerance = <2>; /* 2 percentage */
56 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]57 };
58 };
59
60 /*
61 * The soc node represents the soc top level view. It is uses for IPs
62 * that are not memory mapped in the MPU view or for the MPU itself.
63 */
64 soc {
65 compatible = "ti,omap-infra";
66 mpu {
67 compatible = "ti,omap3-mpu";
68 ti,hwmods = "mpu";
69 };
70 };
71
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]72 am33xx_pinmux: pinmux@44e10800 {
73 compatible = "pinctrl-single";
74 reg = <0x44e10800 0x0238>;
75 #address-cells = <1>;
76 #size-cells = <0>;
77 pinctrl-single,register-width = <32>;
78 pinctrl-single,function-mask = <0x7f>;
79 };
80
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]81 /*
82 * XXX: Use a flat representation of the AM33XX interconnect.
83 * The real AM33XX interconnect network is quite complex.Since
84 * that will not bring real advantage to represent that in DT
85 * for the moment, just use a fake OCP bus entry to represent
86 * the whole bus hierarchy.
87 */
88 ocp {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93 ti,hwmods = "l3_main";
94
95 intc: interrupt-controller@48200000 {
96 compatible = "ti,omap2-intc";
97 interrupt-controller;
98 #interrupt-cells = <1>;
99 ti,intc-size = <128>;
100 reg = <0x48200000 0x1000>;
101 };
102
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]103 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]104 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio1";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]110 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]111 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]112 };
113
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]114 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]115 compatible = "ti,omap4-gpio";
116 ti,hwmods = "gpio2";
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]121 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]122 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]123 };
124
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]125 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]126 compatible = "ti,omap4-gpio";
127 ti,hwmods = "gpio3";
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]132 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]133 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]134 };
135
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]136 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]137 compatible = "ti,omap4-gpio";
138 ti,hwmods = "gpio4";
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]143 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]144 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]145 };
146
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]147 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]148 compatible = "ti,omap3-uart";
149 ti,hwmods = "uart1";
150 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]151 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]153 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]154 };
155
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]156 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]157 compatible = "ti,omap3-uart";
158 ti,hwmods = "uart2";
159 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]160 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]161 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]162 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]163 };
164
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]165 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]166 compatible = "ti,omap3-uart";
167 ti,hwmods = "uart3";
168 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]171 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]172 };
173
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]174 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]175 compatible = "ti,omap3-uart";
176 ti,hwmods = "uart4";
177 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]178 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]180 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 };
182
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]183 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]184 compatible = "ti,omap3-uart";
185 ti,hwmods = "uart5";
186 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]187 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]188 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]189 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]190 };
191
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]192 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]193 compatible = "ti,omap3-uart";
194 ti,hwmods = "uart6";
195 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]198 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]199 };
200
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]201 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]202 compatible = "ti,omap4-i2c";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]206 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]207 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]208 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 };
210
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]211 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]212 compatible = "ti,omap4-i2c";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]216 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]218 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]219 };
220
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]221 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]222 compatible = "ti,omap4-i2c";
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]228 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]229 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]230
231 wdt2: wdt@44e35000 {
232 compatible = "ti,omap3-wdt";
233 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]234 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]236 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]237
238 dcan0: d_can@481cc000 {
239 compatible = "bosch,d_can";
240 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]241 reg = <0x481cc000 0x2000
242 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]243 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]244 status = "disabled";
245 };
246
247 dcan1: d_can@481d0000 {
248 compatible = "bosch,d_can";
249 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]250 reg = <0x481d0000 0x2000
251 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]252 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]253 status = "disabled";
254 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]255
256 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]257 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]258 reg = <0x44e31000 0x400>;
259 interrupts = <67>;
260 ti,hwmods = "timer1";
261 ti,timer-alwon;
262 };
263
264 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]265 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]266 reg = <0x48040000 0x400>;
267 interrupts = <68>;
268 ti,hwmods = "timer2";
269 };
270
271 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]272 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]273 reg = <0x48042000 0x400>;
274 interrupts = <69>;
275 ti,hwmods = "timer3";
276 };
277
278 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]279 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]280 reg = <0x48044000 0x400>;
281 interrupts = <92>;
282 ti,hwmods = "timer4";
283 ti,timer-pwm;
284 };
285
286 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]287 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]288 reg = <0x48046000 0x400>;
289 interrupts = <93>;
290 ti,hwmods = "timer5";
291 ti,timer-pwm;
292 };
293
294 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]295 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]296 reg = <0x48048000 0x400>;
297 interrupts = <94>;
298 ti,hwmods = "timer6";
299 ti,timer-pwm;
300 };
301
302 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]303 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]304 reg = <0x4804a000 0x400>;
305 interrupts = <95>;
306 ti,hwmods = "timer7";
307 ti,timer-pwm;
308 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]309
310 rtc@44e3e000 {
311 compatible = "ti,da830-rtc";
312 reg = <0x44e3e000 0x1000>;
313 interrupts = <75
314 76>;
315 ti,hwmods = "rtc";
316 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]317
318 spi0: spi@48030000 {
319 compatible = "ti,omap4-mcspi";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]323 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]324 ti,spi-num-cs = <2>;
325 ti,hwmods = "spi0";
326 status = "disabled";
327 };
328
329 spi1: spi@481a0000 {
330 compatible = "ti,omap4-mcspi";
331 #address-cells = <1>;
332 #size-cells = <0>;
333 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]334 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]335 ti,spi-num-cs = <2>;
336 ti,hwmods = "spi1";
337 status = "disabled";
338 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]339
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame^]340 usb: usb@47400000 {
341 compatible = "ti,am33xx-usb";
342 reg = <0x47400000 0x1000>;
343 ranges;
344 #address-cells = <1>;
345 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]346 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame^]347 status = "disabled";
348
349 ctrl_mod: control@44e10000 {
350 compatible = "ti,am335x-usb-ctrl-module";
351 reg = <0x44e10620 0x10
352 0x44e10648 0x4>;
353 reg-names = "phy_ctrl", "wakeup";
354 status = "disabled";
355 };
356
357 usb0_phy: phy@47401300 {
358 compatible = "ti,am335x-usb-phy";
359 reg = <0x47401300 0x100>;
360 reg-names = "phy";
361 status = "disabled";
362 ti,ctrl_mod = <&ctrl_mod>;
363 };
364
365 usb0: usb@47401000 {
366 compatible = "ti,musb-am33xx";
367 ranges;
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0x47401000 0x200>;
371 reg-names = "control";
372 status = "disabled";
373
374 musb0: usb@47401400 {
375 compatible = "mg,musbmhdrc";
376 reg = <0x47401400 0x400>;
377 reg-names = "mc";
378 interrupts = <18>;
379 interrupt-names = "mc";
380 multipoint = <1>;
381 num-eps = <16>;
382 ram-bits = <12>;
383 port-mode = <3>;
384 power = <250>;
385 phys = <&usb0_phy>;
386 };
387 };
388
389 usb1_phy: phy@47401b00 {
390 compatible = "ti,am335x-usb-phy";
391 reg = <0x47401b00 0x100>;
392 reg-names = "phy";
393 status = "disabled";
394 ti,ctrl_mod = <&ctrl_mod>;
395 };
396
397 usb1: usb@47401800 {
398 compatible = "ti,musb-am33xx";
399 ranges;
400 #address-cells = <1>;
401 #size-cells = <1>;
402 reg = <0x47401800 0x200>;
403 reg-names = "control";
404 status = "disabled";
405
406 musb1: usb@47401c00 {
407 compatible = "mg,musbmhdrc";
408 reg = <0x47401c00 0x400>;
409 reg-names = "mc";
410 interrupts = <19>;
411 interrupt-names = "mc";
412 multipoint = <1>;
413 num-eps = <16>;
414 ram-bits = <12>;
415 port-mode = <3>;
416 power = <250>;
417 phys = <&usb1_phy>;
418 };
419 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]420 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]421
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]422 epwmss0: epwmss@48300000 {
423 compatible = "ti,am33xx-pwmss";
424 reg = <0x48300000 0x10>;
425 ti,hwmods = "epwmss0";
426 #address-cells = <1>;
427 #size-cells = <1>;
428 status = "disabled";
429 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
430 0x48300180 0x48300180 0x80 /* EQEP */
431 0x48300200 0x48300200 0x80>; /* EHRPWM */
432
433 ecap0: ecap@48300100 {
434 compatible = "ti,am33xx-ecap";
435 #pwm-cells = <3>;
436 reg = <0x48300100 0x80>;
437 ti,hwmods = "ecap0";
438 status = "disabled";
439 };
440
441 ehrpwm0: ehrpwm@48300200 {
442 compatible = "ti,am33xx-ehrpwm";
443 #pwm-cells = <3>;
444 reg = <0x48300200 0x80>;
445 ti,hwmods = "ehrpwm0";
446 status = "disabled";
447 };
448 };
449
450 epwmss1: epwmss@48302000 {
451 compatible = "ti,am33xx-pwmss";
452 reg = <0x48302000 0x10>;
453 ti,hwmods = "epwmss1";
454 #address-cells = <1>;
455 #size-cells = <1>;
456 status = "disabled";
457 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
458 0x48302180 0x48302180 0x80 /* EQEP */
459 0x48302200 0x48302200 0x80>; /* EHRPWM */
460
461 ecap1: ecap@48302100 {
462 compatible = "ti,am33xx-ecap";
463 #pwm-cells = <3>;
464 reg = <0x48302100 0x80>;
465 ti,hwmods = "ecap1";
466 status = "disabled";
467 };
468
469 ehrpwm1: ehrpwm@48302200 {
470 compatible = "ti,am33xx-ehrpwm";
471 #pwm-cells = <3>;
472 reg = <0x48302200 0x80>;
473 ti,hwmods = "ehrpwm1";
474 status = "disabled";
475 };
476 };
477
478 epwmss2: epwmss@48304000 {
479 compatible = "ti,am33xx-pwmss";
480 reg = <0x48304000 0x10>;
481 ti,hwmods = "epwmss2";
482 #address-cells = <1>;
483 #size-cells = <1>;
484 status = "disabled";
485 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
486 0x48304180 0x48304180 0x80 /* EQEP */
487 0x48304200 0x48304200 0x80>; /* EHRPWM */
488
489 ecap2: ecap@48304100 {
490 compatible = "ti,am33xx-ecap";
491 #pwm-cells = <3>;
492 reg = <0x48304100 0x80>;
493 ti,hwmods = "ecap2";
494 status = "disabled";
495 };
496
497 ehrpwm2: ehrpwm@48304200 {
498 compatible = "ti,am33xx-ehrpwm";
499 #pwm-cells = <3>;
500 reg = <0x48304200 0x80>;
501 ti,hwmods = "ehrpwm2";
502 status = "disabled";
503 };
504 };
505
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]506 mac: ethernet@4a100000 {
507 compatible = "ti,cpsw";
508 ti,hwmods = "cpgmac0";
509 cpdma_channels = <8>;
510 ale_entries = <1024>;
511 bd_ram_size = <0x2000>;
512 no_bd_ram = <0>;
513 rx_descs = <64>;
514 mac_control = <0x20>;
515 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]516 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]517 cpts_clock_mult = <0x80000000>;
518 cpts_clock_shift = <29>;
519 reg = <0x4a100000 0x800
520 0x4a101200 0x100>;
521 #address-cells = <1>;
522 #size-cells = <1>;
523 interrupt-parent = <&intc>;
524 /*
525 * c0_rx_thresh_pend
526 * c0_rx_pend
527 * c0_tx_pend
528 * c0_misc_pend
529 */
530 interrupts = <40 41 42 43>;
531 ranges;
532
533 davinci_mdio: mdio@4a101000 {
534 compatible = "ti,davinci_mdio";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 ti,hwmods = "davinci_mdio";
538 bus_freq = <1000000>;
539 reg = <0x4a101000 0x100>;
540 };
541
542 cpsw_emac0: slave@4a100200 {
543 /* Filled in by U-Boot */
544 mac-address = [ 00 00 00 00 00 00 ];
545 };
546
547 cpsw_emac1: slave@4a100300 {
548 /* Filled in by U-Boot */
549 mac-address = [ 00 00 00 00 00 00 ];
550 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]551 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]552
553 ocmcram: ocmcram@40300000 {
554 compatible = "ti,am3352-ocmcram";
555 reg = <0x40300000 0x10000>;
556 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]557 };
558
559 wkup_m3: wkup_m3@44d00000 {
560 compatible = "ti,am3353-wkup-m3";
561 reg = <0x44d00000 0x4000 /* M3 UMEM */
562 0x44d80000 0x2000>; /* M3 DMEM */
563 ti,hwmods = "wkup_m3";
564 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]565
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]566 elm: elm@48080000 {
567 compatible = "ti,am3352-elm";
568 reg = <0x48080000 0x2000>;
569 interrupts = <4>;
570 ti,hwmods = "elm";
571 status = "disabled";
572 };
573
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]574 tscadc: tscadc@44e0d000 {
575 compatible = "ti,am3359-tscadc";
576 reg = <0x44e0d000 0x1000>;
577 interrupt-parent = <&intc>;
578 interrupts = <16>;
579 ti,hwmods = "adc_tsc";
580 status = "disabled";
581
582 tsc {
583 compatible = "ti,am3359-tsc";
584 };
585 am335x_adc: adc {
586 #io-channel-cells = <1>;
587 compatible = "ti,am3359-adc";
588 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]589 };
590
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]591 gpmc: gpmc@50000000 {
592 compatible = "ti,am3352-gpmc";
593 ti,hwmods = "gpmc";
594 reg = <0x50000000 0x2000>;
595 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]596 gpmc,num-cs = <7>;
597 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]598 #address-cells = <2>;
599 #size-cells = <1>;
600 status = "disabled";
601 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]602 };
603};