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gerrit-public.fairphone.software / kernel / msm-4.19 / be76fd3197df608e1b010bf5ab90377205f54344 / . / arch / arm / boot / dts / omap3.dtsi
blob: ecf5eb584c75058598b9c90bc3f3568bf3a7ce7e [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]15/ {
16 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]17 interrupt-parent = <&intc>;
Javier Martinez Canillas008a2eb2016-08-31 12:35:18 +0200[diff] [blame]18 #address-cells = <1>;
19 #size-cells = <1>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]20
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]21 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]28 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]30 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]34 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]36 device_type = "cpu";
37 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]38
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]43 };
44 };
45
Javier Martinez Canillas2995a9e2016-04-01 16:20:20 -0400[diff] [blame]46 pmu@54000000 {
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]47 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]48 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]49 interrupts = <3>;
50 ti,hwmods = "debugss";
51 };
52
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]53 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]54 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]55 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]59 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
63
Suman Anna4c051602014-04-22 17:23:37 -0500[diff] [blame]64 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]65 compatible = "ti,iva2.2";
66 ti,hwmods = "iva";
67
68 dsp {
69 compatible = "ti,omap3-c64";
70 };
71 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]72 };
73
74 /*
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]77 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]78 * the moment, just use a fake OCP bus entry to represent the whole bus
79 * hierarchy.
80 */
Javier Martinez Canillasf515f812016-08-01 12:46:55 -0400[diff] [blame]81 ocp@68000000 {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -0800[diff] [blame]82 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]83 reg = <0x68000000 0x10000>;
84 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 ti,hwmods = "l3_main";
89
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame^]109 #pinctrl-cells = <1>;
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]110 #interrupt-cells = <1>;
111 interrupt-controller;
112 pinctrl-single,register-width = <16>;
113 pinctrl-single,function-mask = <0xff1f>;
114 };
115
116 scm_conf: scm_conf@270 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]117 compatible = "syscon", "simple-bus";
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]118 reg = <0x270 0x330>;
119 #address-cells = <1>;
120 #size-cells = <1>;
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]121 ranges = <0 0x270 0x330>;
122
Javier Martinez Canillas308cfda2016-04-01 16:20:18 -0400[diff] [blame]123 pbias_regulator: pbias_regulator@2b0 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]124 compatible = "ti,pbias-omap3", "ti,pbias-omap";
125 reg = <0x2b0 0x4>;
126 syscon = <&scm_conf>;
127 pbias_mmc_reg: pbias_mmc_omap2430 {
128 regulator-name = "pbias_mmc_omap2430";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <3000000>;
131 };
132 };
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]133
134 scm_clocks: clocks {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 };
138 };
139
140 scm_clockdomains: clockdomains {
141 };
142
143 omap3_pmx_wkup: pinmux@a00 {
144 compatible = "ti,omap3-padconf",
145 "pinctrl-single";
146 reg = <0xa00 0x5c>;
147 #address-cells = <1>;
148 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame^]149 #pinctrl-cells = <1>;
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]150 #interrupt-cells = <1>;
151 interrupt-controller;
152 pinctrl-single,register-width = <16>;
153 pinctrl-single,function-mask = <0xff1f>;
154 };
155 };
156 };
157
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]158 aes: aes@480c5000 {
159 compatible = "ti,omap3-aes";
160 ti,hwmods = "aes";
161 reg = <0x480c5000 0x50>;
162 interrupts = <0>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]163 dmas = <&sdma 65 &sdma 66>;
164 dma-names = "tx", "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]165 };
166
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]167 prm: prm@48306000 {
168 compatible = "ti,omap3-prm";
169 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500[diff] [blame]170 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]171
172 prm_clocks: clocks {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 };
176
177 prm_clockdomains: clockdomains {
178 };
179 };
180
181 cm: cm@48004000 {
182 compatible = "ti,omap3-cm";
183 reg = <0x48004000 0x4000>;
184
185 cm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 cm_clockdomains: clockdomains {
191 };
192 };
193
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]194 counter32k: counter@48320000 {
195 compatible = "ti,omap-counter32k";
196 reg = <0x48320000 0x20>;
197 ti,hwmods = "counter_32k";
198 };
199
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]200 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]201 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]202 interrupt-controller;
203 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]204 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]205 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]206
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]207 sdma: dma-controller@48056000 {
208 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
209 reg = <0x48056000 0x1000>;
210 interrupts = <12>,
211 <13>,
212 <14>,
213 <15>;
214 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200[diff] [blame]215 dma-channels = <32>;
216 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]217 };
218
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]219 gpio1: gpio@48310000 {
220 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]221 reg = <0x48310000 0x200>;
222 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]223 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]224 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]228 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]229 };
230
231 gpio2: gpio@49050000 {
232 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]233 reg = <0x49050000 0x200>;
234 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]235 ti,hwmods = "gpio2";
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]239 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]240 };
241
242 gpio3: gpio@49052000 {
243 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]244 reg = <0x49052000 0x200>;
245 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]246 ti,hwmods = "gpio3";
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]250 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]251 };
252
253 gpio4: gpio@49054000 {
254 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]255 reg = <0x49054000 0x200>;
256 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]257 ti,hwmods = "gpio4";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]261 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]262 };
263
264 gpio5: gpio@49056000 {
265 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]266 reg = <0x49056000 0x200>;
267 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]268 ti,hwmods = "gpio5";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]272 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]273 };
274
275 gpio6: gpio@49058000 {
276 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]277 reg = <0x49058000 0x200>;
278 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]279 ti,hwmods = "gpio6";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]283 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]284 };
285
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]286 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]287 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]288 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]289 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]290 dmas = <&sdma 49 &sdma 50>;
291 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]292 ti,hwmods = "uart1";
293 clock-frequency = <48000000>;
294 };
295
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]296 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]297 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]298 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]299 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]300 dmas = <&sdma 51 &sdma 52>;
301 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]302 ti,hwmods = "uart2";
303 clock-frequency = <48000000>;
304 };
305
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]306 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]307 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]308 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]309 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]310 dmas = <&sdma 53 &sdma 54>;
311 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]312 ti,hwmods = "uart3";
313 clock-frequency = <48000000>;
314 };
315
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]316 i2c1: i2c@48070000 {
317 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]318 reg = <0x48070000 0x80>;
319 interrupts = <56>;
320 dmas = <&sdma 27 &sdma 28>;
321 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]322 #address-cells = <1>;
323 #size-cells = <0>;
324 ti,hwmods = "i2c1";
325 };
326
327 i2c2: i2c@48072000 {
328 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]329 reg = <0x48072000 0x80>;
330 interrupts = <57>;
331 dmas = <&sdma 29 &sdma 30>;
332 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]333 #address-cells = <1>;
334 #size-cells = <0>;
335 ti,hwmods = "i2c2";
336 };
337
338 i2c3: i2c@48060000 {
339 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]340 reg = <0x48060000 0x80>;
341 interrupts = <61>;
342 dmas = <&sdma 25 &sdma 26>;
343 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]344 #address-cells = <1>;
345 #size-cells = <0>;
346 ti,hwmods = "i2c3";
347 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]348
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]349 mailbox: mailbox@48094000 {
350 compatible = "ti,omap3-mailbox";
351 ti,hwmods = "mailbox";
352 reg = <0x48094000 0x200>;
353 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]354 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]355 ti,mbox-num-users = <2>;
356 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]357 mbox_dsp: dsp {
358 ti,mbox-tx = <0 0 0>;
359 ti,mbox-rx = <1 0 0>;
360 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]361 };
362
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]363 mcspi1: spi@48098000 {
364 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]365 reg = <0x48098000 0x100>;
366 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]367 #address-cells = <1>;
368 #size-cells = <0>;
369 ti,hwmods = "mcspi1";
370 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]371 dmas = <&sdma 35>,
372 <&sdma 36>,
373 <&sdma 37>,
374 <&sdma 38>,
375 <&sdma 39>,
376 <&sdma 40>,
377 <&sdma 41>,
378 <&sdma 42>;
379 dma-names = "tx0", "rx0", "tx1", "rx1",
380 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]381 };
382
383 mcspi2: spi@4809a000 {
384 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]385 reg = <0x4809a000 0x100>;
386 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]387 #address-cells = <1>;
388 #size-cells = <0>;
389 ti,hwmods = "mcspi2";
390 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]391 dmas = <&sdma 43>,
392 <&sdma 44>,
393 <&sdma 45>,
394 <&sdma 46>;
395 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]396 };
397
398 mcspi3: spi@480b8000 {
399 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]400 reg = <0x480b8000 0x100>;
401 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]402 #address-cells = <1>;
403 #size-cells = <0>;
404 ti,hwmods = "mcspi3";
405 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]406 dmas = <&sdma 15>,
407 <&sdma 16>,
408 <&sdma 23>,
409 <&sdma 24>;
410 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]411 };
412
413 mcspi4: spi@480ba000 {
414 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]415 reg = <0x480ba000 0x100>;
416 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]417 #address-cells = <1>;
418 #size-cells = <0>;
419 ti,hwmods = "mcspi4";
420 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]421 dmas = <&sdma 70>, <&sdma 71>;
422 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]423 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]424
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]425 hdqw1w: 1w@480b2000 {
426 compatible = "ti,omap3-1w";
427 reg = <0x480b2000 0x1000>;
428 interrupts = <58>;
429 ti,hwmods = "hdq1w";
430 };
431
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]432 mmc1: mmc@4809c000 {
433 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]434 reg = <0x4809c000 0x200>;
435 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]436 ti,hwmods = "mmc1";
437 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]438 dmas = <&sdma 61>, <&sdma 62>;
439 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]440 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]441 };
442
443 mmc2: mmc@480b4000 {
444 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]445 reg = <0x480b4000 0x200>;
446 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]447 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]448 dmas = <&sdma 47>, <&sdma 48>;
449 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]450 };
451
452 mmc3: mmc@480ad000 {
453 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]454 reg = <0x480ad000 0x200>;
455 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]456 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]457 dmas = <&sdma 77>, <&sdma 78>;
458 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]459 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]460
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]461 mmu_isp: mmu@480bd400 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]462 #iommu-cells = <0>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]463 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]464 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]465 interrupts = <24>;
466 ti,hwmods = "mmu_isp";
467 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]468 };
469
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]470 mmu_iva: mmu@5d000000 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]471 #iommu-cells = <0>;
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]472 compatible = "ti,omap2-iommu";
473 reg = <0x5d000000 0x80>;
474 interrupts = <28>;
475 ti,hwmods = "mmu_iva";
476 status = "disabled";
477 };
478
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]479 wdt2: wdt@48314000 {
480 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]481 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]482 ti,hwmods = "wd_timer2";
483 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]484
485 mcbsp1: mcbsp@48074000 {
486 compatible = "ti,omap3-mcbsp";
487 reg = <0x48074000 0xff>;
488 reg-names = "mpu";
489 interrupts = <16>, /* OCP compliant interrupt */
490 <59>, /* TX interrupt */
491 <60>; /* RX interrupt */
492 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]493 ti,buffer-size = <128>;
494 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]495 dmas = <&sdma 31>,
496 <&sdma 32>;
497 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]498 clocks = <&mcbsp1_fck>;
499 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]500 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]501 };
502
503 mcbsp2: mcbsp@49022000 {
504 compatible = "ti,omap3-mcbsp";
505 reg = <0x49022000 0xff>,
506 <0x49028000 0xff>;
507 reg-names = "mpu", "sidetone";
508 interrupts = <17>, /* OCP compliant interrupt */
509 <62>, /* TX interrupt */
510 <63>, /* RX interrupt */
511 <4>; /* Sidetone */
512 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]513 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]514 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]515 dmas = <&sdma 33>,
516 <&sdma 34>;
517 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]518 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
519 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]520 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]521 };
522
523 mcbsp3: mcbsp@49024000 {
524 compatible = "ti,omap3-mcbsp";
525 reg = <0x49024000 0xff>,
526 <0x4902a000 0xff>;
527 reg-names = "mpu", "sidetone";
528 interrupts = <22>, /* OCP compliant interrupt */
529 <89>, /* TX interrupt */
530 <90>, /* RX interrupt */
531 <5>; /* Sidetone */
532 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]533 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]534 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]535 dmas = <&sdma 17>,
536 <&sdma 18>;
537 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]538 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
539 clock-names = "fck", "ick";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]540 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]541 };
542
543 mcbsp4: mcbsp@49026000 {
544 compatible = "ti,omap3-mcbsp";
545 reg = <0x49026000 0xff>;
546 reg-names = "mpu";
547 interrupts = <23>, /* OCP compliant interrupt */
548 <54>, /* TX interrupt */
549 <55>; /* RX interrupt */
550 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]551 ti,buffer-size = <128>;
552 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]553 dmas = <&sdma 19>,
554 <&sdma 20>;
555 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]556 clocks = <&mcbsp4_fck>;
557 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]558 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]559 };
560
561 mcbsp5: mcbsp@48096000 {
562 compatible = "ti,omap3-mcbsp";
563 reg = <0x48096000 0xff>;
564 reg-names = "mpu";
565 interrupts = <27>, /* OCP compliant interrupt */
566 <81>, /* TX interrupt */
567 <82>; /* RX interrupt */
568 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]569 ti,buffer-size = <128>;
570 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]571 dmas = <&sdma 21>,
572 <&sdma 22>;
573 dma-names = "tx", "rx";
Peter Ujfalusi138e9962016-05-30 11:23:44 +0300[diff] [blame]574 clocks = <&mcbsp5_fck>;
575 clock-names = "fck";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]576 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]577 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]578
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]579 sham: sham@480c3000 {
580 compatible = "ti,omap3-sham";
581 ti,hwmods = "sham";
582 reg = <0x480c3000 0x64>;
583 interrupts = <49>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]584 dmas = <&sdma 69>;
585 dma-names = "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]586 };
587
588 smartreflex_core: smartreflex@480cb000 {
589 compatible = "ti,omap3-smartreflex-core";
590 ti,hwmods = "smartreflex_core";
591 reg = <0x480cb000 0x400>;
592 interrupts = <19>;
593 };
594
595 smartreflex_mpu_iva: smartreflex@480c9000 {
596 compatible = "ti,omap3-smartreflex-iva";
597 ti,hwmods = "smartreflex_mpu_iva";
598 reg = <0x480c9000 0x400>;
599 interrupts = <18>;
600 };
601
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]602 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]603 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]604 reg = <0x48318000 0x400>;
605 interrupts = <37>;
606 ti,hwmods = "timer1";
607 ti,timer-alwon;
608 };
609
610 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]611 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]612 reg = <0x49032000 0x400>;
613 interrupts = <38>;
614 ti,hwmods = "timer2";
615 };
616
617 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]618 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]619 reg = <0x49034000 0x400>;
620 interrupts = <39>;
621 ti,hwmods = "timer3";
622 };
623
624 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]625 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]626 reg = <0x49036000 0x400>;
627 interrupts = <40>;
628 ti,hwmods = "timer4";
629 };
630
631 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]632 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]633 reg = <0x49038000 0x400>;
634 interrupts = <41>;
635 ti,hwmods = "timer5";
636 ti,timer-dsp;
637 };
638
639 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]640 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]641 reg = <0x4903a000 0x400>;
642 interrupts = <42>;
643 ti,hwmods = "timer6";
644 ti,timer-dsp;
645 };
646
647 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]648 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]649 reg = <0x4903c000 0x400>;
650 interrupts = <43>;
651 ti,hwmods = "timer7";
652 ti,timer-dsp;
653 };
654
655 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]656 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]657 reg = <0x4903e000 0x400>;
658 interrupts = <44>;
659 ti,hwmods = "timer8";
660 ti,timer-pwm;
661 ti,timer-dsp;
662 };
663
664 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]665 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]666 reg = <0x49040000 0x400>;
667 interrupts = <45>;
668 ti,hwmods = "timer9";
669 ti,timer-pwm;
670 };
671
672 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]673 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]674 reg = <0x48086000 0x400>;
675 interrupts = <46>;
676 ti,hwmods = "timer10";
677 ti,timer-pwm;
678 };
679
680 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]681 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]682 reg = <0x48088000 0x400>;
683 interrupts = <47>;
684 ti,hwmods = "timer11";
685 ti,timer-pwm;
686 };
687
688 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]689 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]690 reg = <0x48304000 0x400>;
691 interrupts = <95>;
692 ti,hwmods = "timer12";
693 ti,timer-alwon;
694 ti,timer-secure;
695 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]696
697 usbhstll: usbhstll@48062000 {
698 compatible = "ti,usbhs-tll";
699 reg = <0x48062000 0x1000>;
700 interrupts = <78>;
701 ti,hwmods = "usb_tll_hs";
702 };
703
704 usbhshost: usbhshost@48064000 {
705 compatible = "ti,usbhs-host";
706 reg = <0x48064000 0x400>;
707 ti,hwmods = "usb_host_hs";
708 #address-cells = <1>;
709 #size-cells = <1>;
710 ranges;
711
712 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]713 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]714 reg = <0x48064400 0x400>;
715 interrupt-parent = <&intc>;
716 interrupts = <76>;
717 };
718
719 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]720 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]721 reg = <0x48064800 0x400>;
722 interrupt-parent = <&intc>;
723 interrupts = <77>;
724 };
725 };
726
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]727 gpmc: gpmc@6e000000 {
728 compatible = "ti,omap3430-gpmc";
729 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]730 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]731 interrupts = <20>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]732 dmas = <&sdma 4>;
733 dma-names = "rxtx";
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]734 gpmc,num-cs = <8>;
735 gpmc,num-waitpins = <4>;
736 #address-cells = <2>;
737 #size-cells = <1>;
Roger Quadros44e47162016-02-23 18:37:25 +0200[diff] [blame]738 interrupt-controller;
739 #interrupt-cells = <2>;
Roger Quadros94f56c82016-04-07 13:25:34 +0300[diff] [blame]740 gpio-controller;
741 #gpio-cells = <2>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]742 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]743
744 usb_otg_hs: usb_otg_hs@480ab000 {
745 compatible = "ti,omap3-musb";
746 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]747 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]748 interrupt-names = "mc", "dma";
749 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]750 multipoint = <1>;
751 num-eps = <16>;
752 ram-bits = <12>;
753 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200[diff] [blame]754
755 dss: dss@48050000 {
756 compatible = "ti,omap3-dss";
757 reg = <0x48050000 0x200>;
758 status = "disabled";
759 ti,hwmods = "dss_core";
760 clocks = <&dss1_alwon_fck>;
761 clock-names = "fck";
762 #address-cells = <1>;
763 #size-cells = <1>;
764 ranges;
765
766 dispc@48050400 {
767 compatible = "ti,omap3-dispc";
768 reg = <0x48050400 0x400>;
769 interrupts = <25>;
770 ti,hwmods = "dss_dispc";
771 clocks = <&dss1_alwon_fck>;
772 clock-names = "fck";
773 };
774
775 dsi: encoder@4804fc00 {
776 compatible = "ti,omap3-dsi";
777 reg = <0x4804fc00 0x200>,
778 <0x4804fe00 0x40>,
779 <0x4804ff00 0x20>;
780 reg-names = "proto", "phy", "pll";
781 interrupts = <25>;
782 status = "disabled";
783 ti,hwmods = "dss_dsi1";
784 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
785 clock-names = "fck", "sys_clk";
786 };
787
788 rfbi: encoder@48050800 {
789 compatible = "ti,omap3-rfbi";
790 reg = <0x48050800 0x100>;
791 status = "disabled";
792 ti,hwmods = "dss_rfbi";
793 clocks = <&dss1_alwon_fck>, <&dss_ick>;
794 clock-names = "fck", "ick";
795 };
796
797 venc: encoder@48050c00 {
798 compatible = "ti,omap3-venc";
799 reg = <0x48050c00 0x100>;
800 status = "disabled";
801 ti,hwmods = "dss_venc";
802 clocks = <&dss_tv_fck>;
803 clock-names = "fck";
804 };
805 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]806
807 ssi: ssi-controller@48058000 {
808 compatible = "ti,omap3-ssi";
809 ti,hwmods = "ssi";
810
811 status = "disabled";
812
813 reg = <0x48058000 0x1000>,
814 <0x48059000 0x1000>;
815 reg-names = "sys",
816 "gdd";
817
818 interrupts = <71>;
819 interrupt-names = "gdd_mpu";
820
821 #address-cells = <1>;
822 #size-cells = <1>;
823 ranges;
824
825 ssi_port1: ssi-port@4805a000 {
826 compatible = "ti,omap3-ssi-port";
827
828 reg = <0x4805a000 0x800>,
829 <0x4805a800 0x800>;
830 reg-names = "tx",
831 "rx";
832
833 interrupt-parent = <&intc>;
834 interrupts = <67>,
835 <68>;
836 };
837
838 ssi_port2: ssi-port@4805b000 {
839 compatible = "ti,omap3-ssi-port";
840
841 reg = <0x4805b000 0x800>,
842 <0x4805b800 0x800>;
843 reg-names = "tx",
844 "rx";
845
846 interrupt-parent = <&intc>;
847 interrupts = <69>,
848 <70>;
849 };
850 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]851 };
852};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]853
854/include/ "omap3xxx-clocks.dtsi"