blob: 93e7df824650e8fab69beefddc9fa27e10e88dd4 [file] [log] [blame]
Paul Walmsleyad67ef62008-08-19 11:08:40 +03001/*
Paul Walmsleya64bb9c2010-12-21 21:05:14 -07002 * OMAP2/3/4 powerdomain control
Paul Walmsleyad67ef62008-08-19 11:08:40 +03003 *
Paul Walmsley72e06d02010-12-21 21:05:16 -07004 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
Paul Walmsley694606c2011-03-07 19:28:15 -07005 * Copyright (C) 2007-2011 Nokia Corporation
Paul Walmsleyad67ef62008-08-19 11:08:40 +03006 *
Paul Walmsley72e06d02010-12-21 21:05:16 -07007 * Paul Walmsley
Paul Walmsleyad67ef62008-08-19 11:08:40 +03008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
Paul Walmsley6e014782010-12-21 20:01:20 -070012 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
Paul Walmsleyad67ef62008-08-19 11:08:40 +030015 */
16
Paul Walmsley72e06d02010-12-21 21:05:16 -070017#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
Paul Walmsleyad67ef62008-08-19 11:08:40 +030019
20#include <linux/types.h>
21#include <linux/list.h>
22
Paul Walmsley72e06d02010-12-21 21:05:16 -070023#include <linux/atomic.h>
Paul Walmsleyad67ef62008-08-19 11:08:40 +030024
Kevin Hilman8f1bec22011-03-23 07:22:23 -070025#include "voltage.h"
26
Paul Walmsleyad67ef62008-08-19 11:08:40 +030027/* Powerdomain basic power states */
28#define PWRDM_POWER_OFF 0x0
29#define PWRDM_POWER_RET 0x1
30#define PWRDM_POWER_INACTIVE 0x2
31#define PWRDM_POWER_ON 0x3
32
Paul Walmsley2354eb52009-12-08 16:33:12 -070033#define PWRDM_MAX_PWRSTS 4
34
Paul Walmsleyad67ef62008-08-19 11:08:40 +030035/* Powerdomain allowable state bitfields */
Rajendra Nayakd3353e12010-05-18 20:24:01 -060036#define PWRSTS_ON (1 << PWRDM_POWER_ON)
Paul Walmsley694606c2011-03-07 19:28:15 -070037#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
38#define PWRSTS_RET (1 << PWRDM_POWER_RET)
Rajendra Nayakbb722f32010-09-27 14:02:56 -060039#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
Paul Walmsleyad67ef62008-08-19 11:08:40 +030040
Paul Walmsley694606c2011-03-07 19:28:15 -070041#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
42#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
Paul Walmsleyad67ef62008-08-19 11:08:40 +030045
46
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -060047/* Powerdomain flags */
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
Thara Gopinath3863c742009-12-08 16:33:15 -070049#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
50 * in MEM bank 1 position. This is
51 * true for OMAP3430
52 */
Rajendra Nayak90dbc7b2010-05-18 20:24:03 -060053#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -060059
Paul Walmsleyad67ef62008-08-19 11:08:40 +030060/*
Abhijit Pagare38900c22010-01-26 20:12:52 -070061 * Number of memory banks that are power-controllable. On OMAP4430, the
62 * maximum is 5.
Paul Walmsleyad67ef62008-08-19 11:08:40 +030063 */
Abhijit Pagare38900c22010-01-26 20:12:52 -070064#define PWRDM_MAX_MEM_BANKS 5
Paul Walmsleyad67ef62008-08-19 11:08:40 +030065
Paul Walmsley8420bb12008-08-19 11:08:44 +030066/*
67 * Maximum number of clockdomains that can be associated with a powerdomain.
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -060068 * PER powerdomain on AM33XX is the worst case
Paul Walmsley8420bb12008-08-19 11:08:44 +030069 */
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -060070#define PWRDM_MAX_CLKDMS 11
Paul Walmsley8420bb12008-08-19 11:08:44 +030071
Paul Walmsleyad67ef62008-08-19 11:08:40 +030072/* XXX A completely arbitrary number. What is reasonable here? */
73#define PWRDM_TRANSITION_BAILOUT 100000
74
Paul Walmsley8420bb12008-08-19 11:08:44 +030075struct clockdomain;
Paul Walmsleyad67ef62008-08-19 11:08:40 +030076struct powerdomain;
77
Paul Walmsleyf0271d62010-01-26 20:13:02 -070078/**
79 * struct powerdomain - OMAP powerdomain
80 * @name: Powerdomain name
Kevin Hilman8f1bec22011-03-23 07:22:23 -070081 * @voltdm: voltagedomain containing this powerdomain
Paul Walmsleyf0271d62010-01-26 20:13:02 -070082 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
Paul Walmsleya64bb9c2010-12-21 21:05:14 -070083 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
Paul Walmsleyf0271d62010-01-26 20:13:02 -070084 * @pwrsts: Possible powerdomain power states
85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
86 * @flags: Powerdomain flags
87 * @banks: Number of software-controllable memory banks in this powerdomain
88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
90 * @pwrdm_clkdms: Clockdomains in this powerdomain
91 * @node: list_head linking all powerdomains
Kevin Hilmane69c22b2011-03-16 16:13:15 -070092 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -060093 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
94 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
95 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
96 * in @pwrstctrl_offs
97 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
98 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
99 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
100 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
101 * in @pwrstctrl_offs
Paul Walmsleyf0271d62010-01-26 20:13:02 -0700102 * @state:
103 * @state_counter:
104 * @timer:
105 * @state_timer:
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700106 *
107 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
Paul Walmsleyf0271d62010-01-26 20:13:02 -0700108 */
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300109struct powerdomain {
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300110 const char *name;
Kevin Hilman8f1bec22011-03-23 07:22:23 -0700111 union {
112 const char *name;
113 struct voltagedomain *ptr;
114 } voltdm;
Paul Walmsleye0594b42010-01-26 20:13:01 -0700115 const s16 prcm_offs;
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300116 const u8 pwrsts;
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300117 const u8 pwrsts_logic_ret;
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -0600118 const u8 flags;
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300119 const u8 banks;
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300120 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300121 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
Paul Walmsleya64bb9c2010-12-21 21:05:14 -0700122 const u8 prcm_partition;
Paul Walmsley8420bb12008-08-19 11:08:44 +0300123 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300124 struct list_head node;
Kevin Hilmane69c22b2011-03-16 16:13:15 -0700125 struct list_head voltdm_node;
Peter 'p2' De Schrijverba20bb12008-10-15 17:48:43 +0300126 int state;
Paul Walmsley2354eb52009-12-08 16:33:12 -0700127 unsigned state_counter[PWRDM_MAX_PWRSTS];
Thara Gopinathcde08f82010-02-24 12:05:50 -0700128 unsigned ret_logic_off_counter;
129 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
Peter 'p2' De Schrijver331b93f2008-10-15 18:13:48 +0300130
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600131 const u8 pwrstctrl_offs;
132 const u8 pwrstst_offs;
133 const u32 logicretstate_mask;
134 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
135 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
136 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
138
Peter 'p2' De Schrijver331b93f2008-10-15 18:13:48 +0300139#ifdef CONFIG_PM_DEBUG
140 s64 timer;
Paul Walmsley2354eb52009-12-08 16:33:12 -0700141 s64 state_timer[PWRDM_MAX_PWRSTS];
Peter 'p2' De Schrijver331b93f2008-10-15 18:13:48 +0300142#endif
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300143};
144
Rajendra Nayak3b1e8b22010-12-21 20:01:18 -0700145/**
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300146 * struct pwrdm_ops - Arch specific function implementations
Rajendra Nayak3b1e8b22010-12-21 20:01:18 -0700147 * @pwrdm_set_next_pwrst: Set the target power state for a pd
148 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
149 * @pwrdm_read_pwrst: Read the current power state of a pd
150 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
151 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
152 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
153 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
154 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
155 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
156 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
157 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
158 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
159 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
160 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
161 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
162 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
163 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
164 * @pwrdm_wait_transition: Wait for a pd state transition to complete
Paul Walmsleyc4978fb2013-01-29 13:45:09 -0700165 *
166 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
167 * chips, a powerdomain's power state is not allowed to directly
168 * transition from one low-power state (e.g., CSWR) to another
169 * low-power state (e.g., OFF) without first waking up the
170 * powerdomain. This wastes energy. So OMAP4 chips support the
171 * ability to transition a powerdomain power state directly from one
172 * low-power state to another. The function pointed to by
173 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
174 * hardware powerdomain state machine to enable this feature.
Rajendra Nayak3b1e8b22010-12-21 20:01:18 -0700175 */
176struct pwrdm_ops {
177 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
178 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
179 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
180 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
181 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
182 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
183 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
184 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
185 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
186 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
187 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
188 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
189 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
190 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
191 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
192 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
193 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
194 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
195};
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300196
Paul Walmsley129c65e2011-09-14 16:01:21 -0600197int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
198int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
199int pwrdm_complete_init(void);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300200
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300201struct powerdomain *pwrdm_lookup(const char *name);
202
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300203int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
204 void *user);
Artem Bityutskiyee894b12009-10-01 10:01:55 +0300205int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
206 void *user);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300207
Paul Walmsley8420bb12008-08-19 11:08:44 +0300208int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
209int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
210int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
211 int (*fn)(struct powerdomain *pwrdm,
212 struct clockdomain *clkdm));
Kevin Hilman048a7032011-03-16 15:52:47 -0700213struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
Paul Walmsley8420bb12008-08-19 11:08:44 +0300214
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300215int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
216
217int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
218int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
Paul Walmsleyfecb4942009-01-27 19:12:50 -0700219int pwrdm_read_pwrst(struct powerdomain *pwrdm);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300220int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
221int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
222
223int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
224int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
225int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
226
227int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
228int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
Thara Gopinath1e3d0d22010-02-24 12:05:49 -0700229int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300230int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
231int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
Thara Gopinath1e3d0d22010-02-24 12:05:49 -0700232int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300233
Paul Walmsley0b7cbfb2008-06-25 18:09:37 -0600234int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
235int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
236bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
237
Peter 'p2' De Schrijverba20bb12008-10-15 17:48:43 +0300238int pwrdm_state_switch(struct powerdomain *pwrdm);
Kevin Hilmane0555482012-05-11 16:00:24 -0700239int pwrdm_pre_transition(struct powerdomain *pwrdm);
240int pwrdm_post_transition(struct powerdomain *pwrdm);
Tomi Valkeinenfc013872011-06-09 16:56:23 +0300241int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
Paul Walmsley694606c2011-03-07 19:28:15 -0700242bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
Peter 'p2' De Schrijverba20bb12008-10-15 17:48:43 +0300243
Paul Walmsleyc4978fb2013-01-29 13:45:09 -0700244extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
245
Paul Walmsley81794882011-09-14 11:34:21 -0600246extern void omap242x_powerdomains_init(void);
247extern void omap243x_powerdomains_init(void);
Paul Walmsley6e014782010-12-21 20:01:20 -0700248extern void omap3xxx_powerdomains_init(void);
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600249extern void am33xx_powerdomains_init(void);
Paul Walmsley6e014782010-12-21 20:01:20 -0700250extern void omap44xx_powerdomains_init(void);
251
Paul Walmsley72e06d02010-12-21 21:05:16 -0700252extern struct pwrdm_ops omap2_pwrdm_operations;
253extern struct pwrdm_ops omap3_pwrdm_operations;
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600254extern struct pwrdm_ops am33xx_pwrdm_operations;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700255extern struct pwrdm_ops omap4_pwrdm_operations;
256
257/* Common Internal functions used across OMAP rev's */
258extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
259extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
260extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
261
262extern struct powerdomain wkup_omap2_pwrdm;
263extern struct powerdomain gfx_omap2_pwrdm;
264
265
Paul Walmsleyad67ef62008-08-19 11:08:40 +0300266#endif