Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 5 | * Copyright (C) 2010 ST-Ericsson SA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/device.h> |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 16 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
Russell King | 613b152 | 2011-01-30 21:06:53 +0000 | [diff] [blame] | 18 | #include <linux/kernel.h> |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 19 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/highmem.h> |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 23 | #include <linux/log2.h> |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 24 | #include <linux/mmc/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/mmc/host.h> |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 26 | #include <linux/mmc/card.h> |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 27 | #include <linux/mmc/slot-gpio.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 28 | #include <linux/amba/bus.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 29 | #include <linux/clk.h> |
Jens Axboe | bd6dee6 | 2007-10-24 09:01:09 +0200 | [diff] [blame] | 30 | #include <linux/scatterlist.h> |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 31 | #include <linux/gpio.h> |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 32 | #include <linux/of_gpio.h> |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 33 | #include <linux/regulator/consumer.h> |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 34 | #include <linux/dmaengine.h> |
| 35 | #include <linux/dma-mapping.h> |
| 36 | #include <linux/amba/mmci.h> |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 37 | #include <linux/pm_runtime.h> |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 38 | #include <linux/types.h> |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 39 | #include <linux/pinctrl/consumer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 41 | #include <asm/div64.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | #include <asm/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
| 44 | #include "mmci.h" |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 45 | #include "mmci_qcom_dml.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | |
| 47 | #define DRIVER_NAME "mmci-pl18x" |
| 48 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | static unsigned int fmax = 515633; |
| 50 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 51 | /** |
| 52 | * struct variant_data - MMCI variant-specific quirks |
| 53 | * @clkreg: default value for MCICLOCK register |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 54 | * @clkreg_enable: enable value for MMCICLOCK register |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 55 | * @clkreg_8bit_bus_enable: enable value for 8 bit bus |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 56 | * @clkreg_neg_edge_enable: enable value for inverted data/cmd output |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 57 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 58 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
| 59 | * is asserted (likewise for RX) |
| 60 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY |
| 61 | * is asserted (likewise for RX) |
Srinivas Kandagatla | ae7b006 | 2014-06-02 10:09:39 +0100 | [diff] [blame] | 62 | * @data_cmd_enable: enable value for data commands. |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 63 | * @st_sdio: enable ST specific SDIO logic |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 64 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
Srinivas Kandagatla | e17dca2 | 2014-06-02 10:09:15 +0100 | [diff] [blame] | 65 | * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 66 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
Srinivas Kandagatla | ff78323 | 2014-06-02 10:09:06 +0100 | [diff] [blame] | 67 | * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl |
| 68 | * register |
Srinivas Kandagatla | 5df014d | 2014-08-22 05:54:55 +0100 | [diff] [blame] | 69 | * @datactrl_mask_sdio: SDIO enable mask in datactrl register |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 70 | * @pwrreg_powerup: power up value for MMCIPOWER register |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 71 | * @f_max: maximum clk frequency supported by the controller. |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 72 | * @signal_direction: input/out direction of bus signals can be indicated |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 73 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 74 | * @busy_detect: true if the variant supports busy detection on DAT0. |
| 75 | * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM |
| 76 | * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register |
| 77 | * indicating that the card is busy |
| 78 | * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for |
| 79 | * getting busy end detection interrupts |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 80 | * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 81 | * @explicit_mclk_control: enable explicit mclk control in driver. |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 82 | * @qcom_fifo: enables qcom specific fifo pio read logic. |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 83 | * @qcom_dml: enables qcom specific dma glue for dma transfers. |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 84 | * @reversed_irq_handling: handle data irq before cmd irq. |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 85 | */ |
| 86 | struct variant_data { |
| 87 | unsigned int clkreg; |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 88 | unsigned int clkreg_enable; |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 89 | unsigned int clkreg_8bit_bus_enable; |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 90 | unsigned int clkreg_neg_edge_enable; |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 91 | unsigned int datalength_bits; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 92 | unsigned int fifosize; |
| 93 | unsigned int fifohalfsize; |
Srinivas Kandagatla | ae7b006 | 2014-06-02 10:09:39 +0100 | [diff] [blame] | 94 | unsigned int data_cmd_enable; |
Srinivas Kandagatla | e17dca2 | 2014-06-02 10:09:15 +0100 | [diff] [blame] | 95 | unsigned int datactrl_mask_ddrmode; |
Srinivas Kandagatla | 5df014d | 2014-08-22 05:54:55 +0100 | [diff] [blame] | 96 | unsigned int datactrl_mask_sdio; |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 97 | bool st_sdio; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 98 | bool st_clkdiv; |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 99 | bool blksz_datactrl16; |
Srinivas Kandagatla | ff78323 | 2014-06-02 10:09:06 +0100 | [diff] [blame] | 100 | bool blksz_datactrl4; |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 101 | u32 pwrreg_powerup; |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 102 | u32 f_max; |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 103 | bool signal_direction; |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 104 | bool pwrreg_clkgate; |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 105 | bool busy_detect; |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 106 | u32 busy_dpsm_flag; |
| 107 | u32 busy_detect_flag; |
| 108 | u32 busy_detect_mask; |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 109 | bool pwrreg_nopower; |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 110 | bool explicit_mclk_control; |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 111 | bool qcom_fifo; |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 112 | bool qcom_dml; |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 113 | bool reversed_irq_handling; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | static struct variant_data variant_arm = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 117 | .fifosize = 16 * 4, |
| 118 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 119 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 120 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 121 | .f_max = 100000000, |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 122 | .reversed_irq_handling = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 123 | }; |
| 124 | |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 125 | static struct variant_data variant_arm_extended_fifo = { |
| 126 | .fifosize = 128 * 4, |
| 127 | .fifohalfsize = 64 * 4, |
| 128 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 129 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 130 | .f_max = 100000000, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 131 | }; |
| 132 | |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 133 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
| 134 | .fifosize = 128 * 4, |
| 135 | .fifohalfsize = 64 * 4, |
| 136 | .clkreg_enable = MCI_ARM_HWFCEN, |
| 137 | .datalength_bits = 16, |
| 138 | .pwrreg_powerup = MCI_PWR_UP, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 139 | .f_max = 100000000, |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 140 | }; |
| 141 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 142 | static struct variant_data variant_u300 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 143 | .fifosize = 16 * 4, |
| 144 | .fifohalfsize = 8 * 4, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 145 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 146 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 147 | .datalength_bits = 16, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 148 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 149 | .st_sdio = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 150 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 151 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 152 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 153 | .pwrreg_clkgate = true, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 154 | .pwrreg_nopower = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 155 | }; |
| 156 | |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 157 | static struct variant_data variant_nomadik = { |
| 158 | .fifosize = 16 * 4, |
| 159 | .fifohalfsize = 8 * 4, |
| 160 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | f5abc76 | 2016-01-04 02:22:08 +0100 | [diff] [blame] | 161 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 162 | .datalength_bits = 24, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 163 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 164 | .st_sdio = true, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 165 | .st_clkdiv = true, |
| 166 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 167 | .f_max = 100000000, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 168 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 169 | .pwrreg_clkgate = true, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 170 | .pwrreg_nopower = true, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 171 | }; |
| 172 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 173 | static struct variant_data variant_ux500 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 174 | .fifosize = 30 * 4, |
| 175 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 176 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 177 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 178 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 179 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 180 | .datalength_bits = 24, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 181 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 182 | .st_sdio = true, |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 183 | .st_clkdiv = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 184 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 185 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 186 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 187 | .pwrreg_clkgate = true, |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 188 | .busy_detect = true, |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 189 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
| 190 | .busy_detect_flag = MCI_ST_CARDBUSY, |
| 191 | .busy_detect_mask = MCI_ST_BUSYENDMASK, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 192 | .pwrreg_nopower = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 193 | }; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 194 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 195 | static struct variant_data variant_ux500v2 = { |
| 196 | .fifosize = 30 * 4, |
| 197 | .fifohalfsize = 8 * 4, |
| 198 | .clkreg = MCI_CLK_ENABLE, |
| 199 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 200 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 201 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 202 | .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 203 | .datalength_bits = 24, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 204 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 205 | .st_sdio = true, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 206 | .st_clkdiv = true, |
| 207 | .blksz_datactrl16 = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 208 | .pwrreg_powerup = MCI_PWR_ON, |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 209 | .f_max = 100000000, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 210 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 211 | .pwrreg_clkgate = true, |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 212 | .busy_detect = true, |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 213 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
| 214 | .busy_detect_flag = MCI_ST_CARDBUSY, |
| 215 | .busy_detect_mask = MCI_ST_BUSYENDMASK, |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 216 | .pwrreg_nopower = true, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 217 | }; |
| 218 | |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 219 | static struct variant_data variant_qcom = { |
| 220 | .fifosize = 16 * 4, |
| 221 | .fifohalfsize = 8 * 4, |
| 222 | .clkreg = MCI_CLK_ENABLE, |
| 223 | .clkreg_enable = MCI_QCOM_CLK_FLOWENA | |
| 224 | MCI_QCOM_CLK_SELECT_IN_FBCLK, |
| 225 | .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, |
| 226 | .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, |
Linus Walleij | 5db3eee | 2016-10-25 11:06:05 +0200 | [diff] [blame] | 227 | .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 228 | .blksz_datactrl4 = true, |
| 229 | .datalength_bits = 24, |
| 230 | .pwrreg_powerup = MCI_PWR_UP, |
| 231 | .f_max = 208000000, |
| 232 | .explicit_mclk_control = true, |
| 233 | .qcom_fifo = true, |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 234 | .qcom_dml = true, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 235 | }; |
| 236 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 237 | /* Busy detection for the ST Micro variant */ |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 238 | static int mmci_card_busy(struct mmc_host *mmc) |
| 239 | { |
| 240 | struct mmci_host *host = mmc_priv(mmc); |
| 241 | unsigned long flags; |
| 242 | int busy = 0; |
| 243 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 244 | spin_lock_irqsave(&host->lock, flags); |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 245 | if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 246 | busy = 1; |
| 247 | spin_unlock_irqrestore(&host->lock, flags); |
| 248 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 249 | return busy; |
| 250 | } |
| 251 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 252 | /* |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 253 | * Validate mmc prerequisites |
| 254 | */ |
| 255 | static int mmci_validate_data(struct mmci_host *host, |
| 256 | struct mmc_data *data) |
| 257 | { |
| 258 | if (!data) |
| 259 | return 0; |
| 260 | |
| 261 | if (!is_power_of_2(data->blksz)) { |
| 262 | dev_err(mmc_dev(host->mmc), |
| 263 | "unsupported block size (%d bytes)\n", data->blksz); |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
Ulf Hansson | f829c04 | 2013-09-04 09:01:15 +0100 | [diff] [blame] | 270 | static void mmci_reg_delay(struct mmci_host *host) |
| 271 | { |
| 272 | /* |
| 273 | * According to the spec, at least three feedback clock cycles |
| 274 | * of max 52 MHz must pass between two writes to the MMCICLOCK reg. |
| 275 | * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. |
| 276 | * Worst delay time during card init is at 100 kHz => 30 us. |
| 277 | * Worst delay time when up and running is at 25 MHz => 120 ns. |
| 278 | */ |
| 279 | if (host->cclk < 25000000) |
| 280 | udelay(30); |
| 281 | else |
| 282 | ndelay(120); |
| 283 | } |
| 284 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 285 | /* |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 286 | * This must be called with host->lock held |
| 287 | */ |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 288 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) |
| 289 | { |
| 290 | if (host->clk_reg != clk) { |
| 291 | host->clk_reg = clk; |
| 292 | writel(clk, host->base + MMCICLOCK); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | /* |
| 297 | * This must be called with host->lock held |
| 298 | */ |
| 299 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) |
| 300 | { |
| 301 | if (host->pwr_reg != pwr) { |
| 302 | host->pwr_reg = pwr; |
| 303 | writel(pwr, host->base + MMCIPOWER); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * This must be called with host->lock held |
| 309 | */ |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 310 | static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) |
| 311 | { |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 312 | /* Keep busy mode in DPSM if enabled */ |
| 313 | datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 314 | |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 315 | if (host->datactrl_reg != datactrl) { |
| 316 | host->datactrl_reg = datactrl; |
| 317 | writel(datactrl, host->base + MMCIDATACTRL); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | /* |
| 322 | * This must be called with host->lock held |
| 323 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 324 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) |
| 325 | { |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 326 | struct variant_data *variant = host->variant; |
| 327 | u32 clk = variant->clkreg; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 328 | |
Ulf Hansson | c58a850 | 2013-05-13 15:40:03 +0100 | [diff] [blame] | 329 | /* Make sure cclk reflects the current calculated clock */ |
| 330 | host->cclk = 0; |
| 331 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 332 | if (desired) { |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 333 | if (variant->explicit_mclk_control) { |
| 334 | host->cclk = host->mclk; |
| 335 | } else if (desired >= host->mclk) { |
Linus Walleij | 991a86e | 2010-12-10 09:35:53 +0100 | [diff] [blame] | 336 | clk = MCI_CLK_BYPASS; |
Linus Walleij | 399bc48 | 2011-04-01 07:59:17 +0100 | [diff] [blame] | 337 | if (variant->st_clkdiv) |
| 338 | clk |= MCI_ST_UX500_NEG_EDGE; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 339 | host->cclk = host->mclk; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 340 | } else if (variant->st_clkdiv) { |
| 341 | /* |
| 342 | * DB8500 TRM says f = mclk / (clkdiv + 2) |
| 343 | * => clkdiv = (mclk / f) - 2 |
| 344 | * Round the divider up so we don't exceed the max |
| 345 | * frequency |
| 346 | */ |
| 347 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; |
| 348 | if (clk >= 256) |
| 349 | clk = 255; |
| 350 | host->cclk = host->mclk / (clk + 2); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 351 | } else { |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 352 | /* |
| 353 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) |
| 354 | * => clkdiv = mclk / (2 * f) - 1 |
| 355 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 356 | clk = host->mclk / (2 * desired) - 1; |
| 357 | if (clk >= 256) |
| 358 | clk = 255; |
| 359 | host->cclk = host->mclk / (2 * (clk + 1)); |
| 360 | } |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 361 | |
| 362 | clk |= variant->clkreg_enable; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 363 | clk |= MCI_CLK_ENABLE; |
| 364 | /* This hasn't proven to be worthwhile */ |
| 365 | /* clk |= MCI_CLK_PWRSAVE; */ |
| 366 | } |
| 367 | |
Ulf Hansson | c58a850 | 2013-05-13 15:40:03 +0100 | [diff] [blame] | 368 | /* Set actual clock for debug */ |
| 369 | host->mmc->actual_clock = host->cclk; |
| 370 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 371 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 372 | clk |= MCI_4BIT_BUS; |
| 373 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
Srinivas Kandagatla | e1412d8 | 2014-06-02 10:09:23 +0100 | [diff] [blame] | 374 | clk |= variant->clkreg_8bit_bus_enable; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 375 | |
Seungwon Jeon | 6dad6c9 | 2014-03-14 21:12:13 +0900 | [diff] [blame] | 376 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
| 377 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) |
Srinivas Kandagatla | e874064 | 2014-06-02 10:09:30 +0100 | [diff] [blame] | 378 | clk |= variant->clkreg_neg_edge_enable; |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 379 | |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 380 | mmci_write_clkreg(host, clk); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 381 | } |
| 382 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | static void |
| 384 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) |
| 385 | { |
| 386 | writel(0, host->base + MMCICOMMAND); |
| 387 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 388 | BUG_ON(host->data); |
| 389 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | host->mrq = NULL; |
| 391 | host->cmd = NULL; |
| 392 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | mmc_request_done(host->mmc, mrq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | } |
| 395 | |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 396 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
| 397 | { |
| 398 | void __iomem *base = host->base; |
| 399 | |
| 400 | if (host->singleirq) { |
| 401 | unsigned int mask0 = readl(base + MMCIMASK0); |
| 402 | |
| 403 | mask0 &= ~MCI_IRQ1MASK; |
| 404 | mask0 |= mask; |
| 405 | |
| 406 | writel(mask0, base + MMCIMASK0); |
| 407 | } |
| 408 | |
| 409 | writel(mask, base + MMCIMASK1); |
| 410 | } |
| 411 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | static void mmci_stop_data(struct mmci_host *host) |
| 413 | { |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 414 | mmci_write_datactrlreg(host, 0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 415 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | host->data = NULL; |
| 417 | } |
| 418 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 419 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 420 | { |
| 421 | unsigned int flags = SG_MITER_ATOMIC; |
| 422 | |
| 423 | if (data->flags & MMC_DATA_READ) |
| 424 | flags |= SG_MITER_TO_SG; |
| 425 | else |
| 426 | flags |= SG_MITER_FROM_SG; |
| 427 | |
| 428 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
| 429 | } |
| 430 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 431 | /* |
| 432 | * All the DMA operation mode stuff goes inside this ifdef. |
| 433 | * This assumes that you have a generic DMA device interface, |
| 434 | * no custom DMA interfaces are supported. |
| 435 | */ |
| 436 | #ifdef CONFIG_DMA_ENGINE |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 437 | static void mmci_dma_setup(struct mmci_host *host) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 438 | { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 439 | const char *rxname, *txname; |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 440 | struct variant_data *variant = host->variant; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 441 | |
Lee Jones | 1fd83f0 | 2013-05-03 12:51:17 +0100 | [diff] [blame] | 442 | host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); |
| 443 | host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 444 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 445 | /* initialize pre request cookie */ |
| 446 | host->next_data.cookie = 1; |
| 447 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 448 | /* |
| 449 | * If only an RX channel is specified, the driver will |
| 450 | * attempt to use it bidirectionally, however if it is |
| 451 | * is specified but cannot be located, DMA will be disabled. |
| 452 | */ |
Lee Jones | 1fd83f0 | 2013-05-03 12:51:17 +0100 | [diff] [blame] | 453 | if (host->dma_rx_channel && !host->dma_tx_channel) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 454 | host->dma_tx_channel = host->dma_rx_channel; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 455 | |
| 456 | if (host->dma_rx_channel) |
| 457 | rxname = dma_chan_name(host->dma_rx_channel); |
| 458 | else |
| 459 | rxname = "none"; |
| 460 | |
| 461 | if (host->dma_tx_channel) |
| 462 | txname = dma_chan_name(host->dma_tx_channel); |
| 463 | else |
| 464 | txname = "none"; |
| 465 | |
| 466 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", |
| 467 | rxname, txname); |
| 468 | |
| 469 | /* |
| 470 | * Limit the maximum segment size in any SG entry according to |
| 471 | * the parameters of the DMA engine device. |
| 472 | */ |
| 473 | if (host->dma_tx_channel) { |
| 474 | struct device *dev = host->dma_tx_channel->device->dev; |
| 475 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 476 | |
| 477 | if (max_seg_size < host->mmc->max_seg_size) |
| 478 | host->mmc->max_seg_size = max_seg_size; |
| 479 | } |
| 480 | if (host->dma_rx_channel) { |
| 481 | struct device *dev = host->dma_rx_channel->device->dev; |
| 482 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 483 | |
| 484 | if (max_seg_size < host->mmc->max_seg_size) |
| 485 | host->mmc->max_seg_size = max_seg_size; |
| 486 | } |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 487 | |
| 488 | if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) |
| 489 | if (dml_hw_init(host, host->mmc->parent->of_node)) |
| 490 | variant->qcom_dml = false; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | /* |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 494 | * This is used in or so inline it |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 495 | * so it can be discarded. |
| 496 | */ |
| 497 | static inline void mmci_dma_release(struct mmci_host *host) |
| 498 | { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 499 | if (host->dma_rx_channel) |
| 500 | dma_release_channel(host->dma_rx_channel); |
Ulf Hansson | 8c3a05b | 2014-05-20 06:45:54 +0200 | [diff] [blame] | 501 | if (host->dma_tx_channel) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 502 | dma_release_channel(host->dma_tx_channel); |
| 503 | host->dma_rx_channel = host->dma_tx_channel = NULL; |
| 504 | } |
| 505 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 506 | static void mmci_dma_data_error(struct mmci_host *host) |
| 507 | { |
| 508 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); |
| 509 | dmaengine_terminate_all(host->dma_current); |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 510 | host->dma_in_progress = false; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 511 | host->dma_current = NULL; |
| 512 | host->dma_desc_current = NULL; |
| 513 | host->data->host_cookie = 0; |
| 514 | } |
| 515 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 516 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 517 | { |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 518 | struct dma_chan *chan; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 519 | enum dma_data_direction dir; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 520 | |
| 521 | if (data->flags & MMC_DATA_READ) { |
| 522 | dir = DMA_FROM_DEVICE; |
| 523 | chan = host->dma_rx_channel; |
| 524 | } else { |
| 525 | dir = DMA_TO_DEVICE; |
| 526 | chan = host->dma_tx_channel; |
| 527 | } |
| 528 | |
| 529 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); |
| 530 | } |
| 531 | |
| 532 | static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) |
| 533 | { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 534 | u32 status; |
| 535 | int i; |
| 536 | |
| 537 | /* Wait up to 1ms for the DMA to complete */ |
| 538 | for (i = 0; ; i++) { |
| 539 | status = readl(host->base + MMCISTATUS); |
| 540 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) |
| 541 | break; |
| 542 | udelay(10); |
| 543 | } |
| 544 | |
| 545 | /* |
| 546 | * Check to see whether we still have some data left in the FIFO - |
| 547 | * this catches DMA controllers which are unable to monitor the |
| 548 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- |
| 549 | * contiguous buffers. On TX, we'll get a FIFO underrun error. |
| 550 | */ |
| 551 | if (status & MCI_RXDATAAVLBLMASK) { |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 552 | mmci_dma_data_error(host); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 553 | if (!data->error) |
| 554 | data->error = -EIO; |
| 555 | } |
| 556 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 557 | if (!data->host_cookie) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 558 | mmci_dma_unmap(host, data); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 559 | |
| 560 | /* |
| 561 | * Use of DMA with scatter-gather is impossible. |
| 562 | * Give up with DMA and switch back to PIO mode. |
| 563 | */ |
| 564 | if (status & MCI_RXDATAAVLBLMASK) { |
| 565 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); |
| 566 | mmci_dma_release(host); |
| 567 | } |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 568 | |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 569 | host->dma_in_progress = false; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 570 | host->dma_current = NULL; |
| 571 | host->dma_desc_current = NULL; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 574 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
| 575 | static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
| 576 | struct dma_chan **dma_chan, |
| 577 | struct dma_async_tx_descriptor **dma_desc) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 578 | { |
| 579 | struct variant_data *variant = host->variant; |
| 580 | struct dma_slave_config conf = { |
| 581 | .src_addr = host->phybase + MMCIFIFO, |
| 582 | .dst_addr = host->phybase + MMCIFIFO, |
| 583 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 584 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 585 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
| 586 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 587 | .device_fc = false, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 588 | }; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 589 | struct dma_chan *chan; |
| 590 | struct dma_device *device; |
| 591 | struct dma_async_tx_descriptor *desc; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 592 | enum dma_data_direction buffer_dirn; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 593 | int nr_sg; |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 594 | unsigned long flags = DMA_CTRL_ACK; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 595 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 596 | if (data->flags & MMC_DATA_READ) { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 597 | conf.direction = DMA_DEV_TO_MEM; |
| 598 | buffer_dirn = DMA_FROM_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 599 | chan = host->dma_rx_channel; |
| 600 | } else { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 601 | conf.direction = DMA_MEM_TO_DEV; |
| 602 | buffer_dirn = DMA_TO_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 603 | chan = host->dma_tx_channel; |
| 604 | } |
| 605 | |
| 606 | /* If there's no DMA channel, fall back to PIO */ |
| 607 | if (!chan) |
| 608 | return -EINVAL; |
| 609 | |
| 610 | /* If less than or equal to the fifo size, don't bother with DMA */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 611 | if (data->blksz * data->blocks <= variant->fifosize) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 612 | return -EINVAL; |
| 613 | |
| 614 | device = chan->device; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 615 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 616 | if (nr_sg == 0) |
| 617 | return -EINVAL; |
| 618 | |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 619 | if (host->variant->qcom_dml) |
| 620 | flags |= DMA_PREP_INTERRUPT; |
| 621 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 622 | dmaengine_slave_config(chan, &conf); |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 623 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 624 | conf.direction, flags); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 625 | if (!desc) |
| 626 | goto unmap_exit; |
| 627 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 628 | *dma_chan = chan; |
| 629 | *dma_desc = desc; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 630 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 631 | return 0; |
| 632 | |
| 633 | unmap_exit: |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 634 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 635 | return -ENOMEM; |
| 636 | } |
| 637 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 638 | static inline int mmci_dma_prep_data(struct mmci_host *host, |
| 639 | struct mmc_data *data) |
| 640 | { |
| 641 | /* Check if next job is already prepared. */ |
| 642 | if (host->dma_current && host->dma_desc_current) |
| 643 | return 0; |
| 644 | |
| 645 | /* No job were prepared thus do it now. */ |
| 646 | return __mmci_dma_prep_data(host, data, &host->dma_current, |
| 647 | &host->dma_desc_current); |
| 648 | } |
| 649 | |
| 650 | static inline int mmci_dma_prep_next(struct mmci_host *host, |
| 651 | struct mmc_data *data) |
| 652 | { |
| 653 | struct mmci_host_next *nd = &host->next_data; |
| 654 | return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); |
| 655 | } |
| 656 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 657 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 658 | { |
| 659 | int ret; |
| 660 | struct mmc_data *data = host->data; |
| 661 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 662 | ret = mmci_dma_prep_data(host, host->data); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 663 | if (ret) |
| 664 | return ret; |
| 665 | |
| 666 | /* Okay, go for it. */ |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 667 | dev_vdbg(mmc_dev(host->mmc), |
| 668 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", |
| 669 | data->sg_len, data->blksz, data->blocks, data->flags); |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 670 | host->dma_in_progress = true; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 671 | dmaengine_submit(host->dma_desc_current); |
| 672 | dma_async_issue_pending(host->dma_current); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 673 | |
Srinivas Kandagatla | 9cb1514 | 2014-07-29 03:50:30 +0100 | [diff] [blame] | 674 | if (host->variant->qcom_dml) |
| 675 | dml_start_xfer(host, data); |
| 676 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 677 | datactrl |= MCI_DPSM_DMAENABLE; |
| 678 | |
| 679 | /* Trigger the DMA transfer */ |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 680 | mmci_write_datactrlreg(host, datactrl); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 681 | |
| 682 | /* |
| 683 | * Let the MMCI say when the data is ended and it's time |
| 684 | * to fire next DMA request. When that happens, MMCI will |
| 685 | * call mmci_data_end() |
| 686 | */ |
| 687 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, |
| 688 | host->base + MMCIMASK0); |
| 689 | return 0; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 690 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 691 | |
| 692 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 693 | { |
| 694 | struct mmci_host_next *next = &host->next_data; |
| 695 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 696 | WARN_ON(data->host_cookie && data->host_cookie != next->cookie); |
| 697 | WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 698 | |
| 699 | host->dma_desc_current = next->dma_desc; |
| 700 | host->dma_current = next->dma_chan; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 701 | next->dma_desc = NULL; |
| 702 | next->dma_chan = NULL; |
| 703 | } |
| 704 | |
Linus Walleij | d3c6aac | 2016-11-23 11:02:24 +0100 | [diff] [blame] | 705 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 706 | { |
| 707 | struct mmci_host *host = mmc_priv(mmc); |
| 708 | struct mmc_data *data = mrq->data; |
| 709 | struct mmci_host_next *nd = &host->next_data; |
| 710 | |
| 711 | if (!data) |
| 712 | return; |
| 713 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 714 | BUG_ON(data->host_cookie); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 715 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 716 | if (mmci_validate_data(host, data)) |
| 717 | return; |
| 718 | |
| 719 | if (!mmci_dma_prep_next(host, data)) |
| 720 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 724 | int err) |
| 725 | { |
| 726 | struct mmci_host *host = mmc_priv(mmc); |
| 727 | struct mmc_data *data = mrq->data; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 728 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 729 | if (!data || !data->host_cookie) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 730 | return; |
| 731 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 732 | mmci_dma_unmap(host, data); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 733 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 734 | if (err) { |
| 735 | struct mmci_host_next *next = &host->next_data; |
| 736 | struct dma_chan *chan; |
| 737 | if (data->flags & MMC_DATA_READ) |
| 738 | chan = host->dma_rx_channel; |
| 739 | else |
| 740 | chan = host->dma_tx_channel; |
| 741 | dmaengine_terminate_all(chan); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 742 | |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 743 | if (host->dma_desc_current == next->dma_desc) |
| 744 | host->dma_desc_current = NULL; |
| 745 | |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 746 | if (host->dma_current == next->dma_chan) { |
| 747 | host->dma_in_progress = false; |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 748 | host->dma_current = NULL; |
Linus Walleij | e13934b | 2017-01-27 15:04:54 +0100 | [diff] [blame] | 749 | } |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 750 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 751 | next->dma_desc = NULL; |
| 752 | next->dma_chan = NULL; |
Srinivas Kandagatla | b5c16a6 | 2014-10-08 12:25:17 +0100 | [diff] [blame] | 753 | data->host_cookie = 0; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 754 | } |
| 755 | } |
| 756 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 757 | #else |
| 758 | /* Blank functions if the DMA engine is not available */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 759 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 760 | { |
| 761 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 762 | static inline void mmci_dma_setup(struct mmci_host *host) |
| 763 | { |
| 764 | } |
| 765 | |
| 766 | static inline void mmci_dma_release(struct mmci_host *host) |
| 767 | { |
| 768 | } |
| 769 | |
| 770 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 771 | { |
| 772 | } |
| 773 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 774 | static inline void mmci_dma_finalize(struct mmci_host *host, |
| 775 | struct mmc_data *data) |
| 776 | { |
| 777 | } |
| 778 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 779 | static inline void mmci_dma_data_error(struct mmci_host *host) |
| 780 | { |
| 781 | } |
| 782 | |
| 783 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 784 | { |
| 785 | return -ENOSYS; |
| 786 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 787 | |
| 788 | #define mmci_pre_request NULL |
| 789 | #define mmci_post_request NULL |
| 790 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 791 | #endif |
| 792 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
| 794 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 795 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | unsigned int datactrl, timeout, irqmask; |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 797 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 798 | void __iomem *base; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 799 | int blksz_bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 800 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 801 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 802 | data->blksz, data->blocks, data->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 803 | |
| 804 | host->data = data; |
Rabin Vincent | 528320d | 2010-07-21 12:49:49 +0100 | [diff] [blame] | 805 | host->size = data->blksz * data->blocks; |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 806 | data->bytes_xfered = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 808 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
Srinivas Kandagatla | c4a3576 | 2014-06-02 10:08:39 +0100 | [diff] [blame] | 809 | do_div(clks, NSEC_PER_SEC); |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 810 | |
| 811 | timeout = data->timeout_clks + (unsigned int)clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 812 | |
| 813 | base = host->base; |
| 814 | writel(timeout, base + MMCIDATATIMER); |
| 815 | writel(host->size, base + MMCIDATALENGTH); |
| 816 | |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 817 | blksz_bits = ffs(data->blksz) - 1; |
| 818 | BUG_ON(1 << blksz_bits != data->blksz); |
| 819 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 820 | if (variant->blksz_datactrl16) |
| 821 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); |
Srinivas Kandagatla | ff78323 | 2014-06-02 10:09:06 +0100 | [diff] [blame] | 822 | else if (variant->blksz_datactrl4) |
| 823 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 824 | else |
| 825 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 826 | |
| 827 | if (data->flags & MMC_DATA_READ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | datactrl |= MCI_DPSM_DIRECTION; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 829 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 830 | if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { |
| 831 | u32 clk; |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 832 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 833 | datactrl |= variant->datactrl_mask_sdio; |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 834 | |
Srinivas Kandagatla | c735413 | 2014-08-22 05:55:16 +0100 | [diff] [blame] | 835 | /* |
| 836 | * The ST Micro variant for SDIO small write transfers |
| 837 | * needs to have clock H/W flow control disabled, |
| 838 | * otherwise the transfer will not start. The threshold |
| 839 | * depends on the rate of MCLK. |
| 840 | */ |
| 841 | if (variant->st_sdio && data->flags & MMC_DATA_WRITE && |
| 842 | (host->size < 8 || |
| 843 | (host->size <= 8 && host->mclk > 50000000))) |
| 844 | clk = host->clk_reg & ~variant->clkreg_enable; |
| 845 | else |
| 846 | clk = host->clk_reg | variant->clkreg_enable; |
| 847 | |
| 848 | mmci_write_clkreg(host, clk); |
| 849 | } |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 850 | |
Seungwon Jeon | 6dad6c9 | 2014-03-14 21:12:13 +0900 | [diff] [blame] | 851 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
| 852 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) |
Srinivas Kandagatla | e17dca2 | 2014-06-02 10:09:15 +0100 | [diff] [blame] | 853 | datactrl |= variant->datactrl_mask_ddrmode; |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 854 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 855 | /* |
| 856 | * Attempt to use DMA operation mode, if this |
| 857 | * should fail, fall back to PIO mode |
| 858 | */ |
| 859 | if (!mmci_dma_start_data(host, datactrl)) |
| 860 | return; |
| 861 | |
| 862 | /* IRQ mode, map the SG list for CPU reading/writing */ |
| 863 | mmci_init_sg(host, data); |
| 864 | |
| 865 | if (data->flags & MMC_DATA_READ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 866 | irqmask = MCI_RXFIFOHALFFULLMASK; |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 867 | |
| 868 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 869 | * If we have less than the fifo 'half-full' threshold to |
| 870 | * transfer, trigger a PIO interrupt as soon as any data |
| 871 | * is available. |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 872 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 873 | if (host->size < variant->fifohalfsize) |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 874 | irqmask |= MCI_RXDATAAVLBLMASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | } else { |
| 876 | /* |
| 877 | * We don't actually need to include "FIFO empty" here |
| 878 | * since its implicit in "FIFO half empty". |
| 879 | */ |
| 880 | irqmask = MCI_TXFIFOHALFEMPTYMASK; |
| 881 | } |
| 882 | |
Ulf Hansson | 9cc639a | 2013-05-15 20:48:23 +0100 | [diff] [blame] | 883 | mmci_write_datactrlreg(host, datactrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 885 | mmci_set_mask1(host, irqmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | static void |
| 889 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) |
| 890 | { |
| 891 | void __iomem *base = host->base; |
| 892 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 893 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | cmd->opcode, cmd->arg, cmd->flags); |
| 895 | |
| 896 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
| 897 | writel(0, base + MMCICOMMAND); |
Srinivas Kandagatla | 6adb2a8 | 2014-06-02 10:08:57 +0100 | [diff] [blame] | 898 | mmci_reg_delay(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | } |
| 900 | |
| 901 | c |= cmd->opcode | MCI_CPSM_ENABLE; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 902 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 903 | if (cmd->flags & MMC_RSP_136) |
| 904 | c |= MCI_CPSM_LONGRSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | c |= MCI_CPSM_RESPONSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | } |
| 907 | if (/*interrupt*/0) |
| 908 | c |= MCI_CPSM_INTERRUPT; |
| 909 | |
Srinivas Kandagatla | ae7b006 | 2014-06-02 10:09:39 +0100 | [diff] [blame] | 910 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) |
| 911 | c |= host->variant->data_cmd_enable; |
| 912 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 913 | host->cmd = cmd; |
| 914 | |
| 915 | writel(cmd->arg, base + MMCIARGUMENT); |
| 916 | writel(c, base + MMCICOMMAND); |
| 917 | } |
| 918 | |
| 919 | static void |
| 920 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, |
| 921 | unsigned int status) |
| 922 | { |
Ulf Hansson | 1cb9da5 | 2014-06-12 14:42:23 +0200 | [diff] [blame] | 923 | /* Make sure we have data to handle */ |
| 924 | if (!data) |
| 925 | return; |
| 926 | |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 927 | /* First check for errors */ |
Ulf Hansson | b63038d | 2011-12-13 16:51:04 +0100 | [diff] [blame] | 928 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
| 929 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 930 | u32 remain, success; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 931 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 932 | /* Terminate the DMA transfer */ |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 933 | if (dma_inprogress(host)) { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 934 | mmci_dma_data_error(host); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 935 | mmci_dma_unmap(host, data); |
| 936 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 937 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 938 | /* |
| 939 | * Calculate how far we are into the transfer. Note that |
| 940 | * the data counter gives the number of bytes transferred |
| 941 | * on the MMC bus, not on the host side. On reads, this |
| 942 | * can be as much as a FIFO-worth of data ahead. This |
| 943 | * matters for FIFO overruns only. |
| 944 | */ |
Linus Walleij | f5a106d | 2011-01-27 17:44:34 +0100 | [diff] [blame] | 945 | remain = readl(host->base + MMCIDATACNT); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 946 | success = data->blksz * data->blocks - remain; |
| 947 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 948 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
| 949 | status, success); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 950 | if (status & MCI_DATACRCFAIL) { |
| 951 | /* Last block was not successful */ |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 952 | success -= 1; |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 953 | data->error = -EILSEQ; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 954 | } else if (status & MCI_DATATIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 955 | data->error = -ETIMEDOUT; |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 956 | } else if (status & MCI_STARTBITERR) { |
| 957 | data->error = -ECOMM; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 958 | } else if (status & MCI_TXUNDERRUN) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 959 | data->error = -EIO; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 960 | } else if (status & MCI_RXOVERRUN) { |
| 961 | if (success > host->variant->fifosize) |
| 962 | success -= host->variant->fifosize; |
| 963 | else |
| 964 | success = 0; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 965 | data->error = -EIO; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 966 | } |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 967 | data->bytes_xfered = round_down(success, data->blksz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | } |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 969 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 970 | if (status & MCI_DATABLOCKEND) |
| 971 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 972 | |
Russell King | ccff9b5 | 2011-01-30 21:03:50 +0000 | [diff] [blame] | 973 | if (status & MCI_DATAEND || data->error) { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 974 | if (dma_inprogress(host)) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 975 | mmci_dma_finalize(host, data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | mmci_stop_data(host); |
| 977 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 978 | if (!data->error) |
| 979 | /* The error clause is handled above, success! */ |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 980 | data->bytes_xfered = data->blksz * data->blocks; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 981 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 982 | if (!data->stop || host->mrq->sbc) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | mmci_request_end(host, data->mrq); |
| 984 | } else { |
| 985 | mmci_start_command(host, data->stop, 0); |
| 986 | } |
| 987 | } |
| 988 | } |
| 989 | |
| 990 | static void |
| 991 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, |
| 992 | unsigned int status) |
| 993 | { |
| 994 | void __iomem *base = host->base; |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 995 | bool sbc; |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 996 | |
| 997 | if (!cmd) |
| 998 | return; |
| 999 | |
| 1000 | sbc = (cmd == host->mrq->sbc); |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 1001 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1002 | /* |
| 1003 | * We need to be one of these interrupts to be considered worth |
| 1004 | * handling. Note that we tag on any latent IRQs postponed |
| 1005 | * due to waiting for busy status. |
| 1006 | */ |
| 1007 | if (!((status|host->busy_status) & |
| 1008 | (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) |
Ulf Hansson | ad82bfe | 2014-06-12 15:01:57 +0200 | [diff] [blame] | 1009 | return; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1010 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1011 | /* |
| 1012 | * ST Micro variant: handle busy detection. |
| 1013 | */ |
| 1014 | if (host->variant->busy_detect) { |
| 1015 | bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1016 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1017 | /* We are busy with a command, return */ |
| 1018 | if (host->busy_status && |
| 1019 | (status & host->variant->busy_detect_flag)) |
| 1020 | return; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1021 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1022 | /* |
| 1023 | * We were not busy, but we now got a busy response on |
| 1024 | * something that was not an error, and we double-check |
| 1025 | * that the special busy status bit is still set before |
| 1026 | * proceeding. |
| 1027 | */ |
| 1028 | if (!host->busy_status && busy_resp && |
| 1029 | !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && |
| 1030 | (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1031 | |
| 1032 | /* Clear the busy start IRQ */ |
| 1033 | writel(host->variant->busy_detect_mask, |
| 1034 | host->base + MMCICLEAR); |
| 1035 | |
| 1036 | /* Unmask the busy end IRQ */ |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1037 | writel(readl(base + MMCIMASK0) | |
| 1038 | host->variant->busy_detect_mask, |
| 1039 | base + MMCIMASK0); |
| 1040 | /* |
| 1041 | * Now cache the last response status code (until |
| 1042 | * the busy bit goes low), and return. |
| 1043 | */ |
| 1044 | host->busy_status = |
| 1045 | status & (MCI_CMDSENT|MCI_CMDRESPEND); |
| 1046 | return; |
| 1047 | } |
| 1048 | |
| 1049 | /* |
| 1050 | * At this point we are not busy with a command, we have |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1051 | * not received a new busy request, clear and mask the busy |
| 1052 | * end IRQ and fall through to process the IRQ. |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1053 | */ |
| 1054 | if (host->busy_status) { |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1055 | |
| 1056 | writel(host->variant->busy_detect_mask, |
| 1057 | host->base + MMCICLEAR); |
| 1058 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1059 | writel(readl(base + MMCIMASK0) & |
| 1060 | ~host->variant->busy_detect_mask, |
| 1061 | base + MMCIMASK0); |
| 1062 | host->busy_status = 0; |
| 1063 | } |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1064 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1065 | |
| 1066 | host->cmd = NULL; |
| 1067 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1068 | if (status & MCI_CMDTIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1069 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1070 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1071 | cmd->error = -EILSEQ; |
Russell King - ARM Linux | 9047b43 | 2011-01-11 16:35:56 +0000 | [diff] [blame] | 1072 | } else { |
| 1073 | cmd->resp[0] = readl(base + MMCIRESPONSE0); |
| 1074 | cmd->resp[1] = readl(base + MMCIRESPONSE1); |
| 1075 | cmd->resp[2] = readl(base + MMCIRESPONSE2); |
| 1076 | cmd->resp[3] = readl(base + MMCIRESPONSE3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1077 | } |
| 1078 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1079 | if ((!sbc && !cmd->data) || cmd->error) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 1080 | if (host->data) { |
| 1081 | /* Terminate the DMA transfer */ |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 1082 | if (dma_inprogress(host)) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 1083 | mmci_dma_data_error(host); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 1084 | mmci_dma_unmap(host, host->data); |
| 1085 | } |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 1086 | mmci_stop_data(host); |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 1087 | } |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1088 | mmci_request_end(host, host->mrq); |
| 1089 | } else if (sbc) { |
| 1090 | mmci_start_command(host, host->mrq->cmd, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
| 1092 | mmci_start_data(host, cmd->data); |
| 1093 | } |
| 1094 | } |
| 1095 | |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1096 | static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) |
| 1097 | { |
| 1098 | return remain - (readl(host->base + MMCIFIFOCNT) << 2); |
| 1099 | } |
| 1100 | |
| 1101 | static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) |
| 1102 | { |
| 1103 | /* |
| 1104 | * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses |
| 1105 | * from the fifo range should be used |
| 1106 | */ |
| 1107 | if (status & MCI_RXFIFOHALFFULL) |
| 1108 | return host->variant->fifohalfsize; |
| 1109 | else if (status & MCI_RXDATAAVLBL) |
| 1110 | return 4; |
| 1111 | |
| 1112 | return 0; |
| 1113 | } |
| 1114 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
| 1116 | { |
| 1117 | void __iomem *base = host->base; |
| 1118 | char *ptr = buffer; |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1119 | u32 status = readl(host->base + MMCISTATUS); |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 1120 | int host_remain = host->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | |
| 1122 | do { |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1123 | int count = host->get_rx_fifocnt(host, status, host_remain); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1124 | |
| 1125 | if (count > remain) |
| 1126 | count = remain; |
| 1127 | |
| 1128 | if (count <= 0) |
| 1129 | break; |
| 1130 | |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1131 | /* |
| 1132 | * SDIO especially may want to send something that is |
| 1133 | * not divisible by 4 (as opposed to card sectors |
| 1134 | * etc). Therefore make sure to always read the last bytes |
| 1135 | * while only doing full 32-bit reads towards the FIFO. |
| 1136 | */ |
| 1137 | if (unlikely(count & 0x3)) { |
| 1138 | if (count < 4) { |
| 1139 | unsigned char buf[4]; |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1140 | ioread32_rep(base + MMCIFIFO, buf, 1); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1141 | memcpy(ptr, buf, count); |
| 1142 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1143 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1144 | count &= ~0x3; |
| 1145 | } |
| 1146 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1147 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 1148 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | |
| 1150 | ptr += count; |
| 1151 | remain -= count; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 1152 | host_remain -= count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1153 | |
| 1154 | if (remain == 0) |
| 1155 | break; |
| 1156 | |
| 1157 | status = readl(base + MMCISTATUS); |
| 1158 | } while (status & MCI_RXDATAAVLBL); |
| 1159 | |
| 1160 | return ptr - buffer; |
| 1161 | } |
| 1162 | |
| 1163 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) |
| 1164 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1165 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | void __iomem *base = host->base; |
| 1167 | char *ptr = buffer; |
| 1168 | |
| 1169 | do { |
| 1170 | unsigned int count, maxcnt; |
| 1171 | |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1172 | maxcnt = status & MCI_TXFIFOEMPTY ? |
| 1173 | variant->fifosize : variant->fifohalfsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | count = min(remain, maxcnt); |
| 1175 | |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 1176 | /* |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 1177 | * SDIO especially may want to send something that is |
| 1178 | * not divisible by 4 (as opposed to card sectors |
| 1179 | * etc), and the FIFO only accept full 32-bit writes. |
| 1180 | * So compensate by adding +3 on the count, a single |
| 1181 | * byte become a 32bit write, 7 bytes will be two |
| 1182 | * 32bit writes etc. |
| 1183 | */ |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 1184 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | |
| 1186 | ptr += count; |
| 1187 | remain -= count; |
| 1188 | |
| 1189 | if (remain == 0) |
| 1190 | break; |
| 1191 | |
| 1192 | status = readl(base + MMCISTATUS); |
| 1193 | } while (status & MCI_TXFIFOHALFEMPTY); |
| 1194 | |
| 1195 | return ptr - buffer; |
| 1196 | } |
| 1197 | |
| 1198 | /* |
| 1199 | * PIO data transfer IRQ handler. |
| 1200 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1201 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1202 | { |
| 1203 | struct mmci_host *host = dev_id; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1204 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 1205 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1206 | void __iomem *base = host->base; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1207 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | u32 status; |
| 1209 | |
| 1210 | status = readl(base + MMCISTATUS); |
| 1211 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1212 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1213 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1214 | local_irq_save(flags); |
| 1215 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1217 | unsigned int remain, len; |
| 1218 | char *buffer; |
| 1219 | |
| 1220 | /* |
| 1221 | * For write, we only need to test the half-empty flag |
| 1222 | * here - if the FIFO is completely empty, then by |
| 1223 | * definition it is more than half empty. |
| 1224 | * |
| 1225 | * For read, check for data available. |
| 1226 | */ |
| 1227 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) |
| 1228 | break; |
| 1229 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1230 | if (!sg_miter_next(sg_miter)) |
| 1231 | break; |
| 1232 | |
| 1233 | buffer = sg_miter->addr; |
| 1234 | remain = sg_miter->length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | |
| 1236 | len = 0; |
| 1237 | if (status & MCI_RXACTIVE) |
| 1238 | len = mmci_pio_read(host, buffer, remain); |
| 1239 | if (status & MCI_TXACTIVE) |
| 1240 | len = mmci_pio_write(host, buffer, remain, status); |
| 1241 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1242 | sg_miter->consumed = len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1243 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1244 | host->size -= len; |
| 1245 | remain -= len; |
| 1246 | |
| 1247 | if (remain) |
| 1248 | break; |
| 1249 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1250 | status = readl(base + MMCISTATUS); |
| 1251 | } while (1); |
| 1252 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1253 | sg_miter_stop(sg_miter); |
| 1254 | |
| 1255 | local_irq_restore(flags); |
| 1256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1258 | * If we have less than the fifo 'half-full' threshold to transfer, |
| 1259 | * trigger a PIO interrupt as soon as any data is available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1260 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1261 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1262 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1263 | |
| 1264 | /* |
| 1265 | * If we run out of data, disable the data IRQs; this |
| 1266 | * prevents a race where the FIFO becomes empty before |
| 1267 | * the chip itself has disabled the data path, and |
| 1268 | * stops us racing with our data end IRQ. |
| 1269 | */ |
| 1270 | if (host->size == 0) { |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1271 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1272 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
| 1273 | } |
| 1274 | |
| 1275 | return IRQ_HANDLED; |
| 1276 | } |
| 1277 | |
| 1278 | /* |
| 1279 | * Handle completion of command and data transfers. |
| 1280 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1281 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | { |
| 1283 | struct mmci_host *host = dev_id; |
| 1284 | u32 status; |
| 1285 | int ret = 0; |
| 1286 | |
| 1287 | spin_lock(&host->lock); |
| 1288 | |
| 1289 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1290 | status = readl(host->base + MMCISTATUS); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1291 | |
| 1292 | if (host->singleirq) { |
| 1293 | if (status & readl(host->base + MMCIMASK1)) |
| 1294 | mmci_pio_irq(irq, dev_id); |
| 1295 | |
| 1296 | status &= ~MCI_IRQ1MASK; |
| 1297 | } |
| 1298 | |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1299 | /* |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1300 | * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's |
| 1301 | * enabled) in mmci_cmd_irq() function where ST Micro busy |
| 1302 | * detection variant is handled. Considering the HW seems to be |
| 1303 | * triggering the IRQ on both edges while monitoring DAT0 for |
| 1304 | * busy completion and that same status bit is used to monitor |
| 1305 | * start and end of busy detection, special care must be taken |
| 1306 | * to make sure that both start and end interrupts are always |
| 1307 | * cleared one after the other. |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1308 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | status &= readl(host->base + MMCIMASK0); |
Jean-Nicolas Graux | 5cad24d | 2017-02-07 12:12:41 +0100 | [diff] [blame] | 1310 | if (host->variant->busy_detect) |
| 1311 | writel(status & ~host->variant->busy_detect_mask, |
| 1312 | host->base + MMCICLEAR); |
| 1313 | else |
| 1314 | writel(status, host->base + MMCICLEAR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1315 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1316 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | |
Ulf Hansson | 7878289 | 2014-06-13 13:21:38 +0200 | [diff] [blame] | 1318 | if (host->variant->reversed_irq_handling) { |
| 1319 | mmci_data_irq(host, host->data, status); |
| 1320 | mmci_cmd_irq(host, host->cmd, status); |
| 1321 | } else { |
| 1322 | mmci_cmd_irq(host, host->cmd, status); |
| 1323 | mmci_data_irq(host, host->data, status); |
| 1324 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1325 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1326 | /* |
| 1327 | * Don't poll for busy completion in irq context. |
| 1328 | */ |
| 1329 | if (host->variant->busy_detect && host->busy_status) |
| 1330 | status &= ~host->variant->busy_detect_flag; |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | ret = 1; |
| 1333 | } while (status); |
| 1334 | |
| 1335 | spin_unlock(&host->lock); |
| 1336 | |
| 1337 | return IRQ_RETVAL(ret); |
| 1338 | } |
| 1339 | |
| 1340 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1341 | { |
| 1342 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1343 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | |
| 1345 | WARN_ON(host->mrq != NULL); |
| 1346 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 1347 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
| 1348 | if (mrq->cmd->error) { |
Pierre Ossman | 255d01a | 2007-07-24 20:38:53 +0200 | [diff] [blame] | 1349 | mmc_request_done(mmc, mrq); |
| 1350 | return; |
| 1351 | } |
| 1352 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1353 | spin_lock_irqsave(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | |
| 1355 | host->mrq = mrq; |
| 1356 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1357 | if (mrq->data) |
| 1358 | mmci_get_next_data(host, mrq->data); |
| 1359 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1360 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
| 1361 | mmci_start_data(host, mrq->data); |
| 1362 | |
Ulf Hansson | 024629c | 2013-05-13 15:40:56 +0100 | [diff] [blame] | 1363 | if (mrq->sbc) |
| 1364 | mmci_start_command(host, mrq->sbc, 0); |
| 1365 | else |
| 1366 | mmci_start_command(host, mrq->cmd, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1367 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1368 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1369 | } |
| 1370 | |
| 1371 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1372 | { |
| 1373 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1374 | struct variant_data *variant = host->variant; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1375 | u32 pwr = 0; |
| 1376 | unsigned long flags; |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1377 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | |
Ulf Hansson | bc52181 | 2011-12-13 16:57:55 +0100 | [diff] [blame] | 1379 | if (host->plat->ios_handler && |
| 1380 | host->plat->ios_handler(mmc_dev(mmc), ios)) |
| 1381 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); |
| 1382 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | switch (ios->power_mode) { |
| 1384 | case MMC_POWER_OFF: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1385 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1386 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1387 | |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1388 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1389 | regulator_disable(mmc->supply.vqmmc); |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1390 | host->vqmmc_enabled = false; |
| 1391 | } |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1392 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1393 | break; |
| 1394 | case MMC_POWER_UP: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1395 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1396 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
| 1397 | |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1398 | /* |
| 1399 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP |
| 1400 | * and instead uses MCI_PWR_ON so apply whatever value is |
| 1401 | * configured in the variant data. |
| 1402 | */ |
| 1403 | pwr |= variant->pwrreg_powerup; |
| 1404 | |
| 1405 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | case MMC_POWER_ON: |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1407 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1408 | ret = regulator_enable(mmc->supply.vqmmc); |
| 1409 | if (ret < 0) |
| 1410 | dev_err(mmc_dev(mmc), |
| 1411 | "failed to enable vqmmc regulator\n"); |
Ulf Hansson | 7c0136e | 2013-05-14 13:53:10 +0100 | [diff] [blame] | 1412 | else |
| 1413 | host->vqmmc_enabled = true; |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1414 | } |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1415 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | pwr |= MCI_PWR_ON; |
| 1417 | break; |
| 1418 | } |
| 1419 | |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1420 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
| 1421 | /* |
| 1422 | * The ST Micro variant has some additional bits |
| 1423 | * indicating signal direction for the signals in |
| 1424 | * the SD/MMC bus and feedback-clock usage. |
| 1425 | */ |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1426 | pwr |= host->pwr_reg_add; |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1427 | |
| 1428 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1429 | pwr &= ~MCI_ST_DATA74DIREN; |
| 1430 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1431 | pwr &= (~MCI_ST_DATA74DIREN & |
| 1432 | ~MCI_ST_DATA31DIREN & |
| 1433 | ~MCI_ST_DATA2DIREN); |
| 1434 | } |
| 1435 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1436 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
Linus Walleij | f17a1f0 | 2009-08-04 01:01:02 +0100 | [diff] [blame] | 1437 | if (host->hw_designer != AMBA_VENDOR_ST) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1438 | pwr |= MCI_ROD; |
| 1439 | else { |
| 1440 | /* |
| 1441 | * The ST Micro variant use the ROD bit for something |
| 1442 | * else and only has OD (Open Drain). |
| 1443 | */ |
| 1444 | pwr |= MCI_OD; |
| 1445 | } |
| 1446 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1447 | |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 1448 | /* |
| 1449 | * If clock = 0 and the variant requires the MMCIPOWER to be used for |
| 1450 | * gating the clock, the MCI_PWR_ON bit is cleared. |
| 1451 | */ |
| 1452 | if (!ios->clock && variant->pwrreg_clkgate) |
| 1453 | pwr &= ~MCI_PWR_ON; |
| 1454 | |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1455 | if (host->variant->explicit_mclk_control && |
| 1456 | ios->clock != host->clock_cache) { |
| 1457 | ret = clk_set_rate(host->clk, ios->clock); |
| 1458 | if (ret < 0) |
| 1459 | dev_err(mmc_dev(host->mmc), |
| 1460 | "Error setting clock rate (%d)\n", ret); |
| 1461 | else |
| 1462 | host->mclk = clk_get_rate(host->clk); |
| 1463 | } |
| 1464 | host->clock_cache = ios->clock; |
| 1465 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1466 | spin_lock_irqsave(&host->lock, flags); |
| 1467 | |
| 1468 | mmci_set_clkreg(host, ios->clock); |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 1469 | mmci_write_pwrreg(host, pwr); |
Ulf Hansson | f829c04 | 2013-09-04 09:01:15 +0100 | [diff] [blame] | 1470 | mmci_reg_delay(host); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1471 | |
| 1472 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1473 | } |
| 1474 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1475 | static int mmci_get_cd(struct mmc_host *mmc) |
| 1476 | { |
| 1477 | struct mmci_host *host = mmc_priv(mmc); |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1478 | struct mmci_platform_data *plat = host->plat; |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1479 | unsigned int status = mmc_gpio_get_cd(mmc); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1480 | |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1481 | if (status == -ENOSYS) { |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1482 | if (!plat->status) |
| 1483 | return 1; /* Assume always present */ |
| 1484 | |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1485 | status = plat->status(mmc_dev(host->mmc)); |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1486 | } |
Russell King | 74bc809 | 2010-07-29 15:58:59 +0100 | [diff] [blame] | 1487 | return status; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1488 | } |
| 1489 | |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1490 | static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1491 | { |
| 1492 | int ret = 0; |
| 1493 | |
| 1494 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1495 | |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1496 | switch (ios->signal_voltage) { |
| 1497 | case MMC_SIGNAL_VOLTAGE_330: |
| 1498 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1499 | 2700000, 3600000); |
| 1500 | break; |
| 1501 | case MMC_SIGNAL_VOLTAGE_180: |
| 1502 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1503 | 1700000, 1950000); |
| 1504 | break; |
| 1505 | case MMC_SIGNAL_VOLTAGE_120: |
| 1506 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
| 1507 | 1100000, 1300000); |
| 1508 | break; |
| 1509 | } |
| 1510 | |
| 1511 | if (ret) |
| 1512 | dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1513 | } |
| 1514 | |
| 1515 | return ret; |
| 1516 | } |
| 1517 | |
Ulf Hansson | 0125962 | 2013-05-15 20:53:22 +0100 | [diff] [blame] | 1518 | static struct mmc_host_ops mmci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1519 | .request = mmci_request, |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1520 | .pre_req = mmci_pre_request, |
| 1521 | .post_req = mmci_post_request, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1522 | .set_ios = mmci_set_ios, |
Ulf Hansson | d276209 | 2014-03-17 13:56:19 +0100 | [diff] [blame] | 1523 | .get_ro = mmc_gpio_get_ro, |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1524 | .get_cd = mmci_get_cd, |
Ulf Hansson | 0f3ed7f | 2013-05-15 20:47:33 +0100 | [diff] [blame] | 1525 | .start_signal_voltage_switch = mmci_sig_volt_switch, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | }; |
| 1527 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1528 | static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) |
| 1529 | { |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1530 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1531 | int ret = mmc_of_parse(mmc); |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1532 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1533 | if (ret) |
| 1534 | return ret; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1535 | |
Ulf Hansson | 4593df2 | 2014-03-21 10:13:05 +0100 | [diff] [blame] | 1536 | if (of_get_property(np, "st,sig-dir-dat0", NULL)) |
| 1537 | host->pwr_reg_add |= MCI_ST_DATA0DIREN; |
| 1538 | if (of_get_property(np, "st,sig-dir-dat2", NULL)) |
| 1539 | host->pwr_reg_add |= MCI_ST_DATA2DIREN; |
| 1540 | if (of_get_property(np, "st,sig-dir-dat31", NULL)) |
| 1541 | host->pwr_reg_add |= MCI_ST_DATA31DIREN; |
| 1542 | if (of_get_property(np, "st,sig-dir-dat74", NULL)) |
| 1543 | host->pwr_reg_add |= MCI_ST_DATA74DIREN; |
| 1544 | if (of_get_property(np, "st,sig-dir-cmd", NULL)) |
| 1545 | host->pwr_reg_add |= MCI_ST_CMDDIREN; |
| 1546 | if (of_get_property(np, "st,sig-pin-fbclk", NULL)) |
| 1547 | host->pwr_reg_add |= MCI_ST_FBCLKEN; |
| 1548 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1549 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1550 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1551 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1552 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1553 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1554 | return 0; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1555 | } |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1556 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1557 | static int mmci_probe(struct amba_device *dev, |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 1558 | const struct amba_id *id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | { |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 1560 | struct mmci_platform_data *plat = dev->dev.platform_data; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1561 | struct device_node *np = dev->dev.of_node; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1562 | struct variant_data *variant = id->data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | struct mmci_host *host; |
| 1564 | struct mmc_host *mmc; |
| 1565 | int ret; |
| 1566 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1567 | /* Must have platform data or Device Tree. */ |
| 1568 | if (!plat && !np) { |
| 1569 | dev_err(&dev->dev, "No plat data or DT found\n"); |
| 1570 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1571 | } |
| 1572 | |
Lee Jones | b9b5291 | 2012-06-12 10:49:51 +0100 | [diff] [blame] | 1573 | if (!plat) { |
| 1574 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); |
| 1575 | if (!plat) |
| 1576 | return -ENOMEM; |
| 1577 | } |
| 1578 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1579 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1580 | if (!mmc) |
| 1581 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1582 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1583 | ret = mmci_of_parse(np, mmc); |
| 1584 | if (ret) |
| 1585 | goto host_free; |
| 1586 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1587 | host = mmc_priv(mmc); |
Rabin Vincent | 4ea580f | 2009-04-17 08:44:19 +0530 | [diff] [blame] | 1588 | host->mmc = mmc; |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1589 | |
| 1590 | host->hw_designer = amba_manf(dev); |
| 1591 | host->hw_revision = amba_rev(dev); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1592 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 1593 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1594 | |
Ulf Hansson | 665ba56 | 2013-05-13 15:39:17 +0100 | [diff] [blame] | 1595 | host->clk = devm_clk_get(&dev->dev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1596 | if (IS_ERR(host->clk)) { |
| 1597 | ret = PTR_ERR(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | goto host_free; |
| 1599 | } |
| 1600 | |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1601 | ret = clk_prepare_enable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1602 | if (ret) |
Ulf Hansson | 665ba56 | 2013-05-13 15:39:17 +0100 | [diff] [blame] | 1603 | goto host_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | |
Srinivas Kandagatla | 9c34b73 | 2014-06-02 10:10:04 +0100 | [diff] [blame] | 1605 | if (variant->qcom_fifo) |
| 1606 | host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; |
| 1607 | else |
| 1608 | host->get_rx_fifocnt = mmci_get_rx_fifocnt; |
| 1609 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1610 | host->plat = plat; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1611 | host->variant = variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1612 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1613 | /* |
| 1614 | * According to the spec, mclk is max 100 MHz, |
| 1615 | * so we try to adjust the clock down to this, |
| 1616 | * (if possible). |
| 1617 | */ |
Srinivas Kandagatla | dc6500b | 2014-06-02 10:09:47 +0100 | [diff] [blame] | 1618 | if (host->mclk > variant->f_max) { |
| 1619 | ret = clk_set_rate(host->clk, variant->f_max); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1620 | if (ret < 0) |
| 1621 | goto clk_disable; |
| 1622 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1623 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 1624 | host->mclk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1625 | } |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1626 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1627 | host->phybase = dev->res.start; |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1628 | host->base = devm_ioremap_resource(&dev->dev, &dev->res); |
| 1629 | if (IS_ERR(host->base)) { |
| 1630 | ret = PTR_ERR(host->base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1631 | goto clk_disable; |
| 1632 | } |
| 1633 | |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1634 | /* |
| 1635 | * The ARM and ST versions of the block have slightly different |
| 1636 | * clock divider equations which means that the minimum divider |
| 1637 | * differs too. |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1638 | * on Qualcomm like controllers get the nearest minimum clock to 100Khz |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1639 | */ |
| 1640 | if (variant->st_clkdiv) |
| 1641 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1642 | else if (variant->explicit_mclk_control) |
| 1643 | mmc->f_min = clk_round_rate(host->clk, 100000); |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1644 | else |
| 1645 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1646 | /* |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1647 | * If no maximum operating frequency is supplied, fall back to use |
| 1648 | * the module parameter, which has a (low) default value in case it |
| 1649 | * is not specified. Either value must not exceed the clock rate into |
Ulf Hansson | 5080a08 | 2014-03-21 10:46:39 +0100 | [diff] [blame] | 1650 | * the block, of course. |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1651 | */ |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1652 | if (mmc->f_max) |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1653 | mmc->f_max = variant->explicit_mclk_control ? |
| 1654 | min(variant->f_max, mmc->f_max) : |
| 1655 | min(host->mclk, mmc->f_max); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1656 | else |
Srinivas Kandagatla | 3f4e6f7 | 2014-06-02 10:09:55 +0100 | [diff] [blame] | 1657 | mmc->f_max = variant->explicit_mclk_control ? |
| 1658 | fmax : min(host->mclk, fmax); |
| 1659 | |
| 1660 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1661 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
| 1662 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1663 | /* Get regulators and the supported OCR mask */ |
Bjorn Andersson | 9369c97 | 2015-03-24 18:39:49 -0700 | [diff] [blame] | 1664 | ret = mmc_regulator_get_supply(mmc); |
| 1665 | if (ret == -EPROBE_DEFER) |
| 1666 | goto clk_disable; |
| 1667 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1668 | if (!mmc->ocr_avail) |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 1669 | mmc->ocr_avail = plat->ocr_mask; |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1670 | else if (plat->ocr_mask) |
| 1671 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); |
| 1672 | |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1673 | /* DT takes precedence over platform data. */ |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1674 | if (!np) { |
| 1675 | if (!plat->cd_invert) |
| 1676 | mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; |
| 1677 | mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; |
| 1678 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1679 | |
Ulf Hansson | 9dd8a8b | 2014-03-19 13:54:18 +0100 | [diff] [blame] | 1680 | /* We support these capabilities. */ |
| 1681 | mmc->caps |= MMC_CAP_CMD23; |
| 1682 | |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1683 | /* |
| 1684 | * Enable busy detection. |
| 1685 | */ |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1686 | if (variant->busy_detect) { |
| 1687 | mmci_ops.card_busy = mmci_card_busy; |
Linus Walleij | 49adc0c | 2016-10-25 11:06:06 +0200 | [diff] [blame] | 1688 | /* |
| 1689 | * Not all variants have a flag to enable busy detection |
| 1690 | * in the DPSM, but if they do, set it here. |
| 1691 | */ |
| 1692 | if (variant->busy_dpsm_flag) |
| 1693 | mmci_write_datactrlreg(host, |
| 1694 | host->variant->busy_dpsm_flag); |
Ulf Hansson | 8d94b54 | 2014-01-13 16:49:31 +0100 | [diff] [blame] | 1695 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; |
| 1696 | mmc->max_busy_timeout = 0; |
| 1697 | } |
| 1698 | |
| 1699 | mmc->ops = &mmci_ops; |
| 1700 | |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1701 | /* We support these PM capabilities. */ |
Ulf Hansson | 78f87df | 2014-03-17 15:53:07 +0100 | [diff] [blame] | 1702 | mmc->pm_caps |= MMC_PM_KEEP_POWER; |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1703 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | /* |
| 1705 | * We can do SGIO |
| 1706 | */ |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 1707 | mmc->max_segs = NR_SG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1708 | |
| 1709 | /* |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1710 | * Since only a certain number of bits are valid in the data length |
| 1711 | * register, we must ensure that we don't exceed 2^num-1 bytes in a |
| 1712 | * single request. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | */ |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1714 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1715 | |
| 1716 | /* |
| 1717 | * Set the maximum segment size. Since we aren't doing DMA |
| 1718 | * (yet) we are only limited by the data length register. |
| 1719 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1720 | mmc->max_seg_size = mmc->max_req_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1722 | /* |
| 1723 | * Block size can be up to 2048 bytes, but must be a power of two. |
| 1724 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1725 | mmc->max_blk_size = 1 << 11; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1726 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1727 | /* |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1728 | * Limit the number of blocks transferred so that we don't overflow |
| 1729 | * the maximum request size. |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1730 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1731 | mmc->max_blk_count = mmc->max_req_size >> 11; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1732 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1733 | spin_lock_init(&host->lock); |
| 1734 | |
| 1735 | writel(0, host->base + MMCIMASK0); |
| 1736 | writel(0, host->base + MMCIMASK1); |
| 1737 | writel(0xfff, host->base + MMCICLEAR); |
| 1738 | |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1739 | /* |
| 1740 | * If: |
| 1741 | * - not using DT but using a descriptor table, or |
| 1742 | * - using a table of descriptors ALONGSIDE DT, or |
| 1743 | * look up these descriptors named "cd" and "wp" right here, fail |
| 1744 | * silently of these do not exist and proceed to try platform data |
| 1745 | */ |
| 1746 | if (!np) { |
Linus Walleij | 89168b4 | 2014-10-02 09:08:46 +0200 | [diff] [blame] | 1747 | ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1748 | if (ret < 0) { |
| 1749 | if (ret == -EPROBE_DEFER) |
| 1750 | goto clk_disable; |
| 1751 | else if (gpio_is_valid(plat->gpio_cd)) { |
| 1752 | ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); |
| 1753 | if (ret) |
| 1754 | goto clk_disable; |
| 1755 | } |
| 1756 | } |
| 1757 | |
Linus Walleij | 89168b4 | 2014-10-02 09:08:46 +0200 | [diff] [blame] | 1758 | ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); |
Linus Walleij | ce437aa | 2014-08-27 15:13:54 +0200 | [diff] [blame] | 1759 | if (ret < 0) { |
| 1760 | if (ret == -EPROBE_DEFER) |
| 1761 | goto clk_disable; |
| 1762 | else if (gpio_is_valid(plat->gpio_wp)) { |
| 1763 | ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); |
| 1764 | if (ret) |
| 1765 | goto clk_disable; |
| 1766 | } |
| 1767 | } |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1768 | } |
| 1769 | |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1770 | ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, |
| 1771 | DRIVER_NAME " (cmd)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | if (ret) |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1773 | goto clk_disable; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1774 | |
Russell King | dfb85185 | 2012-05-03 11:33:15 +0100 | [diff] [blame] | 1775 | if (!dev->irq[1]) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1776 | host->singleirq = true; |
| 1777 | else { |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1778 | ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, |
| 1779 | IRQF_SHARED, DRIVER_NAME " (pio)", host); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1780 | if (ret) |
Ulf Hansson | ef28998 | 2014-03-17 13:56:32 +0100 | [diff] [blame] | 1781 | goto clk_disable; |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1782 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1783 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1784 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1785 | |
| 1786 | amba_set_drvdata(dev, mmc); |
| 1787 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1788 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
| 1789 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), |
| 1790 | amba_rev(dev), (unsigned long long)dev->res.start, |
| 1791 | dev->irq[0], dev->irq[1]); |
| 1792 | |
| 1793 | mmci_dma_setup(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1794 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1795 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
| 1796 | pm_runtime_use_autosuspend(&dev->dev); |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1797 | |
Russell King | 8c11a94 | 2010-12-28 19:40:40 +0000 | [diff] [blame] | 1798 | mmc_add_host(mmc); |
| 1799 | |
Ulf Hansson | 6f2d3c8 | 2014-12-11 14:35:55 +0100 | [diff] [blame] | 1800 | pm_runtime_put(&dev->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1801 | return 0; |
| 1802 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1803 | clk_disable: |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1804 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1805 | host_free: |
| 1806 | mmc_free_host(mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1807 | return ret; |
| 1808 | } |
| 1809 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1810 | static int mmci_remove(struct amba_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1811 | { |
| 1812 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 1813 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1814 | if (mmc) { |
| 1815 | struct mmci_host *host = mmc_priv(mmc); |
| 1816 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1817 | /* |
| 1818 | * Undo pm_runtime_put() in probe. We use the _sync |
| 1819 | * version here so that we can access the primecell. |
| 1820 | */ |
| 1821 | pm_runtime_get_sync(&dev->dev); |
| 1822 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1823 | mmc_remove_host(mmc); |
| 1824 | |
| 1825 | writel(0, host->base + MMCIMASK0); |
| 1826 | writel(0, host->base + MMCIMASK1); |
| 1827 | |
| 1828 | writel(0, host->base + MMCICOMMAND); |
| 1829 | writel(0, host->base + MMCIDATACTRL); |
| 1830 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1831 | mmci_dma_release(host); |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1832 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1833 | mmc_free_host(mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1834 | } |
| 1835 | |
| 1836 | return 0; |
| 1837 | } |
| 1838 | |
Ulf Hansson | 571dce4 | 2014-01-23 00:38:00 +0100 | [diff] [blame] | 1839 | #ifdef CONFIG_PM |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1840 | static void mmci_save(struct mmci_host *host) |
| 1841 | { |
| 1842 | unsigned long flags; |
| 1843 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1844 | spin_lock_irqsave(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1845 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1846 | writel(0, host->base + MMCIMASK0); |
| 1847 | if (host->variant->pwrreg_nopower) { |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1848 | writel(0, host->base + MMCIDATACTRL); |
| 1849 | writel(0, host->base + MMCIPOWER); |
| 1850 | writel(0, host->base + MMCICLOCK); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1851 | } |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1852 | mmci_reg_delay(host); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1853 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1854 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1855 | } |
| 1856 | |
| 1857 | static void mmci_restore(struct mmci_host *host) |
| 1858 | { |
| 1859 | unsigned long flags; |
| 1860 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1861 | spin_lock_irqsave(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1862 | |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1863 | if (host->variant->pwrreg_nopower) { |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1864 | writel(host->clk_reg, host->base + MMCICLOCK); |
| 1865 | writel(host->datactrl_reg, host->base + MMCIDATACTRL); |
| 1866 | writel(host->pwr_reg, host->base + MMCIPOWER); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1867 | } |
Ulf Hansson | 42dcc89a | 2014-01-23 00:19:38 +0100 | [diff] [blame] | 1868 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
| 1869 | mmci_reg_delay(host); |
| 1870 | |
| 1871 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1872 | } |
| 1873 | |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1874 | static int mmci_runtime_suspend(struct device *dev) |
| 1875 | { |
| 1876 | struct amba_device *adev = to_amba_device(dev); |
| 1877 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1878 | |
| 1879 | if (mmc) { |
| 1880 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | e36bd9c6 | 2013-09-04 09:00:37 +0100 | [diff] [blame] | 1881 | pinctrl_pm_select_sleep_state(dev); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1882 | mmci_save(host); |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1883 | clk_disable_unprepare(host->clk); |
| 1884 | } |
| 1885 | |
| 1886 | return 0; |
| 1887 | } |
| 1888 | |
| 1889 | static int mmci_runtime_resume(struct device *dev) |
| 1890 | { |
| 1891 | struct amba_device *adev = to_amba_device(dev); |
| 1892 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1893 | |
| 1894 | if (mmc) { |
| 1895 | struct mmci_host *host = mmc_priv(mmc); |
| 1896 | clk_prepare_enable(host->clk); |
Ulf Hansson | 1ff4443 | 2013-09-04 09:05:17 +0100 | [diff] [blame] | 1897 | mmci_restore(host); |
Ulf Hansson | e36bd9c6 | 2013-09-04 09:00:37 +0100 | [diff] [blame] | 1898 | pinctrl_pm_select_default_state(dev); |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1899 | } |
| 1900 | |
| 1901 | return 0; |
| 1902 | } |
| 1903 | #endif |
| 1904 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1905 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
Ulf Hansson | f3737fa | 2014-01-23 01:11:33 +0100 | [diff] [blame] | 1906 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
| 1907 | pm_runtime_force_resume) |
Rafael J. Wysocki | 6ed23b8 | 2014-12-04 00:34:11 +0100 | [diff] [blame] | 1908 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1909 | }; |
| 1910 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1911 | static struct amba_id mmci_ids[] = { |
| 1912 | { |
| 1913 | .id = 0x00041180, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1914 | .mask = 0xff0fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1915 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1916 | }, |
| 1917 | { |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1918 | .id = 0x01041180, |
| 1919 | .mask = 0xff0fffff, |
| 1920 | .data = &variant_arm_extended_fifo, |
| 1921 | }, |
| 1922 | { |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 1923 | .id = 0x02041180, |
| 1924 | .mask = 0xff0fffff, |
| 1925 | .data = &variant_arm_extended_fifo_hwfc, |
| 1926 | }, |
| 1927 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1928 | .id = 0x00041181, |
| 1929 | .mask = 0x000fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1930 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1931 | }, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1932 | /* ST Micro variants */ |
| 1933 | { |
| 1934 | .id = 0x00180180, |
| 1935 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1936 | .data = &variant_u300, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1937 | }, |
| 1938 | { |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 1939 | .id = 0x10180180, |
| 1940 | .mask = 0xf0ffffff, |
| 1941 | .data = &variant_nomadik, |
| 1942 | }, |
| 1943 | { |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1944 | .id = 0x00280180, |
| 1945 | .mask = 0x00ffffff, |
Linus Walleij | 0bcb7ef | 2016-01-04 02:21:55 +0100 | [diff] [blame] | 1946 | .data = &variant_nomadik, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1947 | }, |
| 1948 | { |
| 1949 | .id = 0x00480180, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1950 | .mask = 0xf0ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1951 | .data = &variant_ux500, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1952 | }, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1953 | { |
| 1954 | .id = 0x10480180, |
| 1955 | .mask = 0xf0ffffff, |
| 1956 | .data = &variant_ux500v2, |
| 1957 | }, |
Srinivas Kandagatla | 55b604a | 2014-06-02 10:10:13 +0100 | [diff] [blame] | 1958 | /* Qualcomm variants */ |
| 1959 | { |
| 1960 | .id = 0x00051180, |
| 1961 | .mask = 0x000fffff, |
| 1962 | .data = &variant_qcom, |
| 1963 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1964 | { 0, 0 }, |
| 1965 | }; |
| 1966 | |
Dave Martin | 9f99835 | 2011-10-05 15:15:21 +0100 | [diff] [blame] | 1967 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
| 1968 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1969 | static struct amba_driver mmci_driver = { |
| 1970 | .drv = { |
| 1971 | .name = DRIVER_NAME, |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1972 | .pm = &mmci_dev_pm_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1973 | }, |
| 1974 | .probe = mmci_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 1975 | .remove = mmci_remove, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1976 | .id_table = mmci_ids, |
| 1977 | }; |
| 1978 | |
viresh kumar | 9e5ed09 | 2012-03-15 10:40:38 +0100 | [diff] [blame] | 1979 | module_amba_driver(mmci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1980 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1981 | module_param(fmax, uint, 0444); |
| 1982 | |
| 1983 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); |
| 1984 | MODULE_LICENSE("GPL"); |