blob: 0659db3747312baf2b4a558e066a1d177d1664e6 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00003 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00004 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Arun Chandran92980402014-10-10 12:31:24 +01005 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08007 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07008 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01009 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010010 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020011 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010012 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000013 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000014 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000015 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000016 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000017 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010018 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000019 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010020 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000021 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010022 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000023 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070024 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000025 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000026 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070027 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010028 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010029 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000030 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070031 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010032 select GENERIC_IRQ_PROBE
33 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010034 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070035 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010036 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000037 select GENERIC_STRNCPY_FROM_USER
38 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010040 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010041 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010042 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010043 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010044 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080045 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000046 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000047 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010048 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070049 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010050 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010051 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010052 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070053 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070054 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010055 select HAVE_DMA_API_DEBUG
56 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000057 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010058 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000059 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010060 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090061 select HAVE_FUNCTION_TRACER
62 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010063 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010064 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010065 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000066 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010067 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010068 select HAVE_PERF_REGS
69 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070070 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010071 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010073 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010074 select NO_BOOTMEM
75 select OF
76 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010077 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010078 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000079 select POWER_RESET
80 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010081 select RTC_LIB
82 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070083 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070084 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010085 help
86 ARM 64-bit (AArch64) Linux support.
87
88config 64BIT
89 def_bool y
90
91config ARCH_PHYS_ADDR_T_64BIT
92 def_bool y
93
94config MMU
95 def_bool y
96
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070097config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010098 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010099
100config STACKTRACE_SUPPORT
101 def_bool y
102
103config LOCKDEP_SUPPORT
104 def_bool y
105
106config TRACE_IRQFLAGS_SUPPORT
107 def_bool y
108
Will Deaconc209f792014-03-14 17:47:05 +0000109config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100110 def_bool y
111
112config GENERIC_HWEIGHT
113 def_bool y
114
115config GENERIC_CSUM
116 def_bool y
117
118config GENERIC_CALIBRATE_DELAY
119 def_bool y
120
Catalin Marinas19e76402014-02-27 12:09:22 +0000121config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100122 def_bool y
123
Steve Capper29e56942014-10-09 15:29:25 -0700124config HAVE_GENERIC_RCU_GUP
125 def_bool y
126
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100127config ARCH_DMA_ADDR_T_64BIT
128 def_bool y
129
130config NEED_DMA_MAP_STATE
131 def_bool y
132
133config NEED_SG_DMA_LENGTH
134 def_bool y
135
136config SWIOTLB
137 def_bool y
138
139config IOMMU_HELPER
140 def_bool SWIOTLB
141
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100142config KERNEL_MODE_NEON
143 def_bool y
144
Rob Herring92cc15f2014-04-18 17:19:59 -0500145config FIX_EARLYCON_MEM
146 def_bool y
147
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100148source "init/Kconfig"
149
150source "kernel/Kconfig.freezer"
151
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100152menu "Platform selection"
153
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900154config ARCH_EXYNOS
155 bool
156 help
157 This enables support for Samsung Exynos SoC family
158
159config ARCH_EXYNOS7
160 bool "ARMv8 based Samsung Exynos7"
161 select ARCH_EXYNOS
162 select COMMON_CLK_SAMSUNG
163 select HAVE_S3C2410_WATCHDOG if WATCHDOG
164 select HAVE_S3C_RTC if RTC_CLASS
165 select PINCTRL
166 select PINCTRL_EXYNOS
167
168 help
169 This enables support for Samsung Exynos7 SoC family
170
Olof Johansson5118a6a2015-01-27 16:19:11 -0800171config ARCH_FSL_LS2085A
172 bool "Freescale LS2085A SOC"
173 help
174 This enables support for Freescale LS2085A SOC.
175
Eddie Huang4727a6f2015-12-01 10:14:00 +0100176config ARCH_MEDIATEK
177 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
178 select ARM_GIC
179 help
180 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
181
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700182config ARCH_SEATTLE
183 bool "AMD Seattle SoC Family"
184 help
185 This enables support for AMD Seattle SOC Family
186
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700187config ARCH_TEGRA
188 bool "NVIDIA Tegra SoC Family"
189 select ARCH_HAS_RESET_CONTROLLER
190 select ARCH_REQUIRE_GPIOLIB
191 select CLKDEV_LOOKUP
192 select CLKSRC_MMIO
193 select CLKSRC_OF
194 select GENERIC_CLOCKEVENTS
195 select HAVE_CLK
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700196 select PINCTRL
197 select RESET_CONTROLLER
198 help
199 This enables support for the NVIDIA Tegra SoC family.
200
201config ARCH_TEGRA_132_SOC
202 bool "NVIDIA Tegra132 SoC"
203 depends on ARCH_TEGRA
204 select PINCTRL_TEGRA124
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700205 select USB_ULPI if USB_PHY
206 select USB_ULPI_VIEWPORT if USB_PHY
207 help
208 Enable support for NVIDIA Tegra132 SoC, based on the Denver
209 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
210 but contains an NVIDIA Denver CPU complex in place of
211 Tegra124's "4+1" Cortex-A15 CPU complex.
212
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530213config ARCH_THUNDER
214 bool "Cavium Inc. Thunder SoC Family"
215 help
216 This enables support for Cavium's Thunder Family of SoCs.
217
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100218config ARCH_VEXPRESS
219 bool "ARMv8 software model (Versatile Express)"
220 select ARCH_REQUIRE_GPIOLIB
221 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000222 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100223 select VEXPRESS_CONFIG
224 help
225 This enables support for the ARMv8 software model (Versatile
226 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100227
Vinayak Kale15942852013-04-24 10:06:57 +0100228config ARCH_XGENE
229 bool "AppliedMicro X-Gene SOC Family"
230 help
231 This enables support for AppliedMicro X-Gene SOC Family
232
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100233endmenu
234
235menu "Bus support"
236
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100237config PCI
238 bool "PCI support"
239 help
240 This feature enables support for PCI bus system. If you say Y
241 here, the kernel will include drivers and infrastructure code
242 to support PCI bus devices.
243
244config PCI_DOMAINS
245 def_bool PCI
246
247config PCI_DOMAINS_GENERIC
248 def_bool PCI
249
250config PCI_SYSCALL
251 def_bool PCI
252
253source "drivers/pci/Kconfig"
254source "drivers/pci/pcie/Kconfig"
255source "drivers/pci/hotplug/Kconfig"
256
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100257endmenu
258
259menu "Kernel Features"
260
Andre Przywarac0a01b82014-11-14 15:54:12 +0000261menu "ARM errata workarounds via the alternatives framework"
262
263config ARM64_ERRATUM_826319
264 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
265 default y
266 help
267 This option adds an alternative code sequence to work around ARM
268 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
269 AXI master interface and an L2 cache.
270
271 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
272 and is unable to accept a certain write via this interface, it will
273 not progress on read data presented on the read data channel and the
274 system can deadlock.
275
276 The workaround promotes data cache clean instructions to
277 data cache clean-and-invalidate.
278 Please note that this does not necessarily enable the workaround,
279 as it depends on the alternative framework, which will only patch
280 the kernel if an affected CPU is detected.
281
282 If unsure, say Y.
283
284config ARM64_ERRATUM_827319
285 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
286 default y
287 help
288 This option adds an alternative code sequence to work around ARM
289 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
290 master interface and an L2 cache.
291
292 Under certain conditions this erratum can cause a clean line eviction
293 to occur at the same time as another transaction to the same address
294 on the AMBA 5 CHI interface, which can cause data corruption if the
295 interconnect reorders the two transactions.
296
297 The workaround promotes data cache clean instructions to
298 data cache clean-and-invalidate.
299 Please note that this does not necessarily enable the workaround,
300 as it depends on the alternative framework, which will only patch
301 the kernel if an affected CPU is detected.
302
303 If unsure, say Y.
304
305config ARM64_ERRATUM_824069
306 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
307 default y
308 help
309 This option adds an alternative code sequence to work around ARM
310 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
311 to a coherent interconnect.
312
313 If a Cortex-A53 processor is executing a store or prefetch for
314 write instruction at the same time as a processor in another
315 cluster is executing a cache maintenance operation to the same
316 address, then this erratum might cause a clean cache line to be
317 incorrectly marked as dirty.
318
319 The workaround promotes data cache clean instructions to
320 data cache clean-and-invalidate.
321 Please note that this option does not necessarily enable the
322 workaround, as it depends on the alternative framework, which will
323 only patch the kernel if an affected CPU is detected.
324
325 If unsure, say Y.
326
327config ARM64_ERRATUM_819472
328 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
329 default y
330 help
331 This option adds an alternative code sequence to work around ARM
332 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
333 present when it is connected to a coherent interconnect.
334
335 If the processor is executing a load and store exclusive sequence at
336 the same time as a processor in another cluster is executing a cache
337 maintenance operation to the same address, then this erratum might
338 cause data corruption.
339
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
345
346 If unsure, say Y.
347
348config ARM64_ERRATUM_832075
349 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
350 default y
351 help
352 This option adds an alternative code sequence to work around ARM
353 erratum 832075 on Cortex-A57 parts up to r1p2.
354
355 Affected Cortex-A57 parts might deadlock when exclusive load/store
356 instructions to Write-Back memory are mixed with Device loads.
357
358 The workaround is to promote device loads to use Load-Acquire
359 semantics.
360 Please note that this does not necessarily enable the workaround,
361 as it depends on the alternative framework, which will only patch
362 the kernel if an affected CPU is detected.
363
364 If unsure, say Y.
365
366endmenu
367
368
Jungseok Leee41ceed2014-05-12 10:40:38 +0100369choice
370 prompt "Page size"
371 default ARM64_4K_PAGES
372 help
373 Page size (translation granule) configuration.
374
375config ARM64_4K_PAGES
376 bool "4KB"
377 help
378 This feature enables 4KB pages support.
379
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100380config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100381 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100382 help
383 This feature enables 64KB pages support (4KB by default)
384 allowing only two levels of page tables and faster TLB
385 look-up. AArch32 emulation is not available when this feature
386 is enabled.
387
Jungseok Leee41ceed2014-05-12 10:40:38 +0100388endchoice
389
390choice
391 prompt "Virtual address space size"
392 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
393 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
394 help
395 Allows choosing one of multiple possible virtual address
396 space sizes. The level of translation table is determined by
397 a combination of page size and virtual address space size.
398
399config ARM64_VA_BITS_39
400 bool "39-bit"
401 depends on ARM64_4K_PAGES
402
403config ARM64_VA_BITS_42
404 bool "42-bit"
405 depends on ARM64_64K_PAGES
406
Jungseok Leec79b9542014-05-12 18:40:51 +0900407config ARM64_VA_BITS_48
408 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900409
Jungseok Leee41ceed2014-05-12 10:40:38 +0100410endchoice
411
412config ARM64_VA_BITS
413 int
414 default 39 if ARM64_VA_BITS_39
415 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900416 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100417
Catalin Marinasabe669d2014-07-15 15:37:21 +0100418config ARM64_PGTABLE_LEVELS
419 int
420 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100421 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100422 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
423 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900424
Will Deacona8720132013-10-11 14:52:19 +0100425config CPU_BIG_ENDIAN
426 bool "Build big-endian kernel"
427 help
428 Say Y if you plan on running a kernel in big-endian mode.
429
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100430config SMP
431 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100432 help
433 This enables support for systems with more than one CPU. If
434 you say N here, the kernel will run on single and
435 multiprocessor machines, but will use only one CPU of a
436 multiprocessor machine. If you say Y here, the kernel will run
437 on many, but not all, single processor machines. On a single
438 processor machine, the kernel will run faster if you say N
439 here.
440
441 If you don't know what to do here, say N.
442
Mark Brownf6e763b2014-03-04 07:51:17 +0000443config SCHED_MC
444 bool "Multi-core scheduler support"
445 depends on SMP
446 help
447 Multi-core scheduler support improves the CPU scheduler's decision
448 making when dealing with multi-core CPU chips at a cost of slightly
449 increased overhead in some places. If unsure say N here.
450
451config SCHED_SMT
452 bool "SMT scheduler support"
453 depends on SMP
454 help
455 Improves the CPU scheduler's decision making when dealing with
456 MultiThreading at a cost of slightly increased overhead in some
457 places. If unsure say N here.
458
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100459config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100460 int "Maximum number of CPUs (2-64)"
461 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100462 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100463 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100464 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100465
Mark Rutland9327e2c2013-10-24 20:30:18 +0100466config HOTPLUG_CPU
467 bool "Support for hot-pluggable CPUs"
468 depends on SMP
469 help
470 Say Y here to experiment with turning CPUs off and on. CPUs
471 can be controlled through /sys/devices/system/cpu.
472
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100473source kernel/Kconfig.preempt
474
475config HZ
476 int
477 default 100
478
479config ARCH_HAS_HOLES_MEMORYMODEL
480 def_bool y if SPARSEMEM
481
482config ARCH_SPARSEMEM_ENABLE
483 def_bool y
484 select SPARSEMEM_VMEMMAP_ENABLE
485
486config ARCH_SPARSEMEM_DEFAULT
487 def_bool ARCH_SPARSEMEM_ENABLE
488
489config ARCH_SELECT_MEMORY_MODEL
490 def_bool ARCH_SPARSEMEM_ENABLE
491
492config HAVE_ARCH_PFN_VALID
493 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
494
495config HW_PERF_EVENTS
496 bool "Enable hardware performance counter support for perf events"
497 depends on PERF_EVENTS
498 default y
499 help
500 Enable hardware performance counter support for perf events. If
501 disabled, perf events will use software events only.
502
Steve Capper084bd292013-04-10 13:48:00 +0100503config SYS_SUPPORTS_HUGETLBFS
504 def_bool y
505
506config ARCH_WANT_GENERAL_HUGETLB
507 def_bool y
508
509config ARCH_WANT_HUGE_PMD_SHARE
510 def_bool y if !ARM64_64K_PAGES
511
Steve Capperaf074842013-04-19 16:23:57 +0100512config HAVE_ARCH_TRANSPARENT_HUGEPAGE
513 def_bool y
514
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100515config ARCH_HAS_CACHE_LINE_SIZE
516 def_bool y
517
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100518source "mm/Kconfig"
519
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000520config SECCOMP
521 bool "Enable seccomp to safely compute untrusted bytecode"
522 ---help---
523 This kernel feature is useful for number crunching applications
524 that may need to compute untrusted bytecode during their
525 execution. By using pipes or other transports made available to
526 the process as file descriptors supporting the read/write
527 syscalls, it's possible to isolate those applications in
528 their own address space using seccomp. Once seccomp is
529 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
530 and the task is only allowed to execute a few safe syscalls
531 defined by each seccomp mode.
532
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000533config XEN_DOM0
534 def_bool y
535 depends on XEN
536
537config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700538 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000539 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000540 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000541 help
542 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
543
Steve Capperd03bb142013-04-25 15:19:21 +0100544config FORCE_MAX_ZONEORDER
545 int
546 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
547 default "11"
548
Will Deacon1b907f42014-11-20 16:51:10 +0000549menuconfig ARMV8_DEPRECATED
550 bool "Emulate deprecated/obsolete ARMv8 instructions"
551 depends on COMPAT
552 help
553 Legacy software support may require certain instructions
554 that have been deprecated or obsoleted in the architecture.
555
556 Enable this config to enable selective emulation of these
557 features.
558
559 If unsure, say Y
560
561if ARMV8_DEPRECATED
562
563config SWP_EMULATION
564 bool "Emulate SWP/SWPB instructions"
565 help
566 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
567 they are always undefined. Say Y here to enable software
568 emulation of these instructions for userspace using LDXR/STXR.
569
570 In some older versions of glibc [<=2.8] SWP is used during futex
571 trylock() operations with the assumption that the code will not
572 be preempted. This invalid assumption may be more likely to fail
573 with SWP emulation enabled, leading to deadlock of the user
574 application.
575
576 NOTE: when accessing uncached shared regions, LDXR/STXR rely
577 on an external transaction monitoring block called a global
578 monitor to maintain update atomicity. If your system does not
579 implement a global monitor, this option can cause programs that
580 perform SWP operations to uncached memory to deadlock.
581
582 If unsure, say Y
583
584config CP15_BARRIER_EMULATION
585 bool "Emulate CP15 Barrier instructions"
586 help
587 The CP15 barrier instructions - CP15ISB, CP15DSB, and
588 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
589 strongly recommended to use the ISB, DSB, and DMB
590 instructions instead.
591
592 Say Y here to enable software emulation of these
593 instructions for AArch32 userspace code. When this option is
594 enabled, CP15 barrier usage is traced which can help
595 identify software that needs updating.
596
597 If unsure, say Y
598
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000599config SETEND_EMULATION
600 bool "Emulate SETEND instruction"
601 help
602 The SETEND instruction alters the data-endianness of the
603 AArch32 EL0, and is deprecated in ARMv8.
604
605 Say Y here to enable software emulation of the instruction
606 for AArch32 userspace code.
607
608 Note: All the cpus on the system must have mixed endian support at EL0
609 for this feature to be enabled. If a new CPU - which doesn't support mixed
610 endian - is hotplugged in after this feature has been enabled, there could
611 be unexpected results in the applications.
612
613 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000614endif
615
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100616endmenu
617
618menu "Boot options"
619
620config CMDLINE
621 string "Default kernel command string"
622 default ""
623 help
624 Provide a set of default command-line options at build time by
625 entering them here. As a minimum, you should specify the the
626 root device (e.g. root=/dev/nfs).
627
628config CMDLINE_FORCE
629 bool "Always use the default kernel command string"
630 help
631 Always use the default kernel command string, even if the boot
632 loader passes other arguments to the kernel.
633 This is useful if you cannot or don't want to change the
634 command-line options your boot loader passes to the kernel.
635
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200636config EFI_STUB
637 bool
638
Mark Salterf84d0272014-04-15 21:59:30 -0400639config EFI
640 bool "UEFI runtime support"
641 depends on OF && !CPU_BIG_ENDIAN
642 select LIBFDT
643 select UCS2_STRING
644 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200645 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200646 select EFI_STUB
647 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400648 default y
649 help
650 This option provides support for runtime services provided
651 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400652 clock, and platform reset). A UEFI stub is also provided to
653 allow the kernel to be booted as an EFI application. This
654 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400655
Yi Lid1ae8c02014-10-04 23:46:43 +0800656config DMI
657 bool "Enable support for SMBIOS (DMI) tables"
658 depends on EFI
659 default y
660 help
661 This enables SMBIOS/DMI feature for systems.
662
663 This option is only useful on systems that have UEFI firmware.
664 However, even with this option, the resultant kernel should
665 continue to boot on existing non-UEFI platforms.
666
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100667endmenu
668
669menu "Userspace binary formats"
670
671source "fs/Kconfig.binfmt"
672
673config COMPAT
674 bool "Kernel support for 32-bit EL0"
675 depends on !ARM64_64K_PAGES
676 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700677 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500678 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500679 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100680 help
681 This option enables support for a 32-bit EL0 running under a 64-bit
682 kernel at EL1. AArch32-specific components such as system calls,
683 the user helper functions, VFP support and the ptrace interface are
684 handled appropriately by the kernel.
685
686 If you want to execute 32-bit userspace applications, say Y.
687
688config SYSVIPC_COMPAT
689 def_bool y
690 depends on COMPAT && SYSVIPC
691
692endmenu
693
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000694menu "Power management options"
695
696source "kernel/power/Kconfig"
697
698config ARCH_SUSPEND_POSSIBLE
699 def_bool y
700
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000701endmenu
702
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100703menu "CPU Power Management"
704
705source "drivers/cpuidle/Kconfig"
706
Rob Herring52e7e812014-02-24 11:27:57 +0900707source "drivers/cpufreq/Kconfig"
708
709endmenu
710
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100711source "net/Kconfig"
712
713source "drivers/Kconfig"
714
Mark Salterf84d0272014-04-15 21:59:30 -0400715source "drivers/firmware/Kconfig"
716
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000717source "drivers/acpi/Kconfig"
718
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100719source "fs/Kconfig"
720
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100721source "arch/arm64/kvm/Kconfig"
722
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100723source "arch/arm64/Kconfig.debug"
724
725source "security/Kconfig"
726
727source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800728if CRYPTO
729source "arch/arm64/crypto/Kconfig"
730endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100731
732source "lib/Kconfig"