Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / f9953c5e2a84ffc309ca5f6a281528907a3c8a39 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: bb1ca158273c8f90d43d8e9833f4d4e76d5ac510 [file] [log] [blame]
Thierry Reding5780c202014-12-18 14:58:20 +0100[diff] [blame]1#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]2#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]3
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]4/**
5 * This file contains common DT entry for all fab version of Cardhu.
6 * There is multiple fab version of Cardhu starting from A01 to A07.
7 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
8 * A02 will have different sets of GPIOs for fixed regulator compare to
9 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
10 * compatible with fab version A04. Based on Cardhu fab version, the
11 * related dts file need to be chosen like for Cardhu fab version A02,
12 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
13 * tegra30-cardhu-a04.dts.
14 * The identification of board is done in two ways, by looking the sticker
15 * on PCB and by reading board id eeprom.
Marcel Ziswilerdb374062015-04-10 23:35:56 +0200[diff] [blame]16 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]17 * number is the fab version like here it is 002 and hence fab version A02.
18 * The (downstream internal) U-Boot of Cardhu display the board-id as
19 * follows:
20 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
21 * In this Fab version is 02 i.e. A02.
22 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
23 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
24 * wide.
25 */
26
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]27/ {
28 model = "NVIDIA Tegra30 Cardhu evaluation board";
29 compatible = "nvidia,cardhu", "nvidia,tegra30";
30
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]31 aliases {
Stephen Warren763fbff2014-02-13 17:18:26 -0700[diff] [blame]32 rtc0 = "/i2c@7000d000/tps65911@2d";
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]33 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -0800[diff] [blame]34 serial0 = &uarta;
35 serial1 = &uartc;
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]36 };
37
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]38 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]39 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]40 };
41
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]42 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]43 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200[diff] [blame]44
45 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
46 avdd-pexb-supply = <&ldo1_reg>;
47 vdd-pexb-supply = <&ldo1_reg>;
48 avdd-pex-pll-supply = <&ldo1_reg>;
49 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
50 vddio-pex-ctl-supply = <&sys_3v3_reg>;
51 avdd-plle-supply = <&ldo2_reg>;
52
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]53 pci@1,0 {
54 nvidia,num-lanes = <4>;
55 };
56
57 pci@2,0 {
58 nvidia,num-lanes = <1>;
59 };
60
61 pci@3,0 {
62 status = "okay";
63 nvidia,num-lanes = <1>;
64 };
65 };
66
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]67 host1x@50000000 {
68 dc@54200000 {
69 rgb {
70 status = "okay";
71
72 nvidia,panel = <&panel>;
73 };
74 };
75 };
76
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]77 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]78 pinctrl-names = "default";
79 pinctrl-0 = <&state_default>;
80
81 state_default: pinmux {
82 sdmmc1_clk_pz0 {
83 nvidia,pins = "sdmmc1_clk_pz0";
84 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]85 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]87 };
88 sdmmc1_cmd_pz1 {
89 nvidia,pins = "sdmmc1_cmd_pz1",
90 "sdmmc1_dat0_py7",
91 "sdmmc1_dat1_py6",
92 "sdmmc1_dat2_py5",
93 "sdmmc1_dat3_py4";
94 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]95 nvidia,pull = <TEGRA_PIN_PULL_UP>;
96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]97 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]98 sdmmc3_clk_pa6 {
99 nvidia,pins = "sdmmc3_clk_pa6";
100 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]103 };
104 sdmmc3_cmd_pa7 {
105 nvidia,pins = "sdmmc3_cmd_pa7",
106 "sdmmc3_dat0_pb7",
107 "sdmmc3_dat1_pb6",
108 "sdmmc3_dat2_pb5",
109 "sdmmc3_dat3_pb4";
110 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]111 nvidia,pull = <TEGRA_PIN_PULL_UP>;
112 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]113 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]114 sdmmc4_clk_pcc4 {
115 nvidia,pins = "sdmmc4_clk_pcc4",
116 "sdmmc4_rst_n_pcc3";
117 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]120 };
121 sdmmc4_dat0_paa0 {
122 nvidia,pins = "sdmmc4_dat0_paa0",
123 "sdmmc4_dat1_paa1",
124 "sdmmc4_dat2_paa2",
125 "sdmmc4_dat3_paa3",
126 "sdmmc4_dat4_paa4",
127 "sdmmc4_dat5_paa5",
128 "sdmmc4_dat6_paa6",
129 "sdmmc4_dat7_paa7";
130 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]131 nvidia,pull = <TEGRA_PIN_PULL_UP>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]133 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]134 dap2_fs_pa2 {
135 nvidia,pins = "dap2_fs_pa2",
136 "dap2_sclk_pa3",
137 "dap2_din_pa4",
138 "dap2_dout_pa5";
139 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]142 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]143 sdio3 {
144 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]145 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
146 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]147 nvidia,pull-down-strength = <46>;
148 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]149 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
150 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]151 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]152 uart3_txd_pw6 {
153 nvidia,pins = "uart3_txd_pw6",
154 "uart3_cts_n_pa1",
155 "uart3_rts_n_pc0",
156 "uart3_rxd_pw7";
157 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]160 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]161 };
162 };
163
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]164 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]165 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]166 };
167
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]168 serial@70006200 {
169 compatible = "nvidia,tegra30-hsuart";
170 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]171 };
172
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]173 pwm@7000a000 {
174 status = "okay";
175 };
176
177 panelddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]178 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]179 clock-frequency = <100000>;
180 };
181
182 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]183 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]184 clock-frequency = <100000>;
185 };
186
187 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]188 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]189 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]190
191 /* ALS and Proximity sensor */
192 isl29028@44 {
Arnaud Ebalard62981232014-12-16 22:21:16 +0100[diff] [blame]193 compatible = "isil,isl29028";
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]194 reg = <0x44>;
195 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]196 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]197 };
Bryan Wu40431d12014-02-07 15:54:58 -0800[diff] [blame]198
199 i2cmux@70 {
200 compatible = "nxp,pca9546";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 reg = <0x70>;
204 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]205 };
206
207 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]208 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]209 clock-frequency = <100000>;
210 };
211
212 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]213 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]214 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]215
216 wm8903: wm8903@1a {
217 compatible = "wlf,wm8903";
218 reg = <0x1a>;
219 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]220 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]221
222 gpio-controller;
223 #gpio-cells = <2>;
224
225 micdet-cfg = <0>;
226 micdet-delay = <100>;
227 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
228 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]229
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]230 pmic: tps65911@2d {
231 compatible = "ti,tps65911";
232 reg = <0x2d>;
233
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]234 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]235 #interrupt-cells = <2>;
236 interrupt-controller;
237
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]238 ti,system-power-controller;
239
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]240 #gpio-cells = <2>;
241 gpio-controller;
242
243 vcc1-supply = <&vdd_ac_bat_reg>;
244 vcc2-supply = <&vdd_ac_bat_reg>;
245 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]246 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]247 vcc5-supply = <&vdd_ac_bat_reg>;
248 vcc6-supply = <&vdd2_reg>;
249 vcc7-supply = <&vdd_ac_bat_reg>;
250 vccio-supply = <&vdd_ac_bat_reg>;
251
252 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]253 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]254 regulator-name = "vddio_ddr_1v2";
255 regulator-min-microvolt = <1200000>;
256 regulator-max-microvolt = <1200000>;
257 regulator-always-on;
258 };
259
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]260 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]261 regulator-name = "vdd_1v5_gen";
262 regulator-min-microvolt = <1500000>;
263 regulator-max-microvolt = <1500000>;
264 regulator-always-on;
265 };
266
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]267 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]268 regulator-name = "vdd_cpu,vdd_sys";
269 regulator-min-microvolt = <1000000>;
270 regulator-max-microvolt = <1000000>;
271 regulator-always-on;
272 };
273
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]274 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]275 regulator-name = "vdd_1v8_gen";
276 regulator-min-microvolt = <1800000>;
277 regulator-max-microvolt = <1800000>;
278 regulator-always-on;
279 };
280
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]281 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]282 regulator-name = "vdd_pexa,vdd_pexb";
283 regulator-min-microvolt = <1050000>;
284 regulator-max-microvolt = <1050000>;
285 };
286
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]287 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]288 regulator-name = "vdd_sata,avdd_plle";
289 regulator-min-microvolt = <1050000>;
290 regulator-max-microvolt = <1050000>;
291 };
292
293 /* LDO3 is not connected to anything */
294
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]295 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]296 regulator-name = "vdd_rtc";
297 regulator-min-microvolt = <1200000>;
298 regulator-max-microvolt = <1200000>;
299 regulator-always-on;
300 };
301
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]302 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]303 regulator-name = "vddio_sdmmc,avdd_vdac";
304 regulator-min-microvolt = <3300000>;
305 regulator-max-microvolt = <3300000>;
306 regulator-always-on;
307 };
308
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]309 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]310 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
311 regulator-min-microvolt = <1200000>;
312 regulator-max-microvolt = <1200000>;
313 };
314
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]315 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]316 regulator-name = "vdd_pllm,x,u,a_p_c_s";
317 regulator-min-microvolt = <1200000>;
318 regulator-max-microvolt = <1200000>;
319 regulator-always-on;
320 };
321
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]322 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]323 regulator-name = "vdd_ddr_hs";
324 regulator-min-microvolt = <1000000>;
325 regulator-max-microvolt = <1000000>;
326 regulator-always-on;
327 };
328 };
329 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]330
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]331 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]332 compatible = "onnn,nct1008";
333 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]334 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]335 interrupt-parent = <&gpio>;
336 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
337 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]338
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]339 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]340 compatible = "ti,tps62361";
341 reg = <0x60>;
342
343 regulator-name = "tps62361-vout";
344 regulator-min-microvolt = <500000>;
345 regulator-max-microvolt = <1500000>;
346 regulator-boot-on;
347 regulator-always-on;
348 ti,vsel0-state-high;
349 ti,vsel1-state-high;
350 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]351 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]352
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]353 spi@7000da00 {
354 status = "okay";
355 spi-max-frequency = <25000000>;
356 spi-flash@1 {
357 compatible = "winbond,w25q32";
358 reg = <1>;
359 spi-max-frequency = <20000000>;
360 };
361 };
362
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]363 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]364 status = "okay";
365 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]366 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]367 nvidia,cpu-pwr-good-time = <2000>;
368 nvidia,cpu-pwr-off-time = <200>;
369 nvidia,core-pwr-good-time = <3845 3845>;
370 nvidia,core-pwr-off-time = <0>;
371 nvidia,core-power-req-active-high;
372 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]373 };
374
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]375 ahub@70080000 {
376 i2s@70080400 {
377 status = "okay";
378 };
379 };
380
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]381 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]382 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]383 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
384 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
385 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]386 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]387 };
388
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]389 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]390 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]391 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]392 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]393 };
394
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]395 usb@7d008000 {
396 status = "okay";
397 };
398
399 usb-phy@7d008000 {
400 vbus-supply = <&usb3_vbus_reg>;
401 status = "okay";
402 };
403
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]404 backlight: backlight {
405 compatible = "pwm-backlight";
406
407 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
408 power-supply = <&vdd_bl_reg>;
409 pwms = <&pwm 0 5000000>;
410
411 brightness-levels = <0 4 8 16 32 64 128 255>;
412 default-brightness-level = <6>;
413 };
414
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]415 clocks {
416 compatible = "simple-bus";
417 #address-cells = <1>;
418 #size-cells = <0>;
419
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]420 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]421 compatible = "fixed-clock";
422 reg=<0>;
423 #clock-cells = <0>;
424 clock-frequency = <32768>;
425 };
426 };
427
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]428 panel: panel {
429 compatible = "chunghwa,claa101wb01", "simple-panel";
430 ddc-i2c-bus = <&panelddc>;
431
432 power-supply = <&vdd_pnl1_reg>;
433 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
434
435 backlight = <&backlight>;
436 };
437
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]438 regulators {
439 compatible = "simple-bus";
440 #address-cells = <1>;
441 #size-cells = <0>;
442
443 vdd_ac_bat_reg: regulator@0 {
444 compatible = "regulator-fixed";
445 reg = <0>;
446 regulator-name = "vdd_ac_bat";
447 regulator-min-microvolt = <5000000>;
448 regulator-max-microvolt = <5000000>;
449 regulator-always-on;
450 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]451
452 cam_1v8_reg: regulator@1 {
453 compatible = "regulator-fixed";
454 reg = <1>;
455 regulator-name = "cam_1v8";
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
458 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]459 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]460 vin-supply = <&vio_reg>;
461 };
462
463 cp_5v_reg: regulator@2 {
464 compatible = "regulator-fixed";
465 reg = <2>;
466 regulator-name = "cp_5v";
467 regulator-min-microvolt = <5000000>;
468 regulator-max-microvolt = <5000000>;
469 regulator-boot-on;
470 regulator-always-on;
471 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]472 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]473 };
474
475 emmc_3v3_reg: regulator@3 {
476 compatible = "regulator-fixed";
477 reg = <3>;
478 regulator-name = "emmc_3v3";
479 regulator-min-microvolt = <3300000>;
480 regulator-max-microvolt = <3300000>;
481 regulator-always-on;
482 regulator-boot-on;
483 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]484 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]485 vin-supply = <&sys_3v3_reg>;
486 };
487
488 modem_3v3_reg: regulator@4 {
489 compatible = "regulator-fixed";
490 reg = <4>;
491 regulator-name = "modem_3v3";
492 regulator-min-microvolt = <3300000>;
493 regulator-max-microvolt = <3300000>;
494 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]495 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]496 };
497
498 pex_hvdd_3v3_reg: regulator@5 {
499 compatible = "regulator-fixed";
500 reg = <5>;
501 regulator-name = "pex_hvdd_3v3";
502 regulator-min-microvolt = <3300000>;
503 regulator-max-microvolt = <3300000>;
504 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]505 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]506 vin-supply = <&sys_3v3_reg>;
507 };
508
509 vdd_cam1_ldo_reg: regulator@6 {
510 compatible = "regulator-fixed";
511 reg = <6>;
512 regulator-name = "vdd_cam1_ldo";
513 regulator-min-microvolt = <2800000>;
514 regulator-max-microvolt = <2800000>;
515 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]516 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]517 vin-supply = <&sys_3v3_reg>;
518 };
519
520 vdd_cam2_ldo_reg: regulator@7 {
521 compatible = "regulator-fixed";
522 reg = <7>;
523 regulator-name = "vdd_cam2_ldo";
524 regulator-min-microvolt = <2800000>;
525 regulator-max-microvolt = <2800000>;
526 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]527 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]528 vin-supply = <&sys_3v3_reg>;
529 };
530
531 vdd_cam3_ldo_reg: regulator@8 {
532 compatible = "regulator-fixed";
533 reg = <8>;
534 regulator-name = "vdd_cam3_ldo";
535 regulator-min-microvolt = <3300000>;
536 regulator-max-microvolt = <3300000>;
537 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]538 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]539 vin-supply = <&sys_3v3_reg>;
540 };
541
542 vdd_com_reg: regulator@9 {
543 compatible = "regulator-fixed";
544 reg = <9>;
545 regulator-name = "vdd_com";
546 regulator-min-microvolt = <3300000>;
547 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]548 regulator-always-on;
549 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]550 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]551 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]552 vin-supply = <&sys_3v3_reg>;
553 };
554
555 vdd_fuse_3v3_reg: regulator@10 {
556 compatible = "regulator-fixed";
557 reg = <10>;
558 regulator-name = "vdd_fuse_3v3";
559 regulator-min-microvolt = <3300000>;
560 regulator-max-microvolt = <3300000>;
561 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]562 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]563 vin-supply = <&sys_3v3_reg>;
564 };
565
566 vdd_pnl1_reg: regulator@11 {
567 compatible = "regulator-fixed";
568 reg = <11>;
569 regulator-name = "vdd_pnl1";
570 regulator-min-microvolt = <3300000>;
571 regulator-max-microvolt = <3300000>;
572 regulator-always-on;
573 regulator-boot-on;
574 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]575 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]576 vin-supply = <&sys_3v3_reg>;
577 };
578
579 vdd_vid_reg: regulator@12 {
580 compatible = "regulator-fixed";
581 reg = <12>;
582 regulator-name = "vddio_vid";
583 regulator-min-microvolt = <5000000>;
584 regulator-max-microvolt = <5000000>;
585 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]586 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]587 gpio-open-drain;
588 vin-supply = <&vdd_5v0_reg>;
589 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]590 };
591
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]592 sound {
593 compatible = "nvidia,tegra-audio-wm8903-cardhu",
594 "nvidia,tegra-audio-wm8903";
595 nvidia,model = "NVIDIA Tegra Cardhu";
596
597 nvidia,audio-routing =
598 "Headphone Jack", "HPOUTR",
599 "Headphone Jack", "HPOUTL",
600 "Int Spk", "ROP",
601 "Int Spk", "RON",
602 "Int Spk", "LOP",
603 "Int Spk", "LON",
604 "Mic Jack", "MICBIAS",
605 "IN1L", "Mic Jack";
606
607 nvidia,i2s-controller = <&tegra_i2s1>;
608 nvidia,audio-codec = <&wm8903>;
609
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]610 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
611 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
612 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]613
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]614 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
615 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
616 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]617 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]618 };
Thierry Reding5780c202014-12-18 14:58:20 +0100[diff] [blame]619
620 gpio-keys {
621 compatible = "gpio-keys";
622
623 power {
624 label = "Power";
625 interrupt-parent = <&pmic>;
626 interrupts = <2 0>;
627 linux,code = <KEY_POWER>;
628 debounce-interval = <100>;
629 gpio-key,wakeup;
630 };
631
632 volume-down {
633 label = "Volume Down";
634 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
635 linux,code = <KEY_VOLUMEDOWN>;
636 debounce-interval = <10>;
637 };
638
639 volume-up {
640 label = "Volume Up";
641 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
642 linux,code = <KEY_VOLUMEUP>;
643 debounce-interval = <10>;
644 };
645 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]646};