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Sergei Shtylyovf138e542015-10-01 02:02:27 +03001/*
2 * Device Tree Source for the Porter board
3 *
4 * Copyright (C) 2015 Cogent Embedded, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Sergei Shtylyov493b4da2016-01-21 14:36:01 -080011/*
12 * SSI-AK4642
13 *
Sergei Shtylyovf3b063c82016-02-12 00:49:52 +030014 * JP3: 2-1: AK4642
15 * 2-3: ADV7511
Sergei Shtylyov493b4da2016-01-21 14:36:01 -080016 *
17 * This command is required before playback/capture:
18 *
19 * amixer set "LINEOUT Mixer DACL" on
20 */
21
Sergei Shtylyovf138e542015-10-01 02:02:27 +030022/dts-v1/;
23#include "r8a7791.dtsi"
Sergei Shtylyovb941a5c2015-10-07 02:05:41 +030024#include <dt-bindings/gpio/gpio.h>
Sergei Shtylyovf138e542015-10-01 02:02:27 +030025
26/ {
27 model = "Porter";
28 compatible = "renesas,porter", "renesas,r8a7791";
29
30 aliases {
31 serial0 = &scif0;
32 };
33
34 chosen {
Sergei Shtylyov08770982015-10-06 01:51:01 +030035 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
Geert Uytterhoevenbf204762015-12-08 18:54:17 +010036 stdout-path = "serial0:115200n8";
Sergei Shtylyovf138e542015-10-01 02:02:27 +030037 };
38
39 memory@40000000 {
40 device_type = "memory";
41 reg = <0 0x40000000 0 0x40000000>;
42 };
43
44 memory@200000000 {
45 device_type = "memory";
46 reg = <2 0x00000000 0 0x40000000>;
47 };
Sergei Shtylyovb941a5c2015-10-07 02:05:41 +030048
49 vcc_sdhi0: regulator@0 {
50 compatible = "regulator-fixed";
51
52 regulator-name = "SDHI0 Vcc";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-always-on;
56 };
57
58 vccq_sdhi0: regulator@1 {
59 compatible = "regulator-gpio";
60
61 regulator-name = "SDHI0 VccQ";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <3300000>;
64
65 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
66 gpios-states = <1>;
67 states = <3300000 1
68 1800000 0>;
69 };
70
71 vcc_sdhi2: regulator@2 {
72 compatible = "regulator-fixed";
73
74 regulator-name = "SDHI2 Vcc";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-always-on;
78 };
79
80 vccq_sdhi2: regulator@3 {
81 compatible = "regulator-gpio";
82
83 regulator-name = "SDHI2 VccQ";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <3300000>;
86
87 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
88 gpios-states = <1>;
89 states = <3300000 1
90 1800000 0>;
91 };
Sergei Shtylyovc5af8a42015-12-25 01:45:30 +030092
93 hdmi-out {
94 compatible = "hdmi-connector";
95 type = "a";
96
97 port {
98 hdmi_con: endpoint {
99 remote-endpoint = <&adv7511_out>;
100 };
101 };
102 };
103
104 x3_clk: x3-clock {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <148500000>;
108 };
109
110 x16_clk: x16-clock {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <74250000>;
114 };
Sergei Shtylyov493b4da2016-01-21 14:36:01 -0800115
116 x14_clk: x14-clock {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <11289600>;
120 clock-output-names = "audio_clock";
121 };
122
123 sound {
124 compatible = "simple-audio-card";
125
126 simple-audio-card,format = "left_j";
127 simple-audio-card,bitclock-master = <&soundcodec>;
128 simple-audio-card,frame-master = <&soundcodec>;
129
130 simple-audio-card,cpu {
131 sound-dai = <&rcar_sound>;
132 };
133
134 soundcodec: simple-audio-card,codec {
135 sound-dai = <&ak4642>;
136 clocks = <&x14_clk>;
137 };
138 };
Sergei Shtylyovf138e542015-10-01 02:02:27 +0300139};
140
141&extal_clk {
142 clock-frequency = <20000000>;
143};
144
145&pfc {
Geert Uytterhoeven19417bd2016-01-29 11:17:24 +0100146 pinctrl-0 = <&scif_clk_pins>;
147 pinctrl-names = "default";
148
Sergei Shtylyovf138e542015-10-01 02:02:27 +0300149 scif0_pins: serial0 {
150 renesas,groups = "scif0_data_d";
151 renesas,function = "scif0";
152 };
Sergei Shtylyov08770982015-10-06 01:51:01 +0300153
Geert Uytterhoeven19417bd2016-01-29 11:17:24 +0100154 scif_clk_pins: scif_clk {
155 renesas,groups = "scif_clk";
156 renesas,function = "scif_clk";
157 };
158
Sergei Shtylyov08770982015-10-06 01:51:01 +0300159 ether_pins: ether {
160 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
161 renesas,function = "eth";
162 };
163
164 phy1_pins: phy1 {
165 renesas,groups = "intc_irq0";
166 renesas,function = "intc";
167 };
Sergei Shtylyovb941a5c2015-10-07 02:05:41 +0300168
169 sdhi0_pins: sd0 {
170 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
171 renesas,function = "sdhi0";
172 };
173
174 sdhi2_pins: sd2 {
175 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
176 renesas,function = "sdhi2";
177 };
Sergei Shtylyovd6b94032015-10-09 00:44:18 +0300178
Sergei Shtylyov2685a2c2015-10-10 00:40:31 +0300179 qspi_pins: spi0 {
180 renesas,groups = "qspi_ctrl", "qspi_data4";
181 renesas,function = "qspi";
182 };
183
Sergei Shtylyovd6b94032015-10-09 00:44:18 +0300184 i2c2_pins: i2c2 {
185 renesas,groups = "i2c2";
186 renesas,function = "i2c2";
187 };
Sergei Shtylyov778f2e72015-10-09 00:45:49 +0300188
Sergei Shtylyov99f74452015-10-13 01:12:18 +0300189 usb0_pins: usb0 {
190 renesas,groups = "usb0";
191 renesas,function = "usb0";
192 };
193
194 usb1_pins: usb1 {
195 renesas,groups = "usb1";
196 renesas,function = "usb1";
197 };
198
Sergei Shtylyov778f2e72015-10-09 00:45:49 +0300199 vin0_pins: vin0 {
200 renesas,groups = "vin0_data8", "vin0_clk";
201 renesas,function = "vin0";
202 };
Sergei Shtylyov0768fba2015-10-28 00:03:22 +0300203
204 can0_pins: can0 {
205 renesas,groups = "can0_data";
206 renesas,function = "can0";
207 };
Sergei Shtylyovc5af8a42015-12-25 01:45:30 +0300208
209 du_pins: du {
210 renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
211 renesas,function = "du";
212 };
Sergei Shtylyov493b4da2016-01-21 14:36:01 -0800213
214 ssi_pins: sound {
215 renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
216 renesas,function = "ssi";
217 };
218
219 audio_clk_pins: audio_clk {
220 renesas,groups = "audio_clk_a";
221 renesas,function = "audio_clk";
222 };
Sergei Shtylyovf138e542015-10-01 02:02:27 +0300223};
224
225&scif0 {
226 pinctrl-0 = <&scif0_pins>;
227 pinctrl-names = "default";
228
229 status = "okay";
230};
Sergei Shtylyov08770982015-10-06 01:51:01 +0300231
Geert Uytterhoeven19417bd2016-01-29 11:17:24 +0100232&scif_clk {
233 clock-frequency = <14745600>;
234 status = "okay";
235};
236
Sergei Shtylyov08770982015-10-06 01:51:01 +0300237&ether {
238 pinctrl-0 = <&ether_pins &phy1_pins>;
239 pinctrl-names = "default";
240
241 phy-handle = <&phy1>;
242 renesas,ether-link-active-low;
243 status = "ok";
244
245 phy1: ethernet-phy@1 {
246 reg = <1>;
247 interrupt-parent = <&irqc0>;
248 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
249 micrel,led-mode = <1>;
250 };
251};
Sergei Shtylyovb941a5c2015-10-07 02:05:41 +0300252
253&sdhi0 {
254 pinctrl-0 = <&sdhi0_pins>;
255 pinctrl-names = "default";
256
257 vmmc-supply = <&vcc_sdhi0>;
258 vqmmc-supply = <&vccq_sdhi0>;
259 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
260 wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
261 status = "okay";
262};
263
264&sdhi2 {
265 pinctrl-0 = <&sdhi2_pins>;
266 pinctrl-names = "default";
267
268 vmmc-supply = <&vcc_sdhi2>;
269 vqmmc-supply = <&vccq_sdhi2>;
270 cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
271 status = "okay";
272};
Sergei Shtylyovefbb05c22015-10-08 01:00:06 +0300273
Sergei Shtylyov2685a2c2015-10-10 00:40:31 +0300274&qspi {
275 pinctrl-0 = <&qspi_pins>;
276 pinctrl-names = "default";
277
278 status = "okay";
279
280 flash@0 {
Sergei Shtylyov2685a2c2015-10-10 00:40:31 +0300281 compatible = "spansion,s25fl512s", "jedec,spi-nor";
282 reg = <0>;
283 spi-max-frequency = <30000000>;
284 spi-tx-bus-width = <4>;
285 spi-rx-bus-width = <4>;
286 m25p,fast-read;
287
Geert Uytterhoeven26fac0e2015-11-20 11:38:54 -0800288 partitions {
Geert Uytterhoeven947ef622015-12-21 11:33:50 +0100289 compatible = "fixed-partitions";
Geert Uytterhoeven26fac0e2015-11-20 11:38:54 -0800290 #address-cells = <1>;
291 #size-cells = <1>;
292
293 partition@0 {
294 label = "loader_prg";
295 reg = <0x00000000 0x00040000>;
296 read-only;
297 };
298 partition@40000 {
299 label = "user_prg";
300 reg = <0x00040000 0x00400000>;
301 read-only;
302 };
303 partition@440000 {
304 label = "flash_fs";
305 reg = <0x00440000 0x03bc0000>;
306 };
Sergei Shtylyov2685a2c2015-10-10 00:40:31 +0300307 };
308 };
309};
310
Sergei Shtylyovd6b94032015-10-09 00:44:18 +0300311&i2c2 {
312 pinctrl-0 = <&i2c2_pins>;
313 pinctrl-names = "default";
314
315 status = "okay";
316 clock-frequency = <400000>;
Sergei Shtylyov778f2e72015-10-09 00:45:49 +0300317
Sergei Shtylyov493b4da2016-01-21 14:36:01 -0800318 ak4642: codec@12 {
319 compatible = "asahi-kasei,ak4642";
320 #sound-dai-cells = <0>;
321 reg = <0x12>;
322 };
323
Sergei Shtylyov778f2e72015-10-09 00:45:49 +0300324 composite-in@20 {
325 compatible = "adi,adv7180";
326 reg = <0x20>;
327 remote = <&vin0>;
328
329 port {
330 adv7180: endpoint {
331 bus-width = <8>;
332 remote-endpoint = <&vin0ep>;
333 };
334 };
335 };
Sergei Shtylyovc5af8a42015-12-25 01:45:30 +0300336
337 hdmi@39 {
338 compatible = "adi,adv7511w";
339 reg = <0x39>;
340 interrupt-parent = <&gpio3>;
341 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
342
343 adi,input-depth = <8>;
344 adi,input-colorspace = "rgb";
345 adi,input-clock = "1x";
346 adi,input-style = <1>;
347 adi,input-justification = "evenly";
348
349 ports {
350 #address-cells = <1>;
351 #size-cells = <0>;
352
353 port@0 {
354 reg = <0>;
355 adv7511_in: endpoint {
356 remote-endpoint = <&du_out_rgb>;
357 };
358 };
359
360 port@1 {
361 reg = <1>;
362 adv7511_out: endpoint {
363 remote-endpoint = <&hdmi_con>;
364 };
365 };
366 };
367 };
Sergei Shtylyovd6b94032015-10-09 00:44:18 +0300368};
369
Sergei Shtylyovefbb05c22015-10-08 01:00:06 +0300370&sata0 {
371 status = "okay";
372};
Sergei Shtylyov778f2e72015-10-09 00:45:49 +0300373
374/* composite video input */
375&vin0 {
376 status = "ok";
377 pinctrl-0 = <&vin0_pins>;
378 pinctrl-names = "default";
379
380 port {
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 vin0ep: endpoint {
385 remote-endpoint = <&adv7180>;
386 bus-width = <8>;
387 };
388 };
389};
Sergei Shtylyovf9953c52015-10-10 00:41:26 +0300390
Sergei Shtylyov99f74452015-10-13 01:12:18 +0300391&pci0 {
392 pinctrl-0 = <&usb0_pins>;
393 pinctrl-names = "default";
394
395 status = "okay";
396};
397
398&pci1 {
399 pinctrl-0 = <&usb1_pins>;
400 pinctrl-names = "default";
401
402 status = "okay";
403};
404
Sergei Shtylyovc794f6a2015-10-14 22:35:46 +0300405&hsusb {
406 pinctrl-0 = <&usb0_pins>;
407 pinctrl-names = "default";
408
409 status = "okay";
Sergei Shtylyovc794f6a2015-10-14 22:35:46 +0300410};
411
Sergei Shtylyov99f74452015-10-13 01:12:18 +0300412&usbphy {
413 status = "okay";
414};
415
Sergei Shtylyovf9953c52015-10-10 00:41:26 +0300416&pcie_bus_clk {
417 status = "okay";
418};
419
420&pciec {
421 status = "okay";
422};
Sergei Shtylyov0768fba2015-10-28 00:03:22 +0300423
424&can0 {
425 pinctrl-0 = <&can0_pins>;
426 pinctrl-names = "default";
427
428 status = "okay";
429};
Sergei Shtylyovc5af8a42015-12-25 01:45:30 +0300430
431&du {
432 pinctrl-0 = <&du_pins>;
433 pinctrl-names = "default";
434 status = "okay";
435
436 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
437 <&mstp7_clks R8A7791_CLK_DU1>,
438 <&mstp7_clks R8A7791_CLK_LVDS0>,
439 <&x3_clk>, <&x16_clk>;
440 clock-names = "du.0", "du.1", "lvds.0",
441 "dclkin.0", "dclkin.1";
442
443 ports {
444 port@1 {
445 endpoint {
446 remote-endpoint = <&adv7511_in>;
447 };
448 };
449 };
450};
Sergei Shtylyov493b4da2016-01-21 14:36:01 -0800451
452&rcar_sound {
453 pinctrl-0 = <&ssi_pins &audio_clk_pins>;
454 pinctrl-names = "default";
455 status = "okay";
456
457 /* Single DAI */
458 #sound-dai-cells = <0>;
459
460 rcar_sound,dai {
461 dai0 {
462 playback = <&ssi0>;
463 capture = <&ssi1>;
464 };
465 };
466};
467
468&ssi1 {
469 shared-pin;
470};