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Aneesh V7ec94452012-04-27 17:54:05 +05301#
2# Memory devices
3#
4
5menuconfig MEMORY
6 bool "Memory Controller drivers"
7
8if MEMORY
9
Alexandre Bellonie81b6ab2014-07-08 18:21:12 +020010config ATMEL_SDRAMC
11 bool "Atmel (Multi-port DDR-)SDRAM Controller"
12 default y
13 depends on ARCH_AT91 && OF
14 help
15 This driver is for Atmel SDRAM Controller or Atmel Multi-port
16 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
17 Starting with the at91sam9g45, this controller supports SDR, DDR and
18 LP-DDR memories.
19
Ivan Khoronzhuk5a7c8152014-02-24 19:26:11 +020020config TI_AEMIF
21 tristate "Texas Instruments AEMIF driver"
22 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
23 help
24 This driver is for the AEMIF module available in Texas Instruments
25 SoCs. AEMIF stands for Asynchronous External Memory Interface and
26 is intended to provide a glue-less interface to a variety of
27 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
28 of 256M bytes of any of these memories can be accessed at a given
29 time via four chip selects with 64M byte access per chip select.
30
Aneesh V7ec94452012-04-27 17:54:05 +053031config TI_EMIF
32 tristate "Texas Instruments EMIF driver"
Santosh Shilimkar18e9a972012-05-04 11:38:11 +053033 depends on ARCH_OMAP2PLUS
Aneesh V7ec94452012-04-27 17:54:05 +053034 select DDR
35 help
36 This driver is for the EMIF module available in Texas Instruments
37 SoCs. EMIF is an SDRAM controller that, based on its revision,
38 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
39 This driver takes care of only LPDDR2 memories presently. The
40 functions of the driver includes re-configuring AC timing
41 parameters and other settings during frequency, voltage and
42 temperature changes
43
Ezequiel Garcia3edad322013-04-23 16:21:26 -030044config MVEBU_DEVBUS
45 bool "Marvell EBU Device Bus Controller"
46 default y
47 depends on PLAT_ORION && OF
48 help
49 This driver is for the Device Bus controller available in some
50 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
51 Armada 370 and Armada XP. This controller allows to handle flash
52 devices such as NOR, NAND, SRAM, and FPGA.
53
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030054config TEGRA20_MC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030055 bool "Tegra20 Memory Controller(MC) driver"
56 default y
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030057 depends on ARCH_TEGRA_2x_SOC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030058 help
59 This driver is for the Memory Controller(MC) module available
60 in Tegra20 SoCs, mainly for a address translation fault
61 analysis, especially for IOMMU/GART(Graphics Address
62 Relocation Table) module.
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030063
Hiroshi DOYUaf468102012-05-10 10:42:32 +030064config TEGRA30_MC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030065 bool "Tegra30 Memory Controller(MC) driver"
66 default y
Hiroshi DOYUaf468102012-05-10 10:42:32 +030067 depends on ARCH_TEGRA_3x_SOC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030068 help
69 This driver is for the Memory Controller(MC) module available
70 in Tegra30 SoCs, mainly for a address translation fault
71 analysis, especially for IOMMU/SMMU(System Memory Management
72 Unit) module.
Hiroshi DOYUaf468102012-05-10 10:42:32 +030073
Scott Wood54afbec2014-07-02 18:52:11 -050074config FSL_CORENET_CF
75 tristate "Freescale CoreNet Error Reporting"
76 depends on FSL_SOC_BOOKE
77 help
78 Say Y for reporting of errors from the Freescale CoreNet
79 Coherency Fabric. Errors reported include accesses to
80 physical addresses that mapped by no local access window
81 (LAW) or an invalid LAW, as well as bad cache state that
82 represents a coherency violation.
83
Paul Gortmaker42d87b12014-02-19 17:46:40 -050084config FSL_IFC
85 bool
86 depends on FSL_SOC
87
Aneesh V7ec94452012-04-27 17:54:05 +053088endif