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Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
Scott Teel51c35132014-02-18 13:57:26 -06003 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
Stephen M. Cameronedd16362009-12-08 14:09:11 -08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_H
22#define HPSA_H
23
24#include <scsi/scsicam.h>
25
26#define IO_OK 0
27#define IO_ERROR 1
28
29struct ctlr_info;
30
31struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 unsigned long (*fifo_full)(struct ctlr_info *h);
Stephen M. Cameron900c5442010-02-04 08:42:35 -060036 bool (*intr_pending)(struct ctlr_info *h);
Matt Gates254f7962012-05-01 11:43:06 -050037 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
Stephen M. Cameronedd16362009-12-08 14:09:11 -080038};
39
40struct hpsa_scsi_dev_t {
41 int devtype;
42 int bus, target, lun; /* as presented to the OS */
43 unsigned char scsi3addr[8]; /* as presented to the HW */
44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model[16]; /* bytes 16-31 of inquiry data */
Stephen M. Cameronedd16362009-12-08 14:09:11 -080048 unsigned char raid_level; /* from inquiry page 0xC1 */
Stephen M. Cameron98465902014-02-21 16:25:00 -060049 unsigned char volume_offline; /* discovered via TUR or VPD */
Matt Gatese1f7de02014-02-18 13:55:17 -060050 u32 ioaccel_handle;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -060051 int offload_config; /* I/O accel RAID offload configured */
52 int offload_enabled; /* I/O accel RAID offload enabled */
53 int offload_to_mirror; /* Send next I/O accelerator RAID
54 * offload request to mirror drive
55 */
56 struct raid_map_data raid_map; /* I/O accelerator RAID map */
57
Stephen M. Cameronedd16362009-12-08 14:09:11 -080058};
59
Stephen M. Cameron072b0512014-05-29 10:53:07 -050060struct reply_queue_buffer {
Matt Gates254f7962012-05-01 11:43:06 -050061 u64 *head;
62 size_t size;
63 u8 wraparound;
64 u32 current_entry;
Stephen M. Cameron072b0512014-05-29 10:53:07 -050065 dma_addr_t busaddr;
Matt Gates254f7962012-05-01 11:43:06 -050066};
67
Stephen M. Cameron316b2212014-02-21 16:25:15 -060068#pragma pack(1)
69struct bmic_controller_parameters {
70 u8 led_flags;
71 u8 enable_command_list_verification;
72 u8 backed_out_write_drives;
73 u16 stripes_for_parity;
74 u8 parity_distribution_mode_flags;
75 u16 max_driver_requests;
76 u16 elevator_trend_count;
77 u8 disable_elevator;
78 u8 force_scan_complete;
79 u8 scsi_transfer_mode;
80 u8 force_narrow;
81 u8 rebuild_priority;
82 u8 expand_priority;
83 u8 host_sdb_asic_fix;
84 u8 pdpi_burst_from_host_disabled;
85 char software_name[64];
86 char hardware_name[32];
87 u8 bridge_revision;
88 u8 snapshot_priority;
89 u32 os_specific;
90 u8 post_prompt_timeout;
91 u8 automatic_drive_slamming;
92 u8 reserved1;
93 u8 nvram_flags;
Joe Handzik6e8e8082014-05-15 15:44:42 -050094#define HBA_MODE_ENABLED_FLAG (1 << 3)
Stephen M. Cameron316b2212014-02-21 16:25:15 -060095 u8 cache_nvram_flags;
96 u8 drive_config_flags;
97 u16 reserved2;
98 u8 temp_warning_level;
99 u8 temp_shutdown_level;
100 u8 temp_condition_reset;
101 u8 max_coalesce_commands;
102 u32 max_coalesce_delay;
103 u8 orca_password[4];
104 u8 access_id[16];
105 u8 reserved[356];
106};
107#pragma pack()
108
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800109struct ctlr_info {
110 int ctlr;
111 char devname[8];
112 char *product_name;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800113 struct pci_dev *pdev;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600114 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800115 void __iomem *vaddr;
116 unsigned long paddr;
117 int nr_cmds; /* Number of commands allowed on this controller */
118 struct CfgTable __iomem *cfgtable;
119 int interrupts_enabled;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800120 int max_commands;
121 int commands_outstanding;
Don Brace303932f2010-02-04 08:42:40 -0600122# define PERF_MODE_INT 0
123# define DOORBELL_INT 1
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800124# define SIMPLE_MODE_INT 2
125# define MEMQ_MODE_INT 3
Matt Gates254f7962012-05-01 11:43:06 -0500126 unsigned int intr[MAX_REPLY_QUEUES];
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800127 unsigned int msix_vector;
128 unsigned int msi_vector;
Stephen M. Camerona9a3a272011-02-15 15:32:53 -0600129 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800130 struct access_method access;
Stephen M. Cameron316b2212014-02-21 16:25:15 -0600131 char hba_mode_enabled;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800132
133 /* queue and queue Info */
Stephen M. Cameron9e0fc762011-02-15 15:32:48 -0600134 struct list_head reqQ;
135 struct list_head cmpQ;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800136 unsigned int Qdepth;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800137 unsigned int maxSG;
138 spinlock_t lock;
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -0600139 int maxsgentries;
140 u8 max_cmd_sg_entries;
141 int chainsize;
142 struct SGDescriptor **cmd_sg_list;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800143
144 /* pointers to command and error info pool */
145 struct CommandList *cmd_pool;
146 dma_addr_t cmd_pool_dhandle;
Matt Gatese1f7de02014-02-18 13:55:17 -0600147 struct io_accel1_cmd *ioaccel_cmd_pool;
148 dma_addr_t ioaccel_cmd_pool_dhandle;
Stephen M. Cameronaca90122014-02-18 13:56:14 -0600149 struct io_accel2_cmd *ioaccel2_cmd_pool;
150 dma_addr_t ioaccel2_cmd_pool_dhandle;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800151 struct ErrorInfo *errinfo_pool;
152 dma_addr_t errinfo_pool_dhandle;
153 unsigned long *cmd_pool_bits;
Stephen M. Camerona08a8472010-02-04 08:43:16 -0600154 int scan_finished;
155 spinlock_t scan_lock;
156 wait_queue_head_t scan_wait_queue;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800157
158 struct Scsi_Host *scsi_host;
159 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
160 int ndevices; /* number of used elements in .dev[] array. */
Scott Teelcfe5bad2011-10-26 16:21:07 -0500161 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
Don Brace303932f2010-02-04 08:42:40 -0600162 /*
163 * Performant mode tables.
164 */
165 u32 trans_support;
166 u32 trans_offset;
167 struct TransTable_struct *transtable;
168 unsigned long transMethod;
169
Stephen M. Cameron0390f0c2013-09-23 13:34:12 -0500170 /* cap concurrent passthrus at some reasonable maximum */
171#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
172 spinlock_t passthru_count_lock; /* protects passthru_count */
173 int passthru_count;
174
Don Brace303932f2010-02-04 08:42:40 -0600175 /*
Matt Gates254f7962012-05-01 11:43:06 -0500176 * Performant mode completion buffers
Don Brace303932f2010-02-04 08:42:40 -0600177 */
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500178 size_t reply_queue_size;
179 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
Matt Gates254f7962012-05-01 11:43:06 -0500180 u8 nreply_queues;
Don Brace303932f2010-02-04 08:42:40 -0600181 u32 *blockFetchTable;
Matt Gatese1f7de02014-02-18 13:55:17 -0600182 u32 *ioaccel1_blockFetchTable;
Stephen M. Cameronaca90122014-02-18 13:56:14 -0600183 u32 *ioaccel2_blockFetchTable;
Stephen M. Cameronb9af4932014-02-18 13:56:29 -0600184 u32 *ioaccel2_bft2_regs;
Stephen M. Cameron339b2b12010-02-04 08:42:50 -0600185 unsigned char *hba_inquiry_data;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600186 u32 driver_support;
187 u32 fw_support;
188 int ioaccel_support;
189 int ioaccel_maxsg;
Stephen M. Camerona0c12412011-10-26 16:22:04 -0500190 u64 last_intr_timestamp;
191 u32 last_heartbeat;
192 u64 last_heartbeat_timestamp;
Stephen M. Camerone85c5972012-05-01 11:43:42 -0500193 u32 heartbeat_sample_interval;
194 atomic_t firmware_flash_in_progress;
Stephen M. Cameron094963d2014-05-29 10:53:18 -0500195 u32 *lockup_detected;
Stephen M. Cameron8a98db732013-12-04 17:10:07 -0600196 struct delayed_work monitor_ctlr_work;
197 int remove_in_progress;
Stephen M. Cameron396883e2013-09-23 13:34:17 -0500198 u32 fifo_recently_full;
Matt Gates254f7962012-05-01 11:43:06 -0500199 /* Address of h->q[x] is passed to intr handler to know which queue */
200 u8 q[MAX_REPLY_QUEUES];
Stephen M. Cameron75167d22012-05-01 11:42:51 -0500201 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
202#define HPSATMF_BITS_SUPPORTED (1 << 0)
203#define HPSATMF_PHYS_LUN_RESET (1 << 1)
204#define HPSATMF_PHYS_NEX_RESET (1 << 2)
205#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
206#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
207#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
208#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
209#define HPSATMF_PHYS_QRY_TASK (1 << 7)
210#define HPSATMF_PHYS_QRY_TSET (1 << 8)
211#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
212#define HPSATMF_MASK_SUPPORTED (1 << 16)
213#define HPSATMF_LOG_LUN_RESET (1 << 17)
214#define HPSATMF_LOG_NEX_RESET (1 << 18)
215#define HPSATMF_LOG_TASK_ABORT (1 << 19)
216#define HPSATMF_LOG_TSET_ABORT (1 << 20)
217#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
218#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
219#define HPSATMF_LOG_QRY_TASK (1 << 23)
220#define HPSATMF_LOG_QRY_TSET (1 << 24)
221#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
Stephen M. Cameron76438d02014-02-18 13:55:43 -0600222 u32 events;
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600223#define CTLR_STATE_CHANGE_EVENT (1 << 0)
224#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
225#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
226#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
227#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
228#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
229#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
230
231#define RESCAN_REQUIRED_EVENT_BITS \
Stephen M. Cameron7b2c46e2014-05-29 10:53:44 -0500232 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600233 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
234 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
Stephen M. Cameronfaff6ee2014-02-18 13:57:42 -0600235 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
236 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
Stephen M. Cameron98465902014-02-21 16:25:00 -0600237 spinlock_t offline_device_lock;
238 struct list_head offline_device_list;
Scott Teelda0697b2014-02-18 13:57:00 -0600239 int acciopath_status;
Scott Teele863d682014-02-18 13:57:05 -0600240 int drv_req_rescan; /* flag for driver to request rescan event */
Stephen M. Cameron2ba8bfc2014-02-18 13:57:52 -0600241 int raid_offload_debug;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800242};
Stephen M. Cameron98465902014-02-21 16:25:00 -0600243
244struct offline_device_entry {
245 unsigned char scsi3addr[8];
246 struct list_head offline_list;
247};
248
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800249#define HPSA_ABORT_MSG 0
250#define HPSA_DEVICE_RESET_MSG 1
Stephen M. Cameron64670ac2011-05-03 14:59:51 -0500251#define HPSA_RESET_TYPE_CONTROLLER 0x00
252#define HPSA_RESET_TYPE_BUS 0x01
253#define HPSA_RESET_TYPE_TARGET 0x03
254#define HPSA_RESET_TYPE_LUN 0x04
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800255#define HPSA_MSG_SEND_RETRY_LIMIT 10
Stephen M. Cameron516fda42011-05-03 14:59:15 -0500256#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800257
258/* Maximum time in seconds driver will wait for command completions
259 * when polling before giving up.
260 */
261#define HPSA_MAX_POLL_TIME_SECS (20)
262
263/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
264 * how many times to retry TEST UNIT READY on a device
265 * while waiting for it to become ready before giving up.
266 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
267 * between sending TURs while waiting for a device
268 * to become ready.
269 */
270#define HPSA_TUR_RETRY_LIMIT (20)
271#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
272
273/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
274 * to become ready, in seconds, before giving up on it.
275 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
276 * between polling the board to see if it is ready, in
277 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
278 * HPSA_BOARD_READY_ITERATIONS are derived from those.
279 */
280#define HPSA_BOARD_READY_WAIT_SECS (120)
Stephen M. Cameron2ed71272011-05-03 14:59:31 -0500281#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800282#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
283#define HPSA_BOARD_READY_POLL_INTERVAL \
284 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
285#define HPSA_BOARD_READY_ITERATIONS \
286 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
287 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronfe5389c2011-01-06 14:48:03 -0600288#define HPSA_BOARD_NOT_READY_ITERATIONS \
289 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
290 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800291#define HPSA_POST_RESET_PAUSE_MSECS (3000)
292#define HPSA_POST_RESET_NOOP_RETRIES (12)
293
294/* Defining the diffent access_menthods */
295/*
296 * Memory mapped FIFO interface (SMART 53xx cards)
297 */
298#define SA5_DOORBELL 0x20
299#define SA5_REQUEST_PORT_OFFSET 0x40
300#define SA5_REPLY_INTR_MASK_OFFSET 0x34
301#define SA5_REPLY_PORT_OFFSET 0x44
302#define SA5_INTR_STATUS 0x30
303#define SA5_SCRATCHPAD_OFFSET 0xB0
304
305#define SA5_CTCFG_OFFSET 0xB4
306#define SA5_CTMEM_OFFSET 0xB8
307
308#define SA5_INTR_OFF 0x08
309#define SA5B_INTR_OFF 0x04
310#define SA5_INTR_PENDING 0x08
311#define SA5B_INTR_PENDING 0x04
312#define FIFO_EMPTY 0xffffffff
313#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
314
315#define HPSA_ERROR_BIT 0x02
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800316
Don Brace303932f2010-02-04 08:42:40 -0600317/* Performant mode flags */
318#define SA5_PERF_INTR_PENDING 0x04
319#define SA5_PERF_INTR_OFF 0x05
320#define SA5_OUTDB_STATUS_PERF_BIT 0x01
321#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
322#define SA5_OUTDB_CLEAR 0xA0
323#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
324#define SA5_OUTDB_STATUS 0x9C
325
326
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800327#define HPSA_INTR_ON 1
328#define HPSA_INTR_OFF 0
Mike Millerb66cc252014-02-18 13:56:04 -0600329
330/*
331 * Inbound Post Queue offsets for IO Accelerator Mode 2
332 */
333#define IOACCEL2_INBOUND_POSTQ_32 0x48
334#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
335#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
336
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800337/*
338 Send the command to the hardware
339*/
340static void SA5_submit_command(struct ctlr_info *h,
341 struct CommandList *c)
342{
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800343 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
Stephen M. Cameronfec62c32011-07-21 13:16:05 -0500344 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800345}
346
Stephen M. Cameronb3a52e72014-05-29 10:53:23 -0500347static void SA5_submit_command_no_read(struct ctlr_info *h,
348 struct CommandList *c)
349{
350 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
351}
352
Scott Teelc3497752014-02-18 13:56:34 -0600353static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
354 struct CommandList *c)
355{
Scott Teelc3497752014-02-18 13:56:34 -0600356 if (c->cmd_type == CMD_IOACCEL2)
357 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
358 else
359 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
Scott Teelc3497752014-02-18 13:56:34 -0600360}
361
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800362/*
363 * This card is the opposite of the other cards.
364 * 0 turns interrupts on...
365 * 0x08 turns them off...
366 */
367static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
368{
369 if (val) { /* Turn interrupts on */
370 h->interrupts_enabled = 1;
371 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500372 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800373 } else { /* Turn them off */
374 h->interrupts_enabled = 0;
375 writel(SA5_INTR_OFF,
376 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500377 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800378 }
379}
Don Brace303932f2010-02-04 08:42:40 -0600380
381static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
382{
383 if (val) { /* turn on interrupts */
384 h->interrupts_enabled = 1;
385 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500386 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600387 } else {
388 h->interrupts_enabled = 0;
389 writel(SA5_PERF_INTR_OFF,
390 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500391 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600392 }
393}
394
Matt Gates254f7962012-05-01 11:43:06 -0500395static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
Don Brace303932f2010-02-04 08:42:40 -0600396{
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500397 struct reply_queue_buffer *rq = &h->reply_queue[q];
Matt Gatese16a33a2012-05-01 11:43:11 -0500398 unsigned long flags, register_value = FIFO_EMPTY;
Don Brace303932f2010-02-04 08:42:40 -0600399
Don Brace303932f2010-02-04 08:42:40 -0600400 /* msi auto clears the interrupt pending bit. */
401 if (!(h->msi_vector || h->msix_vector)) {
Stephen M. Cameron2c17d2d2012-05-01 11:42:30 -0500402 /* flush the controller write of the reply queue by reading
403 * outbound doorbell status register.
404 */
405 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
Don Brace303932f2010-02-04 08:42:40 -0600406 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
407 /* Do a read in order to flush the write to the controller
408 * (as per spec.)
409 */
410 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
411 }
412
Matt Gates254f7962012-05-01 11:43:06 -0500413 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
414 register_value = rq->head[rq->current_entry];
415 rq->current_entry++;
Matt Gatese16a33a2012-05-01 11:43:11 -0500416 spin_lock_irqsave(&h->lock, flags);
Don Brace303932f2010-02-04 08:42:40 -0600417 h->commands_outstanding--;
Matt Gatese16a33a2012-05-01 11:43:11 -0500418 spin_unlock_irqrestore(&h->lock, flags);
Don Brace303932f2010-02-04 08:42:40 -0600419 } else {
420 register_value = FIFO_EMPTY;
421 }
422 /* Check for wraparound */
Matt Gates254f7962012-05-01 11:43:06 -0500423 if (rq->current_entry == h->max_commands) {
424 rq->current_entry = 0;
425 rq->wraparound ^= 1;
Don Brace303932f2010-02-04 08:42:40 -0600426 }
Don Brace303932f2010-02-04 08:42:40 -0600427 return register_value;
428}
429
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800430/*
431 * Returns true if fifo is full.
432 *
433 */
434static unsigned long SA5_fifo_full(struct ctlr_info *h)
435{
436 if (h->commands_outstanding >= h->max_commands)
437 return 1;
438 else
439 return 0;
440
441}
442/*
443 * returns value read from hardware.
444 * returns FIFO_EMPTY if there is nothing to read
445 */
Matt Gates254f7962012-05-01 11:43:06 -0500446static unsigned long SA5_completed(struct ctlr_info *h,
447 __attribute__((unused)) u8 q)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800448{
449 unsigned long register_value
450 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
Matt Gatese16a33a2012-05-01 11:43:11 -0500451 unsigned long flags;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800452
Matt Gatese16a33a2012-05-01 11:43:11 -0500453 if (register_value != FIFO_EMPTY) {
454 spin_lock_irqsave(&h->lock, flags);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800455 h->commands_outstanding--;
Matt Gatese16a33a2012-05-01 11:43:11 -0500456 spin_unlock_irqrestore(&h->lock, flags);
457 }
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800458
459#ifdef HPSA_DEBUG
460 if (register_value != FIFO_EMPTY)
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600461 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800462 register_value);
463 else
Stephen M. Cameronf79cfec2012-01-19 14:00:59 -0600464 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800465#endif
466
467 return register_value;
468}
469/*
470 * Returns true if an interrupt is pending..
471 */
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600472static bool SA5_intr_pending(struct ctlr_info *h)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800473{
474 unsigned long register_value =
475 readl(h->vaddr + SA5_INTR_STATUS);
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600476 return register_value & SA5_INTR_PENDING;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800477}
478
Don Brace303932f2010-02-04 08:42:40 -0600479static bool SA5_performant_intr_pending(struct ctlr_info *h)
480{
481 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
482
483 if (!register_value)
484 return false;
485
486 if (h->msi_vector || h->msix_vector)
487 return true;
488
489 /* Read outbound doorbell to flush */
490 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
491 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
492}
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800493
Matt Gatese1f7de02014-02-18 13:55:17 -0600494#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
495
496static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
497{
498 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
499
500 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
501 true : false;
502}
503
504#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
505#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
506#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
507#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
508
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600509static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
Matt Gatese1f7de02014-02-18 13:55:17 -0600510{
511 u64 register_value;
Stephen M. Cameron072b0512014-05-29 10:53:07 -0500512 struct reply_queue_buffer *rq = &h->reply_queue[q];
Matt Gatese1f7de02014-02-18 13:55:17 -0600513 unsigned long flags;
514
515 BUG_ON(q >= h->nreply_queues);
516
517 register_value = rq->head[rq->current_entry];
518 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
519 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
520 if (++rq->current_entry == rq->size)
521 rq->current_entry = 0;
Stephen M. Cameron283b4a92014-02-18 13:55:33 -0600522 /*
523 * @todo
524 *
525 * Don't really need to write the new index after each command,
526 * but with current driver design this is easiest.
527 */
528 wmb();
529 writel((q << 24) | rq->current_entry, h->vaddr +
530 IOACCEL_MODE1_CONSUMER_INDEX);
Matt Gatese1f7de02014-02-18 13:55:17 -0600531 spin_lock_irqsave(&h->lock, flags);
532 h->commands_outstanding--;
533 spin_unlock_irqrestore(&h->lock, flags);
Matt Gatese1f7de02014-02-18 13:55:17 -0600534 }
535 return (unsigned long) register_value;
536}
537
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800538static struct access_method SA5_access = {
539 SA5_submit_command,
540 SA5_intr_mask,
541 SA5_fifo_full,
542 SA5_intr_pending,
543 SA5_completed,
544};
545
Matt Gatese1f7de02014-02-18 13:55:17 -0600546static struct access_method SA5_ioaccel_mode1_access = {
547 SA5_submit_command,
548 SA5_performant_intr_mask,
549 SA5_fifo_full,
550 SA5_ioaccel_mode1_intr_pending,
551 SA5_ioaccel_mode1_completed,
552};
553
Scott Teelc3497752014-02-18 13:56:34 -0600554static struct access_method SA5_ioaccel_mode2_access = {
555 SA5_submit_command_ioaccel2,
556 SA5_performant_intr_mask,
557 SA5_fifo_full,
558 SA5_performant_intr_pending,
559 SA5_performant_completed,
560};
561
Don Brace303932f2010-02-04 08:42:40 -0600562static struct access_method SA5_performant_access = {
563 SA5_submit_command,
564 SA5_performant_intr_mask,
565 SA5_fifo_full,
566 SA5_performant_intr_pending,
567 SA5_performant_completed,
568};
569
Stephen M. Cameronb3a52e72014-05-29 10:53:23 -0500570static struct access_method SA5_performant_access_no_read = {
571 SA5_submit_command_no_read,
572 SA5_performant_intr_mask,
573 SA5_fifo_full,
574 SA5_performant_intr_pending,
575 SA5_performant_completed,
576};
577
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800578struct board_type {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600579 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800580 char *product_name;
581 struct access_method *access;
582};
583
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800584#endif /* HPSA_H */
585