Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC |
| 3 | * |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Cogent Embedded Inc. |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 12 | #include <dt-bindings/clock/r8a7790-clock.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 16 | / { |
| 17 | compatible = "renesas,r8a7790"; |
| 18 | interrupt-parent = <&gic>; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 21 | |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 22 | aliases { |
| 23 | i2c0 = &i2c0; |
| 24 | i2c1 = &i2c1; |
| 25 | i2c2 = &i2c2; |
| 26 | i2c3 = &i2c3; |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame^] | 27 | i2c4 = &iic0; |
| 28 | i2c5 = &iic1; |
| 29 | i2c6 = &iic2; |
| 30 | i2c7 = &iic3; |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 31 | spi0 = &qspi; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 32 | spi1 = &msiof0; |
| 33 | spi2 = &msiof1; |
| 34 | spi3 = &msiof2; |
| 35 | spi4 = &msiof3; |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 36 | }; |
| 37 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 38 | cpus { |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <0>; |
| 41 | |
| 42 | cpu0: cpu@0 { |
| 43 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a15"; |
| 45 | reg = <0>; |
| 46 | clock-frequency = <1300000000>; |
| 47 | }; |
Magnus Damm | c1f9597 | 2013-08-29 08:22:17 +0900 | [diff] [blame] | 48 | |
| 49 | cpu1: cpu@1 { |
| 50 | device_type = "cpu"; |
| 51 | compatible = "arm,cortex-a15"; |
| 52 | reg = <1>; |
| 53 | clock-frequency = <1300000000>; |
| 54 | }; |
| 55 | |
| 56 | cpu2: cpu@2 { |
| 57 | device_type = "cpu"; |
| 58 | compatible = "arm,cortex-a15"; |
| 59 | reg = <2>; |
| 60 | clock-frequency = <1300000000>; |
| 61 | }; |
| 62 | |
| 63 | cpu3: cpu@3 { |
| 64 | device_type = "cpu"; |
| 65 | compatible = "arm,cortex-a15"; |
| 66 | reg = <3>; |
| 67 | clock-frequency = <1300000000>; |
| 68 | }; |
Magnus Damm | 2007e74 | 2013-09-15 00:28:58 +0900 | [diff] [blame] | 69 | |
| 70 | cpu4: cpu@4 { |
| 71 | device_type = "cpu"; |
| 72 | compatible = "arm,cortex-a7"; |
| 73 | reg = <0x100>; |
| 74 | clock-frequency = <780000000>; |
| 75 | }; |
| 76 | |
| 77 | cpu5: cpu@5 { |
| 78 | device_type = "cpu"; |
| 79 | compatible = "arm,cortex-a7"; |
| 80 | reg = <0x101>; |
| 81 | clock-frequency = <780000000>; |
| 82 | }; |
| 83 | |
| 84 | cpu6: cpu@6 { |
| 85 | device_type = "cpu"; |
| 86 | compatible = "arm,cortex-a7"; |
| 87 | reg = <0x102>; |
| 88 | clock-frequency = <780000000>; |
| 89 | }; |
| 90 | |
| 91 | cpu7: cpu@7 { |
| 92 | device_type = "cpu"; |
| 93 | compatible = "arm,cortex-a7"; |
| 94 | reg = <0x103>; |
| 95 | clock-frequency = <780000000>; |
| 96 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | gic: interrupt-controller@f1001000 { |
| 100 | compatible = "arm,cortex-a15-gic"; |
| 101 | #interrupt-cells = <3>; |
| 102 | #address-cells = <0>; |
| 103 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 104 | reg = <0 0xf1001000 0 0x1000>, |
| 105 | <0 0xf1002000 0 0x1000>, |
| 106 | <0 0xf1004000 0 0x2000>, |
| 107 | <0 0xf1006000 0 0x2000>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 108 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 109 | }; |
| 110 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 111 | gpio0: gpio@e6050000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 112 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 113 | reg = <0 0xe6050000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 114 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 115 | #gpio-cells = <2>; |
| 116 | gpio-controller; |
| 117 | gpio-ranges = <&pfc 0 0 32>; |
| 118 | #interrupt-cells = <2>; |
| 119 | interrupt-controller; |
| 120 | }; |
| 121 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 122 | gpio1: gpio@e6051000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 123 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 124 | reg = <0 0xe6051000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 125 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 126 | #gpio-cells = <2>; |
| 127 | gpio-controller; |
| 128 | gpio-ranges = <&pfc 0 32 32>; |
| 129 | #interrupt-cells = <2>; |
| 130 | interrupt-controller; |
| 131 | }; |
| 132 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 133 | gpio2: gpio@e6052000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 134 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 135 | reg = <0 0xe6052000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 136 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 137 | #gpio-cells = <2>; |
| 138 | gpio-controller; |
| 139 | gpio-ranges = <&pfc 0 64 32>; |
| 140 | #interrupt-cells = <2>; |
| 141 | interrupt-controller; |
| 142 | }; |
| 143 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 144 | gpio3: gpio@e6053000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 145 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 146 | reg = <0 0xe6053000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 147 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 148 | #gpio-cells = <2>; |
| 149 | gpio-controller; |
| 150 | gpio-ranges = <&pfc 0 96 32>; |
| 151 | #interrupt-cells = <2>; |
| 152 | interrupt-controller; |
| 153 | }; |
| 154 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 155 | gpio4: gpio@e6054000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 156 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 157 | reg = <0 0xe6054000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 158 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 159 | #gpio-cells = <2>; |
| 160 | gpio-controller; |
| 161 | gpio-ranges = <&pfc 0 128 32>; |
| 162 | #interrupt-cells = <2>; |
| 163 | interrupt-controller; |
| 164 | }; |
| 165 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 166 | gpio5: gpio@e6055000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 167 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 168 | reg = <0 0xe6055000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 169 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 170 | #gpio-cells = <2>; |
| 171 | gpio-controller; |
| 172 | gpio-ranges = <&pfc 0 160 32>; |
| 173 | #interrupt-cells = <2>; |
| 174 | interrupt-controller; |
| 175 | }; |
| 176 | |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 177 | thermal@e61f0000 { |
| 178 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; |
| 179 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 180 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | d3a439d | 2014-01-07 19:57:14 +0100 | [diff] [blame] | 181 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 182 | }; |
| 183 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 184 | timer { |
| 185 | compatible = "arm,armv7-timer"; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 186 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 187 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 188 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 189 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 190 | }; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 191 | |
| 192 | irqc0: interrupt-controller@e61c0000 { |
Magnus Damm | 220fc35 | 2013-11-20 09:07:40 +0900 | [diff] [blame] | 193 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 194 | #interrupt-cells = <2>; |
| 195 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 196 | reg = <0 0xe61c0000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 197 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 198 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 199 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| 200 | <0 3 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 201 | }; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 202 | |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 203 | i2c0: i2c@e6508000 { |
| 204 | #address-cells = <1>; |
| 205 | #size-cells = <0>; |
| 206 | compatible = "renesas,i2c-r8a7790"; |
| 207 | reg = <0 0xe6508000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 208 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 209 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 210 | status = "disabled"; |
| 211 | }; |
| 212 | |
| 213 | i2c1: i2c@e6518000 { |
| 214 | #address-cells = <1>; |
| 215 | #size-cells = <0>; |
| 216 | compatible = "renesas,i2c-r8a7790"; |
| 217 | reg = <0 0xe6518000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 218 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 219 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 220 | status = "disabled"; |
| 221 | }; |
| 222 | |
| 223 | i2c2: i2c@e6530000 { |
| 224 | #address-cells = <1>; |
| 225 | #size-cells = <0>; |
| 226 | compatible = "renesas,i2c-r8a7790"; |
| 227 | reg = <0 0xe6530000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 228 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 229 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 230 | status = "disabled"; |
| 231 | }; |
| 232 | |
| 233 | i2c3: i2c@e6540000 { |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <0>; |
| 236 | compatible = "renesas,i2c-r8a7790"; |
| 237 | reg = <0 0xe6540000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 238 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 239 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 240 | status = "disabled"; |
| 241 | }; |
| 242 | |
Wolfram Sang | 05f3991 | 2014-03-25 19:56:29 +0100 | [diff] [blame^] | 243 | iic0: i2c@e6500000 { |
| 244 | #address-cells = <1>; |
| 245 | #size-cells = <0>; |
| 246 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 247 | reg = <0 0xe6500000 0 0x425>; |
| 248 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; |
| 249 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; |
| 250 | status = "disabled"; |
| 251 | }; |
| 252 | |
| 253 | iic1: i2c@e6510000 { |
| 254 | #address-cells = <1>; |
| 255 | #size-cells = <0>; |
| 256 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 257 | reg = <0 0xe6510000 0 0x425>; |
| 258 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; |
| 259 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; |
| 260 | status = "disabled"; |
| 261 | }; |
| 262 | |
| 263 | iic2: i2c@e6520000 { |
| 264 | #address-cells = <1>; |
| 265 | #size-cells = <0>; |
| 266 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 267 | reg = <0 0xe6520000 0 0x425>; |
| 268 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; |
| 269 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; |
| 270 | status = "disabled"; |
| 271 | }; |
| 272 | |
| 273 | iic3: i2c@e60b0000 { |
| 274 | #address-cells = <1>; |
| 275 | #size-cells = <0>; |
| 276 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; |
| 277 | reg = <0 0xe60b0000 0 0x425>; |
| 278 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; |
| 279 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; |
| 280 | status = "disabled"; |
| 281 | }; |
| 282 | |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 283 | mmcif0: mmcif@ee200000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 284 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 285 | reg = <0 0xee200000 0 0x80>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 286 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 287 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 288 | reg-io-width = <4>; |
| 289 | status = "disabled"; |
| 290 | }; |
| 291 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 292 | mmcif1: mmc@ee220000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 293 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 294 | reg = <0 0xee220000 0 0x80>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 295 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 296 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 297 | reg-io-width = <4>; |
| 298 | status = "disabled"; |
| 299 | }; |
| 300 | |
Laurent Pinchart | 9694c77 | 2013-05-09 15:05:57 +0200 | [diff] [blame] | 301 | pfc: pfc@e6060000 { |
| 302 | compatible = "renesas,pfc-r8a7790"; |
| 303 | reg = <0 0xe6060000 0 0x250>; |
| 304 | }; |
Olof Johansson | 55689bf | 2013-08-14 00:24:05 -0700 | [diff] [blame] | 305 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 306 | sdhi0: sd@ee100000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 307 | compatible = "renesas,sdhi-r8a7790"; |
Ben Dooks | d721a15 | 2013-12-16 12:38:48 +0000 | [diff] [blame] | 308 | reg = <0 0xee100000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 309 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 310 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 311 | cap-sd-highspeed; |
| 312 | status = "disabled"; |
| 313 | }; |
| 314 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 315 | sdhi1: sd@ee120000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 316 | compatible = "renesas,sdhi-r8a7790"; |
Ben Dooks | d721a15 | 2013-12-16 12:38:48 +0000 | [diff] [blame] | 317 | reg = <0 0xee120000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 318 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 319 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 320 | cap-sd-highspeed; |
| 321 | status = "disabled"; |
| 322 | }; |
| 323 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 324 | sdhi2: sd@ee140000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 325 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 326 | reg = <0 0xee140000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 327 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 328 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 329 | cap-sd-highspeed; |
| 330 | status = "disabled"; |
| 331 | }; |
| 332 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 333 | sdhi3: sd@ee160000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 334 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 335 | reg = <0 0xee160000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 336 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 337 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 338 | cap-sd-highspeed; |
| 339 | status = "disabled"; |
| 340 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 341 | |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 342 | scifa0: serial@e6c40000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 343 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 344 | reg = <0 0xe6c40000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 345 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 346 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
| 347 | clock-names = "sci_ick"; |
| 348 | status = "disabled"; |
| 349 | }; |
| 350 | |
| 351 | scifa1: serial@e6c50000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 352 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 353 | reg = <0 0xe6c50000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 354 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 355 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
| 356 | clock-names = "sci_ick"; |
| 357 | status = "disabled"; |
| 358 | }; |
| 359 | |
| 360 | scifa2: serial@e6c60000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 361 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 362 | reg = <0 0xe6c60000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 363 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 364 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
| 365 | clock-names = "sci_ick"; |
| 366 | status = "disabled"; |
| 367 | }; |
| 368 | |
| 369 | scifb0: serial@e6c20000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 370 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 371 | reg = <0 0xe6c20000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 372 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 373 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
| 374 | clock-names = "sci_ick"; |
| 375 | status = "disabled"; |
| 376 | }; |
| 377 | |
| 378 | scifb1: serial@e6c30000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 379 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 380 | reg = <0 0xe6c30000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 381 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 382 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
| 383 | clock-names = "sci_ick"; |
| 384 | status = "disabled"; |
| 385 | }; |
| 386 | |
| 387 | scifb2: serial@e6ce0000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 388 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 389 | reg = <0 0xe6ce0000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 390 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 391 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
| 392 | clock-names = "sci_ick"; |
| 393 | status = "disabled"; |
| 394 | }; |
| 395 | |
| 396 | scif0: serial@e6e60000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 397 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 398 | reg = <0 0xe6e60000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 399 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 400 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
| 401 | clock-names = "sci_ick"; |
| 402 | status = "disabled"; |
| 403 | }; |
| 404 | |
| 405 | scif1: serial@e6e68000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 406 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 407 | reg = <0 0xe6e68000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 408 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 409 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
| 410 | clock-names = "sci_ick"; |
| 411 | status = "disabled"; |
| 412 | }; |
| 413 | |
| 414 | hscif0: serial@e62c0000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 415 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 416 | reg = <0 0xe62c0000 0 96>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 417 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 418 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
| 419 | clock-names = "sci_ick"; |
| 420 | status = "disabled"; |
| 421 | }; |
| 422 | |
| 423 | hscif1: serial@e62c8000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 424 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 425 | reg = <0 0xe62c8000 0 96>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 426 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 427 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
| 428 | clock-names = "sci_ick"; |
| 429 | status = "disabled"; |
| 430 | }; |
| 431 | |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 432 | ether: ethernet@ee700000 { |
| 433 | compatible = "renesas,ether-r8a7790"; |
| 434 | reg = <0 0xee700000 0 0x400>; |
| 435 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; |
| 436 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; |
| 437 | phy-mode = "rmii"; |
| 438 | #address-cells = <1>; |
| 439 | #size-cells = <0>; |
| 440 | status = "disabled"; |
| 441 | }; |
| 442 | |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 443 | sata0: sata@ee300000 { |
| 444 | compatible = "renesas,sata-r8a7790"; |
| 445 | reg = <0 0xee300000 0 0x2000>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 446 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 447 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; |
| 448 | status = "disabled"; |
| 449 | }; |
| 450 | |
| 451 | sata1: sata@ee500000 { |
| 452 | compatible = "renesas,sata-r8a7790"; |
| 453 | reg = <0 0xee500000 0 0x2000>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 454 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 455 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; |
| 456 | status = "disabled"; |
| 457 | }; |
| 458 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 459 | clocks { |
| 460 | #address-cells = <2>; |
| 461 | #size-cells = <2>; |
| 462 | ranges; |
| 463 | |
| 464 | /* External root clock */ |
| 465 | extal_clk: extal_clk { |
| 466 | compatible = "fixed-clock"; |
| 467 | #clock-cells = <0>; |
| 468 | /* This value must be overriden by the board. */ |
| 469 | clock-frequency = <0>; |
| 470 | clock-output-names = "extal"; |
| 471 | }; |
| 472 | |
Kuninori Morimoto | c7c2ec3 | 2014-01-13 18:25:39 -0800 | [diff] [blame] | 473 | /* |
| 474 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by |
| 475 | * default. Boards that provide audio clocks should override them. |
| 476 | */ |
| 477 | audio_clk_a: audio_clk_a { |
| 478 | compatible = "fixed-clock"; |
| 479 | #clock-cells = <0>; |
| 480 | clock-frequency = <0>; |
| 481 | clock-output-names = "audio_clk_a"; |
| 482 | }; |
| 483 | audio_clk_b: audio_clk_b { |
| 484 | compatible = "fixed-clock"; |
| 485 | #clock-cells = <0>; |
| 486 | clock-frequency = <0>; |
| 487 | clock-output-names = "audio_clk_b"; |
| 488 | }; |
| 489 | audio_clk_c: audio_clk_c { |
| 490 | compatible = "fixed-clock"; |
| 491 | #clock-cells = <0>; |
| 492 | clock-frequency = <0>; |
| 493 | clock-output-names = "audio_clk_c"; |
| 494 | }; |
| 495 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 496 | /* Special CPG clocks */ |
| 497 | cpg_clocks: cpg_clocks@e6150000 { |
| 498 | compatible = "renesas,r8a7790-cpg-clocks", |
| 499 | "renesas,rcar-gen2-cpg-clocks"; |
| 500 | reg = <0 0xe6150000 0 0x1000>; |
| 501 | clocks = <&extal_clk>; |
| 502 | #clock-cells = <1>; |
| 503 | clock-output-names = "main", "pll0", "pll1", "pll3", |
| 504 | "lb", "qspi", "sdh", "sd0", "sd1", |
| 505 | "z"; |
| 506 | }; |
| 507 | |
| 508 | /* Variable factor clocks */ |
| 509 | sd2_clk: sd2_clk@e6150078 { |
| 510 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 511 | reg = <0 0xe6150078 0 4>; |
| 512 | clocks = <&pll1_div2_clk>; |
| 513 | #clock-cells = <0>; |
| 514 | clock-output-names = "sd2"; |
| 515 | }; |
| 516 | sd3_clk: sd3_clk@e615007c { |
| 517 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 518 | reg = <0 0xe615007c 0 4>; |
| 519 | clocks = <&pll1_div2_clk>; |
| 520 | #clock-cells = <0>; |
| 521 | clock-output-names = "sd3"; |
| 522 | }; |
| 523 | mmc0_clk: mmc0_clk@e6150240 { |
| 524 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 525 | reg = <0 0xe6150240 0 4>; |
| 526 | clocks = <&pll1_div2_clk>; |
| 527 | #clock-cells = <0>; |
| 528 | clock-output-names = "mmc0"; |
| 529 | }; |
| 530 | mmc1_clk: mmc1_clk@e6150244 { |
| 531 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 532 | reg = <0 0xe6150244 0 4>; |
| 533 | clocks = <&pll1_div2_clk>; |
| 534 | #clock-cells = <0>; |
| 535 | clock-output-names = "mmc1"; |
| 536 | }; |
| 537 | ssp_clk: ssp_clk@e6150248 { |
| 538 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 539 | reg = <0 0xe6150248 0 4>; |
| 540 | clocks = <&pll1_div2_clk>; |
| 541 | #clock-cells = <0>; |
| 542 | clock-output-names = "ssp"; |
| 543 | }; |
| 544 | ssprs_clk: ssprs_clk@e615024c { |
| 545 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 546 | reg = <0 0xe615024c 0 4>; |
| 547 | clocks = <&pll1_div2_clk>; |
| 548 | #clock-cells = <0>; |
| 549 | clock-output-names = "ssprs"; |
| 550 | }; |
| 551 | |
| 552 | /* Fixed factor clocks */ |
| 553 | pll1_div2_clk: pll1_div2_clk { |
| 554 | compatible = "fixed-factor-clock"; |
| 555 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 556 | #clock-cells = <0>; |
| 557 | clock-div = <2>; |
| 558 | clock-mult = <1>; |
| 559 | clock-output-names = "pll1_div2"; |
| 560 | }; |
| 561 | z2_clk: z2_clk { |
| 562 | compatible = "fixed-factor-clock"; |
| 563 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 564 | #clock-cells = <0>; |
| 565 | clock-div = <2>; |
| 566 | clock-mult = <1>; |
| 567 | clock-output-names = "z2"; |
| 568 | }; |
| 569 | zg_clk: zg_clk { |
| 570 | compatible = "fixed-factor-clock"; |
| 571 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 572 | #clock-cells = <0>; |
| 573 | clock-div = <3>; |
| 574 | clock-mult = <1>; |
| 575 | clock-output-names = "zg"; |
| 576 | }; |
| 577 | zx_clk: zx_clk { |
| 578 | compatible = "fixed-factor-clock"; |
| 579 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 580 | #clock-cells = <0>; |
| 581 | clock-div = <3>; |
| 582 | clock-mult = <1>; |
| 583 | clock-output-names = "zx"; |
| 584 | }; |
| 585 | zs_clk: zs_clk { |
| 586 | compatible = "fixed-factor-clock"; |
| 587 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 588 | #clock-cells = <0>; |
| 589 | clock-div = <6>; |
| 590 | clock-mult = <1>; |
| 591 | clock-output-names = "zs"; |
| 592 | }; |
| 593 | hp_clk: hp_clk { |
| 594 | compatible = "fixed-factor-clock"; |
| 595 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 596 | #clock-cells = <0>; |
| 597 | clock-div = <12>; |
| 598 | clock-mult = <1>; |
| 599 | clock-output-names = "hp"; |
| 600 | }; |
| 601 | i_clk: i_clk { |
| 602 | compatible = "fixed-factor-clock"; |
| 603 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 604 | #clock-cells = <0>; |
| 605 | clock-div = <2>; |
| 606 | clock-mult = <1>; |
| 607 | clock-output-names = "i"; |
| 608 | }; |
| 609 | b_clk: b_clk { |
| 610 | compatible = "fixed-factor-clock"; |
| 611 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 612 | #clock-cells = <0>; |
| 613 | clock-div = <12>; |
| 614 | clock-mult = <1>; |
| 615 | clock-output-names = "b"; |
| 616 | }; |
| 617 | p_clk: p_clk { |
| 618 | compatible = "fixed-factor-clock"; |
| 619 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 620 | #clock-cells = <0>; |
| 621 | clock-div = <24>; |
| 622 | clock-mult = <1>; |
| 623 | clock-output-names = "p"; |
| 624 | }; |
| 625 | cl_clk: cl_clk { |
| 626 | compatible = "fixed-factor-clock"; |
| 627 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 628 | #clock-cells = <0>; |
| 629 | clock-div = <48>; |
| 630 | clock-mult = <1>; |
| 631 | clock-output-names = "cl"; |
| 632 | }; |
| 633 | m2_clk: m2_clk { |
| 634 | compatible = "fixed-factor-clock"; |
| 635 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 636 | #clock-cells = <0>; |
| 637 | clock-div = <8>; |
| 638 | clock-mult = <1>; |
| 639 | clock-output-names = "m2"; |
| 640 | }; |
| 641 | imp_clk: imp_clk { |
| 642 | compatible = "fixed-factor-clock"; |
| 643 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 644 | #clock-cells = <0>; |
| 645 | clock-div = <4>; |
| 646 | clock-mult = <1>; |
| 647 | clock-output-names = "imp"; |
| 648 | }; |
| 649 | rclk_clk: rclk_clk { |
| 650 | compatible = "fixed-factor-clock"; |
| 651 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 652 | #clock-cells = <0>; |
| 653 | clock-div = <(48 * 1024)>; |
| 654 | clock-mult = <1>; |
| 655 | clock-output-names = "rclk"; |
| 656 | }; |
| 657 | oscclk_clk: oscclk_clk { |
| 658 | compatible = "fixed-factor-clock"; |
| 659 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 660 | #clock-cells = <0>; |
| 661 | clock-div = <(12 * 1024)>; |
| 662 | clock-mult = <1>; |
| 663 | clock-output-names = "oscclk"; |
| 664 | }; |
| 665 | zb3_clk: zb3_clk { |
| 666 | compatible = "fixed-factor-clock"; |
| 667 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 668 | #clock-cells = <0>; |
| 669 | clock-div = <4>; |
| 670 | clock-mult = <1>; |
| 671 | clock-output-names = "zb3"; |
| 672 | }; |
| 673 | zb3d2_clk: zb3d2_clk { |
| 674 | compatible = "fixed-factor-clock"; |
| 675 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 676 | #clock-cells = <0>; |
| 677 | clock-div = <8>; |
| 678 | clock-mult = <1>; |
| 679 | clock-output-names = "zb3d2"; |
| 680 | }; |
| 681 | ddr_clk: ddr_clk { |
| 682 | compatible = "fixed-factor-clock"; |
| 683 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 684 | #clock-cells = <0>; |
| 685 | clock-div = <8>; |
| 686 | clock-mult = <1>; |
| 687 | clock-output-names = "ddr"; |
| 688 | }; |
| 689 | mp_clk: mp_clk { |
| 690 | compatible = "fixed-factor-clock"; |
| 691 | clocks = <&pll1_div2_clk>; |
| 692 | #clock-cells = <0>; |
| 693 | clock-div = <15>; |
| 694 | clock-mult = <1>; |
| 695 | clock-output-names = "mp"; |
| 696 | }; |
| 697 | cp_clk: cp_clk { |
| 698 | compatible = "fixed-factor-clock"; |
| 699 | clocks = <&extal_clk>; |
| 700 | #clock-cells = <0>; |
| 701 | clock-div = <2>; |
| 702 | clock-mult = <1>; |
| 703 | clock-output-names = "cp"; |
| 704 | }; |
| 705 | |
| 706 | /* Gate clocks */ |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 707 | mstp0_clks: mstp0_clks@e6150130 { |
| 708 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 709 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 710 | clocks = <&mp_clk>; |
| 711 | #clock-cells = <1>; |
| 712 | renesas,clock-indices = <R8A7790_CLK_MSIOF0>; |
| 713 | clock-output-names = "msiof0"; |
| 714 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 715 | mstp1_clks: mstp1_clks@e6150134 { |
| 716 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 717 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| 718 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, |
| 719 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, |
| 720 | <&zs_clk>; |
| 721 | #clock-cells = <1>; |
| 722 | renesas,clock-indices = < |
| 723 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 |
| 724 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 |
| 725 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY |
| 726 | >; |
| 727 | clock-output-names = |
| 728 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
| 729 | "vsp1-du0", "vsp1-rt", "vsp1-sy"; |
| 730 | }; |
| 731 | mstp2_clks: mstp2_clks@e6150138 { |
| 732 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 733 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 734 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 735 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 736 | #clock-cells = <1>; |
| 737 | renesas,clock-indices = < |
| 738 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 739 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
| 740 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 741 | >; |
| 742 | clock-output-names = |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 743 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| 744 | "scifb1", "msiof1", "msiof3", "scifb2"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 745 | }; |
| 746 | mstp3_clks: mstp3_clks@e615013c { |
| 747 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 748 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 749 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
| 750 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, |
| 751 | <&hp_clk>, <&hp_clk>, <&rclk_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 752 | #clock-cells = <1>; |
| 753 | renesas,clock-indices = < |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 754 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 755 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 |
| 756 | R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 757 | >; |
| 758 | clock-output-names = |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 759 | "iic2", "tpu0", "mmcif1", "sdhi3", |
| 760 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", |
| 761 | "iic0", "iic1", "cmt1"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 762 | }; |
| 763 | mstp5_clks: mstp5_clks@e6150144 { |
| 764 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 765 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
| 766 | clocks = <&extal_clk>, <&p_clk>; |
| 767 | #clock-cells = <1>; |
| 768 | renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; |
| 769 | clock-output-names = "thermal", "pwm"; |
| 770 | }; |
| 771 | mstp7_clks: mstp7_clks@e615014c { |
| 772 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 773 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| 774 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 775 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, |
| 776 | <&zx_clk>; |
| 777 | #clock-cells = <1>; |
| 778 | renesas,clock-indices = < |
| 779 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 |
| 780 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 |
| 781 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 |
| 782 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 |
| 783 | >; |
| 784 | clock-output-names = |
| 785 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", |
| 786 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; |
| 787 | }; |
| 788 | mstp8_clks: mstp8_clks@e6150990 { |
| 789 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 790 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 791 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
| 792 | <&zs_clk>, <&zs_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 793 | #clock-cells = <1>; |
Laurent Pinchart | 3f2beaa | 2014-01-07 09:22:53 +0100 | [diff] [blame] | 794 | renesas,clock-indices = < |
| 795 | R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 796 | R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 |
| 797 | R8A7790_CLK_SATA0 |
Laurent Pinchart | 3f2beaa | 2014-01-07 09:22:53 +0100 | [diff] [blame] | 798 | >; |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 799 | clock-output-names = |
| 800 | "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 801 | }; |
| 802 | mstp9_clks: mstp9_clks@e6150994 { |
| 803 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 804 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 805 | clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, |
Laurent Pinchart | 3672b05 | 2014-04-01 13:02:17 +0200 | [diff] [blame] | 806 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 807 | #clock-cells = <1>; |
| 808 | renesas,clock-indices = < |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 809 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
| 810 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 811 | >; |
Laurent Pinchart | 91b56ca | 2013-12-19 16:51:03 +0100 | [diff] [blame] | 812 | clock-output-names = |
Wolfram Sang | 1746514 | 2014-03-11 22:24:37 +0100 | [diff] [blame] | 813 | "rcan1", "rcan0", "qspi_mod", "iic3", |
| 814 | "i2c3", "i2c2", "i2c1", "i2c0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 815 | }; |
| 816 | }; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 817 | |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 818 | qspi: spi@e6b10000 { |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 819 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
| 820 | reg = <0 0xe6b10000 0 0x2c>; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 821 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 822 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; |
| 823 | num-cs = <1>; |
| 824 | #address-cells = <1>; |
| 825 | #size-cells = <0>; |
| 826 | status = "disabled"; |
| 827 | }; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 828 | |
| 829 | msiof0: spi@e6e20000 { |
| 830 | compatible = "renesas,msiof-r8a7790"; |
| 831 | reg = <0 0xe6e20000 0 0x0064>; |
| 832 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
| 833 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; |
| 834 | #address-cells = <1>; |
| 835 | #size-cells = <0>; |
| 836 | status = "disabled"; |
| 837 | }; |
| 838 | |
| 839 | msiof1: spi@e6e10000 { |
| 840 | compatible = "renesas,msiof-r8a7790"; |
| 841 | reg = <0 0xe6e10000 0 0x0064>; |
| 842 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
| 843 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; |
| 844 | #address-cells = <1>; |
| 845 | #size-cells = <0>; |
| 846 | status = "disabled"; |
| 847 | }; |
| 848 | |
| 849 | msiof2: spi@e6e00000 { |
| 850 | compatible = "renesas,msiof-r8a7790"; |
| 851 | reg = <0 0xe6e00000 0 0x0064>; |
| 852 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
| 853 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; |
| 854 | #address-cells = <1>; |
| 855 | #size-cells = <0>; |
| 856 | status = "disabled"; |
| 857 | }; |
| 858 | |
| 859 | msiof3: spi@e6c90000 { |
| 860 | compatible = "renesas,msiof-r8a7790"; |
| 861 | reg = <0 0xe6c90000 0 0x0064>; |
| 862 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; |
| 863 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; |
| 864 | #address-cells = <1>; |
| 865 | #size-cells = <0>; |
| 866 | status = "disabled"; |
| 867 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 868 | }; |